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2011-05-15Enable 33 MHz fast mode SPI read early to reduce boot time.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6582 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15Move mmconf base from e0000000 to f8000000 to avoid conflict with UMA BAR.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6578 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15Match DIMM SPD addressing to implemented slots.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6575 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-15Size mmconf according to CONFIG_MMCONF_BUS_NUMBER.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6574 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-151) Use D18F1xF4 VGA Enable to simplify legacy video I/O support.Scott Duplichan
2) Extend PCI MMIO limit from dfffffff to fecfffff. 3) Add AMD recommended non-posted mapping for SB800 legacy devices. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6573 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-151) Set I/O APIC ID according to BKDG recommendationScott Duplichan
2) Correct I/O APIC ID reported by mptable Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-13siemens/sitemp_g1p1: Adapt read_option() to latest changesJosef Kellermann
Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6569 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-12Remove uart_init() in Siemens sitemp-g1p1Patrick Georgi
uart_init() was moved to common code in r6531, but I missed that when integrating the new mainboard code. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6568 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-11Add Siemens SITEMP-G1 boardJosef Kellermann
The code is loosely based on AMD dbm690t (and copied from there) and adapted to match the Siemens SITEMP-G1 board. It boots both Linux and Windows XP (and if it doesn't then complain with me [Patrick] because in that case I must have messed it up when integrating the patch) Signed-off-by: Josef Kellermann <seppk@arcor.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6567 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-10Change read_option() to a macro that wraps some API uglynessPatrick Georgi
Simplify read_option(CMOS_VSTART_foo, CMOS_VLEN_foo, somedefault) to read_option(foo, somedefault) Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6565 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-05-07ADVANSUS A785E-I Mainboard support, Family10h ASB2, RS880(RS785E) + SB820 ↵Kerry She
platform. Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6561 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-28Thinkpad: Enable Battery eventsSven Schnelle
Enable the following events for battery objects on Thinkpad X60/T60: 24: BAT0 critical 25: BAT1 critical 4A: BAT0 present 4B: BAT0 state change 4C: BAT1 present 4D: BAT1 state change Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6549 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27X60: enable Ultrabay if device is plugged inSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6548 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-27T60: enable Ultrabay if device is plugged inSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6547 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-22The UART divider should be calculated based on the base frequencyStefan Reinauer
and baudrate, not hardcoded in addition to that. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6538 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-21some ifdef --> if fixesStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6535 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20run uart_init() from console_init, just like the other console ↵Stefan Reinauer
initialization functions. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6531 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20Add Lenovo ThinkPad T60Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6530 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: remove latency/bridge control/cacheline size settingsSven Schnelle
Those settings should be handled by the generic PCI/Cardbus code, and not by the driver itself. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6528 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: use pci_ops set_subsystem instead of custom codeSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6526 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-20pci1x2x: use devicetree register configurationSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6524 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-19Drop baud rate init to an arbitrary baud rate from Super I/O code. ↵Stefan Reinauer
See discussion at http://www.mail-archive.com/coreboot@coreboot.org/msg29394.html config->com1, devicetree.cb cleanup and init_uart8250() removal will follow once this patch is comitted Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> Updated to drop com1, com2.... from config structure and devicetree.cb git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6521 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-18* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that valueStefan Reinauer
to unify calls to *_enable_usbdebug() * rename *_enable_usbdebug() to enable_usbdebug() * move enable_usbdebug() to generic romstage console init code and drop it from the individual romstage.c files. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6513 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-15fix mainboards that were including earlymtrr.c without actually using it.Stefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6502 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11Unify use of post_codeAlexandru Gagniuc
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6487 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11PMH7: Add chip configSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6486 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-11EC: Add Lenovo H8Sven Schnelle
Move the EC support code from the X60 mainboard to a generic driver, as this EC is used in many thinkpads. Also move the ACPI code to this directory for this reason. This patch also adds a chip config, so that the initial setting for basic register can be specified in devicetree.cb Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6485 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-10In 2007 Adrian Reber suggested that we drop ASSEMBLY in favor of __ASSEMBLER__.Stefan Reinauer
http://www.coreboot.org/pipermail/coreboot/2007-September/024665.html It's about time we follow this advice. Also move some manually set __PRE_RAM__ defines (ap_romstage.c) to the Makefile and drop unused CPP define Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6482 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-05X60: use pnp_write_config() instead of custom functionSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6481 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-05X60: move ec version info code to log_ec_version()Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6480 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: assert audio mute before entering SuspendSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6479 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: log firmware versionSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6478 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: blink suspend LED during resumeSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6477 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: we have ACPI_RESUMESven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6476 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-04X60: deassert audio mute on bootSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6475 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01remove swp files accidently addedSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6474 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01X60: add dock code for Ultrabase X6Sven Schnelle
Move the old docking code from romstage.c to dock.c, and use that code both in romstage and SMM code. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6473 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-04-01ICH7: Fix register naming errorSven Schnelle
There's an off-by-one error in the ACPI GP_LVL declaration: it declares GL00 with a bit count of 6, and continues with GP07 afterwards. This should be GP06, as the first bitfield covers GP00-GP05. While at it, change it to GP00-GP05, as right now GL00 isn't used, and single bitfield are more usable here. Also adjust the Getac P470, as this is the only user of those defintions right now. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6471 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28Add support for Supermicro H8scm.Zheng Bao
It is AMD C32 + SR5650 + SP5100. It is created by svn copy amd/tilapia_fam10. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6466 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-28SP5100's code is based on SB700. Change the legacy sb700 of sb7xx_51xx.Zheng Bao
Since the SB700 has changed to sb7xx_51xx, change legacy name in other mainboard. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6463 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-21X60: Add notification for LID objectsSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6458 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-21X60: remove beep call from _Q26/_Q27Sven Schnelle
no need to trigger sound, the EC takes care of generating the annoying AC state beep if enabled in the sound mask. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6457 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-15X60: Clear EC events when wake GPE is triggeredSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6448 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14X60: LPC bus is LPCB, not LPCSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6446 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14X60: fix typo in dsdt.aslSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6445 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-14X60: Add _PRW/_PSW methods to LID/SLPB objectsSven Schnelle
This patch adds the required methods for enabling/disabling the LID and SLPB objects as wake source. On Thinkpads, the Fn key can (and is by the Vendor BIOS) programmed as Wake source, so let's do it the same way. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6444 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-08Enable mahogany_fam10 and Kino family 10h to run the SB HT link at the ↵Scott Duplichan
expected HT3 frequency and width by matching the BUID swap list to the production BIOS. In addition, the BUID swap list has been moved into the project-specific file romstage.c for the other 13 AMD family 10h projects as well. For projects using a desktop AMD family 10h processor, pasting in the mahogany_fam10 swap list will likely allow HT3 operation. This should be confirmed on real hardware before commiting any swap list change. A different swap list will be needed for server projects. For serengeti_cheetah_fam10, a reference BIOS swap list to try is: 0x00, 0x0A, 0x00, 0x06, 0xFF, 0x0A, 0x06, 0xFF. The patch makes these changes: 1) Remove the BUID swap list from ht_wrapper.c and put it in each of 15 romstage.c files where it is used (AMD family 10h projects). 2) Add a prototype to amdfam10.h. 3) Modify the swap list and test in real hardware for mahogany_fam10 and kino family 10h and confirm HT3 operation for the SB link. Abuild tested. Signed-off-by: Scott Duplichan <sc...@notabs.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6439 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-07X60: add thermal zone 1Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-07X60: add thermal zone 0Sven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6434 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-04Redo r6099 after copy&pasted code reintroduced DIMMx #definesPatrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6431 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-03Configure PCIe lanes on ms7135 as original BIOS does.jakllsch
Signed-off-by: <jakllsch@kollasch.net> Acked-by: <jakllsch@kollasch.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6428 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Fix some subsystemid statements in r6421Sylvain "ythier" Hitier
Signed-off-by: Sylvain "ythier" Hitier <sylvain.hitier@gmail.com> Acked-by: Sven Schnelle <svens@stackframe.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6425 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-03-01Use subsystem id from devicetree.cb instead of Kconfig and moveSven Schnelle
all boards to the new config scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6421 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-28Kino devicetree.cb SIO PNP devices were not matched up with theMarc Jones
actual SIO. This fixes the serial device being disabled during PNP init. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Scott Duplichan <scott@notabs.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6400 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Make AMD Fam10h CPU microcode updates optional in Expert modeXavi Drudis Ferran
Signed-off-by: Xavi Drudis Ferran <xdrudis@tinet.cat> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6385 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Following patch fills in the callbacks for PCIe x16 resets. This board uses ↵Rudolf Marek
GPM8,GPM9 as reset toggles. Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6384 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Correct error in ASRock E350M1 commit that breaks build for ASRock 939a785gmh.Scott Duplichan
Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6383 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-26Add support for the ASRock E350M1, an AMD family 14h Fusion board.Scott Duplichan
A video option rom must be added for UMA graphics support. It can be extracted from the supplied UEFI BIOS. ASRock E350M1 support is based on the AMD persimmon project. The major differences are SIO model and DIMM SDP addressing. With this coreboot and seabios, the board can boot DOS from a SATA drive and can boot WinPE from a USB flash drive. I was unable to get Windows setup to run. The board has a socketed SPI flash BIOS chip and a serial port header. The SIO is Nuvoton NCT5572D. Using coreboot's existing Winbond w83627hf is a good enough match to get the serial port and keyboard working. Signed-off-by: Scott Duplichan <scott@notabs.org> Acked-by: Peter Stuge <peter@stuge.se> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6382 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24Tyan/s2735 doesn't need to define its own hard_reset function anymore.Patrick Georgi
The southbridge already provides hard_reset. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6378 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-24git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6376 ↵Scott Duplichan
2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-21[i945] Add SPD adress mappingSven Schnelle
The current code works only with dual channel if Channel 0 uses SPD address 0x50/0x51, while the second channel has to use 0x52/0x53. For hardware that uses other addresses (like the ThinkPad X60) this means we get only one module running instead of both. This patch adds a second parameter to sdram_initialize, which is an array with 2 * DIMM_SOCKETS members. It should contain the SPD addresses for every single DIMM socket. If NULL is given as the second parameter, the code uses the old addressing scheme. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6374 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16Add ACPI code for Lenvo X60Sven Schnelle
It currently supports: - Sleepbutton - AC state - Battery state - Interrupt routing - Display Brightness control - Hotkeys Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6368 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-16Lenovo ThinkPad X60: Enable SMI handlerSven Schnelle
Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6366 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15Remove more files and lines mistakenly copied from Roda to X60Peter Stuge
Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6365 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15Remove ACPI mistakenly copied from Roda to ThinkPad X60Peter Stuge
It is incorrect, and will be replaced with proper ACPI for X60. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6364 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-15Remove Inagua Kconfig items for external VGA and AHCI binaries. These can be ↵Marc Jones
addded by the developer if needed. Fixes abuild issues. Signed-off-by: Marc Jones <marcj303@gmail.com> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6363 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Lenovo ThinkPad X60 / X60s SupportSven Schnelle
Adds support for Lenovo X60 series ThinkPads. So far, only X60s (Model 1703) has been tested. It's a basic patch without SMI and ACPI, as this makes it easier to review. SMI and ACPI patches will follow. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6360 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Fix Typo. (and why is that file, and some of its siblings per-board?)Patrick Georgi
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6353 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-02-14Add IBASE DB-FT1 and AMD Inagua motherboards. Patch 8 of 8.Frank Vibrans
This code provides support for IBASE Technology DB-FT1 (AMD code name Persimmon) and AMD Inagua platforms. It is dependent on all other patches in this set. Signed-off-by: Frank Vibrans <frank.vibrans@amd.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Marc Jones <marcj303@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6352 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-28rk886ex lacked EC_ACPIStefan Reinauer
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6306 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27Add new ec subdir for Embedded Controllers and common ACPI EC supportSven Schnelle
Adds a new src/ec subdir for embedded controllers (mostly found in laptops) and converts Getac P470 and Roda RK886EX to use the new ACPI EC instead of having their own copies of those functions. Signed-off-by: Sven Schnelle <svens@stackframe.org> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6304 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27SMM code on i945 platforms needs udelay()Peter Stuge
smm-y wasn't required before, because udelay.c used to be #included from various files in src/mainboard. Signed-off-by: Peter Stuge <peter@stuge.se> Acked-by: Patrick Georgi <patrick.georgi@secunet.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6303 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27Add a new CMOS variable which triggers activation of thePatrick Georgi
LPT port. With the CMOS variable set, LPT is found by SeaBIOS, with the variable reset, it's not. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-27oops. this is weird. CAR addresses should be specified in the socket and not inStefan Reinauer
the board. I thought we did this ages ago. Also push CAR BASE further down so it won't conflict with a 32mbit flash part. Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Acked-by: Stefan Reinauer <stefan.reinauer@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6299 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21Now bimini can boot linux to login.Zheng Bao
Note: 1. bimini_fam10/Kconfig: Set GENERATE_MP_TABLE in Kconfig. This will make sure the smp_write_config_table will run. Then intr_data will be written into 0xC00/0xC01. 2. bootblock: Use PCI_DEV(0, 0x14, 3) instead of pci_locate_device(PCI_ID(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SB800_LPC), 0). The pci_locate_device will cause the system crash. 3. fadt.c: Change fadt revision to 1. 3 will cause the linux hang. Why? 4. early_setup.c: pmio 0x65 has change its meaning. Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6288 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-21push ts5300 rom size to 1MB. In fact the flash part on thatStefan Reinauer
board is 2MB and the entry point is somewhere in the middle. quite weird setup http://www.embeddedarm.com/products/board-detail.php?product=TS-5300 We should probably wipe the board from the tree. It will not work anyways with current coreboot and the architecture is kind of obscure. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6287 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20Remove the code for debugging.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6281 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-20Features of Bimini board:Zheng Bao
RS785 SB800 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6278 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18remove the code which is not ready to release.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6264 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-18remove the code which is not ready to release.Zheng Bao
Signed-off-by: Zheng Bao <zheng.bao@amd.com> Acked-by: Zheng Bao <zheng.bao@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16Ooops lets see if this extra comment removal fixes this.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6257 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-16Trivial, cleanup of GPIO comments.Rudolf Marek
Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Acked-by: Rudolf Marek <r.marek@assembler.cz> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6256 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14Improved GPIO setup for roda/rk886ex, and some documentationPatrick Georgi
on what the GPIOs are used for. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6254 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-14Allow coreboot to initialize CMOS if checksum is invalid.Patrick Georgi
If a file "cmos.default", type "cmos default"(0xaa) is in CBFS, a wrong checksum leads to coreboot rewriting the first 128 bytes (except for clock data) with the data in cmos.default, then reboots the system so every component of coreboot works with the same set of values. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6253 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-13Default to CRT on Kontron/986lcd-m. "default display" doesn't alwaysPatrick Georgi
select the right output device. Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com> Acked-by: Joseph Smith <joe@settoplinux.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6252 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-06Various Nokia IP530 fixes.Marc Bertens
- Correct default ROM image size for this board (512KB is correct). - devicetree.cb: Add AUX I/O config (mainly GPIO settings). This allows you to control the LEDs in the front panel and JP900/JP901 can be read. - irq_tables.c: Rework PIRQ table to make more onboard devices work. Also, avoid IRQ9. - mainboard.c: Drop unneeded functions, everything is done in devicetree.cb. Signed-off-by: Marc Bertens <mbertens@xs4all.nl> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6247 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-04Trivial: use the IO_APIC_ADDR constant defined in ioapic.h, and spell checkKerry She
Signed-off-by: Kerry She <kerry.she@amd.com> Acked-by: Kerry She <kerry.she@amd.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6238 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD SB800: Drop component prefix from filenames.Uwe Hermann
We did the same with other chipsets in r6150. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6236 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD Bimini: Use mptable_init() in mptable.c.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6234 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD Bimini: Small fixes, and updates to recent trunk conventions.Uwe Hermann
- Move CACHE_AS_RAM_ADDRESS_DEBUG #define to Kconfig, where it was renamed to HAVE_DEBUG_CAR in r5898. - Move QRANK_DIMM_SUPPORT to Kconfig, see r6028. - Drop obsolete/unused COMPRESS, see r6145. - Drop obsolete SET_NB_CFG_54, see r6086. - Move SET_FIDVID/SET_FIDVID_CORE_RANGE to Kconfig, see r6077. Actually, the default for SET_FIDVID_CORE_RANGE is 0, so drop it. - Rename some GENERATE_* options to HAVE_*, see r6027. - Drop "select CACHE_AS_RAM", this is now set in the socket, see r6151. - Drop ACPI_SSDTX_NUM, the global default is 0 already. - Random whitespace and coding style fixes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6233 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01AMD Bimini: Drop duplicate ASL files as we did for other boards.Uwe Hermann
Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6232 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2011-01-01Add support for the AMD Bimini eval mainboard.Kerry She
Signed-off-by: Kerry She <Kerry.she@amd.com> Acked-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6231 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-29-Change the remaining GLIU1 port 5 register names from VIP (Video Input Port)Nils Jacobs
to FG (FooGlue). As the GX2 has no VIP port. -Change the Memmory setup MSR register names so they correspond better to the databook. (Part1) This is less confusing for beginners. -Add a MSR printing function to northbridge.c like in the Geode LX code. -Remove the AES register names.(GX2 has no AES registers) -Delete some unused code. -Clean up GX2 northbridge code to match Geode LX code. -Add missing copyright header to northbridge.c. -Move hardcoded IRQ defining from northbridge.c to irq_tables.c . Signed-off-by: Nils Jacobs <njacobs8@hetnet.nl> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6221 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-27Fix most CONFIG_DEBUG_RAM_SETUP issues. Stefan Reinauer
The intel/xe7501devkit is still broken, I think the (romcc) image is too big to fit in the bootblock if CONFIG_DEBUG_RAM_SETUP is enabled. It would make sense to convert all CPU_INTEL_SOCKET_MPGA604 to CAR, but I have no hardware to test. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6215 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26All the values should stay untouched or be set automatically by the resourceStefan Reinauer
allocator. If that does not work out, they should be set in the code. Setting them in Kconfig is the worst possible thing to do. Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Stefan Reinauer <stepan@coreboot.org> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6213 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-26Random fixes for TI pci1x2x / Nokia IP530 / others.Uwe Hermann
- nokia/ip530/devicetree.cb, southbridge/ti/pci1x2x/pci1x2x.c: - Fix SMSC FDC37B787 name (was a typo). - Disable PS/2 keyboard/mouse LDN, the IP530 doesn't have either. - Fix typo: s/PCI_DEVICE_ID_TI_1420/PCI_DEVICE_ID_TI_1520/. - All of these are confirmed by Marc Bertens on IRC. - Fix a few CHIP_NAME HP board names. - Random whitespace and coding-style fixes. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6212 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-25Nokia IP530: Add missing "select SDRAMPWR_4DIMM".Uwe Hermann
This is needed for all Intel 440BX boards with 4 DIMM slots (such as this one). Thanks Marc Bertens <mbertens@xs4all.nl> for bringing up the issue and for the success report for this fix on IRC. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6207 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19The same mechanisms are used for normal and fallback images. Stefan Reinauer
Hence drop the FALLBACK_ prefix Signed-off-by: Stefan Reinauer <stepan@coreboot.org> Acked-by: Patrick Georgi <patrick@georgi-clan.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6204 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-19ASUS M2N-E: Enable PCI-E x16 slot.Uwe Hermann
Simple devicetree.cb fix, tested on hardware using a PCI-E x16 graphics card. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6203 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
2010-12-18SMM for AMD K8 Part 1/2Stefan Reinauer
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6201 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 03:55:47 +0000