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2023-02-08drivers/ocp, mb/ocp/deltalake: move get_loglevel_from_vpd functionJohnny Lin
Move get_loglevel_from_vpd from mb/ocp/deltalake to driver drivers/ocp/vpd/loglevel_vpd.c. Change-Id: I70af1051f63c527fd8150f5ecbe4765b4aaacd20 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71936 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-02-08mb/intel/mtlrvp: Enable PCIE Advanced Error ReportingHarsha B R
This patch enables PCI Express Advanced Error Reporting Capability for WWAN, WLAN, and SSD root ports. On enabling PCIE_RP_AER, PCIE device will automatically report (if any error) about the error nature to the corresponding PCIe root port. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Iab8619818e2219b41287b895513eb04b0464401e Reviewed-on: https://review.coreboot.org/c/coreboot/+/72874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-08mb/google/brya: Add usb_lpm_incapable for Type-C port with PS8815Ron Lee
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. This patch add usb_lpm_incapable config for the following variants with PS8815 retimer: - kinox MLB: C0 - volmar DB: C1 - osiris MLB: C0/C1 - mithrax DB: C1 - felwinter DB: C1 - taeko DB: C1 - gimble DB: C1 - gimble4es DB: C1 - taniks DB: C1 - marasov DB: C2 - gaelin MLB: C0/C1 - skolas DB: C1 - skolas4es DB: C1 - brya0 DB: C1 BUG=b:253402457 TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u2 disabled Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557 Signed-off-by: Ron Lee <ron.lee@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-02-08mb/google/geralt: Add support for VM18 in regulator.cSen Chu
Add regulator VM18 support to supply power for BOE_TV110C9M_LL0. BUG=b:244208960 TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt. Change-Id: I13bafbe10a18a18e253575fd107c9b415f28ef01 Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72748 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/google/corsola: Use function to get regulator IDsLiju-Clr Chen
There might be inconsistence between regulator_id[] and `enum mtk_regulator` when we need to add new regulator IDs for Geralt. Therefore, we implement get_mt6366_regulator_id() to get regulator IDs. BUG=None TEST=build pass. Change-Id: I3d28ebf2affe4e9464b1a7c1fb2bbb9e31d64a5e Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72838 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-02-08mb/amd/mayan: update EC FW offset in spiromRitul Guru
update EC FW offset location in spirom to 0x81000 For mayan board EC FW is located at offset 0x81000 location, 0th location contains pointer to this EC FW location. Change-Id: I63c797e12ed131e8411c11379f4db9bcc29b49a2 Signed-off-by: Ritul Guru <ritul.bits@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-02-08mb/intel/mtlrvp: Add ACPI configuration for USB2/3 portsHarsha B R
This patch adds ACPI configuration for USB2/3 ports for mtlrvp as per schematics. This helps in generating corresponding ACPI code at runtime that includes port information. BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP. Connect USB device and check if corresponding enumeration of USB device (14.0) is observed on executing lspci. 00:14.0 USB controller: Intel Corporation Device 7e7d (rev 01) 00:14.1 USB controller: Intel Corporation Device 7e7e (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie150247661322e3944be15dc70f66033266d8aac Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72787 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Describe mainboard configuration for BB RetimerHarsha B R
This patch describes BB retimer for tcss_dma0 and tcss_dma1 with respect to GPP_B21 as per schematics. +--------------+------------+ | tbt_pcie_rp0 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp1 | tcss_dma0 | +--------------+------------+ | tbt_pcie_rp2 | tcss_dma1 | +--------------+------------+ | tbt_pcie_rp3 | tcss_dma1 | +--------------+------------+ BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of tbt_pcie_rp as part of lspci. 00:07.0 PCI bridge: Intel Corporation Device 7ec4 00:07.1 PCI bridge: Intel Corporation Device 7ec5 00:07.2 PCI bridge: Intel Corporation Device 7ec6 00:07.3 PCI bridge: Intel Corporation Device 7ec7 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie1a0026b064aa4f7fcd27e75c0b0d052ec620dcc Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72786 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Describe TCSS USB portsHarsha B R
This patch describes the TCSS USB ports for mtlrvp as per schematics. This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below, tcss_usb3_port1: USB3 Type-C Port C0 tcss_usb3_port2: USB3 Type-C Port C1 tcss_usb3_port3: USB3 Type-C Port C2 tcss_usb3_port4: USB3 Type-C Port C3 BUG=b:224325352 BRANCH=None TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C ports as part of cbmem -c. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72785 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-08mb/intel/mtlrvp: Enable WWAN ACPIHarsha B R
This patch enables FM350GL 5G WWAN support for mtlrvp. BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module 00:1c.6 is enumerated as part of lspci and cbmem -c in AP console. Also verify generation of PXSX Device as part of SSDT. Able to connect WiFi and access internet. cbmem -c: \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) SSDT: Scope (\_SB.PCI0.RP07) { Device (PXSX) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72779 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-08mb/samsung: Enable VBOOT_VBNV_FLASHYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for samsung boards lumpy and stumpy. 0x8000 unused flash space is allocated for RW_NVRAM. Previously BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES was selected for CPU_INTEL_HASWELL, CPU_INTEL_MODEL_{2065X,206AX} and others (see [2]). However, there seems to be no particular reason on those platforms. We've dropped the config for haswell. Now drop it for CPU_INTEL_MODEL_{2065X,206AX}, so that VBOOT_VBNV_FLASH can be enabled. [1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1 [2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08 ("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config") BUG=b:235293589 TEST=./util/abuild/abuild -a -t SAMSUNG_LUMPY -x Change-Id: I833edd4f7a328b21e81c971ba8a9aec0aad7d3d3 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-02-07mb/google/brya: Create constitution variantMorris Hsu
Create the constitution variant of the brask reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:267539938 TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CONSTITUTION Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72730 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07mb/intel/mtlrvp: Enable GSPI interfaceHarsha B R
This patch enables GSPI [1] interface for mtlrvp based on mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223) SPI[0].Mode = 0 SPI[0].DefaultCsOutput = 0 SPI[0].CsMode = 0 SPI[0].CsState = 0 SPI[1].Mode = 1 SPI[1].DefaultCsOutput = 0 SPI[1].CsMode = 0 SPI[1].CsState = 0 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07mb/intel/mtlrvp: Enable PCIe port 8 for WLANHarsha B R
This patch enables PCIe port for WLAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets is enumerated as part of lspci in AP console. ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE Advanced Modem (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07mb/intel/mtlrvp: Enable EC_GOOGLE_CHROMEEC_SWITCHESHarsha B R
This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for MTL_CHROME_EC which helps in mode switch using dut-control power_state:rec. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command dut-control power_state:rec puts the DUT to recovery mode. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07mb/intel/mtlrvp: Enable PCIe port 7 for WWANHarsha B R
This patch enables PCIe port for WWAN as per mtlrvp schematics BUG=b:224325352 BRANCH=None TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module gets enumerated with cbmem -c. \_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3) \_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72777 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-07mb/intel/mtlrvp: Enable ACPI support for Type-C portsHarsha B R
This patch adds ACPI support for Type-C ports. BUG=b:224325352 BRANCH=None Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding entry, \_SB.PCI0.PMC.MUX.CON0 under Device (CON0) \_SB.PCI0.PMC.MUX.CON1 under Device (CON1) \_SB.PCI0.PMC.MUX.CON2 under Device (CON2) \_SB.PCI0.PMC.MUX.CON3 under Device (CON3) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-07tree: Drop repeated wordsAlexander Goncharov
Found-by: linter Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b Signed-off-by: Alexander Goncharov <chat@joursoir.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795 Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-06mb/google/brya/var/kano: Update ELAN TS delay time to 150msDavid Wu
ELAN updated the datasheet, the HID/I2C protocol's T3 delay time is 150ms now. Modify the kano's delay time to follow the requiremnet. BUG=b:247944006 TEST=Manually checked touchscreen works after reboot and suspend. Change-Id: I42a7737060a82c0b27717f1510b8ec64abd1465a Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paz Zcharya <pazz@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-06soc/amd/mendocino: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Mendocino SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/cezanne: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Cezanne SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/picasso: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Picasso SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2023-02-06soc/amd/stoneyridge: remove LIDS field from global NVSFelix Held
Since the LIDS field is only used in the ACPI code and not in the C code of any mainboard using the Stoneyridge SoC, remove it form the global NVS and add an ACPI object for this in the DSDT of the mainboards that use it in their ACPI code. Eventually the LIDS object should probably be moved to the EC's ACPI code, but that's out of scope for this patch. TEST=google/liara doesn't show ACPI errors in Linux' dmesg Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-02-05mb/intel/mtlrvp: Add chip configuration for I2C devicesHarsha B R
This patch adds below chip configuration for I2C devices for mtlrvp. +-----------+--------------------+-------------+ | INTERFACE | PCI Number (B:D:F) | DEVICE | +-----------+--------------------+-------------+ | I2C0 | 0:0x15:0 | CAM1 | +-----------+--------------------+-------------+ | I2C1 | 0:0x15:1 | CAM0 | +-----------+--------------------+-------------+ | I2C2 | 0:0x15:2 | NC | +-----------+--------------------+-------------+ | I2C3 | 0:0x15:3 | HID | +-----------+--------------------+-------------+ | I2C4 | 0:0x15:4 | NC | +-----------+--------------------+-------------+ | I2C5 | 0:0x15:5 | NC | +-----------+--------------------+-------------+ BUG=b:224325352 BRANCH=None TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus enumeration through lspci. 00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01) 00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01) 00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ia5964472be902041f961187c0072a89055badd4f Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-05mb/intel/mtlrvp: Override display configurationHarsha B R
This patch enables display configuration for mtlrvp. The change follows mtlrvp schematics. BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump. Also verify display over eDP and HDMI. DdiPortAConfig : 0x1 DdiPortBConfig : 0x0 DdiPortAHpd : 0x0 DdiPortBHpd : 0x1 DdiPortCHpd : 0x0 DdiPort1Hpd : 0x0 DdiPort2Hpd : 0x0 DdiPort3Hpd : 0x0 DdiPort4Hpd : 0x0 DdiPortADdc : 0x0 DdiPortBDdc : 0x1 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-02-05mb/intel/mtlrvp: Remove GPP_A12 for chrome platformHarsha B R
This patch removes the configuration of GPP_A12 for mtlrvp. Garfield Peak (WLAN) doesn't use GPP_A12 for WAKE_N. Configuring GPP_A12 pin prevents system entering G3 (reboots) on issuing shutdown -h now. Hence configuring GPP_A12 as PAD_NC. BUG=b:224325352 BRANCH=None TEST=On issuing 'shutdown -h now' system enters G3 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com>
2023-02-05mb/google/brya/var/omnigul: Enable Cnvi BT Audio Offload featureJamie Chen
1. Enable Cnvi BT Audio Offload feature and also configure the virtual GPIO for CNVi Bluetooth I2S pads. 2. According to the SOC_GPIO_Table_20230116, Change GPIO GPP_D15, GPP_D16 to NC. BUG=b:264834572 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I4901c8cd660f2d47018e4cccdb67f666f0800423 Signed-off-by: Jamie chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72035 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-05mb/google/brya/var/omnigul: Add variant specific devicetreeJamie Chen
This variant was added without a devicetree, so add the board specific devicetree according to schematic_20230110. BUG=b:263060849 BRANCH=None TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-02-05mb/google/nissa/var/craask: Modify clkreq to clksrc mappingRen Kuo
NVMe PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware design, Due to inconsistency between PMC firmware and FSP, we need to set clk_src to clk_req number, not same as hardware mapping in coreboot. Then swap correct setting to clk_src=1,clk_req=2 in mFIT. BUG=b:265720813 TEST=build firmware and veirfy suspend function on DUT. Cq-Depend: chrome-internal:5351299 Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72051 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-05mb/google/brya/var/marasov: Turn off camera power during S0ixFrank Chu
Turn off camera power during S0ix to improve power consumption. BUG=b:265754302 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ie2b300783adfc1cab30bc897d086a3674436724a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-05mb/google/skyrim/var/frostflow: Override SPI flash bus speedFrank Wu
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz starting the board version of the current phase. BUG=b:260127676 TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed. Observe that the boot time improved by 100 ms compared to 66 MHz SPI flash bus speed. firmware log: SPI fast read speed: 100 MHz At 66 MHz: Total Time: 1,563,384 At 100 MHz: Total Time: 1,462,570 Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-02-04soc/amd/phoenix/chipset.cb: update USB portsFelix Held
Not exactly sure about the usb4_xhci controllers, but for now I assume those will behave like any other XHCI controller. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I22384f58e245a1486793831d29d22e9c618f646c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: add remaining PCI devicesFelix Held
The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and PPR #57396 Rev 1.54 were used as a reference. Some devices will need to have ops added in future patches. Since the xhci_2 device isn't there any more, also drop it from the mainboard devicetrees. The actual USB port configuration on xhci_0 and xhci_1 is updated in the next patch. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-02-04soc/amd/phoenix/chipset.cb: rename GPP bridges on device 2Felix Held
Now that the PCIe ports on device 1 are added, rename the aliases for the PCIe ports on device 2 to have a common naming scheme. For phoenix the device alias names are based on the device and function number the bridge is connected to. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/google/skyrim: Update ASPM settings for the NVMe deviceMartin Roth
This enables L1.2 for the SSD port. link_hotplug is unused on Mendocino, so remove it while I'm here, just as code cleanup. This has no functional difference. Enabling L1.2 on other devices currently causes problems. Debug is ongoing. BUG=b:265890321 TEST=Build & boot, look at states enabled in lspci. Test device functionality. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-04mb/google/rex: Use OV13B10 sensor for Proto 1 SKUsSubrata Banik
This patch drops the WFC sensor OV8856 (reused from the Brya chassis) support for Rex and added support for Rex specific UFC sensor OV13B10. BUG=b:267264348 TEST=WFC MIPI cameras have been enabled using google/rex Proto 1. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic785b82db4368f40d91921f29c218cf417938541 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-04Revert "UPSTREAM: mb/google/rex: Enable SaGv"Subrata Banik
Enabling `SaGv` along with FSP v2473 is causing blank display issue. Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake. BUG=b:267446159 TEST=Able to see ChromeOS UI in consecutive boot. This reverts commit cbca81c5946384843197c08401c4266f45fef4a2. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/*: Replace SNB PCI devices with references from chipset.cbArthur Heymans
Removing default on/off from mainboard devicetrees is left as a follow-up. Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-02-04mb/google/skyrim: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:266696987 BRANCH=None TEST=Observe kernel ec panic handler run when ec panics Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-04mb/starlabs/starbook/adl: Enable HPD GPIOSean Rhodes
Enable the HPD GPIO so that the USB-C port can be used for DisplayPort. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72431 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-04mb/intel/mtlrvp: Enable CNVi BT Core and WifiHarsha B R
This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp schematics. 1. Enable CNVi BT Core in device tree 2. Enable CNVi Wifi (pci 14.3) device in device tree BUG=b:224325352 BRANCH=None TEST=Able to observe corresponding UPD configuration with FSP dump and able to boot mtlrvp (LP5/DDR5) to ChromeOS. CNVi Mode = 1 Wi-Fi Core = 1 BT Core = 1 BT Audio Offload = 0 BT Interface = 1 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03soc/intel/apl: Move cpu cluster to chipset.cbArthur Heymans
Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-02-03mb/google/brya0,skolas4es,skolas: disable Tccold HandshakeSelma Bensaid
The patch disables Tccold Handshake to prevent possible display flicker issue for skolas board. Please refer to Intel doc#723158 for more information. BUG=b:221461379 BRANCH=firmware-brya-14505.B TEST=Boot to OS on Skolas, verify upd setting. Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856 Signed-off-by: Selma Bensaid <selma.bensaid@intel.com> Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68636 Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-03mb/google/nissa/var/craask: Add DPTF settings for 15W CPURen Kuo
Add ADL-N 15W CPU thermal settings. BUG=b:265101768 TEST=emerge-nissa coreboot Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71860 Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Reka Norman <rekanorman@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-03mb/google/rex: update touchscreen report EN pin settingIvy Jian
Removed workaround since the latest schematics fixed. Power Sequencing of ELAN6918 (in ACPI) after this patch `POWER enabled -> RESET deasserted -> Report EN enabled` BUG=b:247029304 TEST=Verified ELAN touch panel is working as expected after booting Google/rex device to ChromeOS. Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-02-02mb/google/dedede/var/dibbi: Update devicetree and GPIO tableLiam Flaherty
Create overridetree and GPIO config based on latest schematic: 1. Update PCIe ports 2. Update USB ports 3. Remove unused I2Cs 4. Remove unused peripherals (SD card, eDP, speakers) 5. Add LAN 6. Thermal policy for updated temp sensors BUG=b:260934185, b:260934719 BRANCH=dedede TEST=build Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe Signed-off-by: Liam Flaherty <liamflaherty@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882 Reviewed-by: Adam Mills <adamjmills@google.com> Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02drv/i2c/ptn3460: Use PTN_EDID_LEN instead of constantJan Samek
Contents of the EDID are passed by a reference to an array of length 0x80, for which the macro 'PTN_EDID_LEN' has already been around. This patch makes use of this macro within the driver and mainboard implementation utilizing it. BUG=none TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards. Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2023-02-02mb/google/brya: Skip locking for GPP_F14 GPIOMaulik Vaghela
This is regarding issues observed on multiple Brya and Nissa variant such as Skolas and Nivviks. Issue is that once coreboot sets GPE_EN bit for the GPIO pin and locks it, kernel is not able to change the control bit. Hence kernel is not able to control the IRQ on the pin when required. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") This patch skips the locking for GPP_F14 to allow kernel to configure it later during reboot or shutdown as required. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas and Brya board with the patch. Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-02mb/google/skolas: Skip locking for GPP_F14 GPIOMaulik Vaghela
There is an existing issue for skolas boards where board wakes up from shutdown immediately due to touchpad wake signal. This issue was root caused to the patch which was setting GPE_EN bits for the GPIOs before locking. Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking") Later issue was found to be with GPP_F14 configuration for skolas boards. While shutting down, kernel is not able to disable IRQ for touchpad due to GPE_EN register getting locked and it is preventing shutdown of the board. This patch skips the locking for GPP_F14 to allow kernel to configure it later. BUG=b:254064671 BRANCH=None TEST=Shutdown works on Skolas board with the patch. Nissa Bug: 234097956 Signed-off-by: Maulik Vaghela <maulikvaghela@google.com> Change-Id: I09cf1af1f5ab11b06073755374ee8a306984d557 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72426 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/brya/var/omnigul: Add memory configAmanda Huang
Configure the rcomp, dqs and dq tables based on the schematic. BUG=b:264340545 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Marx Wang <marx.wang@intel.com>
2023-02-01mb/google/brya/var/omnigul: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSJamie Chen
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Omnigul variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. BUG=b:263846075 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I90ae116ccccde48792aeafaa683c7420a95c9886 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72509 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/google/geralt: Add USB3 HUB reset funtion to bootblockBo-Chen Chen
After powering on the device, we need to pull USB3_HUB_RST_L up to enable USB3 Hub. TEST=boot kernel from USB ok BUG=b:264841530 Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/prodrive/atlas/data.vbt: Fix VBT lane countMaximilian Brune
Currently there is a problem, where two Displayports are not working. To be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working. Setting the lane count of the TCP0 and TCP1 to x1 works fine. Setting the lane count of the TCP0 and TCP1 to x2 does not work. Setting the lane count of the TCP0 and TCP1 to x4 does not work. The reason for that is currently unknown. This change sets the lane count of the TCP0 and TCP1 Port to x1 length in the VBT binary. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: I182b528275152bf5adcb01a56816afd65674aed3 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-01mb/intel/mtlrvp: Modify the print messageHarsha B R
This patch updates the print message to start with uppercase, 'board' to 'Board'. BUG=b:224325352 BRANCH=None TEST=Able to observe proper print message when invalid board id is configured. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae Reviewed-on: https://review.coreboot.org/c/coreboot/+/72638 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-31mb/google/skyrim/var/winterhold: Update DPTC settings for SMTEricKY Cheng
Follow thermal team's request on b/248086651 comment#27. Update the thermal table setting for each mode and the conditions of temperature switching. BUG=b:248086651 TEST=emerge-skyrim coreboot Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-01-31mb/amd: Include <gpio.h> instead of <soc/gpio.h>Elyes Haouas
<gpio.h> chain-include <soc/gpio.h>. Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-30src/mainboard: Remove unnecessary space after castsElyes Haouas
Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-01-30mb/siemens/mc_ehl3/gpio.c: Disable PSE GBE0 GPIOJan Samek
Since the PSE GBE0 MAC has been disabled on this board in commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0"), therefore disable the corresponding GPIOs as well. BUG=none TEST=Test link detection and IP assignment on the remaining ports (PSE GBE1 and PCH GBE0) of mc_ehl3. Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-30mb/*: Remove lapic from devicetreeArthur Heymans
The parallel mp code picks up lapics at runtime, so remove it from all devicetrees that use this codebase. Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-01-30mb/intel/mtlrvp: Add romstage and configure LP5 memory partsAshish Kumar Mishra
This patch adds initial romstage code and spd data for LP5 memory parts for MTL-RVP. This also configures memory based on the board id. Memory - x32 LPDDR5 Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B Board ID - 0b0000 - Empty spd hex file 0b0001 - DDR5 (Empty spd hex file) 0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B) BUG=b:224325352 TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com> Change-Id: I15b352eb246aed23da273e56490c7094eae9d176 Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-30mb/google/brya: Select USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFSSubrata Banik
This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for Google/Marasov variant which intends to achieve a unified AP firmware image across UFS and non-UFS skus. Note: Enabling this config would introduce an additional warm reset during the cold-reset scenarios due to the function disabling of the UFS controller as results we are expecting ~300ms higher boot time (which might not be user visible because `cbmem -t` can't include impacted boot time due to in-between resets). BUG=b:264838335 TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS during boot path. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-01-27mb/starlabs/starbook/adl: Fix the disable wireless CMOS optionSean Rhodes
The current CMOS option causes Linux to not boot, as the GRUB EFI loader will report an incorrect parameter. Update the CMOS option so that the corresponding UPD is changed when the wireless is set to disable, so that the root port for the wireless is also disabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I607d700319d6a58618ec95b3440e695c82dff196 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27mb/starlabs/starbook/adl: Make Type-C USB a standard portSean Rhodes
Change the Type-C USB 2.0 interface to a standard port, as the Type-C macro will not work in Linux (dmesg says the cable is faulty), This makes the port work reliably in Linux, tested with: * Manjaro 21 * Ubuntu 22.04 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-27drivers/i2c/ptn3460: Use cb_err in mb_adjust_cfgJan Samek
Return generic coreboot error codes from the mb_adjust_cfg callback used in mainboards instead of '-1' constant and a driver-specific success-indicating define. BUG=none TEST=Boards siemens/mc_apl{1,4,5,7} and siemens/mc_ehl3 build correctly. Change-Id: I5e0d4e67703db518ed239a845f43047f569b94ec Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-27mb/siemens/mc_apl1/var/mc_apl5: Enable early POSTJan Samek
Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. BUG=none TEST=Boot on mc_apl5 and observe that POST codes are displayed before DRAM training. Change-Id: I390e0ab09ca830637e7a991db77e994d6c358e75 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72386 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-26src/mb/prodrive/atlas: Add GPIOs for configurationMaximilian Brune
CLKREQ Pins are intentionally not configured, because there seems to be a current Issue with FSP, that causes pci devices to not work if CLKREQ Pins are configured by coreboot. The msi/ms7d25 mainboard seems to have a similar issue and the cause is also documented in it's gpio.c file. Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Change-Id: Iba35076af194de0e85de60ebc93d62fda24e9c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-01-26mb/starlabs/starbook/Kconfig: Move MAINBOARD_HAS_TPM2 to STARBOOK_SERIESElyes Haouas
Change-Id: I5f91ae1b5904405edd797b57fbeb46609301295c Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72434 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mainboard: Drop invalid `hyper_threading` optionAngel Pons
Drop the `hyper_threading` CMOS option from most boards, as it's most likely not working properly and causing problems. The main reasons to remove the option are: * The used enum is backwards (0 ---> Enable, 1 ---> Disable) * Platform/SoC code does not honor the `hyper_threading` option Also, remove the now-unused enum used by the `hyper_threading` option. Change-Id: Ia8980a951f4751bc2e1a5d0e88835f578259b256 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69523 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-01-25mb/starlabs/starbook/adl: Enable pin widget 0x18Sean Rhodes
Enable pin 0x18 which is used for the 3.5mm combo jack microphone detection. Also, disable 0x17 as it is not used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I05856627c073acaff49ea1ddc048a49a74b6268f Reviewed-on: https://review.coreboot.org/c/coreboot/+/71718 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/starlabs/starbook/adl: Change HDA verb hex values to lower caseSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I6a5c54ac46840fc1e03eb15b9ae2ddc34172ec08 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72011 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/prodrive/atlas: Enable audio outputLean Sheng Tan
Before, the Intel HDA PCIe device was showing up in the lspci tool, but Audio wasn't working. This patch enables the corresponding FSP-M settings to make it work. Tested on Prodrive Atlas with Themis carrier board on Windows 10 and Linux 6.1.0-rc3. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I144618c453c1e6a3e759afc7532a4ac4a71814c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72385 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-01-25mb/prodrive/atlas: Disable SaGv by defaultLean Sheng Tan
Customer needs SaGv to be disabled by default. Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com> Change-Id: I8454c267dcc12d2ef7de7bd23296a17294f058a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-01-25mb/google/skyrim/baseboard/devicetree: enable mp2 deviceFelix Held
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. An equivalent change was verified on Chausie. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I1076ccacc6f51bf195b8280a6df5ad1849771519 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72196 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-25mb/amd/chausie/devicetree: enable mp2 deviceFelix Held
The mp2 PCI device is still present when no mp2 firmware is loaded. When this device isn't explicitly enabled in the mainboard's devicetree, the chipset devicetree default of the device being disabled is used. This results in coreboot's resource allocator not allocating resources to the device and since the bridge doesn't have enough MMIO space reserved, the Linux kernel can't assign resources to it. To fix this problem, enable the mp2 device in the mainboard's devicetree so that it gets its resources assigned by coreboot. TEST=Fixes the resource allocation for the mp2 PCI device. dmesg output before the patch: [ 0.210616] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000 [ 0.210631] pci 0000:04:00.7: reg 0x18: [mem 0x00000000-0x000fffff] [ 0.210641] pci 0000:04:00.7: reg 0x24: [mem 0x00000000-0x00001fff] [ 0.210649] pci 0000:04:00.7: enabling Extended Tags [ 0.240570] pci 0000:04:00.7: BAR 2: no space for [mem size 0x00100000] [ 0.240572] pci 0000:04:00.7: BAR 2: failed to assign [mem size 0x00100000] [ 0.240574] pci 0000:04:00.7: BAR 5: assigned [mem 0xd05c6000-0xd05c7fff] dmesg output after the patch: [ 0.210483] pci 0000:04:00.7: [1022:164a] type 00 class 0x118000 [ 0.210501] pci 0000:04:00.7: reg 0x18: [mem 0xd0500000-0xd05fffff] [ 0.210515] pci 0000:04:00.7: reg 0x24: [mem 0xd06c6000-0xd06c7fff] [ 0.210524] pci 0000:04:00.7: enabling Extended Tags Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I680ef9798f2f0e7e0646f0fd30bef58398b7bf19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72197 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-24mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I7cf52b966c1355c1f2bd4ae7c256fa4252a90666 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-01-22mb/amd/(birman|mayan): Update chromeos.fmd filesMartin Roth
Because the EFS is now fixed at 0xff020000, the ChromeOS RO region needs to be moved to the bottom of the ROM area to cover that space. The RO Region 6MiB, but you can't actually set 6MiB as RO - it's either 4 or 8MiB, so that's adjusted. To leave some room for the RW_LEGACY region, the two RW regions are adjusted to 3MiB each, which should be plenty. The GBB region had to be moved from the front of the WP_RO region to the end to avoid conflicting with the EFS, which needs to be inside the coreboot cbfs area. Also get rid of AMD_FWM_POSITION_INDEX. The FWM position is no longer needed. Signed-off-by: Martin Roth <gaumless@gmail.com> Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I683155ec0f4e6a62d862b9e2fa76af45f4cd5493 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-01-22mb/google/brya: Add lp5x memory parts for CrotaTerry Chen
Update the mem_parts_used.txt, generate Makefile.inc and dram_id.generated.txt for this part. DRAM Part Name ID to assign MT62F1G32D2DS-026 WT:B 4 (0100) K3KL8L80CM-MGCT 4 (0100) H58G56BK7BX068 4 (0100) BUG=b:259467147 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Change-Id: I204e871129a1b15d7c373d579e10a7b9ab6deabe Reviewed-on: https://review.coreboot.org/c/coreboot/+/71906 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-22Revert "mb/google/brya: Add EC mux device to brya0"Anil Kumar
This reverts commit 197d550d069f918698fa7cd8dda73e09fbfda30c. Reason for revert: breaks TBT and TypeC display on Brya0 Bug=265375098 Branch=firmware-brya-14505.B Test=Build and boot Skolas board with Brya0 image. Test TBT and TypeC display functionality. Change-Id: Ia0283b023949476e90edff7151d605fa36331bfd Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72081 Reviewed-by: Prashant Malani <pmalani@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-01-22mb/siemens/mc_apl1/var/mc_apl6: Enable early POSTJan Samek
Enable early POST code display on this variant using the common mc_apl1 baseboard functionality. BUG=none TEST=Boot on mc_apl6 and observe that POST codes are displayed before DRAM training. Change-Id: I2a52c241c383f8ebcf05052e9bc0ba13e63e3728 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-22mb/siemens/mc_apl1: Move POST logic to mainboard levelJan Samek
Move logic previously used only in the mc_apl2 variant to the mainboard level so that other variants can also make use of it without code duplication. This functionality on the mc_apl6 variant will be enabled in a follow-up patch. BUG=none TEST=Boot on siemens/mc_apl2 and observe that the POST codes are displayed before DRAM training. Change-Id: I762e328ad06c047d911ce1fc40f12a66cbd14e11 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-20mb/google/brya/acpi: Update NVPCF_FUNC_UPDATE_DYNAMIC_PARAMSTarun Tuli
1) Update location of TGP (MAGA) to Params2[15:0] 2) Add TPPA (value of 25W) Package: ... Case (0x02) { Local0 = Buffer (0x31) { 0x22, 0x05, 0x10, 0x1C, 0x01 } CreateWordField (Local0, 0x1D, MAGA) CreateWordField (Local0, 0x19, TPPA) CreateDWordField (Local0, 0x15, CEO0) MAGA = 0x50 TPPA = 0xC8 CEO0 = 0x0200 Return (Local0) } ... BUG=b:214581372 TEST=build and verify DSDT on device Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I69b80f4af2ecef6cf91034fc15fb6e8715eeca4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/69639 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/google/skyrim/var/frostflow: Update I2C setting for touchpadRex Chou
Update setting for touchpad I2C frequency and hold time to meet touchpad i2c SPEC. - Frequency: 380 ~ 400 kHz - hold time : 0.3 ~ 0.9 us BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: I2C0 (Touchpad): 393.7 kHz Hold time = 0.604 us Change-Id: Iecf4960a12aa56ac307fb9022e47c4e94a2551c1 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72114 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/siemens: Unify and clean lcd_panel.c coding styleJan Samek
With the addition of the mc_ehl3 board variant, a few points about commenting the code arose either from the review or during the implementation itself. This patch unifies structure of these files, which have a similar structure across more Siemens boards utilizing the PTN3460 eDP-to-LVDS bridge. BUG=none TEST=Check that images for the affected boards can be built. Change-Id: I59820362e1f87e296c5548b9c3cecba4d2710fe7 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72068 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-20mb/siemens/mc_ehl3: Add PTN3460 eDP-to-LVDS bridgeJan Samek
This board contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c, based upon a similar implementation in siemens/mc_apl7. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution, timing etc. Change-Id: Ib8a1a6f47053406e42554c2dd33684165d54be08 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-20mb/google/brya/var/gaelin: Add touch panel module settingMike Shih
1. Enable multiple GPIOs to support the touch panel. 2. Add I2C setting for touch panel. BUG=b:260818082, b:264812909 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot Change-Id: I2b805d1960f8b4e3e27f1af02f9c4d31f973288f Signed-off-by: Mike Shih <mikeshih@msi.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-01-20mb/intel/adlrvp/spd/Makefile.inc: Remove spaces before tabsElyes Haouas
Change-Id: I7bd29bab2c77da2ffe86167d54e87c9941355ea7 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-01-19mb/siemens/mc_ehl3: Use device/mmio.h instead of device/pci_ops.hJan Samek
The {read,write}{16,32}() functions used in this file come from the mmio.h header, so include it directly. BUG=none TEST=Read out the SD card controller (device 1a.1) PCI registers in Linux and check whether the values reflect the ones defined in this file. Change-Id: Iff7b55ef2bf98371b7d7d9114ccf3ebed64772a2 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72009 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-01-19intel/meteorlake: remove skip_mbp_hob SOC chip configKapil Porwal
Introduce at new config option CONFIG_FSP_PUBLISH_MBP_HOB to control the creation of ME_BIOS_PAYLOAD_HOB (MBP HOB) by FSP. This new option is hooked with `SkipMbpHob` UPD and is always disabled for ChromeOS platforms. This made skip_mbp_hob SOC chip config variable redundant which is also removed as part of this change. BUG=none TEST=Build and boot to Google/Rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: Iaba1ea29a92a63d2b287e1ccdea1a81ec07b9971 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19mb/google/skyrim/var/frostflow: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for frostflow in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:259007881, b:248221908 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Iaac331737c83ac7a4a1261c32151359e126a009e Reviewed-on: https://review.coreboot.org/c/coreboot/+/71926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-19tree: Drop Intel Ice Lake supportFelix Singer
Intel Ice Lake is unmaintained and the only user of this platform ever was the Intel CRB (Customer Reference Board). As it looks like, it was never ready for production as only engineering sample CPUIDs are supported. As announced in the 4.19 release notes, remove support for Intel Icelake code and move any maintenance on the 4.19 branch. This affects the following components and their related code: * Intel Ice Lake SoC * Intel Ice Lake CRB mainboard * Documentation Change-Id: Ia796d4dc217bbcc3bbd9522809ccff5a46938094 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72008 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-19mb/google/skyrim/var/markarth: set dxio_tx_vboost_enableFrank Wu
Turn on the dxio_tx_vboost_enable for markarth in coreboot. It needs to confirm the PCIe Signal Integrity after enabled. BUG=b:263534907, b:263216451 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I0798c1d9788e1911c2643bf387722b072aa79045 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-01-18mb/siemens/mc_ehl: Remove '_' from mc_ehl3 part numberJan Samek
Change MAINBOARD_PART_NUMBER Kconfig value for mc_ehl3 from "MC_EHL3" to "MC EHL3". Change-Id: Ie548607c5fb62faaed4921af714bc9b912e558a8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71775 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18mb/google/brya/var/marasov: Remove wlan RTD3 supportFrank Chu
Wlan power enable pin is changed from EN_PP3300_WLAN to SLP_SUS_L. Remove unused RTD3 driver. BUG=b:263448873 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I22448a8cb28ddadb93b114c096e364980feab6fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71693 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-18mb/google/skyrim: Add custom amdfw.cfg file to remove fwTPMMartin Roth
Skyrim doesn't use the firmware TPM, so remove the binary from the image. Note that because this was not used, removing it doesn't change the boot time. BUG=None TEST=Boot Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ia627b128c3346a2556c5306de7506519d1f2d70c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-17mb/google/skyrim: Set winterhold SPI fast read speed to 100MHzMartin Roth
Winterhold runs with the SPI fast read speed set to 100MHz. This decreases boot time by roughly 100ms. BUG=None TEST=Examine boot times. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I879e17fb0212910c7f90ba0e78ee16bea8b7cffa Reviewed-on: https://review.coreboot.org/c/coreboot/+/71888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-01-17mb/google/marasov: Skip MBP HOB creation to save boot timeSubrata Banik
This change skips the MBP HOB creation since coreboot doesn't use it and also helps to reduce the boot time by ~10msec. Boot time data: Before: * 955:returning from FspSiliconInit 897,278 (33,603) After: * 955:returning from FspSiliconInit 864,543 (21,273) Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia97cca560869fcfd55e65c2e1719cceec6f3ab7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71873 Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-01-17treewide: Fix old-style declarationsElyes Haouas
Replace old style declaration "const static" with "static const". This to enable "Wold-style-declaration" command option. Change-Id: I757632befed1854f422daaf4dfea58281b16e2f5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71841 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-01-17mb/starlabs/starbook/adl: Fix alignmentSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I4a3f871f2418438ef8e780a39935dfa2f86d8dbb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71895 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-01-16soc/amd/picasso/include/acpi: introduce and use ACPI_SCI_IRQ definitionFelix Held
The newer AMD SoCs define ACPI_SCI_IRQ in the SoC's acpi.h header file and use this definition in the mainboard code, so port this back to Picasso. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ib569747aa388d7953e79de747905fb52c2a05e74 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-01-16Revert "mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPD"Martin L Roth
This reverts commit 0e945a3426782e3c054a920ff8be3cd865f697ba. Reason for revert: Breaks build. Need to be merged after https://review.coreboot.org/c/coreboot/+/71715 which adds the register that this patch enables Signed-off-by: Martin L Roth <gaumless@gmail.com> Change-Id: I0ac3fb1a44e23e19c9711287f3a6a8402a6ffd79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71283 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-28 12:33:59 +0000