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2016-11-10mainboard/kontron/986lcd-m: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/kontron/986lcd-m. Change-Id: Ib47a4bb3580cb72ee51fb06c6faa6d2d1bd3a80c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17298 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/jetway/j7f2: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/jetway/j7f2. Change-Id: I37f59f74ac22fbf6e036cdb0515301e8dec400fb Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17296 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/iei/pm-lx2-800-r10: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/iei/pm-lx2-800-r10. Change-Id: I60e5b84141aa4998427c3ecaadf8fce1654b8210 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17295 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/ibase/mb899: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/ibase/mb899. Change-Id: Id5b460090db58e91b2c210d8633a69114a9c7f6b Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17294 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/getac/p470: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/getac/p470. Change-Id: Ifb81976ed7068f9d51edb0d297cd4a12265c51ec Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/17293 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/roda: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I4ce2705a8a07d0388bbdb459b63b59fc10a3aa39 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16929 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-09mainboard/google/reef: use common google smbios mainboard versionAaron Durbin
BUG=chromium:663243 Change-Id: Ic78a6aac11a8e842911245c59e8ced7ed2c4e27a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17291 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-09google/pyro: Update WACOM touchscreen ACPI _HIDJanice Li
WACOM request to add a new identifier `WCOMNTN2`, and use that for the board Pyro with all LCD combinations. BRANCH=master BUG=chrome-os-partner:58093 TEST=emerge-pyro vboot_reference coreboot chromeos-bootimage Signed-off-by: Janice Li <janice.li@quantatw.com> Change-Id: I95cf357efba958d7e864d2736d324e0aad70e307 Reviewed-on: https://review.coreboot.org/17257 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-08mb/lenovo/t400: use socket mPGA478MN instead of BGA945Arthur Heymans
The T400 features a socket P (mPGA478MN) and could potentially support model_6fx CPUs. Change-Id: I24f3356aa213c29011953daed31f46404e7a4d9d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17155 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08mb/gigabyte/ga-945gcm-s2l: add mainboardArthur Heymans
Startpoint was Intel d945gclf, which has same chipset and Gigabyte ga-g41m-es2l which has same Superio. What works and is tested: * PCI slot; * PCIe x16 slot with GPU (RADEON HD 2600 XT) and ADD2 DVI card; * onboard VGA output (only textmode implemented) with native graphic init; * 533, 800, 1067MHz FSB CPU (1333MHz is unsupported by the chipset); * serial output during and after boot. What does not work: * resume from suspend (does not work for d945gclf either). Quirks: * The Realtek ethernet card requires a reset which currently also hardcodes a MAC adress. This board was only tested with the SeaBIOS payload due to flash size constraints (512KB) and with GNU/Linux. Change-Id: I0ff9f193105facc1b276a791790e27eb4c275085 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17033 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-08intel/kblrvp: Update mainboard configurationNaresh G Solanki
Update devicetree.cb as per RVP3 mainboard. * Enable & configure PCIE ports, * Enable & configure USB ports, * Enable SSIC for WWAN, * Disable unused I2C ports, * Disable deep S5, * Disable HDA, * Update VR config, Updated gpio.h to disable pull down for SoC power button. Change-Id: I235a1d44dabef16ded2aaad13aef36ca57f37c8e Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17247 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07mainboard/intel/kblrvp: Remove unused code in dptf.aslNaresh G Solanki
Remove unused code from dptf.asl Change-Id: Icaa675fd1052367457d6e50d51d567e7db02fd42 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17249 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Configure usb over current pin & cdclockNaresh G Solanki
Configure overcurrent pins for various usb ports. Configure CdClock to 3. Change-Id: I57f1feb7e03c5bc7b125ea7e0735481fee91b6f6 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17251 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Enable Build with ChromeOSNaresh G Solanki
Enable building with ChromeOS support. Change-Id: I9fbb7422be205b304253478a70e334a63afab71f Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17250 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07mainboard/intel/kblrvp: Add Chrome EC switchNaresh G Solanki
Add Chrome EC switch to enable building with/without Chrome EC. Change-Id: Iaa8102cba0a454a24149d29f044a2284cd29e28b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17248 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-07intel/kunimitsu: Update DPTF settingsSumeet Pawnikar
After tuning the temperature values for optimal performance, this patch updates few DPTF settings for Kunimitsu board. BUG=None BRANCH=None TEST=Built and booted on Kunimitsu boards. Verified these updated DPTF settings with different workloads. Change-Id: Ic1c319262d80cc5cb29a8630af213822308f8bed Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/350223 Reviewed-on: https://review.coreboot.org/17069 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07google/lars: Update DPTF settingsSumeet Pawnikar
After tuning the temperature values for optimal performance, this patch updates few DPTF settings for lars boards. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on lars DVT boards. Verified these updated DPTF settings with different workloads. Change-Id: I4c040526c31c3263ed3a9b4cccff3b7a021cfcdb Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/338877 Reviewed-on: https://review.coreboot.org/17068 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07mainboard/google/reef: update DMIC related pins configurationSathyanarayana Nujella
CLK_B1(GPIO_80) and DATA_2(GPIO_83) pins needs to be configured as native mode to use them for DMIC record on other potential DMIC's. DMIC blobs configure the clocks. For stereo & quad channel record, both CLK_A1 and CLK_B1 are enabled. For mono channel record, only CLK_A1 is enabled. BUG=chrome-os-partner:56918 BRANCH=None TEST=During DMIC record, check CLK_B1 and DATA_2 lines Change-Id: I838009b85190de5360d593238e48c9593c1dc43a Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/17199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-11-07riscv: Unify SBI call implementations under arch/riscv/Jonathan Neuschäfer
Note that currently, traps are only handled by the trap handler installed in the bootblock. The romstage and ramstage don't override it. TEST=Booted emulation/spike-qemu and lowrisc/nexys4ddr with a linux payload. It worked as much as before (Linux didn't boot, but it made some successful SBI calls) Change-Id: Icce96ab3f41ae0f34bd86e30f9ff17c30317854e Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17057 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-07mb/lowrisc/nexys4ddr: Actually fix the UART clock setupJonathan Neuschäfer
Ron's code calculated the DLL and DLM registers of the 8250 UART, but that's the job of the UART driver. uart_input_clock_divider isn't needed anymore because the default value of 16 works. As a bonus, the baud rate can now be selected in Kconfig, instead of being hardcoded at 115200. TEST=Booted the board at 9600 and 115200 baud. Change-Id: I3d5e49568b798a6a6d944db1161def7d0a2d3b48 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/17188 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-11-04reef: tune trackpad i2c frequency to 400kHzAaron Durbin
This brings the frequency down to 400kHz which is spec for fast i2c. BUG=chrome-os-partner:58889 Change-Id: Ibc5f152e55ed618f18ac6425264f086b1f2d1ffa Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17215 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-04reef: tune tpm i2c frequency to 400kHzAaron Durbin
This brings the frequency down to 400kHz which is spec for fast i2c. BUG=chrome-os-partner:58889 Change-Id: I8689a062b5457aa431eaa7fb688a7170dad83fcf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17214 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-11-03mainboard/intel/kblrvp: Update onboard memory specific configsNaresh G Solanki
1. Update dq, dqs map & Rcomp strength & Rcomp target. 2. Fix rvp3.spd.hex byte 2 to 0x0F(JEDEC LPDDR3 memory type). Change-Id: I7efc3499b915d1e414cfe914830232993ef10ba2 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2016-11-03mainboard/intel/kblrvp: Update gpio.h, spd.h & mainboard.cNaresh G Solanki
1. Update gpio.h to set proper pad config for Kaby Lake RVP3. 2. Set spd index to zero. 3. Remove nhlt specific init. Change-Id: I41a312d92acd2c111465a5e8f1771158e3f33e2b Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17161 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03google/veyron*: change .ddrconfig from 14 to 3ZhengShunQian
There are two configs, sdram-lpddr3-hynix-2GB.inc and sdram-lpddr3-samsung-2GB-24EB.inc that use .ddrconfig = 14. Changing .ddrconfig from 14 to 3 improves performance especially on contiguous memory accesses. Comparing the .ddrconfig: - if .ddrconfig = 3, C RDRR RRRR RRRR RRRR RBBB CCCC CCCC C--- - if .ddrconfig = 14, C DRBB BRRR RRRR RRRR RRRR CCCC CCCC C--- where - R: indicates Row bits - B: indicates Bank bits - C: indicates Column bits - D: indicates Chip selects bits .ddrconfig = 3 has multiple banks switching which improves DDR timing. BUG=chrome-os-partner:57321 TEST=Boot from fievel and play video BRANCH=veyron Change-Id: Ifdcedc28e84429b8b79c7553b38b667631d29c09 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93882e4f2000d93c9dae5e6d4b2e1f4b7bc9489e Original-Change-Id: Ic98ebae48609a7604ec678b6bd14dd2b29b669c4 Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/404691 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17210 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-03google/veyron*: add DDR configs for new samsung DDRZhengShunQian
Add the new samsung DDR configs for all veyron except veyron_rialto: * K4E6E304EB-EGCE, ramid = 0010, 4GB * K4E8E324EB-EGCF, ramid = 1100, 2GB BRANCH=veyron BUG=none TEST=boot fievel board Change-Id: I747aa86f8c93174651a28face63b3386e22b23b3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5f55462e71bd481eda85af3d582cfe5b9873cc9c Original-Change-Id: I19123634c994f685683323f7d85cc4d35814e2ab Original-Signed-off-by: ZhengShunQian <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345748 Original-Commit-Queue: Ren Kuo <ren.kuo@quantatw.com> Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-(cherry-pick from cc990f27024255a326fd9fa9644deb28b01a31a7) Original-Reviewed-on: https://chromium-review.googlesource.com/404690 Original-Commit-Ready: Shunqian Zheng <zhengsq@rock-chips.com> Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17209 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: display: Do not allocate framebuffer in corebootLin Huang
framebuffer address is dynamically chosen by libpayload now, so there's no need to configure it in coreboot. CQ-DEPEND=CL:401402 BUG=chrome-os-partner:58675 BRANCH=none TEST=Boot from kevin, dev screen is visible Change-Id: I9f1e581d5c63b3579b26be22ce5c8d1e71679f6f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b3b6675420592c30e1e0abc8f8e9dd6ed5abd04c Original-Change-Id: I7e3162f24a4dc426fe4e10d74865cf0042c80db5 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/401401 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17109 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-02rockchip/rk3399: sdram: also prepare the index1 configurationLin Huang
To enable DDR Dynamic Voltage and Frequency Scaling (DVFS) we need to train alternative configurations first, so do the training and store the values. BUG=None BRANCH=None TEST=Boot from kevin Change-Id: I944a4b297a4ed6966893aa09553da88171307a42 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 94533ff3ba21bcb0ace00bedcf0cebb89a341be2 Original-Change-Id: I4a98bc0db5553d154fedb657e35b926a92aa80c7 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/386596 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17104 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-11-01google/eve: Add new boardDuncan Laurie
Add the eve board files using kabylake and FSP 2.0. BUG=chrome-os-partner:58666 TEST=build and boot on eve board Change-Id: I7ca71fe052608d710ee65d078df7af7b55d382bc Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17177 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-10-28riscv: add the lowrisc/nexys4ddr mainboardRonald G. Minnich
This was tested at the coreboot meeting in Berlin. The uart programming may still not be right but when used with the lowrisc bitstream for the board we were able to load and start linux, although it does not yet get far due to PTE version issues with lowrisc. Change-Id: Ia1de1a92762631c9d7bb3d41b04f95296144caa3 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17132 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-28lars/kunimitsu: Add other sensor in _ART for fan controlSumeet Pawnikar
This patch updates the _ART table with other external sensor TSR0 for Fan speed control on Skylake-U based Kunimitsu and Lars boards. Also, updates the temperature values in DPTF policy for better performance. BUG=chrome-os-partner:51025 BRANCH=firmware-glados-7820.B TEST=Built and booted on kunimitsu and lars EVT boards. Verified this updated _ART table on these boards with different workloads. Change-Id: Ib195910c5eb00e004e8b9bd50e266ade3c175be2 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://chromium-review.googlesource.com/332349 Reviewed-on: https://review.coreboot.org/17066 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-28mainboard/google/reef: allow variants to override NHLT OEM stringsAaron Durbin
In certain cases a board variant may need to override the NHLT OEM strings in the main NHLT table. Therefore, provide that path. BUG=chrome-os-partner:56918 Change-Id: I57cc4fd3665698e41ceebb1949180f86bb60b61f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17167 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
2016-10-28mainboard/google/reef: update comment for DMIC config usageAaron Durbin
Going forward GPIO_17 is used to determine the configuration of the board w.r.t. the number of DMICs on the board. BUG=chrome-os-partner:56918 Change-Id: I03edb880e0649977030c1b87219ebebac631a519 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17163 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-28pcengines/apu1: Add RS485 configurationKyösti Mälkki
In RS485 mode RTS line acts as a transceiver direction control. The datasheet is not very clear about the polarity but register setting here is tested to drive nRTS line high when transmitting. Also note revision of B of the super-IO has errata and 8N1 setting does not work properly, you would need revision C of the chip assembled to fix this. Change-Id: I705fe0c5a5f8369b0a9358a64c74500238b5c4ba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14998 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-10-27mainboard/google/reef: drop disabling periodic training for micronAaron Durbin
In anticipation of getting fixed material remove the disabling of periodic training for MT53B512M32D2NP and MT53B256M32D1NP. BUG=chrome-os-partner:59003 Change-Id: Iaadaa979d85cab78dda527db7480420af02fd832 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17130 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-27mainboard/google/reef: clarify memory part number detailsAaron Durbin
Explain the reasoning for the part_num strings used in the memory SKU table explaining the necessity of keeping mosys in sync with the strings used. It's possible that actual part numbers could change as the higher speed material gets cheaper, for example. BUG=chrome-os-partner:58966 Change-Id: If895e52791dc56e283261b3438106116b8b2ea05 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/17129 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-27skylake: Use COMMON_FADTDuncan Laurie
Remove the FADT from the individual mainboards and select and use COMMON_FADT in the SOC instead. Set the ACPI revision to 5. Change-Id: Ieb87c467c71bc125f80c7d941486c2fbc9cd4020 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17138 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-26google/reef/variants/pyro: Use WCOM Touchscreen driverFurquan Shaikh
BUG=chrome-os-partner:57846 Change-Id: Ibd3ef8cebcf99ee2186dfed98b04373dd17e798e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17093 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-10-26nb/gm45/gma.c: Remove writes to DP, FDI registersArthur Heymans
Those registers are only used on more recent Intel platforms featuring a PCH. The DP registers on G4X hardware are at a different offset. Change-Id: Ib49e54d4e7d6595dc09fb1be35ac8178b80c7f71 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17110 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-25mb/ga-g41m-es2l: remove unneeded IGD IRQ setting in ACPIArthur Heymans
According to: "Intel ® 4 Series Chipset Family datasheet" the IGD only has 1 IRQ pin. Change-Id: I974f002f5a213056f4593a1eab10772527bb241d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17098 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-25mainboard/intel/kblrvp: Initial commit for Intel Kaby Lake RVP3Naresh G Solanki
Add support for Kaby Lake RVP3. Use kunimitsu at commit 028200f as base. Kabylake RVP3 is based on Kabylake-Y with onboard Dual Channel LPDDR3 DIMM. * Update board name to kblrvp * Remove fsp 1.1 specific code( As Kabylake uses fsp2.0) * Remove board id function. * Remove unused spd & add rvp3 spd file. This is an initial commit does not have full support to boot. Will add more CLs to boot Chrome OS with depthcharge. Change-Id: Id8e32c5b93fc32ba84278c5c5da8f8e30c201bea Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17032 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25google/oak: Add derivative board HanaYidi Lin
CQ-DEPEND=CL:379684 BUG=chrome-os-partner:58064 TEST=verified on hana rev0 Change-Id: Icd076dcaf07a97f3b83b428b9619e8a4dafe744d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7c483951a0dcd419735fffb79e6187f9ca3b08a8 Original-Change-Id: I9d886abf15931496ac61e8fd38d7fd306f2a1bf7 Original-Signed-off-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/379504 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Philip Chen <philipchen@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17107 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25rockchip/rk3399: gru/kevin: drop unused sdram configsLin Huang
There are some sdram configurations that are no longer used. Drop them. BUG=None BRANCH=None TEST=None Change-Id: Ib6d2d58c3071147a3095bc1ed7fa7b02c748e1a5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 111d375005ec6a3b91e47acdd676e8f1644c931c Original-Change-Id: I5f9278093f02e785b2894faa8e8cf09ecec20325 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/399122 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17103 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25rockchip/rk3399: reset system if DDR init failsLin Huang
We found sdram may fail in pctl_cfg(), so we check the status in this function. If it exceeds 100ms still in this function, we will restart the system. We also found there are rare chances DDR training fails, so also restart system in that case. BUG=chrome-os-partner:57988 BRANCH=None TEST=coreboot resets on failure and eventually the system comes up Change-Id: Icc0688da028a8f4f81eafe36bbaa79fdf2bcea74 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 89e45f8352f62e19a203316330aba14ccc5c8b11 Original-Change-Id: If4e78983abcfdfe1e0e26847448d86169e598700 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/397439 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/17045 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-25mb/emulation: Select QEMU-i440fx by defaultJonathan Neuschäfer
It's a better default than QEMU-armv7, which is currently the default board when coreboot is configured for the first time, because most coreboot development targets x86. With this patch, the minimal steps to coreboot+SeaBIOS booting in QEMU become: git clone https://review.coreboot.org/coreboot.git && cd coreboot make crossgcc-x86 make olddefconfig && make qemu-system-x86_64 -bios build/coreboot.rom Change-Id: Ie44a5d95547a55df93f29082c3b5a86fb83aa1e7 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16987 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-25mainboard/google/reef: Add PowerResource for ELAN touchscreenFurquan Shaikh
Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:55988 Change-Id: Ia905f9eb630cd96767b639aec74131dbd7952d0e Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/17083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-24mainboard/emulation: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I627338505fe1273366bc8f6f528d829b3162b371 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16916 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/tilapia_fam10: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I7515288190ca57a321fb8ffe57a1181b638c336a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16978 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/serengeti_cheetah*: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I2fae9e02e2fccaff97f2441fd17f8960e8ab9786 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16975 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/mahogany: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: Ife9c0b8a1ab55fe683c88e34239d7f5806e1ff9b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16971 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24mainboard/amd/lamar: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I765814450b82755f84c010f63bc8f919bb0cd4c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16970 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-24RISCV: Clean up the common architectural codeRonald G. Minnich
This version of coreboot successfully starts a Harvey (Plan 9) kernel as a payload, entering main() with no supporting assembly code for startup. The Harvey port is not complete so it just panics but ... it gets started. We provide a standard payload function that takes a pointer argument and makes the jump from machine to supervisor mode; the days of kernels running in machine mode are over. We do some small tweaks to the virtual memory code. We temporarily disable two functions that won't work on some targets as register numbers changed between 1.7 and 1.9. Once lowrisc catches up we'll reenable them. We add the PAGETABLES to the memlayout.ld and use _pagetables in the virtual memory setup code. We now use the _stack and _estack from memlayout so we know where things are. As time goes on maybe we can kill all the magic numbers. Change-Id: I6caadfa9627fa35e31580492be01d4af908d31d9 Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://review.coreboot.org/17058 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-10-21mainboard/amd/db-ft3b-lc: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I2a3bf53e6bc4084305238fa176ae46161da4be8f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16967 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21mainboard/amd/bimini_fam10: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I4e628cbe11da32d291c4b8e4c7be91e9b0a86ad9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16966 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-21mainboard/amd/bettong: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I137b27ffb0e54a9ca6b0bd3a454b1d99b3e1c22b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16907 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-20kunimitsu: Add choice to select FSP driverNaresh G Solanki
Add choice to select between FSP 1.1 & FSP2.0 driver to be used. Change-Id: Ied7eab6f4a2191e0bcf220cde5ca519a3c3e2d76 Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/17051 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-20mainboard/google/reef: add snappy variantWisley Chen
Create the initial Snappy variant which refers to the Reef device. Snappy, an Apollolake-platform, is deviated from reference board Reef. BRANCH=master BUG=None TEST=Built & booted Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I6f32c0b1a154edbd8c4822acdbdbdbeb4a0098e6 Reviewed-on: https://review.coreboot.org/17043 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-19mb/asus/kcma-d8,kgpe-d16: use MAINBOARD_DO_NATIVE_VGA_INITArthur Heymans
MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG should only occur together with MAINBOARD_HAS_NATIVE_VGA_INIT. It seems to be used to just have to have the option to be able to select SEABIOS_VGA_COREBOOT. This patch makes these boards use MAINBOARD_DO_NATIVE_VGA_INIT and MAINBOARD_HAS_NATIVE_VGA_INIT to have it select SEABIOS_VGA_COREBOOT by default when SeaBIOS is chosen. Change-Id: If0a36af1883a3d62b16a61483733be981a85e5e2 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16981 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-10-18mainboard/google/reef: Configure PERST pin for reef DVTVaibhav Shankar
Configure GPIO 122 as PERST on DVT. This is to assert WiFi PERST during s0ix entry. BUG=chrome-os-partner:55877 TEST=S0ix functional on DVT Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Change-Id: Iab18b2de621a1a9226c78493f6defa15081db875 Reviewed-on: https://review.coreboot.org/17030 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-16mainboard/google/reef: Set PL1 override to 12000mWVenkateswarlu Vinjamuri
Reef is using APL SoC SKU's with 6W TDP max. We've done experiments and found the energy calculation is wrong with the current VR solution. Experiments show that SoC TDP max (6W) can be reached when RAPL PL1 is set to 12W. Therefore, we've inserted 12W override after reading the fused value (6W) so that the system can reach the right performance level. BUG=chrome-os-partner:56922 TEST=webGL performance(fps) not impacted before and after S3. Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Change-Id: I21c278e82b82d805f6925f4d9c82187825fd0aa0 Reviewed-on: https://review.coreboot.org/17029 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-10-15riscv: Use the generic src/lib/bootblock.cJonathan Neuschäfer
TEST=Compiled for and ran on spike; it booted as before. Change-Id: Id173643a3571962406f9191db248b206235dca35 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16995 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-15riscv: Clean up {qemu,spike}_utilJonathan Neuschäfer
spike_util.h: - (LOG_)REGBYTES and STORE are already defined in arch/riscv/include/bits.h. - TOHOST_CMD, FROMHOST_* are helper macros for the deprecated Host-Target Interface (HTIF). qemu_util.c: - mcall_query_memory now uses mprv_write_ulong instead of first translating the address and then accessing it normally. Thus, translate_address isn't used anymore. - Several functions used the deprecated HTIF CSRs mtohost/mfromhost. They have mostly been replaced by stub implementations. - htif_interrupt and testPrint were unused and have been deleted. spike_util.c: - translate_address and testPrint were unused and have been deleted. After this commit, spike_util.c and qemu_util.c are exactly the same and can be moved to a common location. Change-Id: I1789bad8bbab964c3f2f0480de8d97588c68ceaf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16985 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-15riscv and power8: Convert printk/while(1) to dieJonathan Neuschäfer
Change-Id: I277cc9ae22cd33f2cd9ded808960349d09e8670d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16984 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-10-13x60,t60: do not add etc/ps2-keyboard-spinup for non-seabios payloadsArthur Heymans
Regardless of the payload chosen a file etc/ps2-keyboard-spinup is added to cbfs. With this fix this file is only added to cbfs when seabios is choses as a payload. Change-Id: I37cf4c998856db2d297356776752643dba46a8f8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16146 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-10-11lenovo/x60: CST table: use MWAIT requests instead of P_LVLx I/O readsArthur Heymans
Requesting low power acpi cpu c-states has two software interfaces: Using P_LVLx I/O reads or using equivalent MWAIT requests. This change makes it more consistent with newer targets that use MWAIT requests. There also exists extended intel acpi c-states which can be enabled in two ways: - using a substate hint to the mwait request (defined in bios); - setting a model specific register (msr) Currently this is done by setting the right msr bits but with this change one can experiment by adding substate hints. Change-Id: I9eeb5b008e2ddc2193725667f2c13582a4877e3c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14801 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-11mainboard/apple: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I81c32c618627507cc3a83f60f565a73e5e6d7a13 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16913 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-11mainboard/aopen: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I0014fc030888d71f7951c97bccc7cef0e1c45186 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16922 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10gigabyte/ga-g41m-es2l: add VESA mode to KconfigArthur Heymans
This patch adds MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG to the gigabyte/ga-g41m-es2l Kconfig to allow selecting between textmode and vesamode in menuconfig. Change-Id: I84b61118fa0419d49d2498b66029711cdce97576 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16501 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-10mainboard/advansus: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: Ib44bc66e02901dbde14361091a049f71c3ecb840 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16921 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-10-10mainboard/avalue: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I416d3c212653260a28cb07ed86fda34b736ba4ca Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16926 Tested-by: build bot (Jenkins) Reviewed-by: Kerry Sheh <shekairui@gmail.com>
2016-10-10google/reef: update timing of sdmode togglingSathyanarayana Nujella
Maxim98357a speaker amp requires BCLK & SFRM to be active and stable before it is unmuted. If there is a BLCK and no SFRM, it results in a pop sound. sdmode_delay property already exists which facilitates this configuration. This patch updates "sdmode_delay" to avoid pop sound. BUG=chrome-os-partner:58356 BRANCH=None TEST=while audio playback via headset, remove headset. Audio will be switched playback to speaker. Observe if pop sound comes from speaker. Change-Id: I7ad68caa88d7b3ff52ac1379fe6564de27d97777 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/16933 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-10-09mainboard/kontron: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: I53a0344686921012f4e031842b5108aa4a7b79b1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16908 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-09mainboard/artecgroup: Use C89 comments style & remove commented codeElyes HAOUAS
Change-Id: Ia1e7f558bbc44001358339a522e59a2ef7c420fb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16923 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-08google/oak: Increase the driving strength for 4GB DRAMsPH Hsu
Some PVT units encountered DRAM calibration failure during power on/off tests. The failure is caused by higher impedance of the DRAM on those units. So increase the driving strength for 4GB DRAMs. BUG=chrome-os-partner:57392 TEST=run cold reboot 100 times on PVT units which have DRAM calibration issue. Change-Id: I8a329093db3f1def566e4b7afec3c4f4bfe44c6a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: cf1aa5ade856af433fa056f51a20d18553ae241d Original-Change-Id: I0d1776cd1a5892d1f82e9bf414620d1ef6d29132 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/394451 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Pin-Huan Hsu <ph.hsu@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/16917 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-08google/gru: Add USB 2.0 PHY tuning for Kevin PHY0 and PHY1William wu
We found that Kevin board PHY0 and PHY1 eye-diagram margin is not enough to make compliance test pass, and the PHY0 USB SI is worse than PHY1, because of the higher PCB impedance. For PHY0, we can't improve the eye-diagram by SW PHY tuning, so we need to reduce the RBIAS resistance from 133 ohm to 115 ohm, it can help to increase the eye-height. For PHY1, we can improve the eye-diagram by setting the max pre-emphasis level. And after the above change, the USB2 signal amplitude will become larger at the test point near to SOC USB2 PHY, in order to avoid mis-trigger the disconnect detection (650mV), we need to disable pre-emphasize in eop state. BRANCH=None BUG=chrome-os-partner:53863 TEST=do USB 2.0 compliance test for Kevin C0 and C1 port. Change-Id: I95c0acd79623aeca9a0ae077b1dd3836d91fe561 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de3cdef128966d76e7d8e2ebd641763b911c3ad5 Original-Change-Id: I00cb325b9938e4276cc77b5d6f5faa7023379608 Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/390615 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16911 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/reef/variants/pyro: Add support for GPIO output polarityMartin Roth
commit 028200f7 - x86/acpi_device: Add support for GPIO output polarity updated ACPI_GPIO_OUTPUT to ACPI_GPIO_OUTPUT_ACTIVE_HIGH for the other boards that needed it, but pyro wasn't in the tree when it was initially pushed. Now that pyro is in the tree, it needs to be updated as well. Change-Id: I617999b06ee584e0543d7ae3232bb2be2ff7429c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16930 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-10-07src/mainboard: Remove whitespace after sizeofElyes HAOUAS
Change-Id: Ie2a047d35e69182812c349daedc5b3b5fde20122 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16860 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07src/mainboard: Remove unnecessary whitespaceElyes HAOUAS
Change-Id: I35cb7e08d5233aa5a3dbb4631ab2ee4dc9596f98 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16849 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07x86/acpi_device: Add support for GPIO output polarityFurquan Shaikh
Instead of hard-coding the polarity of the GPIO to active high/low, accept it as a parameter in devicetree. This polarity can then be used while calling into acpi_dp_add_gpio to determine the active low status correctly. BUG=chrome-os-partner:55988 BRANCH=None TEST=Verified that correct polarity is set for reset-gpio on reef. Change-Id: I4aba4bb8bd61799962deaaa11307c0c5be112919 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/16877 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-07google/gru: drive WLAN_MODULE_RST# low as early as possibleBrian Norris
GPIO1_B3 (WLAN_MODULE_RST#) defaults as a pull-up input, but it is also "pulled up" by 1.8V_WLAN. However, 1.8V_WLAN remains low for some time during early boot. This leaves the signal floating somewhere in the middle. This has two potential issues: (1) we're leaking some power for some (hopefully) short period of time (2) we are possibly screwing with the Wifi power sequence; we aren't supposed to deassert PDn (i.e., MODULE_RST#) until all the rails have fully ramped for some period of time Neither of the above issues are likely to be significant, but it is nice to fix, I expect. BRANCH=gru BUG=chrome-os-partner:54026 TEST=measure WLAN_MODULE_RST# on scope at boot time Change-Id: Ia6af9ad6954ad8feeda33015e3f205842380939e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0e890a2787bf034d3358a33fc88c2dd8078593ab Original-Change-Id: I120e26ad0ca486a326874986e142dcaee965b62d Original-Signed-off-by: Brian Norris <briannorris@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/388009 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16882 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/gru: set W2W_DIFFCS_DLY to 5Lin Huang
PHY_PER_CS_TRAINING is being enabled when DDR frequency >= 666. For per cs training, the controller should consider the PHY delay line switch time and there should be more cycles to switch the delay line, so update the W2W_DIFFCS_DLY_ value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:56940 TEST=do memtester on kevin board, and pass Change-Id: I00df2d4724b0b77f3e7565809fb35bbd2ff01ea5 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c135ea3e33d810ed322d947eb8d512d1ac119cfc Original-Change-Id: I81b99cbc085769b7028e770509d79bd8d550820b Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/387506 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16721 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/gru: pass apio number to arm-trust-firmwareLin Huang
To save power when entering suspend, gpios 2 to 4 need to be set to input and 'pull none' mode. Pass the APIO configuration to ATF so it can do a proper job here. BRANCH=None BUG=chrome-os-partner:56423 TEST=run suspend_stress_test on kevin board Change-Id: Id57fe8f622ae3f9c2bc7e58be89518b2b846cd37 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c42082d1ca9a6baa735821382d3e83c1f8dc9ad Original-Change-Id: Iaf441e8e34c5591ffe7c65f6533fcf0b733ff5ac Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/378475 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16720 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07google/gru: pass the gpio power supply enable pin to bl31Lin Huang
We need to disable some regulators when the device goes into suspend. This means that we need to pass some gpios to bl31, and disable these gpios when bl31 runs the suspend function. BRANCH=None BUG=chrome-os-partner:56423 TEST=enter suspend, measure suspend gpio go to low [pg: also update arm-trusted-firmware to match] Change-Id: Ia0835e16f7e65de6dd24a892241f0af542ec5b4b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0f3332ef2136fd93f7faad579386ba5af003cf70 Original-Change-Id: I03d0407e0ef035823519a997534dcfea078a7ccd Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/374046 Original-Commit-Ready: Caesar Wang <wxt@rock-chips.com> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16719 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-07mainboard/google/reef: add pyro variant.Kevin Chiu
Create the initial Pyro variant which refers to the Reef. Pyro is APL Chrome board that deviate from reference board Reef. BRANCH=master BUG=None TEST=Build Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Change-Id: I9beed1f6895e8891d3d51b563edfe172f566718b Reviewed-on: https://review.coreboot.org/16855 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-10-06rockchip: rk3399: improve write leveling flowJianqun Xu
To improve sdram 800MHz and 933MHz stability, we need to modify write leveling flow to get the proper write leveling value. BUG=chrome-os-partner:56940 BRANCH=none TEST=Boot from kevin on 933MHz, and do stressapptest Change-Id: I5b24c93d4a57917fb9af7e5e2a95d8423ccbaa7e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d84bf25b3e5de373c7913e6d534a810cb984b3fd Original-Change-Id: I87efddf628c3683fcb85d6875e029cf3cbc482be Original-Signed-off-by: Jianqun Xu <jay.xu@rock-chips.com> Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/384292 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16716 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06google/gru: Shrink RW_ELOG region to 4KBJulius Werner
Since there's currently a limitation in coreboot's code that prevents more than 4KB to be used by the eventlog anyway, this patch shrinks the available RW_ELOG area in the FMAP for Gru down to 4KB. This may prove prudent later if we ever resolve that limitation, so that tools can rely on the area in the FMAP being the same as the area actually used by the read-only firmware code on these boards. BRANCH=gru BUG=chrome-os-partner:55593 TEST=Booted Kevin, confirmed that eventlog got written normally. Ran a reboot loop to exhaust eventlog space, confirmed that the shrink code kicks in as expected before reaching 4KB. Change-Id: I3c55d836c72486665a19783fe98ce9e0df174b6d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 05efb82ca00703fd92d925ebf717738e37295c18 Original-Change-Id: Ia2617681f9394e953f5beb4abf419fe8d97e6d3e Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/384585 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Simon Glass <sjg@google.com> Reviewed-on: https://review.coreboot.org/16715 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip: rk3399: improve sdram noc timingLin Huang
sdram noc timing will affect ddr latency, this patch improves rk3399 sdram noc timing so improve memory performance. BRANCH=gru BUG=chrome-os-partner:57248 TEST=Boot from kevin board Change-Id: I09e984490a7ad747ef8abfc6542d0e2c95ec19bc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 43dfe55d713d371e39d21312772fd353614b7642 Original-Change-Id: I393e74ecdeb72930ac38ae9bcf311e5654f65162 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382725 Original-Reviewed-by: Sonny Rao <sonnyrao@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Tested-by: Sonny Rao <sonnyrao@chromium.org> Original-Commit-Queue: Sonny Rao <sonnyrao@chromium.org> Reviewed-on: https://review.coreboot.org/16713 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06rockchip/rk3399: lower kevin board sdram frequency to 800MHzLin Huang
We found some boards are not stable when sdram is run at 933Mhz. Before we can fix it, we need to lower the sdram frequency to 800MHz. In this patch we modify the DQS delay from 0x280 to 0x260 and extend the DQS window. BRANCH=None BUG=chrome-os-partner:56940 TEST=Booted Kevin. Change-Id: I68561c4aa4d9ab66acfa3515a42d696157aff759 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 877a7f6ad22a5bde9f9e458bcb65f133f2f001bd Original-Change-Id: I5eab6bbe96f0dae095c5353403292022e7a25421 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/382724 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16709 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-06google/veyron_rialto: Add lpddr3-K4E6E304EB-2GB-1CH memory configurationJeffy Chen
Add lpddr3-K4E6E304EB-2GB-1CH memory configuration for rialto. BUG=chrome-os-partner:56759 BRANCH=none TEST=Build Change-Id: I698fe450d48b64a06232aa44ecf91d688d9dc17a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d3edecdb135939c3264ab1b831e7821d3a3e0149 Original-Change-Id: I7dae9fd822abeff5b08de0ab9262e1817ac58531 Original-Signed-off-by: Jeffy Chen <jeffy.chen@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380443 Original-Commit-Ready: Alexandru Stan <amstan@chromium.org> Original-Tested-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Alexandru Stan <amstan@chromium.org> Original-Reviewed-by: Jonathan Dixon <joth@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16699 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-10-06rockchip/rk3399: Move big CPU cluster initialization into ramstageJulius Werner
This patch moves the big CPU cluster initialization on the RK3399 from the clock init bootblock function into ramstage. We're only really doing this to put the cluster into a sane state for the OS, we're never actually taking it out of reset ourselves... so there's no reason to do this so early. Also cleaned up the interface for rkclk_configure_cpu() a bit to make it more readable. BRANCH=None BUG=chrome-os-partner:54906 TEST=Booted Kevin. Change-Id: I568b891da0abb404760d120cef847737c1f9e3ec Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: bd7aa7ec3e6d211b17ed61419f80a818cee78919 Original-Change-Id: Ic3d01a51531683b53e17addf1942441663a8ea40 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/377541 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16698 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-05siemens/mc_tcu3: Increase LCD backlight turn-on delay to 500 msWerner Zeh
Due to different LCD panel requirements the delay between LVDS becomes active and the backlight is switched on needs to be increased to 500 ms. Change-Id: I09029624469aef412141c7b46224d48557ba4af1 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16875 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04google/gru: Ensure correct pull resistors for special-function pinsJulius Werner
Several of the special function pins we're using in firmware have a pre-assigned pull-up or pull-down on power-on reset. We don't want those to interfere with any of the signaling we're trying to do on those pins, so this patch disables them. Also do some house-cleaning to group the bootblock code better, and change the setup code for all SPI and I2C buses to first initialize the controller and then mux the pins... I assume this might be a little safer (in case the controller peripheral has some pins in a weird state before it gets fully initialized, we don't want to mux it through too early). BRANCH=None BUG=chrome-os-partner:52526 TEST=Booted Kevin. Change-Id: I4d5bd3f7657b8113d90b65d9571583142ba10a27 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f8f7fd56e945987eb0b1124b699f676bc68d0560 Original-Change-Id: I6bcf2b9a5dc686f2b6f82bd80fc9a1a245661c47 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/382532 Reviewed-on: https://review.coreboot.org/16711 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04gru: Increase SPI speed to 33MHzSimon Glass
Increase the SPI bus speed to speed up boot time. The maximum supported speed at 1.8V is 37.5MHz, and 33MHz is the next lowest convenient speed, given the clock parents. BUG=chrome-os-partner:56556 BRANCH=none TEST=boot on gru and see that things still work correctly. Total time spent on reading from SPI reduces from 185ms to 141ms. Change-Id: I71436c9e343b18360fa63d528dea5cfcfbc831e6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d7576f6e53e407af61160be142c3d589e864a8cf Original-Change-Id: I55a19f523817862e081d23469e94fd795456dd67 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381313 Original-Commit-Ready: Julius Werner <jwerner@chromium.org> Original-Tested-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16708 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-04google/gru: Init the PWM pinmux after setting up the PWMDouglas Anderson
If we setup the PWM _after_ the pinmux then there's a period of time when we're driving the PWM incorrectly. Let's setup the regulator and _then_ configure the pinmux. This fixes no known bugs, but it is more correct and probably makes the signals look better at bootup. BRANCH=None BUG=None TEST=scope Change-Id: I311c0eded873b65e0489373e87b88bcdd8e4b806 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fcf4d0ba29d82cce779c0b25ead36de4a95d97a1 Original-Change-Id: I5124f48d04a18c07bbd2d54bc08ee001c9c7e8d1 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/381592 Original-Reviewed-by: Simon Glass <sjg@google.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16700 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04mainboard/siemens/sitemp_g1p1: Use tabs for indentsElyes HAOUAS
Change-Id: Ia5ea2198cdc93822723a4fe5440d574d76cb4de2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16847 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04nb/gm45: allow use of 352M preallocated ram for igdArthur Heymans
The datasheets on gm45: "Mobile Intel® 4 Series Express Chipset Family" mention the possibility of having 352M ram preallocated for the integrated graphic device. This only worked fine if the amount of ram in the system was 3GB or less. When 4G or more is installed, memory is remapped to create a 1GB large pci mmio hole which is not enough and creates conflicts when 352M vram is used. This patch increases the pci mmio hole size on Lenovo x200 to allow 352M vram to work. TEST: build and flash on target with 4GB ram or more, use nvramtool to set gfx_uma_size to 352M and reboot. Change-Id: I5ab066252339ac7d85149d91b09a9eaaaab3b5b6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16831 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04mainboard/amd/torpedo: Improve code formattingElyes HAOUAS
Change-Id: I18de4740e0d3512ec81e10b32d13d07a35791b57 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16846 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-10-04src/mainboard: Remove unnecessary semicolonElyes HAOUAS
Change-Id: Iab0c7c470a3105b5df7b6b74aebdd1329e7f93ba Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16859 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-10-04samsung/lumpy: Swap SPD assignmentsKyösti Mälkki
On-board memory is on channel 1. This fixes native raminit with 4GiB SO-DIMM installed. Change-Id: If1b94e050d7e8d0dbd349c0415a182730aa5fa90 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/16845 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-10-03google/gale: Remove #ifdef of Kconfig bool symbolMartin Roth
Kconfig symbols of type bool are ALWAYS defined, so this code was always being included and run, which isn't what the author wanted. Change to use IS_ENABLED(), and a regular if() instead of an #ifdef. Change-Id: I72623fa27e47980c602135f4b73f371c7f50139b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16837 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-25 06:50:59 +0000