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2023-05-31mb/google/rex/var/screebo: Add MIPI camera devicejason.z.chen
Enabling MIPI UCAM for screebo project BUG=b:277883010 TEST=none Signed-off-by: jason.z.chen <jason.z.chen@intel.corp-partner.google.com> Change-Id: Id06e5c162d911a4bd78190757c25e7f760160a8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75157 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31mb/google/rex/var/screebo: Set TCC to 90°CWentao Qin
Set tcc_offset value to 20 in devicetree for Thermal Control Circuit (TCC) activation feature for proto phase. BUG=b:282865187 BRANCH=None TEST=Build FW and test on Screebo board Change-Id: I3a929aa20a700376d2a0a150911fed34e67f78eb Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75360 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Haikun Zhou <zhouhaikun5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/dedede/var/boxy: Fix filename "MakeFile.inc" to "Makefile.inc"Kevin Yang
Incorrect filename "MakeFile.inc" cause gpio.c can not be complied. Rename to "Makefile.inc" and confirm gpio.c can load correctly. BUG=b:281620454 BRANCH=dedede TEST=build and confirm gpio.c can be loaded Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I39947c66de04695e5242ab1affc328894f34f9f3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75520 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/rex: Move I2S config from common to boardKapil Porwal
Move I2S config from common to board. BUG=none TEST=Build google/rex Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I51ca902e9b0077d5d5cc9c3507d26301a0f61bc2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75513 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/rex: Enable SoundWire codecsKapil Porwal
Enable drivers for SoundWire codecs and define the topology in the devicetree for the rex0 variant with the SoundWire daughter board connected. +------------------+ +--------------------+ | | | Headphone Codec | | Intel Meteor Lake| +--->|Cirrus Logic CS42L42| | SoundWire | | | ID 0 | | Controller | | +--------------------+ | | | | Link 0 +----+ +-------------------+ | | | Left Speaker Amp | | Link 1 | +--->| Maxim MAX98363 | | | | | ID 0 | | Link 2 +----| +-------------------+ | | | | Link 3 | | +-------------------+ | | | | Right Speaker Amp | +------------------+ +--->| Maxim MAX98363 | | ID 1 | +-------------------+ This was tested by booting the firmware and dumping the SSDT table to ensure that all SoundWire ACPI devices are created as expected with the properties that are defined in coreboot under \_SB.PCI0: HDAS - Intel Meteor Lake HDA PCI device HDAS.SNDW - Intel Meteor Lake SoundWire Controller HDAS.SNDW.SW00 - Cirrus Logic CS42L42 - Headphone Codec HDAS.SNDW.SW20 - Maxim MAX98363 - Left Speaker Amp HDAS.SNDW.SW21 - Maxim MAX98363 - Right Speaker Amp BUG=b:269497731 TEST=Verified SSDT for SNDW in the OS. Playback and recording are also validated on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I3e11dc642ff686ba7da23ed76332f7f10e60fade Reviewed-on: https://review.coreboot.org/c/coreboot/+/73280 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/brya/acpi: FBVDD_PWR_EN should be inverted on AgahTarun Tuli
The FBVDD_PWR_EN signal should be inverted in its control level on Agah v.s. Hades. The original change covered the Hades implementation, but needs to be updated to invert for Agah. This change can be removed once we drop support for Agah. BUG=b:280467267 TEST=built for Hades and Agah Change-Id: I7f90c03b8d9b859004e5c124bf0a1f7b59921c3d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75530 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-31mb/google/nissa/var/uldren: Fine tune eMMC DLL settingsDtrain Hsu
Fine tune eMMC DLL settings based on Uldren board. BUG=b:280120229 TEST=executed 2500 cycles of cold boot successfully on all eMMC sku. Change-Id: I82a55a1fe17aa910eb02464df463603dcbbbef05 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75459 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-31mb/google/nissa/var/uldren: Add ACPI DmaProperty for WLAN deviceDtrain Hsu
Add ACPI DmaProperty for WLAN device. `is_untrusted` is eventually ended up by adding DMA property _DSD which is similar to what `add_acpi_dma_property` does for WWAN drivers, hence it makes sense to have a unified name across different device drivers. BUG=b:279676191 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I6d898a939aa0be31a671d2436a81c34f7a1ec030 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75460 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-31mb/google/skyrim: Add common_config.acp_configTim Van Patten
Add 'common_config.acp_config' to the device tree, so we have the correct pin configuration. BUG=b:225320579 TEST=USE=fwconsole emerge-skyrim ... ; verify 'devbeep' works in depthcharge console TEST=Boot into ChromeOS, verify YouTube sound works with internal speakers and headphone jack TEST=Boot into ChromeOS, verify microphone with Google Meet Change-Id: Ie2d79408104273d8a53214b683800fa0663c14d3 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74962 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-31mb/msi/ms7d25: Add console die notificationMichał Żygowski
Add beeps and blink SATA LED on critical errors. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I45b8b4fda00d58a1ab1d7dfab49d6f841bc0b000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69821 Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-30mb/google/myst: Fix the DRAM Strap IDKarthikeyan Ramasubramanian
Incorrect memory part was used in CB:74745 to generate the DRAM Strap ID. Amend the memory_parts_used.txt and regenerate the DRAM Strap ID. BUG=b:272746814 TEST=Generate the DRAM Strap ID. Change-Id: I0668d7e02345610a11f9113d8bbe99a474f33f1a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75456 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-29mb/google/rex: Update GPIO PAD as per Proto 2 schematicsSubrata Banik
BUG=b:283477280 TEST=Able to build and boot google/rex as per Proto 2 schematics dated 05/16. +-----------------+------------------------------------+---------------------------+--------+ | GPIO | In Proto 1 | In Proto 2 | Impact | +-----------------+------------------------------------+---------------------------+--------+ | GPP_C01 | SOC_TCHSCR_RST_L | SOC_TCHSCR_RST_R_L | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_D19 | NC | EC_SOC_REC_SWITCH_ODL | Y | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E04 | HPS_INT_L | SOC_PEN_DETECT | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_E17 | EN_HPS_PWR | EN_PP3300_SPARE_X | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F13 | GSPI1_SOC_MISO | GSPI1_SOC_MISO_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_F21 | GPIO_F21_SPI_CS_L | SPI_SOC_CS_UWB_L_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H00 | GPIO_H00_SPI_CLK_R | SPI_SOC_CLK_UWB_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H01 | GPIO_H01_SPI_MOSI_R | SPI_SOC_DO_UWB_DI_STRAP_R | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_H02 | GPIO_H02_SPI_MISO | SPI_SOC_DI_UWB_DO_STRAP | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S00 | UNNAMED_8_METEORLAKEU_I137_GPPS00 | SDW_HP_CLK_WLAN_PCM_CLK | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S01 | UNNAMED_8_METEORLAKEU_I137_GPPS01 | SDW_HP_DATA_WLAN_PCM_SYNC | N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S02 | UNNAMED_8_METEORLAKEU_I137_GPPS02 | DMIC_SOC_CLK0_WLAN_PCM_OUT| N | +-----------------+------------------------------------+---------------------------+--------+ | GPP_S03 | UNNAMED_8_METEORLAKEU_I137_GPPS03 | DMIC_SOC_DATA0_WLAN_PCM_IN| N | +-----------------+------------------------------------+---------------------------+--------+ Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4a8c43b0f845d3446188b7c926e482f91e5b45aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/75407 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-28mb/ibm: Add 4 SPR sockets server board IBM SBP1Patrick Rudolph
The IBM SBP1 is an evaluation platform. It's utilising: - 4 SPR sockets, having 16 DIMMs each - 240C/480T at maximum - 32x CPU PCIe slots - 2x M.2 PCH PCIe slots - Dual 200Gbit/s NIC - SPI TPM It has an AST2600 BMC for remote management. It doesn't have: - External facing USB ports - Video outputs - Audio codec Test: The board boots to Linux 5.15 with all 480 cores available. All PCIe devices are working and no errors in ACPI. All 64 memory DIMMS are working and M.2 devices can be used. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Change-Id: Ie21c744224e8d9e5232d63b8366d2981c9575d70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73392 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27mb/google/rex: Update FMD to incorporate ISH firmwareSubrata Banik
This patch adds two new chromeos_*.fmd files for release and debug FSP builds targeting rex_ec_ish. `rex_ec_ish` variant would pack ISH firmware into the CSE boot partition hence, the blob size is expected to increase. Creates separate flash map layout to ensure ISH work is not impacting on the regular `rex0` project SPI flash usage. BUG=b:284254353 TEST=Able to build google/rex_ish_ec board and boot on target hardware. Change-Id: Ife4663d3ccf80a928646eadaac4c9ab49ad29055 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75471 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-27mb/google/rex: Create variant to support ISH enablementSubrata Banik
This patch creates a new variant to support the ISH enablement using Rex platform.The idea here is to leverage the `rex0` code as much as possible and add specific support for ISH enablement as per the hardware schematic differences. BUG=b:284254353 TEST=Able to build google/rex_ish_ec board and boot on target hardware. Change-Id: I625fd0b31aed998f4e8f2d139827bc212ee8a90b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75470 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-26mb/google/rex/variants/baseboard/rex: Add CPU power limit valuesSumeet Pawnikar
Add support of variant_devtree_update() function to override devtree settings for variant boards. Also, add CPU power limit values for rex baseboard. BRANCH=None BUG=b:270664854 TEST=Built and verified power limit values as below log message for 15W SKU on Rex board. Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (57000, 57000) PL4 (W) (114) Change-Id: If46445157358e3e0f227e26a35b4303fc9189a4b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26mb/google/rex: Set frequency and gears for SaGv pointsBora Guvendik
Restrict memory speed to 6400 MTS as per board design. BUG=b:282164577 TEST=Verified the settings on google/rex using debug FSP logs. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I3dec383c7c585b80a73089f3403011c5cda61f65 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75291 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-26mb/purism/librem_cnl: Enable Librem 14 jack detect with fixed ECJonathon Hall
Use verbs enabling jack detect if the EC firmware has been updated with fixed jack detection. Test: Build Librem 14 and boot with latest EC, test headset jack detection. Change-Id: I57a27b1d51e4f6c7c712bcb2823d21692b9c5ce6 Signed-off-by: Jonathon Hall <jonathon.hall@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74364 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-26mb/dell/e6400/acpi: Route Ricoh R5C847 PCI IRQ lines as DBCNicholas Chin
Based on the schematic and vendor ASL code, PCI interrupt lines ABC of the Ricoh R5C847 PC Card/Media Card/FireWire controller are routed DBC. From lspci and the schematic this chip is PCI device 1. The original config copied from the T400 was routed ABCD->BCDA, causing Linux to issue an "irq 18: nobody cared" message when inserting an SD card. This is fixed by this patch and the SD card now works properly. Change-Id: Iede1de72d5369f1aebbac170792733739add3431 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75411 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-26treewide: Remove 'extern' from functions declarationElyes Haouas
"extern" is automatically implied with function declaration. Change-Id: Ic40218acab5a009621b6882faacfcac800aaf0b9 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71890 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-26mb/google/nissa/var/uldren: Add fw_config probe for lteDtrain Hsu
Use fw_config to probe lte. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5596f3536b0a21453f89e67615acabbbf6a8409b Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75337 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-26mb/google/nissa/var/uldren: Add fw_config probe for touchpadDtrain Hsu
Use fw_config to probe touchpad. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib20abac74683c670c174821b821ede461dbb0163 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75336 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-26mb/google/rex/var/screebo: Enable touchpadZhongtian Wu
Enable touchpad for Google Screebo. BUG=b:278160238 BRANCH=none TEST=Build and boot to Google Screebo. Verify touchpad works. Change-Id: Ib83e5ef5ca497592f5a26aa1e85d793d06d9dd7f Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75412 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-25mb/google/skyrim/var/winterhold: Fix USB port register scopeMatt DeVillier
Commit f99d6700 ("mb/google/skyrim/var/winterhold: Fix USB port ACPI generation") fixed the USB-A ports being double-nested, but neglected to move the chip driver registers up into the correct scope. While the generated ACPI is still correct, fix the register scope anyway to avoid confusion. BUG=b:283778468 BRANCH=skyrim TEST=build/boot winterhold, dump ACPI, verify unchanged Change-Id: Ia9982fed0fe2093d787ee9506ac5bbadd6cc03f9 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75389 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25mb/google/skyrim/var/markarth: Fix USB port register scopeMatt DeVillier
Commit d81ee3f1 ("mb/google/skyrim/var/markarth: Fix USB port ACPI generation") fixed the USB-A ports being double-nested, but neglected to move the chip driver registers up into the correct scope. While the generated ACPI is still correct, fix the register scope anyway to avoid confusion. BUG=b:283778468 BRANCH=skyrim TEST=build/boot markarth, dump ACPI, verify unchanged Change-Id: I5c1cd23c49b512f55e9e13b2164d30dfb7fb682d Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75388 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25mb/google/skyrim/var/frostflow: Fix USB port register scopeMatt DeVillier
Commit a539893c ("mb/google/skyrim/var/frostflow: Fix USB port ACPI generation") fixed the USB-A ports being double-nested, but neglected to move the chip driver registers up into the correct scope. While the generated ACPI is still correct, fix the register scope anyway to avoid confusion. BUG=b:283778468 BRANCH=skyrim TEST=build/boot frostflow, dump ACPI, verify unchanged Change-Id: I3912fe1b7d3f2a07cb379928cd4f5d87100d3284 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75387 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-25mb/google/rex: Enable SaGvSubrata Banik
This patch overrides `SaGv` FSP-M UPD to enable SaGv feature to be able to train memory (DIMM) at different frequencies. On all latest Intel based platforms SaGv is expected to be enabled to support dynamic switching of memory operating frequency. BUG=b:267879107 TEST=Able to verify SaGv is enabled with 3 work point (0, 1 and 2) and MRC retraining takes around ~20ms extra compared to SaGv being disabled. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic680bfeab4dd285c0d3916ba5e917cc12bae3284 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73534 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24mb/google/Screebo: Enable AUX DC biasing on C0Simon Zhou
SKU1A C0 has no redriver, so enable SBU muxing in the SoC. BUG=b:283044004 BRANCH=none TEST=Voltages are correct on the C0 and C1 AUX bias pins Change-Id: I18b4ade2c60c270855fb2e733a9201539e08d8ba Signed-off-by: mike <mike5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-24mb/google/rex/var/screebo: Add BT devicetree configqinwentao
Enabling BT for screebo project BUG=b:278169273 TEST=Check whether BT can connect to Bluetooth device Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com> Change-Id: I0ecd62abfbe751e1036948b1490844e7e63d7f0d Signed-off-by: qinwentao <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75352 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-24mb/google/hades: Enable smbus in device treeEric Lai
Hades uses the SODIMM, enable the smbus to see the SPD address for the memory. BUG=b:283138024 TEST=i2cdetect -l can see the smubs adapter. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I3912a025afaf8388d04a4b08852a84d4a2a6bf06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75399 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-24mb/siemens/mc_ehl1: Enable pi608gp I2C driverJan Samek
Add devicetree and Kconfig entries to enable additional configuration of the Pericom PI7C9X2G608GP PCIe switch on this board variant. The amplitude is being adjusted to 425 mV and de-emphasis level to 6.0 mV. BUG=none TEST=Read out the PCIe config space values of the switch and check if they match with the ones configured over SMBus. Change-Id: I11459f0794278ad614aa6e16c56df1ad578fe2f8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-24mb/siemens/mc_ehl4: Double payload size to 256 bytes for PCIe RP #2, #3Mario Scheithauer
To improve the rate of data transfer for PCIe root port #2 (00:1c.1) and root port #3 (00:1c.2) set the max payload size to 256 bytes for both root ports. Change-Id: I553f6cf090d799fbbaafb925646c6566d6951a86 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75127 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-05-24mb/google/nissa/var/uldren: Add fw_config probe for touchscreenDtrain Hsu
Use fw_config to probe touchscreen. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I5d8129b3af3aa09e5bc31160de82d9ef7af0dd59 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75335 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-23mb/intel/archercity_crb: Add EWL Hob processing for MRC errorJohnny Lin
Override the weak function mainboard_ewl_check() and select OCP_EWL. Select IPMI_KCS_ROMSTAGE and IPMI_OCP for OCP IPMI commands which are needed for OCP EWL driver, but they are Meta-specific BMC commands and don't really work for AC, this change is just for a demonstration with AC. Note that FSP UPD promoteWarnings needs to be disabled so that FSP won't block and can return to coreboot for EWL processing when memory EWL type 3 error occurs. Tested=On Intel AC, connected with a faulty DIMM can see EWL type 3 error being generated and halted with coreboot log: [DEBUG] Number of EWL entries 3 [ERROR] EWL type: 3 size:32 severity level:1 [ERROR] Major Warning Code = 0x29, Minor Warning Code = 0x04, [ERROR] Major Checkpoint: 0xb7 [ERROR] Minor Checkpoint: 0x74 [ERROR] Socket 0 [ERROR] Channel 4 [ERROR] Dimm 0 [ERROR] Rank 0 [ERROR] IPMI: ipmi_get_board_config command failed (ret=3 resp=0xc1) [DEBUG] ipmi send memory training error [DEBUG] EWL type: 1 size:19 severity level:1 [DEBUG] 0x6392e968: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04 [DEBUG] 0x6392e978: 00 00 00 [DEBUG] EWL type: 1 size:19 severity level:1 [DEBUG] 0x6392e97b: 01 00 00 00 13 00 01 00 00 00 b7 74 0a 03 00 04 [DEBUG] 0x6392e98b: 00 00 01 [EMERG] Memory Training Error! Change-Id: I4602ae356aa6e55ed0611b8ac9a206db127c297c Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23mb/google/skyrim/var/winterhold: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=untested, but same error/fix as frostflow variant. Change-Id: Ic498afcc8b8e0224f344f405e2f1ef6184df1d6b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75340 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/skyrim/var/markarth: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=untested, but same error/fix as frostflow variant. Change-Id: Ie40541ada508acfa5771ea800249b8a57b168e3b Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75339 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/skyrim/var/frostflow: Fix USB port ACPI generationMatt DeVillier
The overridetree definitions for the USB ports wrongly double-nested the ports, causing the generated SSDT to be incorrect, leading to an error in dmesg: ACPI BIOS error (bug): Could not resolve symbol \ [\_SB.PCI0.GP41.XHC1.RHUB.HS02.HS03], AE_NOT_FOUND BUG=b:283778468 BRANCH=skyrim TEST=build/boot frostflow, verify error no longer present in dmesg. Change-Id: I0b87af6b2c04f9354e6f394a8f987fa660e49134 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75338 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-05-23mb/google/nissa/var/yavilla: Generate LP5 RAM ID for K3KL6L60GM-MGCTShon Wang
Generate the RAM ID for Samsung K3KL6L60GM-MGCT. DRAM Part Name ID to assign K3KL6L60GM-MGCT 6 (0110) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I05a2cd5f2235702dea8fd706349ebda6a9ffa2ef Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-23mb/starlabs/starbook: Add ramtop to CMOS layoutSean Rhodes
Add `ramtop` to CMOS layout so SOC_INTEL_COMMON_BASECODE_RAMTOP can be used. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I88128d2c62bdc3246a3f30e768c353f0fe3faeb7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74432 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-23mb/google/rex: Add FW_CONFIG and device for VPUEran Mitrani
BUG=b:282912666 TEST=set and unset bit20 in HW_CONFIG and check if VPU(0b.0) is enabled when bit20 is set, and disabled when cleared Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Iee6a9026a4d210407350bfb7ecc8a058e7ff5c24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-23mb/google/rex: Add FW_CONFIG for TOUCH over SPIEran Mitrani
TEST=set the corresponding cbi bit, and saw SPI0 under sysfs BUG=b:278783755 Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I7099cde14cff90ad63e9164769f9913a8284a805 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74888 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-23mb/google/skyrim/var/markarth: Update DPTC and STT settingsJohn Su
According to Thermal table 0518, adjust DPTC and STT settings. BRANCH=none BUG=b:273636128 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Id1c1884eabc1ea58148270f39eaca836ccc3fb54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75326 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-05-22mb/amd/majolica: Add default setting PSP_INIT_ESPIZheng Bao
The board needs this setting to boot. Change-Id: I7f507c2478b63daf891430e95b008747b9b95a51 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-22mb/system76/rpl: Add Gazelle 18Tim Crawford
The Gazelle 18 (gaze18) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots - M.2 NVMe SSD slot - M.2 SATA SSD slot - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.6 Not working: - Discrete/Hybrid graphics Change-Id: I4599bf12c0f3048f9328f336cc8971400f5fd1a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-05-22mb/google/nissa/var/pujjo: Add WWAN_5G power on sequenceLeo Chou
Pujjoteen5 support WWAN 5G device, use variant.c to handle the power on sequence. BUG=b:279835626 TEST=Build and check WWAN 5G power on sequence. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I7dc72f2c705bcb41745f4bf08bef286773fe8b13 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75327 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/google/nissa/var/yavilla: Config I2C frequencyTony Huang
Measured the I2C frequency meets spec 1. I2C0 (TPM): 976.1 Khz 2. I2C1 (TouchScreen); 394.0 Khz 3. I2C2 (WCAM); 377.9 Khz 4. I2C3 (Audio): 390.0 Khz 5. I2C5 (Touchpad): 389.3 Khz BUG=b:283374537 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot and check all I2C devices measurement result Change-Id: If6e3a4a2b1ac642561015a290e6579238c3c2b1b Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-22mb/google/skyrim: Enable DmaProperty on WLAN deviceMark Hasemeyer
Set the DmaProperty in the device's _DSD so that the OS can treat the device as untrusted. BUG=b:278310256 TEST=cat /sys/bus/pci/devices/<wifi>/untrusted == 1 iperf3 -c <iperf3-server> -t 60 (No performance regressions seen) Change-Id: I06369a19afa5b881b26f5c1eb243e2db41a9bb36 Signed-off-by: Mark Hasemeyer <markhas@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75095 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-22mb/msi/ms7d25: Re-enable GpioOverrideMichał Żygowski
Set all GPIOs to their target functions and do not depend on FSP to configure them. The board support has stabilized and was tested with many PCIe devices. There is no need to detect CLKREQ signals so we may hardcode them. TEST=Boot MSI PRO Z690-A DDR4 to Linux and check if all ASPM and Clock PM features' state on PCIe root ports are the same before and after the change. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I01dc83ce23ca27525b8905665da942510f249824 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-22mb/google/corsola: Disable backlight before turning on bridgeRuihai Zhou
Disable backlight before turning on bridge, otherwise the bridge will initialize failed. Fixes: d5c1e1(mb/google/corsola: Add support for MIPI panel) Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I7d10bf9e8675b2fb03bfd1e294af66207b9b0620 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75354 Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-05-22mb/google/rex/var/screebo: enable fingerprintSimon Zhou
BUG=b:278156430 TEST=verify the fingerprint on screebo Change-Id: I986e470b28145f7b17427e794055929a4283c721 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75287 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-22mb/google/hatch/jinlon: Add HID to gfx ACPI nodeKornel Dulęba
The upstream kernel privacy screen driver uses HID GOOG0010 to look for firmware node to use. This method is used on other boards, e.g. redrix. See: drivers/platform/chrome/chromeos_privacy_screen.c in linux sources. Update jinlon gfx ACPI node to work with that. BUG=b:279092050 TEST=privacy protection screen works with 5.15 and 4.19 kernels Change-Id: Icba41e7f2be7292f713fea10dbe69b3ca128bde7 Signed-off-by: Kornel Dulęba <korneld@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75289 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-22mb/google/nissa/var/yavilla: Disable unused gpio with fw_configRobert Chen
Disable unused gpio for LTE daughter board, WFC and stylus. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6cc61321cd96a10dd34ff6cd9fcabe85a64bbfa9 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75293 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-22mb/msi/ms7d25: Disable PCIe hotplugMichał Żygowski
The support for the board has stabilized and PCIe ports have been tested with many devices. Although hotplug is not commonly used and it seems pointless to keep it enabled, so disable it. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I338c55cb57d971badd08235b71626a710fafb829 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69822 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21mb/lenovo/x200: Add VBT files by defaultNico Huber
Select INTEL_GMA_HAVE_VBT so VBT files are added by default. This board has two specific VBT files that are hard-coded in the Makefile. Hence set an empty INTEL_GMA_VBT_FILE string. Change-Id: I0508c8016da06b401d6fbefd6e5cec1af018a5c8 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75380 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21nb/intel/gm45/gma: Centralize call to gm45_get_lvds_edid_str()Nico Huber
There is only a single place where we need the LVDS EDID string. Let's call gm45_get_lvds_edid_str() right there. This simplifies the API and helps to follow the execution flow. The function is moved to avoid a forward declaration. Change-Id: I86f3a88e6b661bcf60319edbe301e70304924727 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75378 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-21nb/intel/gm45/gma: Probe PCI resource once and firstNico Huber
The PCI resource should only be probed as part of the device .init process. We can simply do that first and know that we can use the global `gtt_res` from then on. This simplifies the signature of gm45_get_lvds_edid_str(), and makes changes to the API user (lenovo/x200) necessary. Change-Id: I6c96f715abfa56dcb1cd89fde0fbaef3f1cb63ae Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-20mb/intel/galileo: Drop supportFelix Singer
As announced in the 4.20 release notes, support for the Intel Galileo mainboard is moved to the 4.20 branch and dropped from master. Change-Id: I132adf2782721738c954252665fdcd7bb8e1a1cd Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: ron minnich <rminnich@gmail.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-19mb/google/nissa/var/yaviks: Generate LP5 RAM ID for K3KL6L60GM-MGCTWisley Chen
Generate the RAM ID for Samsung K3KL6L60GM-MGCT. DRAM Part Name ID to assign K3KL6L60GM-MGCT 6 (0110) BUG=b:281928906 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia5193d3ab3d654f25d519ad9a954f2ca8a15a978 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75152 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@google.com>
2023-05-19mb/google/brya/acpi: Update GC6 sequencesEran Mitrani
GC6 - Low power mode for system idle on Nvidia GPU In GC6I Before ramp of PEXVDD: Deassert FBVDDQ Enable, no delay is needed before or after. In GC6O After ramp of PEXVDD: Assert FBVDDQ Enable, no delay is needed before or after. BUG=b:280467267 TEST=built for Hades and Agah, tested on Agah Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I0277772b1d2f6f4e6a3f74b92035e8b36f2670ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/75302 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-19mb/google/rex: Enable stylus supportDinesh Gehlot
This patch enables stylus support by configuring the "GPP_D08" irqs for rex SoC. This allows the SoC to detect a stylus device, when in use. However stylus is not a wake up source for the rex. BUG=b:282256460 Test=Stylus is detected on proto1 device. Signed-off-by: Dinesh Gehlot <digehlot@google.com> Change-Id: I84a71aa664698e105b738f8680d0a4751ca1fc72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71820 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-18vc/amd/fsp/phoenix/FspUsb: update USB config struct for Phoenix SoCFelix Held
Phoenix has one more Type C port and two more USB2 ports which are used as the legacy USB part of the two USB4 ports. The USB struct version numbers have also changed, since it's a newer and incompatible version of that struct. TEST=After changing FSP to not hard-code the USB PHY config, but use the configuration provided by coreboot, and applying this patch, the USB connector on the USB2 port 4 lines works. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: If52934595dd612154b97e7b90dbd96243146017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73379 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-18mb/amd/birman: Don't select the console UART, default to yMartin Roth
Things with prompts should not use selects, but should instead default to y. If there's a reason they need to be selected, they should be able to be hidden when they're selected. This isn't one of those cases where a select is needed, so set the default to y instead. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If6de339c3a1ceb3cd71008402bba49b5efc4af3f Reviewed-on: https://review.coreboot.org/c/coreboot/+/75131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-05-18Myst: Update Makefile to remove SPD injectionMartin Roth
The SPD format in the APCB has changed for Phoenix, and the injection tool 'apcbtool' needs to be updated to match. Until this happens, the APCB will be built containing the correct SPD. BUG=b:281983434 TEST=Build Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: If575f98511c796e93c5a12cd450a3a7985e39806 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-05-17nb/intel/i440bx, mb/asus/p3b-f: Abolish disable_spd()Keith Hui
This hook is specifically for asus/p3b-f so its mainboard code has a chance to put SPD away after RAM init completes. What it intends to do is done when GPO gets programmed in ramstage (and it's safe to do so), and no other board needs this hook, so drop it. Change-Id: Ib7874b4d2b69fdaa5f3c5a3421a62a629c4154a4 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-17mb/google/nissa/var/pujjo: Add GPIO setting for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, add GPIO setting for WWAN 5G device BUG=b:281943398 TEST=Build and check serial log Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ie2e0ea34c54a453645d626f892f50654ef5064ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75195 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-17mb/google/nissa/var/pujjo: Enable PCIe port 3 for WWAN_5GLeo Chou
Pujjoteen5 support WWAN 5G device, enable PCIe port 3 for WWAN 5G device BUG=b:281943398 TEST=Build and boot on pujjo Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I6d2e8eaecae968ed51095d9497beab492ba7e0c8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-17mb/google/brya/variants/hades: Set up internal pull-up for GPIOsEran Mitrani
BUG=b:280843816 TEST=builds Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I55a85335a34eee227abb6ff355719f7ca2cbf04a Reviewed-on: https://review.coreboot.org/c/coreboot/+/75035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-17mb/google/volteer: Use FW_CONFIG to determine correct SOF audio profileMatt DeVillier
Use AUDIO PROBE to determine speaker amp config, set SOF driver profile accordingly. TEST=build/boot Win11 on Delbin and Drobit, verify correct audio profile selected, drivers loaded and functional. Change-Id: I13d787cb5ccb74d2774151ccd5deeb45b3364319 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-15mb/google/brya/var/taniks: Update SOF speaker topologyMatt DeVillier
Taniks uses a 4-channel output config, rather than 2-channel. Update the SOF speaker topology accordingly. TEST=build/boot Win11 on taniks, verify speaker output functional. Change-Id: I3c08b12b11464dcada014289174e0cc468d1c39d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-15mb/google/myst: Re-organize the FMAP layoutKarthikeyan Ramasubramanian
By moving certain FW UI assets from RO to RW sections, 4 MiB is sufficient for RO section. Split the resultant available 4 MiB equally between 2 RW sections. This will help in getting to 16 MiB SPI flash for the mainboard. BUG=b:281567816 TEST=Build Myst BIOS image with the updated layout. Cq-Depend: chromium:4519688 Change-Id: I09948ceac0a6a1cb109322fc4856b8b486318664 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75184 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-05-15mb/msi/ms7d25: Update USB port macrosMichał Żygowski
Update USB port macros: - change onboard ports to SHORT: MYSTIC LIGHT, LAN_USB1, PS2_USB1, HUB to USB 2.0 headers, HUB to rear USB 2.0 - change USB type C header to LONG which caused hard lockups on the port making it unable to enumerate in UEFI Payload and Linux - add empty definitions for USBr ports Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I91198aa713e9084ff3906c267ee1b37b10c71843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69820 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-15mb/google/dedede/var/taranza: Copy devicetree and GPIO from var/dibbiSheng-Liang Pan
copy from dibbi since taranza base on dibbi,this is only for first initial configuration, will update the more setting afterward. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ia319f65897c0fea2f0558c20a5bc36bb6fbaea96 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74934 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-05-15mb/google/dedede/var/taranza: Generate SPD ID for supported partsSheng-Liang Pan
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. BUG=b:277664211 BRANCH=dedede TEST=build Signed-off-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I6bbb67ccdd8ebc21719921d00320907f8dbb285f Reviewed-on: https://review.coreboot.org/c/coreboot/+/74933 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14mb/google/rex: Add variant specific SOC chip config update functionAnil Kumar
This patch adds support for variant specific chip config update similar to commit 061a93f93d2 ("mb/google/brya: Add variant specific soc chip config update"). Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I60a4042cba608fd527527af9340ec0215f3086ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/75046 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-14mb/google/rex/var/screebo: Add initial devicetree configKun Liu
add initial devicetree config for screebo BUG=b:276814951 TEST=emerge-rex coreboot Change-Id: Ie64d0e50ec22b3e363597af64eb723ef1f86dfa8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-05-14mb/google/corsola: Add support for MIPI panelRuihai Zhou
The detachable Starmie will use MIPI panels, which require reading serializable data from the CBFS. So we add MIPI panel support to the display configuration and align the configuration sequence with the panels that use MIPI bridges. The PMIC Datasheet: TPS65132-Single-Inductor-Dual-Output-Power-Supply.pdf BUG=b:275470328 BRANCH=corsola TEST=emerge-corsola coreboot chromeos-bootimage and display normally Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: I6f079e54f0317ff2f685f0e3834ebd1ceb8e9fcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/74051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-05-14mb/facebook/fbg1701/board_mboot.h: Remove config from mb_log_listFrans Hendriks
Error message ´Cannot map compressed file config without cbfs_cache' is reported. Compressed parts of CBFS can not be used during bootblock stage. Remove config from mb_log_list. Will be added to verified items by CB:74752. BUG=NA TEST=booting and verify log on facebook FBG1701 Change-Id: Iacf023bc8b9c2ebc66137c4ea683589751a30d2f Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-05-14mb/google/nissa/var/uldren: Add wifi sar tableDtrain Hsu
Add wifi sar table for uldren BUG=b:279679700 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I9e3d7a06beb673b204f2dfe8e7beb919730aa885 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75010 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-14screebo: fix the lp5ccc config from 0x55 to 0xaaSimon Zhou
BUG=b:278022971 TEST=verified on screebo Change-Id: I16f1d66ca7f885120358eb2a2d3c6fb111319f11 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75173 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14mb/google/myst/Kconfig: Select SPI_FLASH_EXIT_4_BYTE_ADDR_MODEFred Reitberger
When using a 32-MiB ROM chip, the ABL leaves the SPI flash in 4-byte addressing mode, so ensure the driver exits that mode for regular operation. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I9a846be743a65ffe5b3ef94e20e0b5fc5e273961 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75182 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-05-14mb/google/hades: update TPM IRQ in early gpio tableEric Lai
TPM IRQ should be A20 not A13. RAM table is correct. BUG=b:282164589 TEST=able to boot up Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I82a709cc280288d612c65697b8da3c4274d4cd3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/75191 Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-14mb/google/hades: Correct TPM I2C bus to 3Eric Lai
Follow schematic to correct I2C bus. BUG=b:282164589 TEST=able to boot up Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I277e5190302c98dbce809d09c1a32fac758aa8e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-05-13mb/samsung/lumpy: Adjust touchpad ACPI for Windows driversReddestDream
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. Change the interrupt type from EDGE to LEVEL. TEST=build/boot samsung/lumpy, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: Ie4268b4de5779ee148699c7bef8c700a99816f1e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13mb/google/parrot: Adjust touchpad ACPI for Windows driversReddestDream
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. TEST=build/boot google/parrot, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: Ic164244eceb52221653bd60f7217f9a09e38c1b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75180 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13mb/google/butterfly: Adjust touchpad ACPI for Windows driversMatt DeVillier
Adjust the touchpad HID/CID/HRV to allow coolstar's crostouchpad Windows drivers to properly attach. Change the interrupt type from EDGE to LEVEL. TEST=build/boot google/butterfly, verify touchpad functional under both Windows 10/11 and Linux, verify Windows overlay driver correctly remaps top row keys. Change-Id: I971795becfb05fb42921ff6f40a20892f4f5654a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-05-13mb/google/stout: Use board-specific PS2M HID/CID to enable multitouchMatt DeVillier
Use board-specific ASL for PS2-attached trackpad rather than the EC/SIO default, so that Windows installs a multitouch-capable driver rather than the standard PS2 mouse driver. TEST=build/boot Win11 on google/stout, verify trackpad is multitouch capable. Change-Id: Id93bbe53f35b1e2c35e36d8175889786b9f5de8b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75176 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-05-13mb/prodrive/hermes: Ensure VMX setting is appliedAngel Pons
VMX is enabled through a bit in the IA32_FEATURE_CONTROL MSR, which can be locked. The MSR remains locked after a non-power cycle reset, though. If the MSR is locked, coreboot bails out and leaves VMX in the state it was found. Because of this, changes to the VMX enable option in the BMC only take effect after the system is power cycled. This behaviour is highly undesirable because users are likely not aware that a power cycle is required for changes to VMX state to take effect. So, if VMX is supported, the IA32_FEATURE_CONTROL MSR is locked and the current VMX state does not match the requested state, then issue a full reset. This will power cycle the system and unlock the MSR, so that the desired VMX state can be programmed into the MSR. This is checked early to avoid needlessly doing time-consuming operations (running FSP) twice if we know we will need to power cycle the system anyway. Note that a user may change the VMX setting after the newly-added check but before the setting is read in ramstage to program the MSR, but this is a non-issue as firmware settings need a reset to take effect anyway. TEST: Toggle VMX setting in BMC and reboot without power cycle, observe coreboot automatically issues a power cycle reset because the MSR is locked and the VMX state differs. Verify that the system boots properly with VMX in the correct state after having power cycled. Change-Id: Id9061ba896a7062da45a86fb26eeb58927184dcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-13cpu,nb/amd/pi/00730F01: dynamically generate CPU devicesFelix Held
Instead of having the maximum number of possible CPU objects defined in the DSDT, dynamically generate the number of needed CPU devices in the SSDT like it's done on all other x86 platforms in coreboot. TEST=APU2 still boots and Linux doesn't show any ACPI errors with this patch applied and it prints "ACPI: \_SB_.P000: Found 2 idle states". Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Id6f057ad130a27b371722fa66ce0a982afc43c6c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73073 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-05-12mb/prodrive/hermes: Simplify handling board cfgAngel Pons
The `get_board_settings()` function always returns non-NULL, so there is no need for NULL checks. When only one member is accessed, also drop the local variable and directly dereference the function's return value. Change-Id: I4fc62ca2454f4da7c8ade506064a7b0e6ba48749 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75140 Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-05-12mb/siemens/mc_ehl5: Add PTN3460 eDP-to-LVDS bridgeMario Scheithauer
This mainboard contains in addition to its base variant, mc_ehl2, an LCD panel driven through the PTN3460 eDP-to-LVDS bridge. This patch enables the PTN3460 support by adding the device to devicetree.cb and board-specific configuration parameters in lcd_panel.c. BUG=none TEST=Boot with the LCD panel attached and observe whether the picture is stable and free of artifacts coming from wrong resolution and timing. Change-Id: I196d7ceeb7ac241c9b95db2ef791a5f3ff7890a7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74936 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-12mb/siemens/mc_ehl5: Add new board variant based on mc_ehl2Mario Scheithauer
This mainboard is based on mc_ehl2. In a first step, it contains a copy of mc_ehl2 directory with minimum changes. Special adaptations for mc_ehl5 mainboard will follow in separate commits. Change-Id: Id80f8eb49dd2fed0ed1ffc479d47d8669eca84c9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-05-12mb/google/nissa/var/uldren: Fix Touch screen power sequenceIan Feng
Based on touchscreen product spec. For uldren variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). BUG=b:279989974 TEST=Build and boot to OS in uldren. Touch screen is workable. Change-Id: Ib1b1ce80aa1dd8c312e3663fc50c9e9f53cc07fe Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74835 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-05-12mb/prodrive/atlas: Shorten FSP-M UPD statementsAngel Pons
Replace `memupd->FspmConfig.` with `mcfg->` for the sake of brevity. Change-Id: If2e7cccca955b0c1e07c1ecf100d29a923107856 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75136 Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-12mb/google/rex: Set WWAN_RF_DISABLE_ODL to NCTarun Tuli
This signal isn't functionally being used and is causing leakage during suspend. Set it to NC. BUG=b:279762779 TEST=builds. WWAN functional. Change-Id: I93f2b0a781e250678280b57e4ab1d80ef27ff460 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75053 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-05-12mb/prodrive/atlas: Make default SN/PN not emptyAngel Pons
If reading the serial/part number fails, returning an empty string is very confusing. Instead, return "INVALID" to make problems obvious. Change-Id: I3c174ca76d51b44456c7b68f4fcffb4c8f9379be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-05-12mb/asus/p8z77-m: Make onboard NIC a child device below PCIe port 5Fabian Groffen
The Realtek RTL8111F NIC is currently not defined at all, nor as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as it's appropriate for on-board ethernet devices. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I95f01a466a59234d1cbe2420f208bf58ae28fcc6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-12mb/asus/p8z77-m: Add TPM configFabian Groffen
This board has a TPM connector, enable support for it. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I1861df95eef15bc2bd29412240d61456eaaad8c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75105 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-05-12mb/google/brya: Fix typo in gma-mainboards filenameTarun Tuli
Small typo in brask/gma-mainboards-ads Should be brask/gma-mainboards.ads BUG=b:277861633 BRANCH=firmware-brya-14505.B TEST=Builds Change-Id: I9800870dcef13a3e16f6235137e79234a5e6bf83 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75052 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-05-11mb/google/brya: Create gothrax variantYunlong Jia
Create the gothrax variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.). BUG=279614675 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_GOTHRAX Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I129e4a55e4b87091e425a45392024d04f3977c79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74748 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-05-11mb/google/dedede/var/boxy: Disable EXT_VRKevin Yang
The boxy removed the APW8738BQBI-TRG and "disable_external_bypass_vr" should be set to "1" to disable BUG=b:271407334 TEST=emerge-dedede coreboot Signed-off-by: Kevin Yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: Ic6667e93de41e84f67363ab7554fe755fe50684a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74889 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 09:21:31 +0000