summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2023-03-17mb/google/nissa/var/uldren: Create RAM ID tablevan_chen
DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) K3KL6L60GM-MGCT 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) K3KL8L80CM-MGCT 2 (0010) H58G56BK7BX068 2 (0010) BUG=b:270103716 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ia53c2be2ec606f42ac8bca06103b028e62ae6dbc Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73733 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-03-17mb/google/nissa/var/yavilla: Generate SPD ID for supported memory partsTony Huang
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) H58G56BK7BX068 1 (0001) MT62F1G32D2DS-026 WT:B 1 (0001) K3KL8L80CM-MGCT 1 (0001) H58G66BK7BX067 2 (0010) MT62F2G32D4DS-026 WT:B 2 (0010) K3KL9L90CM-MGCT 2 (0010) BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I82919919ec33d6bf9d86132490df754873b5df88 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73722 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-17mb/google/brya: Create yavilla variantTony Huang
Create the yavilla variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:273791621 BRANCH=firmware-nissa-15217.B TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_YAVILLA Change-Id: I4539090da5e1db474a8f58a42aecc38659959f75 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-17mb/google/brya/var/omnigul: Update RAM ID tableJamie Chen
Add new ram_id:0010 for Micron MT62F1G32D2DS-023 WT:B. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) MT62F512M32D2DR-031 WT:B 1 (0001) H58G56BK8BX068 2 (0010) MT62F1G32D2DS-023 WT:B 2 (0010) BUG=b:273138520 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: Idc08624469590096047e5f77fb2e4ffb733f09ec Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73726 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-03-17mb/google/skyrim/var/crystaldrift: Add 1 Micron parts to RAM ID tableYunlong Jia
Add new memory MT62F2G32D4DS-026 WT:B to replace H9JCNNNBK3MLYR-N6E． Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-026 WT:B 2 (0010) MT62F2G32D4DS-026 WT:B 3 (0011) K3LKBKB0BM-MGCP 4 (0100) BUG=b:273177939 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I545bd8d9f88e7b3055acef4066769e6fcb766cc0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73681 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-16mb/google/brya/var/taniks: Remove unused temp sensor settingJoey Peng
Rwmove temp sensor 3 for taniks since we do not use it. BUG=b:265075696 TEST=emerge-brya coreboot, flash to DUT and will not see error messages Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib2c0cc8f1b2e65616c71d66632144ac89ca09fa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73718 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-16mb/intel/mtlrvp: Add new MTL-P board variant for MCHP1727Harsha B R
This patch will add new board variant to enable MCHP1727 EC Card for MTL-RVP BUG=b:262800416 BRANCH=none TEST=check if you can observe MEC EC option as part of make menuconfig. Able to boot to ChromeOS with Microchip EC. Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ie0d3c37bcab5e4b90a131e17996c4b6dcbae7d5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/70668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-16mb/google/brask/var/aurash: Allow USB2/3 wakeups to (un)plug events in dtZoey Wu
BUG=b:271373437 BRANCH=none TEST=Verify USB-A device could wake up Aurash. Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com> Change-Id: I67fc02d6c5660e0e3d1ab95bbda8ace1dc14b524 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73414 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15mb/google/rex: Add Hayden Bridge (HB) to USB_DB FW_CONFIGSubrata Banik
This patch increases FW_CONFIG for USB_DB to 3-bits. BUG=b:273346973 TEST=Able to build and boot google/rex with Proto 2 SKU Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ib07ba1d54e7f7e2b09a99438529e503d9c9edb7d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73719 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-15mb/google/dedede: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:268377440 BRANCH=firmware-dedede-13606.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I24f929ae60a406d0091956dc6cab3e2876ca23e9 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73618 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15mb/google/rex: Configure _DSC for camera devicesJamie Ryu
Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that the driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:268607999 TEST=Build and boot rex proto1 to OS and verify privacy LED behavior. Change-Id: Ife849f7407b02867ddb992d7eebb08b0b44aecc8 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15mb/google/skyrim: Do not pass recovery APCBKarthikeyan Ramasubramanian
If recovery APCB is not passed, amdfwtool will build amdfw*.rom with AMD_BIOS_APCB_BK entry pointing to the same offset as AMD_BIOS_APCB entry. This will help to save 40 KiB flash space in each FW slot. On ChromeOS, this means saving ~120 KiB flash space. BUG=b:240696002 TEST=Build and boot to OS in Skyrim. Change-Id: Ib3bbc1eededae20b2cd48f514722a207c46536a0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73662 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-15mb/google/brya/var/omnigul: Correct mux_conn for USB C1Dtrain Hsu
Modify USB C1 mux_conn to 1. It should match ec settings. BUG=b:272394875, b:272667290 BRANCH=firmware-brya-14505.B TEST=Plug USB-C hub in USB C1 and could recognize USB drive and hdmi. Change-Id: I61b77405d1790b044174cef954e5bf910141f424 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-15mb/google/brya/var/omnigul:Fixed can't detect 3.5mm headphone jackJamie Chen
1. Modify irq_gpio GPP_H0 -> GPP_A23 BUG=b:272218750 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8e178b149015ed8027b547e4c2109b3aef8a7484 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-15mb/google/brya/var/omnigul:Fixed Touch screen has no actionJamie Chen
1. Add generic.stop_gpio = GPP_C6 2. Add c.stop_off_delay_ms = 2 BUG=b:271966059 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I33857443d8a68e7b50ac5f8f08afc017fe4f5a59 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73569 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-14mb/google/skyrim/var/frostflow: Update the STT settingsFrank Wu
According to file thermal_table_0310, adjust the STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Change-Id: If4500c85dcea051aca15602f1fb4b5ec80b73e67 Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73698 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
2023-03-14mb/google/dedede/var/dibbi: Configure I2C times for audioAmanda Huang
Configure the I2C bus high and low time for audio. BUG=b:271804915 BRANCH=dedede TEST=Build and confirm I2C clock for audio is between 380 kHz and 400 kHz Change-Id: I2987a39abc5527844424edfa1cf70d5c5cea5357 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-03-14mb/google/brya: Create uldren variantvan_chen
Create the uldren variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:271513530 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_ULDREN Change-Id: Ibbcd34fb4ef1f7464f0c94d2fcf75280c3eed6be Signed-off-by: van_chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73680 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-13mb/google/skyrim/var/winterhold: Change touch controller T3EricKY Cheng
Change stop_delay_ms time(T3) from 180 to 150 to meet specification. T3 min-value of HID-I2C should be 150ms. BUG=b:267280863 TEST=emerge-skyrim coreboot chromeos-bootimage. Change-Id: I7ef7db4edaecece1fa5ab07e30a80e556ed35f8b Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-13mb/google/brask/var/kinox: Allow USB2/3 hotplug to wakeup S0ixDtrain Hsu
Allow USB2/3 hotplug event to wake up S0ix. BUG=b:236189998 BRANCH=firmware-brya-14505.B TEST=Verify USB-A device could wake up Kinox Change-Id: I8aeeeac6c21289b70bdc7ffddc57687ac39e8456 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-10mb/starlabs/starbook/adl: Enable ASPMSean Rhodes
Enable ASPM for RP5 (wireless) and RP9 (SSD). Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I428040caf171bdcfedc285cdeddc55bcbec40f3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/72753 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mb/google/skyrim/var/markarth: Add 2 Micron parts to RAM ID tableJohn Su
Add new ram_id:0011 for Micron MT62F1G32D2DS-023 WT:B. Add new ram_id:0100 for Micron MT62F2G32D4DS-023 WT:B. DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) MT62F1G32D2DS-023 WT:B 3 (0011) H58G66BK8BX067 4 (0100) MT62F2G32D4DS-023 WT:B 4 (0100) BUG=b:271188237 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: I59a6a6dff249cd4fe982a4de824848f1bac0ecba Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73510 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mb/google/brya/var/omnigul: Fix SSD can not boot into OSJamie Chen
1. device ref pcie_rp11 -> pcie_rp9 on. BUG=b:270657362 TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: If23785f42466ba94f33d4d15dde96de29dbb3a1e Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73530 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-10mb/google/brya/var/omnigul: Enable ELAN touchscreenDtrain Hsu
Enable ELAN eKTH5015M touchscreen. BUG=b:271966059 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I41eac949f21a48098b445f8d1b05f308672f7ab8 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73584 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-10mb/starlabs/starbook/{tgl,adl}: Set DmiMaxLinkSpeed to 4Sean Rhodes
Set DmiMaxLinkSpeed to 4 in FSP to ensure that FSP always supports PCIe Gen 4 drives. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I0e31919122dacfbdc2486fa8216a28b479f3bd00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-10amdfwtool: Add HW IPCFG file whose subprog is 1Zheng Bao
And rename PSP_HW_IPCFG_FILE to PSP_HW_IPCFG_FILE_SUB0 Change-Id: Ia1ab8482074105de367905be2b4b0418066823d2 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-03-10Revert "mb/google/skyrim: Create whiterun variant"Jon Murphy
For simplicity, OEM devices are given a single codename per build variant. Winterhold was intended to be the lead device and was chosen as the code name for this OEM. Unfortunately, Winterhold was cancelled. We attempted to rename Winterhold to Whiterun to avoid future confusion. Again, unfortunately, since some devices were already built, changing the name requires a manual change to force the firmware to be taken by the DUT. This was not a reasonable path forward, so we're abandoning the naming to Whiterun. This reverts commit af69de494e2c32140ce5e00a1562c2845345b1bf. Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Idef95f0f4f369b235937e1806ce57c427e441f21 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73583 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-09Revert "ec/starlabs/merlin: Add support for enabling the mirror flag"Sean Rhodes
This reverts commit b42ca4d0b2fafe7214396d30a1a833ac33cf85bc. Reason for revert: The mirror flag "0x01" is mirror once, which relies on the EC remembering that it's been mirrored. However, the EC forgets this if it's been without power for 20 minutes or so. Even if power is connected then, it'll instantly try to mirror and it can't charge whilst doing it. It can either result in incomplete EC firmware, or a loop where it's constantly trying to mirror. Change-Id: I79da9143cc63459e7e29431eff2cb14200424b37 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09Revert "mb/starlabs/*: Enable the Mirror flag for boards that support"Sean Rhodes
This reverts commit 35354583cdc94ced026975ced5170e1c094b258e. Reason for revert: The mirror flag "0x01" is mirror once, which relies on the EC remembering that it's been mirrored. However, the EC forgets this if it's been without power for 20 minutes or so. Even if power is connected then, it'll instantly try to mirror and it can't charge whilst doing it. It can either result in incomplete EC firmware, or a loop where it's constantly trying to mirror. Change-Id: Ie82cbafd4bea2416526e2847738802a05ed45582 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-03-09mb/google/guybrush: Store XHCI resourcesRobert Zieba
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. Example elog contents: ``` 250 | 2022-10-11 16:04:49 | S0ix Enter 251 | 2022-10-11 16:04:53 | S0ix Exit 252 | 2022-10-11 16:04:53 | Wake Source | GPE # | 31 253 | 2022-10-11 16:04:53 | Wake Source | PME - XHCI (USB 2.0 port) | 1 254 | 2022-10-11 16:05:24 | S0ix Enter 255 | 2022-10-11 16:05:27 | S0ix Exit 256 | 2022-10-11 16:05:27 | Wake Source | GPE # | 31 257 | 2022-10-11 16:05:27 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BRANCH=guybrush BUG=b:186792595 TEST=Ran on nipperkin, verified that XHCI wake events show up in elog Change-Id: I1d0911df9e3102791bf7b5723ac38e2ba82a9db6 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68326 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/google/skyrim: Store XHCI PCI resourcessRobert Zieba
Implement `smm_mainboard_pci_resource_store_init` to store the resources for XHCI devices. These stored resources are later used by the elog code to log XHCI wake events. Example elog contents: ``` 244 | 2022-10-11 15:49:24 | S0ix Enter 245 | 2022-10-11 15:49:29 | S0ix Exit 246 | 2022-10-11 15:49:29 | Wake Source | GPE # | 31 247 | 2022-10-11 15:49:29 | Wake Source | PME - XHCI (USB 2.0 port) | 256 248 | 2022-10-11 15:50:08 | S0ix Enter 249 | 2022-10-11 15:50:16 | S0ix Exit 250 | 2022-10-11 15:50:16 | Wake Source | GPE # | 31 251 | 2022-10-11 15:50:16 | Wake Source | PME - XHCI (USB 2.0 port) | 257 ``` BUG=b:186792595 TEST=Ran on skyrim proto, verified that wake events show in elog Change-Id: I529f541a8932267a8825773ddc582beafb27da63 Signed-off-by: Robert Zieba <robertzieba@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68325 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/google/skyrim: override winterhold PCIe configMartin Roth
Winterhold boards populate either NVMe or eMMC, but not both. This means that there is always one link that is unpopulated. The PCIe configuration code takes longer to verify that a link is unpopulated than to just train the link, so this slows down the boot by roughly 80ms vs the case when the device is present. Not training the device at all lowers boot time by another 20ms, for a total of 100ms saved. Looking at the NVMe CLKREQ signal before initializing the ports allows us to identify which device is populated and only initialize that device. BUG=b:271569628 TEST=Boot Whiterun and eMMC or NVMe correctly work, boot time is lower. BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I0b87f5e968cd1c87e62a1c0fbdee1fc0723f655d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09mb/google/skyrim: drop link_hotplug from port descriptorsMatt DeVillier
These ports are not hot pluggable, so drop the parameter, which will result it in being set to zero / not enabled. BUG=none TEST=build boot skyrim, verify all PCIe devices functional. BRANCH=skyrim Change-Id: Iaa55cc765e8f073b31f25771633789ac13e2fffa Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Enable L1 ASPM substates for PCIe devicesMatt DeVillier
Enable both L1.1 and L1.2 substates for the WiFi, SD card reader, and SSD (both NVMe and eMMC). If a given device does not support a particular substate, then it will not be enabled during PCIe enumeration by coreboot. BUG=b:270690572 TEST=build/boot multiple skyrim/whiterun/frostflow SKUs with different storage configs, verify WiFi/SD card/SSD all functional and have L1 substates enabled insofar as they are supported by the device. BRANCH=skyrim Change-Id: Ib84df8b9d97282ae696414e52c4a65cfb0a81194 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-09mb/google/skyrim: Allow port descriptors to be overriddenMartin Roth
This allows variants to override the skyrim port descriptors. BUG=None TEST=Tested with following patches BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8cff44f5b39d130a7191a69970cae8a88bb5d475 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-03-09mb/google/dedede/var/kracko: Generate new SPD ID for new memory partsRobert Chen
Add new memory parts in memory_parts_used.txt and generate SPD id for these parts: Hynix H54G46CYRBX267 Samsung K4U6E3S4AB-MGCL BUG=b:272173189 TEST=run part_id_gen to generate SPD id Change-Id: I141bda6eda3f658ca608c86ad0b320d018598514 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73554 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/google/brya/var/marasov: Half touch power-on delay to 150 msFrank Chu
Decrease Touch i2c delay during power-on sequence from 300 ms to 150 ms to make S0ix resume time meet requirement. BUG=b:264199989 TEST=Run the following test from chroot. test_that -b {BOARD_NAME} {device IP} f:.*power_UiResume/control Check seconds_system_resume value less than 500 msec Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ib81a9c1a90589b8b08e6ce6471db2abef96047ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/73532 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-09mb/asrock/b75pro3-m: Advertise RTL NIC as onboard ethernet deviceFabian Groffen
Move the onboard Realtek NIC definition to a child device of PCIe port 6. This makes sure it is advertised as "onboard", such that it appears as eno0 on systemd/udev-based systems. This commit is very similar to https://review.coreboot.org/c/coreboot/+/73516 Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I0550ee9faddd65011ad914aef413a6d1b316c5ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/73519 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-08mb/google/skyrim: Enable SPL fusing on whiterun/winterholdMartin Roth
Enable whiterun/winterhold platforms to send the fuse SPL (security patch level) command to the PSP. BUG=b:254568112 TEST=On a platform that supports SPL fusing, a message indicating that fusing was requested will appear in the coreboot console log, followed by a puff of smoke when the fuse is set and the message "OK" again on the debug console. (Kidding about the smoke.) BRANCH=skyrim Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I45578597234ba672c89ac421b4626088faca27d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72914 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-03-08mb/google/rex: Rename touchscreen signals as per latest Rex schematicsEran Mitrani
Touchscreen signals were renamed for Rex schematics dated 21st Dec'22. This CL fixes the comments for those signals. BUG=b:263411413 TEST=None required (changed comments only) Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Ic40ef943d199d9f4a2bec9c0e6d4820224ef6adc Reviewed-on: https://review.coreboot.org/c/coreboot/+/71795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08mb/asrock/b75m-itx: Make NIC a child device below PCIe port 4Kevin Keijzer
The Realtek RTL8111E NIC is currently not defined as a child device, resulting in the on_board flag not being set to 1. This means that Linux / udev will call the device enp3s0 rather than eno0, as is appropriate for on-board ethernet devices. Additionally, the comment in devicetree.cb stating that PCIe port 6 is the ethernet controller is incorrect. It's actually port 4. This patch moves the comment to the right port, and defines the NIC as a child device of said port, so that it's properly defined as an on-board device. Link: https://mail.coreboot.org/hyperkitty/list/coreboot@coreboot.org/thread/TFWNW3Y7IWTFD4KIBVNQYW3DODJ6SSC2/ Change-Id: Ie1e3a757a6bd6c7dd1702ced177d13711978dcc4 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73516 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Fabian Groffen <grobian@gentoo.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-08mb/lenovo: Enable VBOOT_VBNV_FLASHYu-Ping Wu
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with VBOOT_VBNV_FLASH for lenovo boards: t400, t410, t420, t420s, t430, t430s, t520, t530, x131e, x1_carbon_gen1, x60, x200, x201, x220, x230. A 0x2000 RW_NVRAM region is allocated for them, with the COREBOOT size reduced by 0x2000. Also remove the VBOOT_VBNV_OFFSET config, since it's only used for VBOOT_VBNV_CMOS. [1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1 BUG=b:235293589 TEST=./util/abuild/abuild -t LENOVO_T430S -a # with VBOOT enabled Change-Id: I7e29db7eeceec499fbbcf902a26bfe9a2076de40 Signed-off-by: Yu-Ping Wu <yupingso@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-08mb/google/brask/var/constitution: update gpio settingsMorris Hsu
Remove GPP_D11,GPP_D12 in ramstage, follow baseboard brask setting. TEST=emerge-brask coreboot make sure HDMIA can display Change-Id: I953170f006699e3dc9d6111ded8234f66b9162c7 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-08mb/{brya,hdaes}/include/ec: Add EC_HOST_EVENT_GPUTarun Tuli
EC_HOST_EVENT_GPU was renamed from EC_HOST_EVENT_USB_CHARGER and thought to no longer be used. It was subsequently removed in I9e3e0e9b45385766343489ae2d8fc43fb0954923 Add back the mask for this event as it is infact required on certain Brya (Agah) and Hades variants. Signed-off-by: Tarun Tuli <taruntuli@google.com> BUG=b:216485035,b:258126464,b:266631157 BRANCH=none TEST=D-notifier events are received again from EC Change-Id: I9d7bf52efa9572e1bbd2f307420e09a7398a1ca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73217 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-08mb/google/nissa/var/craask: Extend sd_hold for touchpad/touchscreenTyler Wang
Extend sd_hold to meet touchpad/touchscreen SPEC. touchscreen: tHD > 100 ns touchpad: 900 ns > tHD > 300 ns After applied the change, the tHD meets reqirement. touchscreen: 35 ns --> 260 ns touchpad: 43 ns --> 368 ns BUG=b:271524470 TEST=build and measure the timing meet SPEC Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Iec2f72da80ffe8d4dd494caabbe1a97e52a81e78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2023-03-07mb/google/hades: Change memory to SODIMMEric Lai
Add SODIMM support, drop the solderdown based on schematics. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I85ec79c3d8f1147a875c4d04017bb50347121ebb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-03-07mb/google/geralt: Set +-5.7V to TPS65132s EEPROMyangcong
It is necessary to increase the AVDD/AVEE of TPS65132s PMIC to +-5.7V for powering on BOE_TV110C9M_LL0. So we set the default value to +-5.7V and program the value to the EEPROM when configuring the display at the first time. In this way, TPS65132s could load the correct setting from the EEPROM after booting into kernel. BUG=b:268292556 TEST=test firmware display pass and AVDD/AVEE is +-5.7V on Geralt. Change-Id: I29236818444cac84d42386a371cd8934048ff948 Signed-off-by: yangcong <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73443 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-03-07mb/google/skyrim: Move SPL setting to variantsChris Wang
Move the sustained_power_limit_mW setting from the baseboard to variants. This setting will be needed before STT is enabled, but once STT is enabled, this setting should be removed. BUG=b:265267957 BRANCH=none TEST=Build/Boot to ChromeOS Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I7b9779600cfa8c7581732e936a714728fd618d20 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-03-07mb/google/brya/var/taeko: Enable Fast VMode for taekoJoey Peng
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I82c2016d9dfb39ff7b372815737d4ae62875340c Reviewed-on: https://review.coreboot.org/c/coreboot/+/73373 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-07mb/google/brya/var/taeko: use RPL FSP headersJoey Peng
To support an RPL SKU on taeko, taeko must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for taeko so that it will use the RPL FSP headers for taeko. BUG=b:270242461 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot taeko to kernel. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Cq-Depend: chrome-internal:5544049, chromium:4302529 Change-Id: Ic97400555dabb237325e7c4a8d5edcbb4779cdb1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-06mb/asrock/b75m-itx: Add Sandy/Ivy Bridge board B75M-ITXFabian Groffen
This board is based off b75pro3-m, which is very similar. Compared to it, it just lacks a COM1 header, and the secondary ASMedia SATA3 controller. Tested with: CPUs: - Core i5-3330 - Core i5-3470 - Core i7-3770 RAM: - single bank 4GB CL11 - two banks 4+4GB CL9 - two banks 8+8GB CL10 OS: - Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72) Working: - GRUB2 payload with embedded default config for boot from USB, disk - UEFI EDK2 payload - Intel ME stripped - Native raminit - Integrated graphics with libgfxinit (HDMI, DVI and VGA) - (boot from) SATA2, SATA3, ports - Rear USB 2 and 3 ports (supports boot) - Internal USB 3.0 ports - Realtek GbE NIC - 2.0 channel audio via lineout jack output - ACPI (power button triggers OS event) Untested: - Internal USB 2.0 ports - eSATA port - 7.1 channel audio Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: Ia6a6eb3e922920f4afbcb7828cd2b779b9caebcb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73097 Reviewed-by: Kevin Keijzer Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-05mb/asrock/b75pro3-m: Add CMOS layout/defaults and vbt.binKevin Keijzer
The ASRock B75 Pro3-M port was lacking a cmos.default and cmos.layout, which means nvramtool could not be used to change any nvram values, and the defaults were always being used. I have "borrowed" the files from the similar h77pro4-m port, which work fine for the b75pro3-m. I can now adjust things like gfx_uma_size and power_on_after_fail, which are quite useful to be able to modify. Additionally, this board did not have a data.vbt, so I extracted vbt.bin from the VGABIOS and added it. Change-Id: I40822f2f7b013b7ac0658d66d7972b447066d593 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73451 Reviewed-by: Fabian Groffen <grobian@gentoo.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-03-05mb/asrock/b75pro3-m: Fix S3 resume and hardware monitoringKevin Keijzer
On the ASRock B75 Pro3-M, resuming from S3 has always been broken; see commit 928c6c6336f2 (mainboard/asrock: add ASRock B75 Pro3-M). This was because 3VSBSW# was not enabled during S3, causing the board to reboot instead of resume. This change enables 3VSBSW# during S3, which leads to S3 resume working normally. Another issue with this board was that hardware monitoring was not working. The nct6775 Linux kernel module could not be loaded, due to the device having a base I/O port of 0. This change also enables the Super I/O properly, so that sensors-detect can find the sensor and the kernel module can be used. Change-Id: I6e504fe4b60da1d7b9830bea5029101bb8cebcb5 Signed-off-by: Kevin Keijzer <kevin@quietlife.nl> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73450 Reviewed-by: Fabian Groffen <grobian@gentoo.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-05mb/google/skyrim: Disable cardbus supportMartin Roth
Skyrim does not have a cardbus socket, so disable it. Maybe cardbus support shouldn't be enabled by default? BUG=None TEST="PC Card (PCMCIA) is supported" no longer shows up in dmidecode output. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic941b075e8b5082b5e61e728a77fd79c0ebba35e Reviewed-on: https://review.coreboot.org/c/coreboot/+/73167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-05skyrim/overridetree.cb: Remove gpio_keys ACPI nodeTim Van Patten
Only Frostflow supports the stylus, so remove the gpio-keys ACPI node from Skyrim. The Kconfig value DRIVERS_GENERIC_GPIO_KEYS is still enabled for all Skyrim variants, since coreboot will drop the driver from the BIOS image if there are no references to it (in the devicetree). If some other design ends up using the stylus in the future we won't have to bring it back. BUG: none TEST: build_packages --board=skyrim chromeos-bootimage --autosetgov Change-Id: I9ffe215741b72b678d74405769f35167d8ded4b5 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73299 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-03-05mb/google/geralt: Add NAU8318 support for GeraltTrevor Wu
Add a config "USE_NAU8318" to enable NAU8318 support. NAU8318 is another speaker used in Geralt. NAU8318 supports beep function via GPIO control. So we configure the GPIO pins and pass them to the payload. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I21009a20809f398de4628ff0c11bcbd0e7591443 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73413 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add MAX98390 support for GeraltTrevor Wu
Add a config "USE_MAX98390" to enable MAX98390 support. MAX98390 is an I2S smart amplifier used in Geralt. It is also the default speaker for Geralt reference board. BUG=b:250459803 BRANCH=none TEST=Verify beep function through CLI in depthcharge successfully. Change-Id: I814f440cc5ac2a13404d01fb3baafeec092b1e74 Signed-off-by: Trevor Wu <trevor.wu@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73412 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/geralt: Add mtcmos bus protection for displayLiju-Clr Chen
Enable bus protection for display to avoid bus hang and incomplete bus transaction. BUG=b:264204465 TEST=test firmware and kernel display pass for MIPI panel on geralt. Change-Id: Iac61a69f2b84966dd468442daaa59d83eec775aa Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Signed-off-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73411 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-03-05mb/google/hades: Add baseboard device treeEric Lai
Add minimum device tree. Leave IOs default disable to optimize variant override complexity. BUG=b:271199379 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ibb056c07193b4265352a9ec74829dcf02a9340bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/73415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-03-04mb/google/skyrim/var/markarth: Update RAM ID tableJohn Su
Add new ram_id:0011 for Hynix H58G56BK8BX068. Add new ram_id:0100 for Hynix H58G66BK8BX067. The RAM ID table has been assigned as: DRAM Part Name ID to assign K3KL8L80CM-MGCT 0 (0000) H58G56BK7BX068 0 (0000) MT62F1G32D2DS-026 WT:B 0 (0000) K3KL9L90CM-MGCT 1 (0001) H58G66BK7BX067 1 (0001) MT62F2G32D4DS-026 WT:B 1 (0001) MT62F512M32D2DR-031 WT:B 2 (0010) H58G56BK8BX068 3 (0011) H58G66BK8BX067 4 (0100) BUG=b:270629852 BRANCH=None TEST=FW_NAME=markarth emerge-skyrim coreboot Change-Id: Ida5c8354af71cd92c056a33e38d1fadfc5704977 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73252 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-04mb/google/skyrim/var/frostflow: Update DPTC and STT settingsFrank Wu
According to thermal_table_0215, adjust DPTC and STT settings. BRANCH=none BUG=b:257149501 TEST=emerge-skyrim coreboot chromeos-bootimage Then the thermal team has verified. Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: Id7df3f9bfa3f0e1337c502bc7db9e09e12cd956a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73081 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04soc/amd/mendocino: Remove the SPL DPTC parameterChris Wang
The SPL parameter for DPTC settings is not available for STT-enabled platforms. It needs to be removed to avoid confusing STT calculations. BUG=b:265267957 BRANCH=none TEST=Run the WebGL aquarium with 5000 fish and verify that there are no power drop peaks. Change-Id: I8e6dad7d24883f8aadce83ebac401ecd4137d61a Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-03-04mb/system76/adl-p: Add Oryx Pro 10 as a variantTim Crawford
oryp10 is nearly identical to the oryp9, with the differences being: - Uses DDR5 RAM instead of DDR4 RAM - Uses Realtek ALC1306 instead of TI TAS5825M - Has an option for OLED display Change-Id: I0cf46cb5d10098dd31f0dc3c620db0c7e20ffba4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/69210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/adl: Add Oryx Pro 9 as a variantTim Crawford
The Oryx Pro 9 (oryp9) is an Alder Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - Both M.2 NVME SSD slots (with MZVL2500HCJQ) - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - Discrete/Hybrid graphics - HDMI output (requires NVIDIA GPU) - Mini DisplayPort output (requires NVIDIA GPU) - Detection of devices in TBT slot on boot Change-Id: I8aac3e83f4423f444cb9ce8aa562ba465eb718c1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/adl: Add Lemur Pro 11 as a variantTim Crawford
The Lemur Pro 11 (lemp11) is an Alder Lake-U board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard, touchpad - DIMM slot (with NMSO480E82-3200EA00) - M.2 NVMe SSD (with MZVL2500HCJQ) - M.2 SATA SSD (with WDS100T2B0B) - All USB ports - SD card reader - Webcam - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headset + mic 3.5mm audio - S0ix suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.1.11 - Internal flashing with flashrom v1.2-1203-gf4ddd3234330 Not working: - On-board RAM: Requires CB:65567 - Detection of devices in TBT slot on boot Change-Id: Ic930df1ebacc8c7ef14dbb6c67a97eddb918b365 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/65384 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/google/brask/var/moli: Allow USB2/3 wakeups to (un)plug events in dtScott Chao
BUG=b:230398487 BRANCH=none TEST=Verify USB-A device could wake up Moli. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I1c8daf62dabe674a39b1416d886f9e470ae23a5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73174 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-04mb/system76: Add custom backlight levels for Intel GMATim Crawford
Add custom backlight levels for all models except: - addw1/addw2: Uses an OLED display - bonw14: Does not use the iGPU Change-Id: Ibea37f19acca0d718211fc41706019a92a240c70 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/61301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/system76/tgl-u: Leave TBT LSX0 as FSP configuredTim Crawford
Do not reconfigured LSX0 so that the FSP values are used. Change-Id: I7ef4af2cde4f3260f2bc2efdbf85569b0eb147fb Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71666 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04{ec,mb}/system76: Move smbios_system_wakeup_typeTim Crawford
Move the implementation of smbios_system_wakeup_type from the mainboards to the EC for all models that use System76 EC (everything except KBL). Change-Id: Iaace234ca87e8a05eaa006a438d2c9eb13ce4d76 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-03-04mb/google/brya: remove the skolas baseboardNick Vaccaro
The skolas baseboard is no longer needed, so this change removes the baseboard files for skolas and adjusts the config settings to that variants that used to select BOARD_GOOGLE_BASEBOARD_SKOLAS now select BOARD_GOOGLE_BASEBOARD_BRYA and SOC_INTEL_RAPTORLAKE. BUG=b:271470530 TEST="emerge-brya coreboot chromeos-bootimage", flash image-skolas.bin onto a skolas and verify it boots to kernel. Change-Id: I34cae7e471851aa52a64ce3af7bb506dc67f806b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73388 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-03mb/google/skyrim: Disable USE_SELECTIVE_GOP_INITMartin Roth
This is causing some issues, so disable it until those issues can be resolved. BUG=b:271437658, b:271199389, b:270077971 TEST=Screen always lights up on boot & after S0i3 Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id4aa441e4b4f76168f8243b6abafa1cf1ea08dbd Reviewed-on: https://review.coreboot.org/c/coreboot/+/73393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-03-03drv/i2c/ptn3460: Add 'mainboard' prefix to mainboard-level callbacksJan Samek
As discused earlier, the callback name 'mb_adjust_cfg' was considered too generic. The new naming is chosen to be consistent with other drivers' callback names designed to be used at mainboard level. Also other functions, namely 'mb_get_edid' and 'mb_select_edid_table' are renamed accordingly. BUG=none TEST=Builds for siemens/mc_apl{1,4,5,7} and siemens/mc_ehl boards complete successfully. Change-Id: I4cbec0e72e5f03e94df0faa36765d1a6cd873a7a Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-03mainboard/protectli/vault_ehl: Add initial structureKacper Stojek
This patch adds base code for the Protectli VP2420. The GPIO config has been extracted with inteltool from the stock firmware and then parsed with intelp2m. As of now, the platform runs with edk2 with no apparent issues. Signed-off-by: Kacper Stojek <kacper.stojek@3mdeb.com> Signed-off-by: Artur Kowalski <artur.kowalski@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com> Change-Id: Ia00c27117d48b76db306d3f988f159fc5d50e4a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/72407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
2023-03-02mb/google/rex: Enable VPURavi Sarawadi
BUG=b:270529665 TEST=Verify the build and boot on Rex board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I0e3d3312c546a2a468fb906a08b8d3ec3e96c46a Reviewed-on: https://review.coreboot.org/c/coreboot/+/72417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-03-02mb/starlabs/starbook/adl: Enable the PchHdaAudioLinkHdaEnable UPDSean Rhodes
Enable the PchHdaAudioLinkHdaEnable UPD so that the sound works. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ie3493af340a42035ee537d83b1542be1b87d8f9c Reviewed-on: https://review.coreboot.org/c/coreboot/+/71979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2023-03-02acpi/ec: Handle new host event EC_HOST_EVENT_BODY_DETECT_CHANGETim Van Patten
Handle the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE. Previously, the EC sent the host event EC_HOST_EVENT_MODE_CHANGE when body detection changed between lap/desk mode. However, that event is a wake event, which resulted in spurious AP wake events being triggered when the EC detected lap/desk mode changes while the AP was suspended. To resolve this, the new host event EC_HOST_EVENT_BODY_DETECT_CHANGE was added, which will not be a wake event. This CL adds handling for the new event to acpi/ec.asl to switch DPTC tables when a change is detected. BRANCH=none BUG=b:261141172 TEST=bodydetectmode on|off, verify host event is received Change-Id: Iabeb7891489a209f45504804355f1fa817082976 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73298 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-03-02mb/siemens/mc_ehl*: Correct comment in gpio.cMario Scheithauer
There were two wrong comments in all mc_ehl gpio.c files. This patch corrects the incorrect comments. Change-Id: Iea356db177227d89b91be32a4e2367c612b77350 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72458 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/siemens/mc_ehl4: Remove TPM from devicetree and KconfigMario Scheithauer
This mainboard does not use security features like TPM. Change-Id: Ieebbf12fc844573ffadb089da78062dd2033517a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/siemens/mc_ehl: Move TPM Kconfig switches to variantsMario Scheithauer
The upcoming mc_ehl4 variant is the first Siemens Elkhart Lake mainboard without a TPM. For this reason, the corresponding Kconfig switches must be moved to variant level. To prevent Jenkins build from complaining, the TPM is removed in the following patch. Change-Id: Ic73ccd1b52e57c1cf1dd7337b0e28beaadbece8e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/siemens/mc_ehl2: Set RGMII output impedance manuallyMario Scheithauer
Measurements have shown that the automatic calibrated values for RGMII output impedances are too low. For this reason, set the PMOS value to 16 and the NMOS to 13. Change-Id: Ic3382889d3281faccb03819f9680a9763703b2a1 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73019 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/siemens/mc_ehl4: Add new board variant based on mc_ehl1Mario Scheithauer
This mainboard is based on mc_ehl1. In a first step, it contains a copy of mc_ehl1 directory with minimum changes. Special adaptations for mc_ehl4 mainboard will follow in separate commits. Change-Id: I3c1f2cf4a3dcae58895f6d14a7fce46b2825e6ba Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72427 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-03-02mb/siemens/mc_ehl2: Fix GPIO settingsMario Scheithauer
With the latest hardware revision, the two GPIOs GPP_B15 and GPP_E19 are no longer connected to a native function. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: I266612f041b749aa83b366497b4211fc075c7bd7 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `K3KL6L60GM-MGCT`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign K3KL6L60GM-MGCT 3 (0011) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Id0925ccec014c9c535178ed3d908e60889df624d Reviewed-on: https://review.coreboot.org/c/coreboot/+/73344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02mb/google/rex: Generate LP5 RAM ID for `H58G56BK7BX068`Subrata Banik
Add the support LP5 RAM parts for rex: DRAM Part Name ID to assign H58G56BK7BX068 1 (0001) BUG=b:270708359 TEST=emerge-rex coreboot Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I9eea7e277628992be9b7768a678a50425444002a Reviewed-on: https://review.coreboot.org/c/coreboot/+/73342 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-03-02mb/google/brask/var/constitution: Enable Fast VMode for constitutionMorris Hsu
Fast VMode makes the SoC throttle when the current exceeds the I_TRIP threshold. TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I1e68f708b7740567e24f8a3ddb9832aeec7ee6b5 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73247 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Pablo Ceballos <pceballos@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-03-01mb/google/brya/acpi: Remove extra DC boost byteTarun Tuli
The DC boost bit was intended to be in the Controller Params word rather than its own byte. Correct this error. BUG=b:214581372 TEST=build Change-Id: Ie65e57a351f0fc1f0c80ef320fd87043ee22916c Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73216 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-03-01mb/siemens/mc_ehl3/lcd_panel.c: Set LVDS re-power delay to 1 sJan Samek
The currently used panel type could work with 500 ms but increasing the value to 1 second allows to use a wider range of LVDS LCD panels, as many of them specify the delay of 1 s as minimum. BUG=none TEST=Test link stability using a panel with minimum re-power delay of 1 s. Change-Id: I2dd86e791c1212b67a80d7e6cfc474ad91b26c6b Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-02-28mb/amd/gardenia,pademelon/mainboard: use ACPI_SCI_IRQ definitionFelix Held
Use the ACPI_SCI_IRQ definition for both the PIC and APIC IRQ number in the fch_irq_map table. Before the PIC mapping was set to PIRQ_NC, but both mb/google/kahlee and the other amd mainboards using newer SoCs set both the PIC and APCI IRQ number to ACPI_SCI_IRQ, so change this here to match the other mainboards. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I29dde7ca8d2ecf00d8174c2d793ef1ad55ae3e28 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73322 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28mb/google/kahlee/mainboard: use ACPI_SCI_IRQ definitionFelix Held
Use the ACPI_SCI_IRQ definition instead of a magic value. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia860668b5c93b1b8882459d9f983cf3a23d16392 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73321 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-28mb/system76: Rename adl-p to adlTim Crawford
The directory holds boards other than ADL-P, such as ADL-U and ADL-H. Change-Id: I8e1b67f83d649cd07645a4a519ba1bf2f6f5e7c6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/72802 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-02-27mb/google/skryim: Add RECOVERY_MRC_CACHE FMAP sectionKarthikeyan Ramasubramanian
Enable HAS_RECOVERY_MRC_CACHE config and add RECOVERY_MRC_CACHE FMAP section to cache the MRC training data in recovery mode. BUG=b:270569389 TEST=Build and boot to OS in Skyrim. Ensure that the Type 0x63 BIOS directory entry is populated with the appropriate MRC_CACHE FMAP section. Change-Id: I3f0f41c20b61c96473e887521f84f3ad240adc2b Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-27mb/google/skyrim/var/winterhold: Use fw_config to probe FPEricKY Cheng
Use fw_config to probe fingerprint. BUG=b:269986245 TEST=emerge-skyrim coreboot chromeos-bootimage. Test result is pass with 1000 reboot cycles. Change-Id: I4b4bca42dd78dfd5b8636ff3cb05406d2d0c94f7 Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73262 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-02-27mb/google/brya/var/osiris: Enable Fast VMode for osirisDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I35f577e1bab0f8dda10061903df13730e2c8ee04 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-27mb/google/brya/var/osiris: use RPL FSP headersDavid Wu
To support an RPL SKU on osiris, osiris must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for osiris so that it will use the RPL FSP headers for osiris. BUG=b:270640775 BRANCH=firmware-brya-14505.B TEST=cherry-pick Cq-Depends, then "emerge-brya intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", flash and boot osiris to kernel. Cq-Depend: chromium:4290627, chrome-internal:5516851 Change-Id: If8de42a82fd85ffa8b9836e6024f119bc798f4fc Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-02-27mb/google/nissa/var/xivu: Disable world-facing microphoneIan Feng
Remove world-facing microphone for xivu360. Switching to world-facing camera will use the user-facing microphone to record sound. BUG=b:263927799 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ibb720974b6488ce4453081e0bc5b4e7f34a6b0f6 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2023-02-27mb/google/dedede/var/dibbi: Improve USB2 strengthAmanda Huang
BUG=b:269786649 TEST=build and test USB2 port function works fine BRANCH=dedede Change-Id: I63928a0d8ce6b2365250fd96572f4a2db948c19d Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
2023-02-27mb/google/brask/var/constitution: use RPL FSP headersMorris Hsu
To support an RPL SKU on constitution, it must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for constitution so that it will use the RPL FSP headers. BUG=b:267539938 TEST=emerge-brask intel-rplfsp coreboot coreboot-private-files-baseboard-brya Change-Id: Ie4f5eb6ebb372ad07308ff25c9eb69a83793c656 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73246 Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-02-27mb/google/brask/var/constitution: Update overridetreeMorris Hsu
Update override devicetree based on schematics. BUG=None TEST=FW_NAME=constitution emerge-brask coreboot Change-Id: I883a806950821e6306242975764930035a94888e Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73110 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pablo Ceballos <pceballos@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-02-27mb/google/rex: Remove `fixme` from gpio.hKapil Porwal
Remove `fixme` from gpio.h since it has been addressed. BUG=none TEST=Only a cosmetic change Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I79a2493dba6becd4b8c1ebf37e452a5a173eb396 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-02-27mb/amd/birman/bootblock.c: Skip EC configuration in SimNowFred Reitberger
SimNow does not support the Birman EC, so skip the EC configuration steps when building for SimNow. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I6e879a13a119d593674d3403d4e1b32e0e244d9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 22:57:27 +0000