| Age | Commit message (Collapse) | Author |
|---|
|
Add LPC common code to be shared across Intel platforms.
Also add LPC library functions to be shared across platforms.
Use common LPC code for Apollo Lake soc. Update existing Apollolake
mainboard variants {google,intel,siemens} to use new common
LPC header file.
Change-Id: I6ac2e9c195b9ecda97415890cc615f4efb04a27a
Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Reviewed-on: https://review.coreboot.org/20659
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Simplify funciton names and remove reference to hudson in stoneyridge.
The southbridge in Stoney Ridge is Kern and hudson naming is
no longer accurate.
BUG=b:62200157
BRANCH=none
TEST=Build and booted on Kahlee.
Change-Id: Ide7a72dae69b881997101f1e37a1ac739901744d
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update PL2 override setting to 15W as per KBL Power Arch Guide.
Change-Id: I4a6f875f8c3bdb012d6ff97c1429f32db5210893
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/20943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add a new Kconfig option to ignore memory fuses that limit the
maximum DRAM frequency to be used. The option is disabled by
default and should only enabled by experienced users as it
might decrease system stability or prevent a successful RAM
training.
Remove conflicting devicetree settings.
Change-Id: I35dd78a02bcaafce8ba522d253c795d7835bacae
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20907
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nicola Corna <nicola@corna.info>
|
|
Get rid of old hybrid graphics driver and use the new one.
1. Disable IGD and PEG in early romstage.
The PEG port will get disabled on devices that do not have a
discrete GPU. The power savings are around ~1Watt.
The disabled IGD does no longer waste GFX stolen memory.
2. Get rid of PCI driver
The Nvidia GPU can be handled by the generic PCI driver and allows
to use the ACPI _ROM generator for Switchable graphics.
3. Settings are stored in devicetree.
One driver for all Lenovo hybrid graphics capable devices.
4. Add support for Thinker1 GPU power handling.
Only boards that do use reference design 2012 are known to be
supported. Needs test on boards that do you use reference design 2013.
Should reduce idle power consumption when using IGD by ~5Watt.
Tested on Lenovo T430 without DGPU. PEG port is disabled.
Needs test on all devices.
Change-Id: Ibf18b75e8afe2568de8498b39a608dac8db3ba73
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20794
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Use new hybrid graphics driver to get device state.
Move remaining code to romstage.c.
Tested on Lenovo T500:
* Linux 4.11.4 on Fedora 25
* Integrated (using NGI)
* Discrete (using VGA OpROM)
* Switchable (using NGI and VGA OpROM), tested with DRI_PRIME
No regressions found.
Change-Id: Iad2eccaab19c71f11308853ba9326d8186e67c93
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20793
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
This mainboard features is an G43 northbridge, ICH10 southbridge and
Winbond W83627dhg SuperI/O. This board is impossible to flash
internally with vendor bios (BIOS region is WP and other regions like
IFD and ME are read only and inaccessible respectively). Due to either
ICH10 or board layout it is also impossible to do ISP, which requires
desoldering flash chip. To make hacking more easy there is an empty
SPI header next to spi flash pads which can be hooked up to a SPI
flash.
What works:
* 2 DDR2 dimms per channel (tested with 1+2G in CH0 and 2+2G in CH1);
* SATA with AHCI
* Integrated GPU with option rom (extracted from a Gigabyte vendor
bios)
* VGA (on DVI) with NGI if patched to use DVI gmbus port for output
* PCI
* Reboot and S3 resume
* Descriptor mode with ME disable straps and ME region absent (no
working gbe in this configuration though)
* USB.
What does not work:
* GBE (probably requires working ME);
* Analog on DVI port out is shaking, which is not the case with vendor
BIOS (setting clockgen on smbus 0x69 like vendor fixes it).
* Booting with ME enabled (needs raminit patches for that)
Not tested:
* Sound;
* All the rest.
Not coreboot related problems:
* Flashing this board with vendor bios is a PITA and requires
desoldering flash chip;
* In situ programming is not possible.
TESTED with SeaBIOS and Linux 4.10.8
Change-Id: If27280feb7cbf0a88f19fe6a63b1f6dbcf9b60f4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19256
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Set AGESA SD/eMMc variable to non-removable eMMc.
BUG=b:63891719
BRANCH=none
TEST=Boot eMMC on Kahlee.
Change-Id: I76ed9cec36a9688ebe75db2077f1ece4ab750c16
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Updating the common smihandler to handler gpi events which
originally were going to be left to each soc to handle. After
some more analysis the gpi handler can also be commonized.
Change-Id: I6273fe846587137938bbcffa3a92736b91982574
Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com>
Reviewed-on: https://review.coreboot.org/20917
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Each line of spd config overwriting the slot 0 instead
of appending it.
Change-Id: I0124aa34f1d4fcb30810fb7eef03d4828a7ac430
Signed-off-by: Alexander Couzens <lynxis@fe80.eu>
Tested-on: lenovo x1 carbon gen 1 with elpida 8GB
Fixes: e9787ff61f81 ("mb/lenovo/x1_carbon_gen1: Add 4GiB SPD index 2")
Reviewed-on: https://review.coreboot.org/20918
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change-Id: I218fd48c8e29563ef089d60ebde7bc36ac8ab189
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
The schematics isn't available for the board, but other L*00 series boards
seem to use a different, compared to T*00 series, GPIO layout.
As it has never been tested, remove the broken driver.
Change-Id: I4bfa02fdbc5da5b556010c2f300faaf6dc845b80
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20798
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Configuring the clockgen like vendor bios fixes the issue where the
display wobbles from left to right on the analog VGA output.
Note: This seems to be common issue/requirement on Intel devices from
that generation (also happens on dg43gt).
TESTED on Intel D510MO.
Change-Id: I08449f0b8b90a1781e6dec91140bf219ea07aaf9
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19595
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
|
some gpio irq need to set input pull initialization status
to guarantee to get the right irq trigger. let's add this argument
in gpio_input_irq() function
BRANCH=None
BUG=None
TEST=boot from bob
Change-Id: I9b8e6497f07146dafdb447a6ea10d039a2a2fa33
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20866
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Decrease the link-frequencies as recommended by Omnivision for OV13858
and OV5670 camera sensors.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I78fb2d3527f66b5147123a9c8fc4cb95650f86b6
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20787
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
|
|
GPP_B8 acts as input to the inverter whose output controls PERST#
signal to wifi module. Out of reset, GPP_B8 is configured as
input by default. Since there is no external pull-down on it, this
line is floating and results in PERST# being asserted until ramstage
where the GPIO was originally configured. Because of this the wifi
chip is not ready during the PCIe initialization step. Move the
configuration of GPP_B8 to bootblock so that wifi device is taken out
of reset as early as possible.
BUG=b:64181150,b:62726961
TEST=Verified with warm reboot and suspend-resume stress test that
wifi is still functional.
Change-Id: I68e1bd67499262a17daade72e9a9fd32934a184d
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20869
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add gpio.c to bootblock so that the variant early_gpio_table can be
used for configuration in bootblock.
BUG=b:64181150,b:62726961
Change-Id: I77181334257f2fd19982ecafc1f58afe912f4280
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20878
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Kahlee uses 3 GPIO(144, 140, 135) pins to identify the
board revision.
Change-Id: Ia9693db6d6506af7ff40db0b3ce4cc6c1469f6ef
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Use the genric GPIO library. Add the required functions.
Also, update the Kahlee mainboard dependency to match.
Change-Id: I2ea562b052401efff3101f736788ca77d21e6de6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20543
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the RT5650 codec ASL for proper Linux driver loading.
Devices visible to OS:
/sys/bus/acpi/devices/AMDI1002:00
/sys/bus/acpi/devices/I2SC1002:00
Change-Id: I60b256f68372c9d17d67c9cb2accaca616a0b9a5
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We define BINARYPI_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: I2900249e60f21a13dc231f4a8a04835e090109d5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19272
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We define AGESA_LEGACY_WRAPPER a method of calling AGESA
via functions in agesawrapper.c file. The approach implemented
there makes it very inconvenient to do board-specific
customisation or present common platform-specific features.
Seems like it also causes assertion errors on AGESA side.
The flag is applied here to all boards and then individually
removed one at a time, as things get tested.
New method is not to call AGESA internal functions directly,
but via the dispatcher. AGESA call parameters are routed to
hooks in both platform and board -directories, to allow for
easy capture or modification as needed.
For each AGESA dispatcher call made, eventlog entries are
replayed to the console log. Also relocations of AGESA heap
that took place are recorded.
New method is expected to be compatible with binaryPI.
Change-Id: Iac3d7f8b0354e9f02c2625576f36fe06b05eb4ce
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
In Scarlet pwm regulatoror minimum value and maximum value differs from
other board variants, Correct it so we can get the right voltage.
Change-Id: I1f722eabb697b3438d9f4aa29c205b0161eb442a
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20831
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
in Scarlet the Sdcard control gpio differs from other
board variants, So set the GPIO to high on Scarlet.
Change-Id: I5fa19b212a716213462eea58b6242392d32a2c5c
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20803
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Scarlet gpio4cd use 1.8V powerdomain, let's make a
correct register setting, otherwise even the uart
does not work.
Change-Id: Ib5a8b2a4d92502fb829688d0a3e1b645d53cd7fc
Signed-off-by: Lin Huang <hl@rock-chips.com>
Reviewed-on: https://review.coreboot.org/20802
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Add the Google mainboard GPIOs to the ACPI table.
Change-Id: I9b5952ed3934b938cb50650890a7b434e6306fd1
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The EC KBC controller was not initialized, so the EC wouldn't put
keys in the output buffer. With nothing in the buffer, vboot didn't
try to boot the USB stick. Add the driver to setup the KBC called by
EC init.
BUG=b:62066405
BRANCH=none
TEST=Boot Kahlee with USB stick and CTRL+U boots the stick.
Change-Id: If9346fda558e802536c7de38da5b21fd25320e40
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20480
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move mainboard_ec_init out of mainboard enable to the more
appropriate mainboard init phase.
Change-Id: Ieabcecf70e4de0b42fc639d031755b6d0b66f08a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20312
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Move the mainboard MADT tables to generic soc ACPI code.
Change-Id: I49fb55b1315da8fe65421b43fc4312ed588d5ecb
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/20277
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add ACPI support for the Google EC, which requires GNVS support
for passing information from the EC to firmware and OS.
Change-Id: I0a308bcd608a135cc9633273a05527f020b60743
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/20276
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set up the TPM decode to SPI prior to verstage.
Enable LPC TPM and remove the mock data.
Note, Kahlee TPM is on SPI, but decoded by the LPC block.
BRANCH=none
BUG=b:62103024
TEST=coreboot and Depthcharge reports TPM found.
Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19848
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Store VBOOT NV data in CMOS. This allows VBOOT to save flags and data
to be used in multiple stages and depthcharge. Fixes developer mode
USB boot.
Change-Id: I50b45e687a1a1c71838bcc390212b28d7e634a19
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19847
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Set DDI port 2 type to Display Port.
Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19846
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Inform AGESA to setup an I2S codec instead of an Azalia codec.
This is step one for audio to work. ASL to connect the
driver and the hardware is in a follow-on patch.
Change-Id: I7ece5d8c317ddc76e0e6b2a005256bc384fe51e2
Signed-off-by: Marc Jones <marc.jones@scarletltd.com>
Reviewed-on: https://review.coreboot.org/19841
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Sync map_oprom_vendev() and autoport with the list of PCI ids in the
`gma.c` driver, remove one obsolete Kconfig default override.
Change-Id: I12f24f415b695c516fbb947114e09c873af2e439
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
All affected boards did the same USE_NATIVE_RAMINIT distinction or
actually selected USE_NATIVE_RAMINIT. Also update autoport.
Change-Id: I924c43cec1e36e84db40e4b8e1dd0e05cad2b978
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/20813
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Add ASL for the Elan touchpad driver connection in ChromeOS.
This is based on the Auron and Rambi ASL. The AMD ACPI code
doesn't have the auto table generation the newer Intel
Chrome SOC use.
Device visible to OS: /sys/bus/acpi/devices/ELAN0000
Change-Id: Id3fc8c8855b0296f43a502e81143498d663468ec
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19844
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Clean up the ASL whitespace and formatting to match the iasl -d
style as other parts of coreboot.
Change-Id: I61689cb55dc26cbad160d45aa0a36c00b386fe0c
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19843
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The AMD internal A-link (AAHB device) doesn't support an IRQ,
so remove it. This solves a conflict with the GPIO IRQ required
for touchpad operation.
Change-Id: Iefaf33cfb2babc29d35b5372fc3a338a72c78a4a
Signed-off-by: Ivy Jian <ivy_jian@compal.com>
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19842
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
WLAN_PE_RST control was moved from EC to SoC, it connected to GPP_B8.
Configure GPP_B8 to drive low.
TEST=Wifi card is detected and connect to an AP.
Change-Id: I6a6ea0ddefe8402284fe37665864c7a1961cbc15
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/20804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The Kahlee Nuvoton EC firmware doesn't support SERIRQ quiet mode, yet.
Set continuous mode until the quiet mode feature is available. This
allows keyboard and other EC based interrupts through.
Change-Id: If77c91fde2bd0f4da85413879fefb753ae6297de
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19840
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
GPIOs for I2C3 were being unset in amdinitmid if the GPIO
enable table wasn't passed. It had been initialy set in amdinitreset.
Pull the GPIO settings into their own file that can be used in
bootblock and later stages.
Change-Id: I41cd7873f8c8543c95ad8653e0a3887f7d0487a2
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Enable:
GPP0 x1 - WLan
GPP1 x1 - Card Reader
Change-Id: Idbfc2a3260b85949810bdd8dc904e59f8a779e48
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
The EC is a legacy 8042 device. Don't set LEGACY_FREE and correctly
report in the FADT.
Change-Id: I041ea4b44372178f3d6073b6ebc8003abc097703
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19836
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add the basics for building as a ChromeOS device. ChromeOS
and ChromeEC are dependent on each other, so bring them in
together. The EC is a Nuvoton and you can find additional
details in the Chromium EC repo.
Add the Google HWID "Kahlee TEST 6421".
The chromeos.fmd for Kahlee takes advantage of the AGESA
located outside cbfs and includes typical RW, VPD, and
MRC areas.
There are some updates required to depthcharge, vboot, GPIOs,
and the ChromeEC before we have a complete-ish system.
Change-Id: Ifb0a6afc01dd80ef9e7bb81039d9152936043999
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Update GPIO settings based on the schematic.
Change-Id: Ic8a876198a3ba9029d1aabb273418923e40bfcc6
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Update for a single DIMM with an SPD at address A0.
Change-Id: I646f079c99cbaffd7094773243600c3030308325
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19833
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Kahlee does not use the AMD IMC. Remove the files and calls.
Change-Id: Ia837551b592b4f473eb38c06c516586fb6c95c88
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19832
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Update for the Stoney Ridge FT4 package and the on chip UART.
Change-Id: I11468834a9ef03da084c156c74d55a19416d98c4
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19831
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Copied from amd/gardenia. Update the appropriate board name strings.
Uses the soc/ structure.
Change-Id: Ia68b16969518f4d63d5d2dea7658a472b2daca05
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/19830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Add dedicated CAR setup and teardown functions and Kconfig
options to force their inclusion into the build. The .S files
are mostly duplicated code from the old cache_as_ram.inc file.
The .S files use global proc names in anticipation for use with
the Kconfig symbols C_ENVIRONMENT_BOOTBLOCK and POSTCAR_STAGE.
Move the mainboard romstage functionality into the soc directory
and change the function name to be compatible with the call
from assembly_entry.S. Drop the BIST check like other devices.
Move InitReset and InitEarly to bootblock. These AGESA entry
points set some default settings, and release/recapture the
AP cores. There are currently some early dependencies on
InitReset. Future work should include:
* Pull the necessary functionality from InitReset into bootblock
* Move InitReset and InitEarly to car_stage_entry() and out of
bootblock
- Add a mechanism for the BSP to give the APs an address
to call and skip most of bootblock and verstage (when
available) (1)
- Reunify BiosCallOuts.c and OemCustomize.c
(1) During the InitReset call, the BSP enables the APs by setting
core enable bits in F18F0x1DC and APs begin fetching/executing
from the reset vector. The BSP waits for all APs to also
reach InitReset, where they enter an endless loop. The BSP
sends a command to them to execute a HLT instruction and the
BSP eventually returns from InitReset. The goal would be to
preserve this process but prevent APs from rerunning early
code.
Change-Id: I811c7ef875b980874f3c4b1f234f969ae5618c44
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/19755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The mc_apl1 mainboard needs to disable the RAPL algorithm for a constant
power management of the processor package. An active RAPL algorithm
leads to negative effects with our real time software.
Change-Id: I09ca56a034fd3896a000e64cac35f12fb507a682
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20760
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Configure GPIO.1 and GPIO.2 as sensor SDA and SCL respectively
for TPS68470 PMIC in daisy chain mode.
* GPIO.1: Sensor SDA in daisy chain mode.
* GPIO.2: Sensor SCL in daisy chain mode.
BUG=b:38326541
BRANCH=none
TEST=Build and boot soraka. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I7f9686427772a33c06e4cdaafee9b0349d700639
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20665
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
resources
This patch controls the camera devices power through ACPI power resource.
* Add Opregions for PMIC1 and PMIC2,
* TI_PMIC_POWER_OPREGION
* TI_PMIC_VR_VAL_OPREGION
* TI_PMIC_CLK_OPREGION
* TI_PMIC_CLK_FREQ_OPREGION
* Add power resources for sensors and VCM,
* OVTH for CAM0
* OVFI for CAM1
* VCMP for VCM
* Implement _ON and _OFF methods for sensor and VCM module's power on
and power off sequences.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries. Verified that sensor probe is successful.
Change-Id: I02c4784ab3f4d6e1f0e657ad50b727ff11da8b9c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20663
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Bind the camera sensor and CIO2 devices through the ports and endpoints
configuration available in _DSD ACPI object.
* Port represents an interface in a device.
* Endpoint represents a connection to that interface.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: If328864dbb61586a4887c7fcae740a12eda7cc92
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
This patch adds mipi_camera.asl and enables
I2C2, I2C3, CIO2 and IMGU devices,
* Add TPS68470 PMIC1 and PMIC2 related ACPI objects.
* Add OV cameras related ACPI objects.
* Add Dongwoon AF DAC related ACPI objects.
* SSDB: Sensor specific database for camera sensor.
* CAMD: ACPI object to specify the camera device type.
KBLRVP has two PMIC's sitting on I2C2 and I2C3. CAM0 and
CAM1 power requirements are handled by PMIC1 and PMIC2 respectively.
BUG=none
BRANCH=none
TEST=Build and boot kblrvp. Dump and verify that the generated DSDT table
has the required entries.
Change-Id: Ibaf26dad74ca1e7c9f415ae75c4ed8558ad99e2f
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20661
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Add both Cannonlake U DDR4 RVP and Cannonlake Y LPDDR4 RVP support.
Implement SPD entry to FSPM for both platforms, seperated platform
specific DQ/DQS/Rcomp input to FSPM as well.
Change-Id: If71662353ddba89a9e831503a2d80dd5ebd65de3
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/20503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Sets RAPL PL1 power to ~6W.
Note: 7.5W setting gives a run-time 6W actual measured power.
Tested on GLK w/kernel 4.11.0 by reading MSR 0x610 at runtime
and comparing to measured power on an instrumented board.
Change-Id: I07caeb2895a579387025d3b0fb7f1d2c3d5e2665
Signed-off-by: Cole Nelson <colex.nelson@intel.com>
Reviewed-on: https://review.coreboot.org/19746
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
GLKRVP is a reference board for GLK SOC
RVP1 has DDR4 and RVP2 has LPDDR4
RVP2 is enabled by default and CONFIG_IS_GLK_RVP_1 should be selected
if building for RVP1
GLKRVP can work with internal Intel EC or external Chrome EC AIC.
For internal EC, CONFIG_EC_GOOGLE_CHROMEEC will not be selected (
CONFIG_GLK_INTEL_EC should be selected for internal EC config)
By default, CONFIG_GLK_CHROME_EC is selected for external ChromeEC AIC
config.
Signed-off-by: Hannah Williams <hannah.williams@intel.com>
Change-Id: Iab688aca6a4f5c5e32801215ba3a1a440e50fbef
Reviewed-on: https://review.coreboot.org/19604
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Fix the OEM settings for two ports. Fix and clarify comments to
reflect Rev. B of the board design.
Change-Id: I2812ea5945f67229872e78041c771606047bbbec
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20744
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Convert from #if to if().
Change-Id: I50b3ed9ecd5947ff625536b196d90ebd4e8f1c56
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20746
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Convert from #if to if().
Change-Id: I7c149856da22b72d2a83bd7f06d031df328dbb35
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/20745
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: I98c700d5b928c031129cf0138d22652a28d1ad1d
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
It requires changes to match the hardware. Except for the weak
attributes that are now removed in coral's copy, the file is identical
to the baseboard version.
BUG=b:63876329
BRANCH=none
TEST=none
Change-Id: Ib0c5f0ecae9919f20631dacef0253416989fb011
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-on: https://review.coreboot.org/20751
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Fix regression introduced by commit 7ffb329f.
The default value for usb_always_on is no longer sane and is replaced
by the same default that is used on all other boards (disabled).
Change-Id: Ia8854a8491bc56507d01e08e1ca1e195a1d62bfc
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/20575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I8febb8d74e2463622cab0313c543ceebec71fdf4
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: Iaab26033e947cb9cf299faf1ce6d40a90a9facbe
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20704
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
After updating to Wacom Firmware version 501, touchscreen can't work.
Wacom FW (ver. 501) enables STOP function.
STOP Pin:
High: Normal Operation
Low: Stop Scanning
So pull TOUCHSCREEN_STOP_L high
BUG=b:37007801, b:37265219
BRANCH=none
TEST=manual testing on Soraka board and touchscreen works at boot
and after suspend/resume.
Change-Id: I8a2bdce1554fd99dea30cf91fa48d0529f40b7b0
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/20664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
The romstage for both is line-for-line identical.
Merge both into P2B-DS so it benefits from my
modernization efforts.
Change-Id: Idd964f4c5c4dfd9e2e0ac4a4f41e4ee9a84a729c
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The romstage for both is line-for-line identical.
Merge both into P2B-LS so it benefits from my
modernization efforts.
Change-Id: I2d1a46236f83a4955ceb5e98b576cce0560f28df
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20690
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Romstage of many 440BX boards included headers that are not used.
Remove them as part of a bigger cleanup effort.
Change-Id: I89ddeda3c90e1a4907c05851185b69f3b29e54ba
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20693
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
I am able to complete a board-status run over onboard ethernet
(ie. it works) without this entry, so it's not necessary.
Change-Id: Iabdf1a1ff3c904bea1b7b5eaefb1d23831dd2cb9
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/20683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Enable S0ix for poppy and soraka in their device trees respectively.
BUG=b:36630881
BRANCH=none
TEST=Verified S0ix and S3 operation on Poppy and Soraka (250+ iterations).
Change-Id: I9ba91499e54f729970448af6f71804ad5b3cb836
Signed-off-by: Rajat Jain <rajatja@google.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20689
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
GPP_B7, GPP_D1 and GPP_D2 are not used going forward. Mark them as NC
in gpio table.
BUG=b:62322846,b:62240755
Change-Id: I7aee08314e6ce96d5913ae315bf75f5c04ab7370
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20672
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Now that soraka is starting to deviate from the baseboard w.r.t. gpio
settings, make a new copy of gpio table before we make any
variant-specific changes in it.
BUG=b:62240755,b:62322846
BRANCH=None
TEST=Verified with gpio_debug=1 in skylake/gpio.c that the gpio
configuration before and after this change remains same.
Change-Id: I448d18f18b63e9bfb739c518d599de3b9b602dc2
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/20671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This mainboard is equipped with DDR3L modules which support ECC. The
BWG says that for activating ECC the FSP-M parameter MemoryDown must be
set to 5.
Change-Id: Idc68df1e2bae2396c9b9788d4a026a75b7d9119b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
The OS of this mainboard needs the _PIC method for the selection of the
type of interrupt routing.
Change-Id: Ic82ba1b368aff0030422d9602ebc882247a2191b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20618
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Initial board files needed to selected to build cannonlake rvp.
Change-Id: I82bd5c785e451f02b827765c54d432517afd7de0
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/20075
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
This patch adds the necessary changes to support Scarlet revision 1.
Since the differences to revision 0 are so deep, we have decided not to
continue support for it in the same image. Therefore, this patch will
break Scarlet rev0.
All the deviations from other Gru boards are currently guarded by
CONFIG_BOARD_GOOGLE_SCARLET. This should be changed later if we
introduce more variants based on the newer Scarlet board design.
Change-Id: I7a7cc11d9387ac1d856663326e35cfa5371e0af2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20587
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Schneider <dnschneid@chromium.org>
|
|
Our structure packing for Rockchip's gpio_t was chosen arbitrarily. ARM
Trusted Firmware has since become a thing and chosen a slightly
different way to represent GPIOs in a 32-bit word. Let's align our
format to them so we don't need to remember to convert the values every
time we pass them through.
CQ-DEPEND=CL:572228
Change-Id: I9ce33da28ee8a34d2d944bee010d8bfc06fe879b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20586
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=none
BRANCH=reef
TEST=emerge-snappy coreboot chromeos-bootimage and verify the keyboard
backlight can be bright and alt+f6, alt+f7 function keys can be used.
Change-Id: I6d06f72e1ccc66292b4e5f867314d84c309af885
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/20633
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
We've just decided to remove the only known use of the VBSD_SW_WP flag
in vboot (https://chromium-review.googlesource.com/c/575389), since it
was unused and never reliable on all platforms anyway. Therefore, we can
now also remove the coreboot infrastructure that supported it. It
doesn't really hurt anyone, but removing it saves a small bit of effort
for future platforms.
Change-Id: I6706eba2761a73482e03f3bf46343cf1d84f154b
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/20628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
SDCARD is not used on this mainboard.
Change-Id: I28d23cdb3652bf736b19daf67c7057c396230e24
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/20611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
The romstage for CS5536 platforms were including early_smbus.c and
early_setup.c. Build these into romstage from the makefile, and remove
the #includes.
Add a Kconfig option for platforms that do not use the
early smbus code.
Change-Id: I2e6a9cd859292b4dd4720b547d1ff0bbb6c319cf
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/20607
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I67c682f79834bed334f26a4c7473eaf463262a85
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20592
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ie17cc7367fc8561e2ecb357d4f8282c1cd444b7f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20591
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Calling disable_cache_as_ram() with valuables in stack is not
a stable solution, as per documentation AMD_DISABLE_STACK
should destroy stack in cache.
While we still preserve cache contents (there is wbinvd deep
inside AMD_DISABLE_STACK macro), we now actually do a stack
switch and much more closely meet the specification of CAR
teardown sequence in AGESA specifications.
We now somewhat incorrectly include files from agesa/ tree,
but the whole agesawrapper.c file removal will address the
issue of overall directory layout.
Change-Id: I2bac098099c1caffea181356c63924f4b5a93b54
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/18525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
Change-Id: Id20a49385aeb336461acd0bd186a4ab7f3fb95b8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Essentially squashes following commits from AGESA side.
45ff9cb AGESA: Reduce typecasting in heapmanager calls
bceccec AGESA: Handle HEAP_CALLOUT_RUNTIME allocation more cleanly
4240277 AGESA: Adjust heap location for S3 resume path
424c639 AGESA: Refactor S3 support functions
50e6daf AGESA: Log heap initialisation
da74041 AGESA: Move heap allocator declarations
c74b53f AGESA: Reduce SPI use by 24kB for S3 support
b1fcbf3 AGESA: Separate HeapManager declarations from BiosCallOuts
f728408 AGESA: Split S3 backup in CBMEM
82fbda7 AGESA: Use same HeapManager for all BiosCallOuts
Change-Id: I537bd05a3e06ff6896f1ac8be93eed5321ca472b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/19271
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Set PL2 and SysPL2 for Fizz based on cpu id.
BUG=b:7473486, b:35775024
BRANCH=None
TEST=On bootup make sure PL2 and PsysPL2 values set
properly (through debug output)
Change-Id: I5c46667fdae9d8eed5346a481753bb69f98a071b
Signed-off-by: Shelley Chen <shchen@chromium.org>
Reviewed-on: https://review.coreboot.org/20420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
Change-Id: I370285aa52776170a32b6dd36c0eef74eea9400c
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/20562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Also unify __attribute__ ((..)) to __attribute__((..)) and
handle ((__packed__)) like ((packed))
Change-Id: Ie60a51c3fa92b5009724a5b7c2932e361bf3490c
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/15921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
All other Sandy/IvyBridge google boards have this function,
which is required by nb/sandybridge/raminit_mrc.c. Without it,
compilation fails when using MRC vs native ram init.
Change-Id: I3318700c540e97baf0a75aafb73f160aaae6703f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add wacom touchscreen support.
BUG=b:37007801, b:37265219
BRANCH=None
TEST=manual testing on Soraka board to ensue that touchscreen works
at boot and after suspend/resume.
Change-Id: I0fbae4782c6442149cda57d23c61ed87546621bb
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/20476
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
|
There will be more follow-up changes.
BUG=b:63537905
BRANCH=None
TEST=emerge-nefario coreboot libpayload
Change-Id: I6bb80723ea2573df617026a4a5740adb89331892
Signed-off-by: Philip Chen <philipchen@google.com>
Reviewed-on: https://review.coreboot.org/20522
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Add capability and location data for USB ports/devices via
_PLD and _UPC ACPI methods, which is utilized by Windows and
required by macOS.
Move inclusion of mainboard.asl after southbridge asl files
so scopes referenced in usb.asl are valid.
Change-Id: Id98aa5f6dbdcbb8da4616d4fce6e7388f3ba4656
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/20515
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Increase PL1 Min to 4.5W
BUG=b:35585781
BRANCH=reef
TEST=build, boot on snappy, and verified by thermal team.
Change-Id: Ia55c5a57e1475fb605929cf33322728bd36295d4
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/20473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Needs the ramstage configuration enabling of SuperIO GPIO pnp devices
for BSEL straps.
Also needs VSBGATE# to be on for ram to be powered during S3.
TESTED with 800MHz and 1067MHz FSB CPUs at the correct straps when
resuming from S3.
Change-Id: I6ac927ee9dcce15fc7621aad57969fae8f5805ca
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/19602
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Enable Azalia controller, HD Audio DSP and select
the HDAudio IoBuffer Ownership for rvp3.
Check if device is enabled in HDA codec init function
to avoid failure when Azalia controller is disabled in
the devicetree.cb.
BUG=None
TEST=Build for kblrvp3, Make sure booting is fine irrespective of HDA
enable/disable.
Change-Id: I87212fe16ecc6053d6d00372904a5fd5d6f6b209
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/20530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
1. Due to reset signal, PMIC loses its internal register state. This
causes PMIC to be in improper state after sleep.
2. The intent of reset signal is to reset internal state of PMIC (which
happens once during power on), hence avoid asserting reset signal
when not needed.
3. As per PMIC (TPS68470) datasheet, device can be kept in SLEEP mode
when not in use to save max possible power.
To fix the same, do not reset PMIC while entering sleep.
By keeping PMIC in SLEEP mode, Power consumption is < 1uW (Typ) upto
3.63uW (Max). Refs: TPS68470 datasheet.
Measured value: 0.66uW
TEST= Build the firmware for Soraka & boot to OS. Do S3 resume & check
whether PMIC internal registers state are preserved.
Change-Id: I93ce4d76b0376b64ae6d1067aca0fd7467af3582
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/20264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
