summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2023-12-15mb/google/brya/var/dochi: Enable LpDdrDqDqsReTrainingMorris Hsu
FSP default value for LpDdrDqDqsReTraining is 1. For boards that didn't set LpDdrDqDqsReTraining to any value, 0 was being assigned and it caused black screen issue. BUG=b:302465393,b:315739133 TEST=Boot to OS with debug FSP, check LpDdrDqDqsReTraining = 1 Change-Id: I5d61301fddac6630bb1c48e992dd76e5cf02a272 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79533 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-14mb/amd/onyx/mainboard: add FCH IRQ mapping tableFelix Held
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iab640551d6dd246884802ced948ff8c359d922a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79470 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14mb/google/rex/var/screebo: Change GPP_B14 from UP_20K to NONEKun Liu
Change GPP_B14 from UP_20K to NONE for compatible with DVT1 and DVT2 board BUG=b:272447747 TEST=enable usb OC2 function to ensure USBA work normal Change-Id: Ib7720980335660f423b3a74199ceedc113ec70df Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79431 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-14mb/google/nissa/var/anraggar: Update DTT settings for thermal controlWeimin Wu
Update DTT settings based on the suggestion of the thermal. BUG=b:313833488 TEST=emerge-nissa coreboot Change-Id: I2296990062cadc05202e3d1ab90af04234bda885 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79442 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Enable USB3 Port3 for WWAN (LTE)Weimin Wu
1. Ref to SCH, LTE use USB3 Port3, enable it. 2. Explicitly define the use of USB3 Port1 & USB3 Port2. BUG=b:315061146 TEST=can pass PCIe Hardware Compliance Test Change-Id: I03d6925020012fa740bbd0168a2f5b02ea6763b4 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-14mb/google/nissa/var/anraggar: Change code style for register usb2_portsWeimin Wu
Change code style to be compatible with Nissa's format: register "option" = "{ [0] = value /* comment */ ... }" to register "option[0]" = "value" /* comment */ BUG=none TEST=abuild -v -a -x -c max -p none -t google/brya -b anraggar Change-Id: I60659bd44813173f9b984216473a0919c5f331b8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-13mb/amd/onyx/dsdt: include acpi/dsdt_top.aslFelix Held
acpi/dsdt_top.asl provides some common functionality and needs to be included at the beginning of the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ia7b5ddce110b35ed65c6df6cc42995abe93a3ffc Reviewed-on: https://review.coreboot.org/c/coreboot/+/79466 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-13soc/amd/genoa/acpi: include globalnvs.asl in SoC codeFelix Held
Instead of including globalnvs.asl in the mainboard's dsdt.asl, include it in Genoa's soc.asl. This aligns Genoa with Cezanne and newer and also moves more SoC-common code to the SoC folder. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie0e3299a95e007188a4d9de824cfff8d25a778be Reviewed-on: https://review.coreboot.org/c/coreboot/+/79465 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-13mb/google/brox: Generate RAM ID for supported memory partIvy Jian
Add the MICRON MT62F1G32D2DS-023 WT:B RAM part for brox: DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) MT62F1G32D2DS-023 WT:B 2 (0010) BUG=b:311450057,b:315913909 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Id120a5eb311d8299a8e59d2c1658fe0742e93934 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79459 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-12-12mb/amd/onyx/devicetree: enable more PCI devicesFelix Held
Early versions of CB:76519 had more devices enabled in the chipset devicetree which shouldn't necessarily be enabled in the chipset devicetree. Enable most of those in the Onyx mainboard's devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieeb96755a007a5ca70e4c31df09325835bb8ef47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
2023-12-12soc/amd/genoa/chipset.cb: disable IOMMU devices by defaultFelix Held
Disable the IOMMU PCI devices in the chipset devicetree. In order for the IOMMU devices on the Onyx mainboard still be enabled, enable them in the mainboard devicetree. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8c1bbbf370a3b5566a8484bcfa88dc4efa31222b Reviewed-on: https://review.coreboot.org/c/coreboot/+/79409 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12mb/amd/onyx: Add MPIO configMartin Roth
Add the device and chip entries for the various PCIe ports and MPIO lane configuration. Below each PCIe bridge device with an external PCIe port on the mainboard, an MPIO chip is added that provides the corresponding MPIO configuration for this external PCIe port. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I8563c5a07eb8fd8ff9dd4e7b63fc9a7d485b1316 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78921 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-12mb/amd/onyx: Add USB configurationMartin Roth
Drive board specific USB configuration from the coreboot devicetree into the opensil input block. In the process of scrubbing opensil for public release USB became non functional. Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: I62eefe1061446612168dd27e673a2742903456c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/78920 Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-12-12mb/google/rex/var/screebo: Increase PL1 max value from 15W to 25WKun Liu
Adjust PL1 max value from 15W to 25W BUG=b:314263021 TEST=emerge-rex coreboot Change-Id: I4122a13d7e33c736299c1a759ec51f7a3b29340f Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79377 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-11mb/google/nissa/var/quandiso: Tune P-sensorRobert Chen
Update proximity sensor tuning value from dedede/kracko tuning. Remove GPIO override to use the configuration from nissa baseboard: - GPP_B5 ==> SOC_I2C_SUB_SDA - GPP_B6 ==> SOC_I2C_SUB_SCL BUG=b:310050220 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I7c687677a797415d80be4c420484d3346a8455f6 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79247 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08Revert "nipperkin: Fix WLAN to GEN2 speed" & "Disable PSPP for WLAN"Zheng Bao
Updated Linux FW works with PCI gen3 speed and PSPP. This reverts commit 05c9a850fd21 ("mb/google/nipperkin: Fix WLAN to GEN2 speed") https://review.coreboot.org/c/coreboot/+/63593 and commit 76fddd963925 ("mb/google/nipperkin: Disable PSPP for WLAN") https://review.coreboot.org/c/coreboot/+/63722 The changes are overlapped and are reverted together. BUG=b:240426142 & b:228830362 The system is able to ran over 2500 cycles on Nipperkin with command suspend_stress_test -c 10000 --wake_min 10 --suspend_min 10 \ --nofw_errors_fatal The whole variant_update_dxio_descriptors is empty and is pushed back to weak function. Change-Id: Id207076542edc8ea0cabc6e02e29856c2b6803c7 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com>
2023-12-08mb/google/rex/var/screebo: set audio GPIO pins based on fw_configTerry Cheong
Enable BT offload when I2S option is selected for screebo. BUG=b:275538390 TEST=Verified audio playback using BT speaker/headset in I2S mode on google/screebo. Fixes: https://review.coreboot.org/c/coreboot/+/77755 Change-Id: I7ebe8e28d35428ce2fb8129dc145fec9ac60f9da Signed-off-by: Terry Cheong <htcheong@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-08mb/google/nissa/var/anraggar: Fix unrecogniz Type-C USB disk on depthchargeWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged, keep mainboard C port to conn0. BUG=b:312998945 TEST=can boot from external Type-c USB disk Change-Id: Ib8df4a256bd9cd1b2ca229b09d68f97babc8092e Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-08mb/google/brox: Update configuration for USB portsIvy Jian
Update brox devicetree based on the latest schematics. - Configure typeC to EC mux ports settings. - Configure USB2/USB3 ports settings. - Configure TCSS ports settings. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: Iac5a2e8be6cea64f107d267d4cf71529f08bb63d Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79391 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-06mb/google/brox: Generate RAM IDs for two modulesIvy Jian
Add the support LP5 RAM parts for brox: 1. HYNIX LPDDR5 6400 2GB H9JCNNNBK3MLYR-N6E 2. MICRON LPDDR5 6400 4GB MT62F1G32D4DR-031 WT:B DRAM Part Name ID to assign H9JCNNNBK3MLYR-N6E 0 (0000) MT62F1G32D4DR-031 WT:B 1 (0001) BUG=b:311450057 BRANCH=None TEST=Run part_id_gen tool without any errors Change-Id: Ib17f26a310435e37088191594863a645aa751440 Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79392 Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-12-06mb/google/rex/variants/deku: Enable CNVi PCI deviceEran Mitrani
BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Change-Id: I41a64252f08304ffc66fd782e54720252064ca49 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-05mb/google/brox: Fix memory configShelley Chen
Fix up the memory config for brox based on the schematics. Also, since memory training needs to happen in romstage, initializing the MEM_STRAP & MEM_CH_SEL gpios for use in romstage. Also consolidating the GPIOs needing to be initialized in romstage into the baseboard gpio.c file. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I17615cda7df10e73e49fb49f736728787ef7625d Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79355 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-12-04mb/google/rex/var/screebo: Override power limitsSubrata Banik
This patch allows variants to override the default baseboard PLx limits. Additionally, rearrange the include header files alphabetically. BUG=b:313667378 TEST=Able to boot google/screebo with modified power limits. Before: [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) After: [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ic66872c530963238a0bf5eebbd5b5a76a7985e5c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-04mb/google/rex/variants/deku: Complete USB configurationEran Mitrani
+-------------+----------------+------------+ | USB 2.0 | Connector Type | OC Mapping | +-------------+----------------+------------+ | 1 | Type-C | OC_0 | +-------------+----------------+------------+ | 2 | Type-C | OC_0 | +-------------+----------------+------------+ | 3 | Type-C | OC-0 | +-------------+----------------+------------+ | 4 | Type-A | OC_3 | +-------------+----------------+------------+ | 5 | Type-C | OC_0 | +-------------+----------------+------------+ | 6 | Type-A | OC_3 | +-------------+----------------+------------+ | 7 | Type-A | OC_3 | +-------------+----------------+------------+ | 8 | Type-A | OC_3 | +-------------+----------------+------------+ | 9 | Type-A | OC_3 | +-------------+----------------+------------+ | 10 | BT | NA | +-------------+----------------+------------+ +---------------------+-------------------+------------+ | USB 3.2 Gen 2x1 | Connector Details | OC Mapping | +---------------------+-------------------+------------+ | 1 | Type-A | OC_3 | +---------------------+-------------------+------------+ | 2 | Type-A | OC_3 | +---------------------+-------------------+------------+ +------+-------------------+------------+ | TCPx | Connector Details | OC Mapping | +------+-------------------+------------+ | 1 | Type C port 0 | OC_0 | +------+-------------------+------------+ | 2 | Type C port 1 | OC_0 | +------+-------------------+------------+ | 3 | Type C port 2 | OC_0 | +------+-------------------+------------+ | 4 | Type C port 3 | OC_0 | +------+-------------------+------------+ BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I90d3d984af6d40efb4553cf5675617700161d2d7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79356 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/variants/deku: Add basic DTTEran Mitrani
Add default Intel DPTF. BUG=b:305793886 TEST=util/abuild/abuild -p none -t google/rex -x -a -b deku Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: Id681754fc8e7b418de35f66df097cadd4aad7448 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/deku: Enable LAN0, LAN1Eran Mitrani
google/deku is a Chromebox featuring two LAN ports. Add overridetree.cb entry to configure the LAN0 LAN1 devices. BUG=b:305793886 TEST=Built FW image correctly. Signed-off-by: Eran Mitrani <mitrani@google.com> Change-Id: I8980dabc7f9fc731a2b60c599e1e48c9b11dabb4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79292 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-12-04mb/google/rex/var/ovis: Add power limit support for MCH ID 0x7d14Subrata Banik
This patch adds the power limit configuration for MCH ID index 3 aka 0x7d14 DID which is identical to MCH ID 0x7d01 (index 1). TEST=Able to perform power limit configuration for google/ovis. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/ovis/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (19000, 28000) PL2 (mW) (64000, 64000) PL4 (W) (120) Change-Id: Iff71adb4e26d18970b5947927c258419f751de32 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79332 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-12-04mb/google/rex: Simplify power limit configuration usageSubrata Banik
This patch removes the deprecated PL_PERFORMANCE and PL_BASELINE configurations, relying instead on the refactored power limit flow. This flow allows for seamless overrides by the baseboard and/or by the variant board, if necessary. Specifically, this patch: - Removes PL_PERFORMANCE and PL_BASELINE configuration options from mainboard.c in the google/rex directory. - Relies on the baseboard_devtree_update() function, which is implemented by the respective baseboard, to handle power limit configuration. - Leverages the variant_devtree_update() function, which is a __weak implementation, to allow overrides by the variant directory. This simplification improves code readability and maintainability while maintaining the flexibility to handle power limit configurations as needed. Change-Id: I872e5cb59d7b2789ef517d4a090189785db46b85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79331 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-02mb/google/rex: Enhance power limit override mechanismSubrata Banik
This patch expands the power limit override capability to include variants directories, enabling them to modify power limit settings configured by the baseboard. Previously, only the baseboard could override power limit settings. For instance, while the google/rex baseboard sets the PL1 max power limit to 15W, the google/screebo variant couldn't override this value. This enhancement empowers variants directories to override baseboard- configured power limit settings, allowing for greater flexibility and control over power limits. BUG=b:313667378 TEST=Able to call into _weak implementation of `variant_devtree_update` unless there is one override. [DEBUG] WEAK: src/mainboard/google/rex/variants/baseboard/rex/ ramstage.c/variant_devtree_update called [INFO ] Overriding power limits PL1 (mW) (10000, 15000) PL2 (mW) (40000, 40000) PL4 (W) (84) Change-Id: Ib07691625e075b0fbab42271512322ffc60ba13b Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-12-01mb/google/nissa/var/anraggar: Trim GPIO commentsWeimin Wu
Trim all GPIO comments like "origin ==> current". BUG=b:304920262 TEST=pass building Change-Id: I05daa4df16b6da3d3f971b75c7c467032e3f854d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79321 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-12-01mb/google/nissa/var/anraggar: Fix the GPP_D6 for LTE power.Weimin Wu
Fix GPP_D6 configuration for LTE power enable. BUG=b:304920262 TEST=mmcli -m any Change-Id: I2996fd35c2897269997bc0290e0ce93bbbaa1bf8 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79166 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/nissa/var/anraggar: Fix Type-C & DP functionsWeimin Wu
Due to TCPC0 & TCPC1 exchanged compare to Neried design, but related USB2 Ports not exchanged. BUG=b:304920262 TEST=Tpye-C & DP functions workable Change-Id: I9dacf06b1e672575a684856acdb10b6c88360b18 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79165 Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01mb/google/nissa/var/anraggar: Enable ILITEK touchscreenWeimin Wu
For proto PCB: GPP_C0 for enable power supply which also for sensor subsystem. GPP_C0 must allways turn power on, so GPP_C6 is not only used for enable function but also for stop report. BUG=b:304920262 TEST=1. touchscreen function workable 2. INT pin no active during suspend Change-Id: I7dabf205dba616f57ef9717f950eba96282d8e3d Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
2023-12-01mb/google/brya/var/dochi: Update overridetree for type c1Morris Hsu
Update overridetree to correct AUX pin to USB-C port 3 BUG=b:299570339 TEST=emerge-brya coreboot chromeos-bootimage Change-Id: I3a5a89c6008fbf28c927f83060e6e508d60845ba Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79343 Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-12-01mb/google/brox: Update storage settings for SSD and UFSIvy Jian
Brox has SSD and UFS storage per different SKU. 1. Set SSD on CPU PCIe port (PCIEX4_A) and configure related gpio settings according to the schematic. 2. Enable UFS, also enable ISH since it is PCI function 0, required for UFS function 7 to be enabled. 3. Set unused SRCCLKREQ signals to NC. 4. Remove unused gpio settings in variant gpio table to prevent unexpected overrides. BUG=b:311450057 BRANCH=None TEST=emerge-brox coreboot Change-Id: I88922bcfa13652006aa10078c3c444624fd4575e Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79295 Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/rex/variants/deku: Add GPIO configurationEran Mitrani
Based on Platform Mapping Document for Deku (go/cros-deku-mapping) from Nov 8, 2023 (Rev 0.4) BUG=b:305793886 TEST=WIP, not tested yet Change-Id: Ib37a7ebf0aca788d14fafea0f97e364beafb4c4d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78960 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-11-30mb/google/corsola: Use fw_config to differentiate audio ampsYidi Lin
Use fw_config to differentiate audio amps instead of the kconfig option. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: I5f887f5e0d16dc14039fb12b636257d01339b2de Signed-off-by: Yidi Lin <yidilin@chromium.org> Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79309 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/quandiso: Add LTE only daughterboard supportRobert Chen
Quandiso does not use DB_1C, replace the fw_config with LTE only daughterboard. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id7129e52d3733f62405f9d766f08563f05016c69 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79297 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Shawn Ku <shawnku@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/galdos/var/lars: Implement touchscreen power sequencingMatt DeVillier
Since lars has two touchscreen options, we need to determine which (if any) are present on a given device at runtime so that there are not multiple ACPI touchscreen devices (as it makes Windows unhappy). Implement power sequencing and runtime detection for both touchscreen options. TEST=build/boot Win11/Linux on google/lars, verify touchscreen detected and functional under both OSes. Change-Id: I49ccb29ec4589315a4abe3c0ea8fa76f97080bcd Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79311 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30mb/google/glados/var/lars: Add Melfas touchscreenMatt DeVillier
LARS has a Melfas touchscreen option, so add an entry for it. Adapted from Chromium branch firmware-glados-7820.315.B, commit a26fe552569f ("Chell: Update DPTF parameters for CPU"). TEST=build/boot Linux on google/lars with Melfas touchscreen, verify functional. Change-Id: Idecd572335d7d5d52e4f89e85ebf7f0c90f23751 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79310 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/siemens/mc_ehl: Enable write access for SPD EEPROM on mc_ehl1Werner Zeh
The address space of possible SPD-EEPROMs 0x50..0x53 on the SMBus interface is per default write-protected in FSP. This avoids that an SPD-EEPROM on a DRAM module gets overwritten by the host. On mc_ehl1, memory-down configuration is used and there is no SPD EEPROM available. Nevertheless, there is a general purpose EEPROM on the same address available which needs to stay writeable. This patch disables the default-enabled write protect feature for the SPD-EEPROM addresses just for mc_ehl1. Test=Boot into Linux and make sure a write access into the EEPROM is possible. Change-Id: I6b0fcdbeb0dbf971cfdceb70d6f4845765a3bdb6 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jan Samek <jan.samek@siemens.com>
2023-11-30mb/google/nissa/var/anraggar: Add OV13B10 MIPI camera deviceWeimin Wu
Enable MIPI camera for anraggar project. Sensor: OV13B10-GA5A Driver: DW9714V EEPROM: GT24P64E Ref to SCH, use MIPI 4-lane serial output interface. BUG=b:309518095 TEST=Google Camera app working Checking log with: coreboot log: \_SB.PCI0.I2C2.CAM0: Intel MIPI Camera Device I2C address 036h \_SB.PCI0.I2C2.VCM0: Intel MIPI Camera Device I2C address 0ch \_SB.PCI0.I2C2.NVM0: Intel MIPI Camera Device I2C address 050h kernel log: kernel: [ 6.140429] intel-ipu6-isys intel-ipu6-isys0: bind ov13b10 11-0036 nlanes is 4 port is 1 cros_camera_service[4755]: Read camera eeprom from /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom cros_camera_service[4755]: Probing media device '/dev/media0' cros_camera_service[4755]: Probing sensor 'ov13b10 11-0036' (v4l-subdev17) cros_camera_service[4755]: Found V4L2 sensor subdev on /sys/devices/pci0000:00/0000:00:15.2/i2c_designware.2/i2c-11/i2c-OVTIDB10:00/video4linux/v4l-subdev17 Change-Id: I6a82557c94203f24449588a6005abc53cc29ca76 Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79163 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arec Kao <arec.kao@intel.corp-partner.google.com>
2023-11-30mb/google/nissa/var/anraggar: Enable CNVi BluetoothWeimin Wu
Intel CNVi WLAN's BT uses USB2 Port 10 inside the SOC, and the relevant configuration needs to be modified in overridtre.cb. BUG=b:304920262 TEST=lsusb ID 8087:0033 Intel Corp. rfkill list hci0:Bluetooth Change-Id: Ibcae800836c17307bc133de5a91658f6dda5985c Signed-off-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79055 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/nissa/var/anraggar: Tune eMMC DLL valuesSimon Yang
Anraggar cannot boot into OS and kernel loading failure. Update eMMC DLL values to improve initialization reliability - Sending different speed TX/RX command/data signal to eMMC and check the response is success or not. - Collecting every eMMC that use for the project - Based on above result to provide a fine tune DLL values BUG=b:308366637 TEST=Cold reboot stress test over 2500 cycles Change-Id: I9ec3cc23000301aa72aed96e74b63114623c4fc2 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78851 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-30mb/google/brya/var/marasov: Update MSR Package Power Limit-1 valuesDaniel Peng
As customer demand, it is necessary to set MSR Package Power Limit-1 to 17W for the DTT setting to optimize performance. The PL1 value (17W) suggested by the thermal team which is different from the reference code(PL1=15W). BUG=b:312321601 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Built and booted into OS, and confirm MSR PL1=17W correctly. Change-Id: If7874d26038118c5605cf0721c30e681b45123fe Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79335 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-30mb/google/brya: Centralize SOC_INTEL_STORE_ISH_FW_VERSION configSubrata Banik
This patch moves the SOC_INTEL_STORE_ISH_FW_VERSION config from the Nissa baseboard to BOARD_GOOGLE_BRYA_COMMON. This allows all baseboards to retrieve the ISH version and store it into memory. Ensure SOC_INTEL_STORE_ISH_FW_VERSION is enabled only for platforms with ISH support (DRIVERS_INTEL_ISH). Additionally, the dedicated SOC_INTEL_STORE_ISH_FW_VERSION config selection for the Nissa baseboard is no longer needed. BUG=b:280722061 TEST=Able to build and boot google/marasov. Change-Id: I99dab43ae4e13869b7f8797a9c4014f60e38a595 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79338 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-29mb/google/rex/var/screebo: Change GPP_B14 from NC to NFKun Liu
Change GPP_B14 from NC to NF BUG=b:272447747 TEST=enable usb OC2 function to ensure USBA work normal Change-Id: Ie0f112bcf183870869d0c1b9a223d4231600a300 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79308 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-29mb/google/brox: Fix configuration for TPMShelley Chen
On Brox, TPM is using i2c4 and GPP_E2, so modifying the Kconfig to reflect this. Also, fixing up the TPM entry in the device tree. Making sure that the GPIO for GSC_PCH_INT_ODL is set correctly. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I0ecaa6fcfc05c3c2e55f857d7a4e59fe46096bb5 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79102 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-11-27mb/google/brya/var/taeko: Generate SPD IDs for 2 new memory partsLeo Chou
Add taeko new supported memory parts in mem_parts_used.txt, generate spd-3.hex for these parts. 1. Samsung K4UBE3D4AB-MGCL 2. Micron MT53E1G32D2NP-046 WT:B BUG=b:312363368 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I221ad3f490f24b43fe1ccd211014787eab5d1038 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: YH Lin <yueherngl@google.com>
2023-11-27mb/asus/p8z77-m_pro: Drop useless early init codeKeith Hui
Drop code that puts Super I/O into config mode, select serial device, then leave config mode right away having done nothing. I'll also take this chance to revise its #includes based on include-what-you-use results. Change-Id: I304fc1610740375b59121b6b8784122440795838 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73693 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-27mb/asus/p8z77-m: Properly configure early serialKeith Hui
Board was not producing serial output until well into ramstage. To fix, select SUPERIO_NUVOTON_COMMON_COM_A Kconfig to tell nuvoton_enable_serial() to route serial port A signals to the outside, not GPIO8x. TEST=Full native raminit debug log received over serial by minicom. Change-Id: I376a79dd76ffa5f4d47e7c0cb53680e173e1ad78 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79222 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-27mb/google/rex/var/screebo: Enable BT audio offload configKapil Porwal
Enable BT audio offload of ALC1019_ALC5682I_I2S based on fw_config. BUG=b:299510759 TEST=Build and boot to Screebo. Verify the config from serial logs. w/o this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 0 [SPEW ] BT Interface = 1 ``` w/ this CL - ``` [SPEW ] ------------------ CNVi Config ------------------ [SPEW ] CNVi Mode = 1 [SPEW ] Wi-Fi Core = 1 [SPEW ] BT Core = 1 [SPEW ] BT Audio Offload = 1 [SPEW ] BT Interface = 1 ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I6c713752f3f0bf58b5ebd78b904e773fdbf16e06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77755 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-27mb/google/nissa/var/craask: Enable PIXA touchpadTyler Wang
Add PIXA touchpad for variants of craask. BUG=b:310489697 TEST=build craask firmware and test with PIXA touchpad Change-Id: I7e68a44eb3d639eaadb5b7b9cb5a6955fd059eeb Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-24mb/google/nissa: make GPP_F17 edge triggered to avoid spamming ECScott Chao
In nissa platform, we configured GPP_F17 as SCI+APIC to wake the system and also generate IRQ to the IOAPIC. Currently, we set GPP_F17 to level triggered and it causes AP (Application Processor) to keep sending GET_NEXT_EVENT to EC during resume from suspend by connecting AC. So we change GPP_F17 to edge triggered to avoid this condition. BUG=b:308716748 TEST=Original failure rate was 7 out of 10 times and it reduced to 0 out of 60 times on six joxer systems. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: I3ceb1dfce46376a6a9a8c6cb6d691d818a0a42ff Reviewed-on: https://review.coreboot.org/c/coreboot/+/79244 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-23mb/google/nissa/var/quandiso: Disable un-used C1 port by daughterboardRobert Chen
Probe usb ports by FW_CONFIG setting to disable C1 port on quandiso new daughterboard without C1 port. BUG=b:312094048 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I6f702f60c772176e80b3452bf957d10625564102 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79173 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/asus/p8z77-m: Ensure RAM stays powered in ACPI S3 suspendKeith Hui
Enable 3VSBSW# in NCT6779D super I/O like other variants in the family, needed to maintain power to memory during S3 suspend. Without it resuming totally fails. (Enabling it in devicetree is OK; it needs not be done in early board init.) TEST=Resuming from S3 works. Change-Id: Ia8059b2a263ab5c459e54685f046eeb913776473 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78205 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Kevin Keijzer <kevin@quietlife.nl> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/google/nissa/var/craaskov: Add 6W and 15W DPTF parametersVan Chen
The DPTF parameters were defined by the thermal team. Based on thermal table in 290705146#comment17. BUG=b:290705146 BRUNCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I02b4187000eec9990bf10a57875b23007f7bdd12 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79183 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22mb/google/rex: Enable FSP logo rendering for all Rex variantsSubrata Banik
This patch enables the FSP (Firmware Splash Screen) rendering feature for all Rex variants, including chromeboxes like Ovis. This will allow users to see the FSP logo during the boot process. BUG=b:284799726 TEST=Verify that the FSP logo is displayed during the boot process on an google/ovis chromebox. Change-Id: I73d82e16f70ffdc8cb168506c86d9c4e9a92c38d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-22mb/google/rex/var/karis: Set pen detect pin to NC for non-stylus skuTyler Wang
Set pen detect pin to NC base on fw_config. BUG=b:304680060 TEST=emerge-rex coreboot pass Change-Id: Icf9171fca49cfed1a05a67ae7fc8d62b7e9630c9 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79213 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-22google/*: Clean up Kconfg board selection for Google MTK boardsJulius Werner
This patch tries to standardize and simplify the Kconfig option layout for Google boards with MediaTek SoCs and align them to the scheme used with other Arm-based Google boards. Change-Id: I40880e7609ba703d0053ad01da742871e54d4e7a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79063 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-22google/*: Clean up Kconfig board selection for non-MTK Google Arm boardsJulius Werner
This patch unifies and simplifies the Kconfig selection model for the Gru, Herobrine, Trogdor and Veyron boards according to the model discussed in CB:78972. Also add missing license headers to two Kconfig files while I'm here. Change-Id: If679a05afd10869afba9c2a33b54862e102b5f40 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79022 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21mb/hp/280_g2: Restore comments documenting root port devicesFelix Singer
While transitioning the devicetree to make use of the chipset devicetree, commit 3b5b9f4c543c ("mb/hp/280_g2: Make use of the chipset devicetree") removed useful comments documenting the endpoints of the root ports. Restore them. Change-Id: I178cb472a8f40baaccc30514689bda2730dfa9dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-11-21mb/{google,intel}/{rex,mtlrvp}: Enable SOC_INTEL_COMMON_BASECODE_RAMTOPSubrata Banik
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` config option for select mainboards, as not all board variants may want to enable this config due to underlying SoC dependencies. Mainboards that attempt to enable early caching have exhibited soft hangs while switching between pre-RAM and post-RAM phases. This patch allows mainboards to choose to enable this option without enabling it by default (which could cause boot hangs). Furthermore, it reorganizes the configuration options under BOARD_GOOGLE_BASEBOARD_REX in alphabetical order for better readability. BUG=b:306677879 TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex and intel/mtlrvp. Change-Id: If380c2ecbee4f6437c3d58bfb55be076a4902997 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-21mb/google/nissa/var/joxer: Add speaker ldo configTerry Chen
Follow thermal validation, add ldo output select for speaker. BUG=b:297298847 TEST=emerge-nissa and deploy to DUT to verify audio functionality. Change-Id: Ie68f2b35f024b4dd066d831ae8fd5a662d407753 Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-21mb/google/byra/var/*: Set LAN device type back to pciMatt DeVillier
This partially reverts commit f493857c9bc1 ("mb/google/brya/var/*: Set dGPU/LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/brya (osiris), verify LAN MAC address programmed correctly. Change-Id: I4fb43b7212e67b5c38724baad572860bc45b558e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79150 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-21mb/google/puff/var/*: Set LAN device type back to pciMatt DeVillier
This mostly reverts commit 6c705e766f7f ("mb/google/puff/var/*: Set LAN/WLAN device type to generic"). Setting the LAN device type to generic broke programming the LAN MAC address, so set it back to pci. TEST=build/boot google/puff (wyvern), verify LAN MAC address programmed correctly. Change-Id: I558ae6dc1366d5a8a22e0383d7d597d15159df03 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable HPS GPIOs if HPS_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for HPS if HPS_ABSENT for skolas and brya0 variants. BUG=b:311740746 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify via "cbmem -c | grep HPS". Change-Id: I8cbe4f40c41f1d06e8f511c3e88c05984566d441 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20mb/goog/brya/var/brya0/skolas: Disable LTE GPIOs if LTE_ABSENTNick Vaccaro
Check FW_CONFIG and disable gpios for LTE if LTE_ABSENT for skolas and brya0 variants. BUG=b:311459627 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel and verify LTE gpios are disabled via "cbmem -c | grep LTE". Change-Id: I3f3bc2b536babf71cc484cce02f96f47707f729c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79122 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-20mb/goog/brya/var/skolas: sync slolas overridetree with brya0Nick Vaccaro
Skolas uses brya0 schematic, so override tree should be almost the same for brya0 and skolas. This change sync's the skolas overridetree.cb with brya0's overridetree.cb. BUG=b:311722825 BRANCH=firmware-brya-14505.B TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot skolas to kernel. Change-Id: I14a2ed803a8ffb8614018af587c66034fb724b38 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79121 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-20mb/google/geralt: Remove unnecessary delay for MIPI panelYidi Lin
According to eDP panel datasheet[1], the eDP panel needs 0 <= x <=200ms delay after VDD powering on. The MIPI panel[2] does not need this delay. Move this delay to eDP path. [1] NE135FBM-N41 V8.0 Product Spec_P2 20191025.pdf [2] B5 TV110C9M-LL0 Product Specification Rev.P0 BRANCH=none BUG=none TEST=check FW screen TEST=check timestamp Before: 60:device initialization 696,422 (1) 15:starting LZMA decompress (ignore for x86) 696,587 (165) 16:finished LZMA decompress (ignore for x86) 696,675 (88) 17:starting LZ4 decompress (ignore for x86) 1,340,226 (643,551) After: 60:device initialization 724,259 (1) 15:starting LZMA decompress (ignore for x86) 724,425 (166) 16:finished LZMA decompress (ignore for x86) 724,512 (87) 17:starting LZ4 decompress (ignore for x86) 1,168,176 (443,664) Change-Id: I92bca5ec8269f4bad4dfab4ee193cdb5665de233 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79109 Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-11-18mb/google/brox: Use Ti50 configShelley Chen
Brox is using Ti50, so make sure that we set the right config for that. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: If4a16448eebc028b2989c1de150b9e0f9067ee92 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-18mb/google/brox: Fix GPIO assignments in gpio.hShelley Chen
Assigning the macros in gpio.h to the correct GPIOs. Also, fixing GPE configurations so that they are mapped to the proper wake sources (GPP_B, D, E groups). BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I6320cd98e560e514e63c52e173cb7923cfd1cdee Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78952 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-11-17mb/google/herobrine: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I25b7adccf60abe515d129f8d00383165eccf6431 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79028 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17mb/google/trogdor: Move selects from Kconfig.name to KconfigFelix Singer
Selects should be done in the Kconfig file instead of Kconfig.name and not mixed over both files. Change-Id: I30a15277527a1e423691ff55ff11cc2136cefc90 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-17soc/qualcomm/{sc7180,sc7280}: Allow building without QC blobs repoFelix Singer
Building coreboot for the Qualcomm SoCs SC7180 and SC7280 requires to include the Qualcomm blobs, which requires to accept their license. However, for various reasons it makes sense to build without blobs, e.g. static analysis or just build-testing. So in order to do that, run the steps integrating the Qualcomm blobs into the coreboot binary only if USE_QC_BLOBS is enabled and also remove guards which prevent building related mainboards when USE_QC_BLOBS is not enabled. Change-Id: I249ac477b8f10e7fa0848e967c23a3b3b9bbd27d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79026 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-17nb/amd/pi/00730F01: restructure chip opsFelix Held
Since this chip is a SoC and also to bring the chipset devicetree more in line with the chipset devicetree of Sandy Bridge, merge the chip operations of the northbridge's root complex and the northbridge itself into one chip operations structure and use it at the top level of the devicetree. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8b42bac07b1409bbc797bc4428cf9f84a40e94c2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17nb/amd/pi/00730F01: introduce and use chipset devicetreeFelix Held
BKDG #52740 Rev 3.05 was used as a reference for the SoC's various PCI devices. The HDA controller in the FCH at function 2 of device 0x14 on bus 0 was missing in the mainboard's devicetrees. TEST=PC Engines APU2 still boots and doesn't show any new problems Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I6970c2f6e6d661d40406586f4e6eeb05bcd07979 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79083 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-17mb/google/corsola: Configure I2C and I2S interface for ALC5650wuyang5
Configure I2S1 and I2C5 for ALC5650 to support beep sound in depthcharge. BRANCH=corsola BUG=b:305828247 TEST=Verify devbeep in depthcharge console Change-Id: Ibd098adb8d5568ad338bbfece0edfd0c38cbf854 Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79064 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-11-17mb/google/zork/morphius: Drop touchscreen detectionMatt DeVillier
Morphius boards using pre-v3.6 schematics don't have a dedicated GPIO for touchscreen power/enable, and so fail with runtime detection enabled. Since it only has one touchscreen option, and no SKUs lack a touchscreen, we can safely assume it is present in all cases. TEST=build/boot morphius w/4k screen, verify touchscreen enabled in cbmem and functional in Linux and Windows. Change-Id: I13e07e14b5a18fa1dd3b18950cf46e9d7821eedc Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78404 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16mb/google/skyrim/frostflow: Drop GPIO override for camera shutterMatt DeVillier
Appears to not be used under Windows, Linux, or ChromeOS, and causes high CPU usage at idle under Windows. BUG=none TEST=build/boot Win11, Linux on google/frostflow, verify camera shutter function unchanged, CPU usage under Windows idles where expected. Change-Id: I8a6ea3b886766bdb055b40949c75bec0264eecc5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77678 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-11-16mb/system76/rpl: Allow 5600 MT/s memory for RPL-HXMatt Parnell
System76 only sells units with memory speeds up to 5200 MT/s, but the i9-13900HX supports up to 5600 MT/s memory. Tested by running memtest and checking dmidecode reports 5600 MT/s when using 2x16 GB 5600 MT/s Crucial SODIMMs (CT2K16G56C46S5) on addw3, bonw15, serw13. Change-Id: I9bb0435769c70c1db06d2c5cca2dd28eb5331f49 Signed-off-by: Matt Parnell <mparnell@gmail.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Levi Portenier <levi@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78912 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16mb/supermicro/x11: Make use of chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I5176aa56ecaa52d0f42455bc7176b0415a6199ec Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78594 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-16mb/google/geralt: Disable SD card support for CiriRuihai Zhou
According to proto schematics, the SD card is removed. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: Id4e021e7896d093560f39c40573ac616d76438c2 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78958 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com>
2023-11-16mb/google/geralt: Move backlight-related functions to common panel.cRuihai Zhou
These backlight related functions can be reused in other variants, move them out to the panel.c. Also the panel_geralt.c should be used for Geralt, enable it on Geralt board only. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: I5d4035d5f480551c428c450826e23bf77f2fe08a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78955 Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com>
2023-11-16mb/google/geralt: Create variant CiriRuihai Zhou
Create the variant Ciri and enable MAX98390 AMP for it. The panel related support will be added in the follow up CLs. BUG=b:308968270 TEST=emerge-geralt coreboot BRANCH=None Change-Id: I7bbe9ed5e722a70bab1c799a61ce38d2ad58ab25 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78954 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-16mb/intel/mtlrvp: Create mtlrvp4es_p_ext_ec variantUsha P
This patch creates a new variant mtlrvp4es_p_ext_ec. The new variant will support ESx samples. The existing mtlrvp_p_ext_ec variant will support the QS samples. BUG=b:310775573 TEST= Build and boot mtlrvp4es_p_ext_ec. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: Iad72c0f6343af149d16d8b1f8639ba496f6aab0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/79052 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-11-16mb/google/brya/var/osiris: Update power limit values for RPL CPUDavid Wu
Update power limit values based on the suggestion of the thermal team for RPL CPU. The PL1 value (28W) suggested by the thermal team which is different from the reference document 686872 (PL1=15W). BUG=b:310834985 TEST=built and booted into OS. Change-Id: Ia2540ecd1fc453701b9160c97d82ba50b88ee848 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79059 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-15mb/google/dedede/var/pirika: Add support for new memory CXMT CXDB4CBAM-ML-ADaniel_Peng
Add support for the new memory CXMT CXDB4CBAM-ML-A. BUG=b:304932936 BRANCH=firmware-dedede-13606.B TEST=Run command "go run \ ./util/spd_tools/src/part_id_gen/part_id_gen.go \ JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" And confirm the mainboard boot normally with CXMT CXDB4CBAM-ML-A memory. Change-Id: Iff2ed16bcbc9b0755e60a284246aa928625fa26a Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78892 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-14mb/apple/macbookair4_2: Drop obsolete spd.bin fileKeith Hui
After commit 940fe080bf1e (mb/apple/macbookair4_2: Correctly implement SPD mapping the Haswell way), this file is obsolete and can be removed. Change-Id: I5afe6809c7097ab8529a3c1ec7befbd0d6f01c5f Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78784 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-11-14mb/lenovo/t530/early_init.c: Drop unused and revise used includesKeith Hui
With commit adaeb1102186 (nb/intel/sandybridge: Clean up post Haswell SPD mapping API migration), raminit_native.h now only includes 4 other headers and offers no original content. Based on the idea that all source files should include what they use directly, drop it in favor of sandybridge.h (which it already includes anyway) and types.h (replacing stdint.h because it also uses boolean constructs). Board appears to not use anything sb/intel/bd82x6x/pch.h provides. And the board still builds after dropping it. Change-Id: I1b201fe4dd29bac5feb08f372d1e36353eac161d Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78783 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-14mb/google/brox: Set unstuffed straps to NCShelley Chen
All of these signals have net names, but are actually unstuffed, so we have to set them to NC. BUG=b:300690448 BRANCH=None TEST=emerge-brox coreboot Change-Id: I27d8b7cd02aefb49a2dc031a30eb0d1e8aa9faa9 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/78951 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-11-14mb/google/eve: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I866250602701e7e83a695d346f4b404b1bbae6d5 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-14mb/google/glados: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I4f2c4f4a576ea2fd2ccb7a7e6b52cf258bac5f84 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79043 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/protectli/vault_kbl: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ie25c56f48648733095ab9d2a565c842b2f90efb2 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79041 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/kontron/bsl6: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic25d112a95903e77b58bda70bbcc3f08df383395 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-11-13mb/purism/librem_skl: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: If4f89fb81664474e03ab0ade76cfbd617127127e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79040 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/intel/kunimitsu: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: I413a3630bda841ae9ed6c4a584d2250a81c28308 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13mb/intel/saddlebrook: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic4043828baf43d14f7f2060fa3946e3a9e2008fc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79038 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-11-13mb/acer/aspire_vn7_572g: Make use of the chipset devicetreeFelix Singer
The comments related to the PCI devices are superfluous since the reference names from the chipset devicetree are used. So remove the comments and also the devices which are turned off, or in general have an equal state compared to the configuration in chipset devicetree. Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ic45446b03a3c571837fc1c41f55d60bdf2a25a7e Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>
2023-11-13mb/facebook/monolith: Make use of the chipset devicetreeFelix Singer
Use the references from the chipset devicetree as this makes the comments superfluous and remove devices which are turned off. Change-Id: Ib1adeaf4745804dfc91f99fb4e4491b68631202c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79036 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com>