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2023-08-17mb/google/rex/var/karis: Update USB settingsTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ia4bd6fe02ffa62ed8aeffb188de5c4c4b64900ff Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77106 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-17mb/google/rex/var/karis: Remove SD card and ISHTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I1575ee1d7e4c834ad15f60a3b7d63c041a8d4890 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77007 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Modify SSD settingsTyler Wang
Follow schematic, modify SSD related settings. BUG=b:294155897, b:289880020 TEST=emerge-rex coreboot Change-Id: Ie9c228ed7ccc83afaa8365f89c1d5cdedc4f0c8c Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77006 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy devicetree from rex0Tyler Wang
Add initial devicetree config for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I89585a86e8afe636d3927a21a64451b59591acda Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-17mb/google/rex/var/karis: Copy Kconfig from rex0Tyler Wang
Add initial Kconfig settings for karis. Copied from rex for support audio codec, SD card and ISH. It's only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4bcea7f5e678f2862b3477206838786ff5bad173 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77182 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Add TPM supportTyler Wang
BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: I4076ee4a16b7260db464760d5a19e1144081bab8 Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77181 Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/karis: Copy GPIO from rex0Tyler Wang
Add initial GPIO settings for karis. It's copied from rex0 and only for initial settings, will update more settings afterward. BUG=b:294155897 TEST=emerge-rex coreboot Change-Id: Ic1e52a1eaca0aa5f68661826a70ccb89d6e302dc Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77003 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-17mb/google/rex/var/ovis: Fix Bluetooth configurationJakub Czapiga
Bluetooth was missing USB configuration, so add it according to the schematics. BUG=b:290111789 TEST=Boot on Ovis and list bluetooth with `hciconfig` Change-Id: Iee8a3368bbad6c5b49f09ec7335d77ed63ecc784 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77146 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/skyrim: Enable SPL fusing on crystaldriftYunlong Jia
Enable Crystaldrift platform to send the fuse SPL (security patch level) command to the PSP. BUG=b:279499517 BRANCH=none TEST=emerge-skyrim coreboot chromeos-bootimage Then get "PSP: SPL Fusing Update Requested." in the firmware log. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1d41505e64bf54ad911ad7d287263013a9c458db Reviewed-on: https://review.coreboot.org/c/coreboot/+/77190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-08-16mb/google: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I8a04068dd986f2d5dbebecd0bff08cc0189a34d6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16mb/google: Re-arrange mainboard_smi_sleep()Kyösti Mälkki
Change the order of enabling EC and GPE wake sources, so it comes more obvious we can use existing chromeec handlers without changes. Change-Id: I5a10afa2b816dc8c01074be68a63114ee027c1e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74604 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/slippy: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I752d5644d6140e5a6d6f53543bbbc5ef7281f3b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74824 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/slippy: Re-arrange mainboard_smi_sleep()Kyösti Mälkki
Change-Id: I9ac7293e03bba773753f48163aca9385f819a71b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74822 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/auron: Use chromeec_smi_sleep()Kyösti Mälkki
Change-Id: I6b67358431d8c2b9f88b4e8948baf3497b902fed Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74821 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16ACPI: Add usb_charge_mode_from_gnvs()Kyösti Mälkki
Early Chromebook generations stored the information about USB port power control for S3/S5 sleepstates in GNVS, although the configuration is static. Reduce code duplication and react to ACPI S4 as if it was ACPI S5 request. Change-Id: I7e6f37a023b0e9317dcf0355dfa70e28d51cdad9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74524 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-16mb/google/nissa/var/pirrha: Update Kconfig for pirrhaSeunghwan Kim
Add support MIPI driver and DA7219 driver for pirrha. BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I6a8f0f942a54909627aad3bf447dc7225f57cef2 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77165 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-16mb/google/nissa/var/pirrha: Update DRIVER_TPM_I2C_BUS for pirrhaSeunghwan Kim
Correct TPM I2C BUS number for pirrha BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I9fa0b46db752d02368f19ce8c58a4122b371c100 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77164 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/nissa/var/pirrha: Increase VBT_DATA_SIZE_KB to 10Seunghwan Kim
Increase VBT_DATA_SIZE_KB to 10 since pirrha uses bigger VBT file. It includes MIPI power sequence data for panel. BUG=b:295112773 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: Ib6c293ccb4a8df3ebbd2271e7db2de4e7bd9cc3e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77163 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-16mb/google/nissa/var/pirrha: Update DQ/DQS tableSeunghwan Kim
BUG=b:292134655 BRANCH=nissa TEST=Boot to OS on pirrha ADV board Change-Id: I65429ec8d30b4458511f7c0138652528aadfde25 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76892 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-16mb/google/nissa/var/yaviks: Add elan i2c touchscreenWisley Chen
Implement support for elan i2c touchscreen and use fw_config to pick between i2c or HID-over-i2c touchscreen. BUG=b:294456574 BRANCH=firmware-nissa-15217.B TEST=build and verified touchscreen work Change-Id: I32ba97f5e5f6d280d1ae47da22360fde421a26c0 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-15mb/google/beltino/smihandler: Remove 'return' from void functionElyes Haouas
Change-Id: Iadd8a0f3bae07918990cba8f33eb1e65f4e1977a Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77188 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-15mb/google/dedede/var/boxy: update DPTF thermal settingsStanley Wu
Update DPTF thermal settings from thermal team suggestion: 1. Modify CPU passive policy to 95. 2. Modify TS0/TS1/TS2 passive policy to 90 for CPU. 3. Modify TS1 passtve policy watt to 6w. 4. Modify TS0/TS1/TS2 critical policy to 100. BUG=b:294479707 TEST=Build and verify DPTF value by thermal team on Boxy system Change-Id: Ic34e44f218ff980c54bf93841880fab5e21b3fca Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77108 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-13mb/google/nissa/var/yavilla: Adjust WLAN_PERST_L power sequenceTony Huang
With this change TPERST_HIGH could met spec. Before 160ms After 460ms(met spec min=400ms) BUG=b:295277868 TEST=emerge coreboot EE measured power sequence met spec boot to system and check wifi connection is fine Change-Id: Ifb909a55b36f2366132c3e20021c4bde4bc87a05 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-13mb/google/nissa/var/pirrha: Add GPIO tableSeunghwan Kim
Add GPIO table for pirrha based on pirrha ADV board schematics. BUG=b:292134655 TEST=FW_NAME=pirrha emerge-nissa coreboot Change-Id: I1f45365665b200fa97766344df2f9e06bc6dfb3d Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76882 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11mb/starlabs/starbook: Add Raptor Lake StarBook Mk VI variantSean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 22.04 * Manjaro 22 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I7c92bf92ab4de546c3633fae7e19a302409508ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/74444 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-11mb/google/rambi: Guard inclusion of DPTF ACPI objectMatt DeVillier
Neither Windows nor mainline Linux make use of DPTF on the Baytrail platform, so guard its inclusion with CONFIG(CHROMEOS) to prevent an unknown device being listed in Windows device manager. TEST=build/boot Win11, Linux 6.2 on google/swanky Change-Id: Ifc4d349691b647fe2d70c92bd20d1b1128b1e10a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77140 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11mb/google/geralt: Add reset.c for bootblockYidi Lin
VBOOT_CBFS_INTEGRATION needs board_reset in its logic. Otherwise, it will cause a build failure. BUG=b:294643742 TEST=build coreboot Change-Id: Ia4b81d8add71e62707f6b5a747d270caba502174 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77118 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-11mb/google/geralt: Move I2C and SPI initialization to verstageYidi Lin
After enabling VBOOT_CBFS_INTEGRATION, bootblock exceeds allocated size (60K) by 3.5K. Since TPM and EC won't be accessed in bootblock, we move I2C and SPI initializaion to verstage to reduce bootblock size. The GSC interrupt pin configuration is also moved to verstage to save more spaces for bootblock. The size of bootblock.raw.bin is reduced from 64,040 bytes to 60,808 bytes. BUG=b:294643742 TEST=boot to kernel Change-Id: I5f6855d5a1a0fce6e739d44652c88e406f6f7b89 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-08-11mb/google/rambi: add expresso variantMatt DeVillier
This variant was inadvertently missed when upstreaming other rambi variants, so add it here for completeness. Add ACPI for the light sensor to common code to match all other i2c devices. Sourced from downstream Google branch firmware-expresso-5216.223.B, commit 6f4073c0e8c8 ("baytrail: implement baytrail technical advisory 556192"). Change-Id: Ia507f95f6af85344e1ab8452f7b3c2cc61526699 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-11mb/google/brya/var/anahera: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I7a775838358e7abe3f03d0ae65fb619c15dbad6f Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76875 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-11mb/google/nissa/var/joxer: Update eMMC DLL settingsChia-Ling Hou
Update eMMC DLL settings to solve eMMC boot error. BUG=b:294196963 TEST=Reboot test 1000 times pass Change-Id: I16f3aa6aab4c58369770acad92c7ee5518c719ab Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77082 Reviewed-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-10mb/google/myst: Enable PSP VerstageKarthikeyan Ramasubramanian
Split the signed AMDFW binaries into their own section and enable PSP verstage. BUG=b:284984667 TEST=Build Myst BIOS image with PSP Verstage. Boot to OS successfully with PSP verstage and a separate section for signed AMDFW binaries. Change-Id: Ie0a54c157ebdebf9a0c95933c96865e0782a0f90 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75703 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-08-10mb/starlabs/starbook: Add support for VBOOTSean Rhodes
Add the required files to support VBOOT for when it is enabled. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I842b79d8e144414ce42b3d0d9dfd2b5180ecf70d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74230 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/adl: Update the VBTSean Rhodes
Adjust the Type-C output ports to "Integrated Displayport" to comply with FSP 4221. Change-Id: Ifcb4a086106f90c70926f44a7566330efd185544 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-10mb/starlabs/lite/glkr: Disable PSRSean Rhodes
Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3640fcea73e278e6c8968a4b0c9ba7cf04a2361f Reviewed-on: https://review.coreboot.org/c/coreboot/+/77134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-10mb/starlabs/lite/glk: Disable PSRSean Rhodes
Disable PSR in the VBT to avoid flickering on kernels later than 5.15. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5b58f4d26fa0032a5aed3af0db71a5daf41fdd8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/76941 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/adl: Enable CNVi Bluetooth UPDsSean Rhodes
Enable "CnviBtCore" and "CnviBtAudioOffload" to increase bluetooth performance. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibafabfaa39ba46620a2e06b288c457267f041ab0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/77090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/starlabs/starbook/adl: Enable the crashlog PCI deviceSean Rhodes
Change-Id: I8dc97ca0fb310417a28e253f378511f510c3b4b3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77124 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/tgl: Enable the crashlog PCI deviceSean Rhodes
Change-Id: I88831f56a259d45e3ae1f66abd1d7aaeac4ede20 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/starlabs/starbook/tgl: Use the merlin ec codeSean Rhodes
Switch the TGL variant to use the "merlin" EC variant, and delete the no longer needed "TGL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Id4d305490b48c1c79ea52b0bbaa79b675412e0b4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76332 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-10mb/starlabs/starbook/adl: Use the merlin ec codeSean Rhodes
Switch the ADL variant to use the "merlin" EC variant, and delete the no longer needed "ADL" EC variant. This is not a functional change. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I61e56cc95a26be60d7f10c89d26bce2d857ae81a Reviewed-on: https://review.coreboot.org/c/coreboot/+/76313 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/google/cyan: Guard I2C devices as wake sources with CONFIG_CHROMEOSMatt DeVillier
The use of a separate _PRW is not necessary when the _CRS interrupt already has the Wake flag set (as these all do). Additionally, Windows does not allow the use of a gpioint for the _PRW source, which results in an ACPI_BIOS_ERROR BSOD. Since ChromeOS builds for CYAN devices use an older kernel and may not make use of _CRS interrupt Wake flag, keep the _PRW around when CONFIG_CHROMEOS is selected. TEST=build/boot Win11 on google/{cyan,edgar} Change-Id: I7d0883e4de9572a14c8bad0ac086370bd00eeb1a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76798 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-08-10mb/starlabs/starbook/adl: Correct the FMAPSean Rhodes
Specify the size of the ME region so that it matches the IFD. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I51ba0a7646ab72d4dd22b99519708649c78b25b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-10mb/starlabs/starbook: Select VALIDATE_INTEL_DESCRIPTORSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I5dac42fb2239e7bc14dbe45442cc562927973b24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-08-10mb/google/rex: Create karis4es variantEran Mitrani
This patch creates a new variant karis4es. The new variant will support only ESx samples. The existing karis variant will support the QS samples. BUG=b:293326312 TEST=Image built properly Change-Id: I854fee7206528a235f027ff8ec98593a02be4806 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76761 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-09mb/facebook/fbg1701: Add config to additional listFrans Hendriks
´config´ is removed from measure list (CB:74750) Add 'config' to ram_stage_additional_list[] to have it measured and verified. BUG=NA TEST=boot and verify coreboot logs on facebook FBG1701 Change-Id: Id4119bc3a01e11f14a091facf81964d1a71092c1 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Himanshu Sahdev <himanshu.sahdev@intel.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09mb/google/kahlee: enable uart0 for console in devicetreeMatt DeVillier
Kahlee selects AMD_SOC_CONSOLE_UART causing UART0 to be used as console, so enable uart_0 in the devicetree to make sure that the UART will be marked as enabled in the SSDT that will be generated with the next patch applied. This also matches the other AMD SoC based Chromebooks. Change-Id: Ibe18f87d8bf63603fb2eb87728395e45e9a9ef69 Signed-off-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77094 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/ibm/sbp1: call soc soc_config_iio to configure IIO UPDJohnny Lin
Change-Id: I56ee0d4a26931fe05d2d35046325901930086e35 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76344 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/intel/archercity_crb: call soc soc_config_iio to configure IIO UPDJohnny Lin
TESTED=On Intel AC, after seleting DISPLAY_UPD_IIO_DATA to compare IIO UPD data are expected. lspci -vvv result is also normal. Change-Id: Icfc2a22cb2e1f95be6bfc1d712e620e19a23ce27 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76343 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-09mb/google/dedede/var/boxy: Generate new SPD ID for CXDB4ABAM-MLStanley Wu
Generate RAM ID for CXMT CXDB4ABAM-ML DRAM Part Name ID to assign CXDB4ABAM-ML 1 (0001) BUG=b:290154780 BRANCH=dedede TEST=FW_NAME=boxy emerge-dedede coreboot chromeos-bootimage Change-Id: Ide44acf6bb8e5d5023c76d9e5e48ef113f7c6ec6 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76825 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-09mb/system76/tgl: Enable Bluetooth audio offloadTim Crawford
This has two noticeable effects: 1. Devices populate the list much quicker while scanning. 2. Devices do not disappear and reappear from the list while scanning. Tested on system76/lemp10. Change-Id: I598c53805785914b4e9ae7f620e724eadbe643d4 Signed-off-by: Tim Crawford <tcrawford@system76.com> Tested-by: Daniel Sutton <daniel@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77047 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/google/brya/var/yavilla: Modify NVM size and width sizeSerin Yeh
NVM has 8KB to store camera module related settings and parameters. According to NVM hardware spec, the NVM size should be 0x400 and the width size should be 0x08. Re-set the right NVM format and ensure camera related configs can get the correct module information. BUG=b:294155898 TEST=none Change-Id: I58932bc0f3dd935aa0ea8e68b2a4b0ae4907b316 Signed-off-by: Serin Yeh <serin.yeh@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76893 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-09mb/google/brya: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. TEST=build/boot Windows/linux on redrix?, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I0273014b2d164f67f503da7b968a09256bffb43c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74929 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-09mb/google/brya: Implement touchscreen power sequencingMatt DeVillier
For brya variants with a touchscreen, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage (done in the baseboard). This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I8e56ac4834ce69de18bef2d34f5c361a7fda1aab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08mb/google/rex/variants/ovis: Use correct device_index for RT8168Stefan Reinauer
Fix ethernet MAC address configuration. Currently, coreboot would use ethernet_mac0 for both ports when setting the system's MAC address. Instead, set the right device_index for the second controller to pick up ethernet_mac1. BUG=b:294856127 TEST=boot device and observe two different MAC addresses on the ethernet ports. Change-Id: I5ff6d62d2f837a120f7095f9b9aed487e6c5aee4 Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77044 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-08mb/google/brask/var/kuldax: Set power limit values for RPL SKUsDavid Wu
Add the RPL CPU power limits and system power limits based on the suggestion of the thermal team for RPL SKUs. The PL4 value suggested by the thermal team which is different from the reference document 686872. BUG=b:292471206 BRANCH=firmware-brya-14505.B TEST=built and booted into OS. Change-Id: Ia030d13ca276c5e8340ae3b20d6e169bb162751d Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76769 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Bob Moragues <moragues@google.com>
2023-08-08mb/asrock/b75pro3-m: Drop destructive GPIO settingsFabian Groffen
Without setting these GPIO bits, you /can/ power on your board after powering it down again. This includes after cutting the power. The only way to recover from this is to pull the CMOS battery and cut the power for 15mins. Then make sure you don't do this GPIO trickery or you end up with the same state of basically an unresponsive "dead" mainboard. So flash the chip before you pull the battery. One small workaround I found when you like to flash from the system, is to press the power button with 1 second after you enable power to the board. In this small timeframe, apparently the superio chip didn't intialise/restore/gets set with the settings that make it never want to power on again. The other workaround is to connect the appriopriate pins on the ATX power connector to force power to the mainboard. Signed-off-by: Fabian Groffen <grobian@gentoo.org> Change-Id: I4c9df200ba3ec5f315ad3d184588551d29fa68ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/75212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-08mb/google/poppy/rammus: Fix jack detect GPIO configurationMatt DeVillier
Copy jack detect GPIO config of NAMI variant, which uses the same codec for the external jack/mic. The internal pull-up isn't needed, and fixes issue of high CPU usage under Windows. TEST=build/boot google/rammus, verify jack detect functional under both Win11 and Linux 6.x, no high CPU usage from excessive interrupts. Change-Id: Ifbe23a6b33343e54b43879a8971c7cb6475cf1f0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76947 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-08mb/google/nissa/var/yavilla: Update eMMC DLL settingsTony Huang
Update eMMC DLL settings to prevent eMMC initialization error BUG=b:290567342 TEST=warm/cold reboot stress test 2500 times pass Change-Id: I418836ec3e2d2221c219eae35e2b22aeaacce4a5 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76823 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-08-08mb/google/rex/var/screebo: Change sdcard clk from 7 to 6Kun Liu
Update firmware to reflect schematics change for SD Card CLKSRC from 7 to 6 for EVT board revision BUG=b:291051683 TEST=emerge-rex coreboot Change-Id: I3347f739650458c833d5a825742cf1d663853cc5 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77023 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-07mainboard/protectli/vault_cml: Switch to IT8784EMichał Żygowski
The first platform samples came with IT8786E. The production units switched to IT8784E in the final design. Change the code to use IT8784E and reflect the proprietary firmware configuration of the SIO chip. TEST=Boot Ubuntu 22.04 on Protectli VP4670 (vault_cml) and dump the configuration with superiotool and compare the configuration with proprietary firmware. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I5dc6669b592484e445c8c4bbe95d73f0a9f0392e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74175 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-08-07mb/google/dedede/var/boxy: Update power limitsStanley Wu
Add ramstage.c in Makefile.inc and update boxy power limits in Boxy ramstage.c. BUG=b:290293153 TEST=emerge-dedede coreboot and check psys and PLx value on boxy Change-Id: I4257dab358f066ebd13b6f251e8a5258a72fbd39 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76877 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mb/google/brya: Add DRIVERS_GFX_GENERIC to BRYA by defaultWon Chung
All boards based on brya will have GFX devices to represent DRM connectors in the kernel's /sys/class/drm/. There should be no functional impact with or without this patch. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I11afa9e8a1c8bf9f57bf6d195f07531182bd36f1 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-06mainboard: Add SPDX license headers to MakefilesMartin Roth
To help identify the licenses of the various files contained in the coreboot source, we've added SPDX headers to the top of all of the .c and .h files. This extends that practice to Makefiles. Any file in the coreboot project without a specific license is bound to the license of the overall coreboot project, GPL Version 2. This patch adds the GPL V2 license identifier to the top of all makefiles in the mainboard directory that don't already have an SPDX license line at the top. Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Ic451e68b1ad9ccdf34484dd98bd7fca7e177ef22 Reviewed-on: https://review.coreboot.org/c/coreboot/+/68982 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2023-08-06mb/google/brya: select ENABLE_TCSS_USB_DETECTIONMatt DeVillier
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable booting from TCSS USB-C ports. TEST=build/boot google/banshee, verify able to boot from all USB ports using edk2 payload. Change-Id: I998cc4a40950f43b4c511ead93ccc02c56c8367c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76945 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-06mb/google/volteer: select ENABLE_TCSS_USB_DETECTIONMatt DeVillier
Select ENABLE_TCSS_USB_DETECTION for non-ChromeOS builds, to enable booting from TCSS USB-C ports. TEST=build/boot google/drobit, verify able to boot from USB ports using edk2 payload. Change-Id: Ic6ab84dd5d1b980296eac043917d2cc7f14a5536 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-08-05mb/system76: Enable C10 reporting on systems using eSPITim Crawford
Report CPU C10 state over eSPI so that the EC can use Virtual Wires to detect if PECI can be used. Change-Id: I301361f35caee8ba1c3fd9227219603897add92b Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76910 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/system76/cml-u: Fix inclusion of romstage.cTim Crawford
When lemp9 was converted to a variant in CB:64528, the Makefile was not updated to handle the variant-specific `romstage.c`. This, as would be expected, caused memory init errors and broke boot on CML-U boards. Tested lemp9 boots to payload again. Fixes: 5b7b04c938f2 ("mb/system76/cml-u: Convert lemp9 to a variant") Change-Id: Ibc11d69a1662df653e6553421d67a9cd1b1d03e2 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-08-05mb/google/dedede: Enable wake from S0ix on EC_HOST_EVENT_HANG_DETECTReka Norman
BUG=b:279097356 TEST=On dibbi: - flash OS 15449.0.0 (where suspend is broken due to b:274531972) - run `suspend_stress_test --count=1 --suspend_max=30 --suspend_min=28` - check the AP wakes up immediately when the EC detects a sleep hang Change-Id: I24a2aa5de1f76e6dd1c1ce726b648583756e5e55 Signed-off-by: Reka Norman <rekanorman@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76938 Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05mb/google/dedede/var/boxy: Add power limits for N4500/N5100Stanley Wu
Add PLx from JSL PDG(ID: 613095) in boxy devicetree. BUG=b:290293153 TEST=emerge-dedede coreboot and read correct value on boxy CPU log: CPU TDP = 6 Watts, CPU PL4 = 60 Watts Change-Id: I7b063dc235fb714ba47eb620b914f2f9e92a2715 Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76876 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05mb/google/nissa/var/craaskov: Add wifi sar tableJamie Chen
Add wifi sar table for craaskov BUG=b:290739538 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ib21f674b6749e125bf76a196902c994bfac15e65 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76576 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/rex: enable d3hot for storage devicesSukumar Ghorai
_DSD "StorageD3Enable" property is needs to be set under the root port in the DSDT or SSDT. The ACPI _DSD method is the preferred way to opt D3hot support for storage devices. This also bypasses the low LTR from SSD that blocking S0i2.2 LTR/latency SoC requirement. Name (_DSD, Package () { ToUUID("5025030F-842F-4AB4-A561-99A5189762D0"), Package () { Package (2) {"StorageD3Enable", 1}, // 1 - Enable; 0 - Disable } } ) BUG=b:289028958 TEST=Check code compiles & boot rex, and verify the "StorageD3Enable" SSDT entry. Change-Id: I19decc2706954e73bc28fc2d9c3c4d18d2c384b7 Signed-off-by: Kangheui Won <khwon@chromium.org> Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76835 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/nissa/var/craaskov: Configure the external V1p05/Vnn/VnnSxRex Chou
This patch configures external V1p05/Vnn/VnnSx rails for Craaskov to follow best practices for power savings – untested though. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:290165011 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ibaf6a285788e26688d3d42691ab40052ef6d6cdb Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76926 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/nissa/var/craaskov: Add DPTF parametersVan Chen
The DPTF parameters were verified by the thermal team. Based on thermal table in 290705146#comment11. Set "tcc_offset" = "8" BUG=b:290705146 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I2d9e1ad2e2fa98757d76578956101a482073885e Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76712 Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-05mb/google/glados: use acpi_is_wakeup_s3() vs FSP UPDMatt DeVillier
To be consistent with other boards setting the keyboard backlight at boot. Change-Id: I40d8ebe468a967f0dfe1e82bff9c63f1986699c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76942 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-05mb/google/eve: Use keyboard backlight for proof-of-life at bootMatt DeVillier
This feature was originally present and then dropped, but turns out that users prefer it. Set the backlight to 50% in romstage, back to zero in ramstage; skip enabling on the S3 resume path. TEST=build/boot google/eve, verify keyboard backlight turns on/off as expected. Change-Id: I33af888d614010538f69512bbd052ed2b83fcaa5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-08-05mb/google/rambi: Fix built-in audio under WindowsMatt DeVillier
Move the jack detect GpioInt resources under the codec (where they belong), but also leave a copy under LPEA for since the Linux drivers (incorrectly) require them there. Add pin list for Windows' SST driver. Adapted from the Intel ValleyView edk2 ACPI reference code. TEST=build/boot Win11, Linux on google/swanky; verify audio functional OOTB under Linux, under Windows with coolstar's drivers. Change-Id: I51c07013fc20f07d2fd3639f7fbc2af0e0e490a0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76795 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2023-08-05mb/google/cyan: Adjust ACPI for Maxim audioMatt DeVillier
- add HRV and GpioIO for coolstar's windows drivers - fix interrupt type for TI jack detect switch TEST=build/boot Win11, Linux on google/cyan; verify audio working OOTB under Linux, under Windows with coolstar's audio drivers. Change-Id: I6bf6bb9e9989ca8f42436800666d95dd05799838 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76800 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-08-04mb/hp: Add EliteBook 820 G2Iru Cai
Most of the components of this laptop are tested to work, which is listed in the documentation. Change-Id: Id8b3b7f735460c5e76a2dc9ab2d10154e6606ad6 Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46630 Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04mb/amd/birman/port_descriptors_phoenix.c: Disable ASPMFred Reitberger
Disable ASPM on ethernet, sd card, wwan, wlan, and ssd0 PCI devices. This reduces kernel error logs such as: [ 15.172613] r8169 0000:01:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I7b1605f18a91ed20bfc6ab70547c415e0278d290 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74970 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-04mb/google/skyrim: Select ACPI_S1_NOT_SUPPORTEDTim Van Patten
As of OS/FW: 15276.0.0 - Skyrim is not able to wake from S1/standby. The wake issue either needs to be fixed, or S1 should not be advertised as a capability in the ACPI table. Select ACPI_S1_NOT_SUPPORTED to indicate that ACPI state S1 is not supported on Skyrim devices. This results in 'standby' being removed from /sys/power/state. BUG=b:263981434 TEST=suspend_stress_test TEST=frostflow-rev2 ~ # cat /sys/power/state freeze mem Change-Id: I85fcdca34187a8c275cf5a93beb931dfb27a7c87 Signed-off-by: Tim Van Patten <timvp@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-08-04mb/google/{rex,ovis}: Disable C1-state auto demotion for rex & ovisSukumar Ghorai
C1-state auto demotion feature allows hardware to determine C1-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. Also, disabling this feature results soc to enter PC2 and lower state in camera preview case and save platform power. Note: C1 demotion heuristics used EPB parameter to balance between power and performance, i.e. low threshold when EPB is low in-order to get C1 demotion faster and vice-versa. ChromeOS operates at default EPB=0x7 (low EPB) in both AC/DC, so in DC mode it gets more C1 demotion hits than expected (similar to AC mode) and losing power respectively. BUG=b:286328295 TEST=Code compiles and correct value of c1-state auto demotion is passed to FSP. Also verified PC residency improvement ~10% in camera preview case. Change-Id: I548e0e5340dec537d05718dd2f4652e10fb36ac0 Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-04mb/google/rex/var/screebo: Add fw_config probe for GL9750 and RTS5227SKun Liu
Add support for SD card reader GL9750 and RTS5227S BUG=b:284273384 TEST=emerge-rex coreboot Change-Id: I98aa0d3e52c355f6c1528c912a6fa0f32652dda8 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-04mb/google/dedede/var/pirika: Support for Samsung K4U6E3S4AB-MGCLDaniel_Peng
Add the new memory support: Samsung K4U6E3S4AB-MGCL BUG=b:294151054 BRANCH=firmware-dedede-13606.B TEST=Run command "go run ./util/spd_tools/lp4x/gen_part_id.go JSL lp4x \ src/mainboard/google/dedede/variants/pirika/memory/ \ src/mainboard/google/dedede/variants/pirika/memory/\ mem_parts_used.txt" Change-Id: Ief9bbf11fc05c8155f1da7188926a29dbbfbe488 Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76542 Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/ibm/sbp1/Kconfig: Remove unused MAX_SOCKET_UPDElyes Haouas
Change-Id: I5d9133f2255a96c8367f69dcbb198a1a142cdb82 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-08-03mb/google/nissa/var/pirrha: Generate SPD ID for supported memory partSeunghwan Kim
Add pirrha supported memory parts in mem_parts_used.txt, generate SPD IDs for them. 1. K3KL8L80CM-MGCT (Samsung) 2. K3KL6L60GM-MGCT (Samsung) BUG=b:292134655 BRANCH=nissa TEST=FW_NAME=pirrha emerge-nissa coreboot chromeos-bootimage Change-Id: Ib3f5a5e5c8296f976d92f0196026d7bb63845664 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76881 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-03mb/google: Add more comment on GFX devices for the future referenceWon Chung
Add more details to instruct future boards/models implementers regarding how GFX devices should be added. If HDMI and DP connectors are enumerated by the kernel in /sys/class/drm/ then corresponding GFX device should be added to ACPI. It is possible that some connectors do not have dedicated ports, but still enumerated. The order of GFX devices is DDIA -> DDIB -> TCPX. BUG=b:277629750 TEST=emerge-brya coreboot Change-Id: I59e82ee954a7d502e419046c1c2d7a20ea8a9224 Signed-off-by: Won Chung <wonchung@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76776 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-08-03mb/google/nissa/var/craaskov: Add overridetreeRex Chou
Add override devicetree based on schematics(ver. 20230714). BUG=b:290248526 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Id002282d91dc94b00f5d133203b62ca39d6cae6d Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76662 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-02mb/google/rex/variants/ovis: Use and configure RT8168 driverStefan Reinauer
This makes sure google/ovis don't get a random mac address on boot. Additionally, program the LAN WAKE GPIO properly as per the Ovis schematics dated July'23. BUG=b:293905992 TEST=Verified on google/ovis that able to get the fixed MAC address across the power cycles. Change-Id: I699e52e25f851de325f96ef885e04d15ca64badd Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76872 Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-08-02mb/google/dedede/var/storo: Generate SPD ID for Samsung K4U6E3S4AB-MGCLtongjian
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for Samsung K4U6E3S4AB-MGCL. BUG=b:293240969 TEST=emerge-dedede coreboot Change-Id: I92a1f2110e74b5d25572e0e86e04b5b32112c1f5 Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-08-02mb/google/nissa/var/craaskov: Configure GPIOs according to schematicsRex Chou
Configure GPIOs based on schematics and confirm with EE. BUG=b:290248526 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I17fc9333a0ef592ea36b196b3fd417be47fb82bb Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76636 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-08-02mb/google/nissa/var/joxer: support DPTF oem_variablesMark Hsieh
1. Joxer uses dptf.dv to distinguish 6W/15W by setting OEM variable. 2. Update passive policy and critical policy. BUG=b:285477026, b:293540179 TEST=emerge-nissa coreboot and check the OEM variable. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I4e52ac624f7d7628cce3035a2bac67fc527bc167 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ivan Chen <yulunchen@google.com>
2023-08-01mb/google/rex/var/screebo: Enable RTD3 for SSDKapil Porwal
Currently, S0iX test is failing because S0i2 susbstate is blocked. Enable RTD3 for SSD to unblock S0i2.2 substate residency. BUG=none TEST=Screebo can enter into S0iX. S0iX substate residency w/o this CL - ``` Substate Residency S0i2.0 0 S0i2.1 38451594 S0i2.2 0 ``` S0iX substate residency w/ this CL - ``` Substate Residency S0i2.0 0 S0i2.1 12108 S0i2.2 33878424 ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I50ac730820b3f29c387dc73bd90f1392a8797e24 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-08-01mb/google/rex/var/screebo: Restrict ASPM to L1 for SD controllerKapil Porwal
Restrict ASPM to L1 for SD controller to avoid AERs. BUG=b:288830220 TEST=No PCIE AER on SD controller on Screebo. w/o this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L0s L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2- PCI-PM_L1.1- ASPM_L1.2- ASPM_L1.1- ~ # dmesg | grep -i -e "pci.*error" [ 0.734597] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 0.734882] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 0.735258] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 0.736159] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.520903] pcieport 0000:00:06.1: AER: Corrected error received: 0000:02:00.0 [ 1.531587] rtsx_pci 0000:02:00.0: PCIe Bus Error: severity=Corrected, type=Data Link Layer, (Transmitter ID) [ 1.548894] rtsx_pci 0000:02:00.0: device [10ec:522a] error status/mask=00001000/00006000 [ 1.567490] pcieport 0000:00:06.1: AER: Multiple Corrected error received: 0000:02:00.0 ``` w/ this CL - ``` ~ # lspci -s 00:06.0 -vvv | grep -i aspm LnkCap: Port #9, Speed 16GT/s, Width x4, ASPM L0s L1, Exit Latency L0s <4us, L1 <64us ClockPM- Surprise- LLActRep+ BwNot+ ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # lspci -s 02:00.0 -vvv | grep -i aspm LnkCap: Port #0, Speed 2.5GT/s, Width x1, ASPM L0s L1, Exit Latency L0s unlimited, L1 <64us ClockPM+ Surprise- LLActRep- BwNot- ASPMOptComp+ LnkCtl: ASPM L1 Enabled; RCB 64 bytes, Disabled- CommClk+ L1SubCap: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ L1_PM_Substates+ L1SubCtl1: PCI-PM_L1.2+ PCI-PM_L1.1+ ASPM_L1.2+ ASPM_L1.1+ ~ # dmesg | grep -i -e "pci.*error" ``` Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I05f02c46486be42286fe9bc4f4be17763bb12b79 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76829 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-08-01mb/google/dedede/var/cret: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. H54G56CYRBX247 2. H9HCNNNCPMMLXR-NEE 3. MT53E1G32D2NP-046 WT:B 4. K4UBE3D4AB-MGCL 5. K4UBE3D4AA-MGCR BUG=b:290811418 BRANCH=dedede TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage Change-Id: Ib7f23dc3604fe1869772d92c9d7b8cc32ed9bbb9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-31mb/google/rex: Allow to show early splash screen using GFX PEIMSubrata Banik
This patch chooses to show the early splash screen which is an OEM feature. The current implementation is relying on the Intel FSP GFX PEIM to perform the display initialization. Having this feature allows the platform to show the user notification with 500ms since boot compared to traditional scenarios where first user notification is coming from kernel (typically ~3sec+ after cpu reset). Eventually this feature will help to improve the user experience while booting Intel SoC platform based chromeos devices. BUG=b:284799726 TEST=Able to see the early splash screen on google/rex. Change-Id: I399ddb6618e774302200e8a87629647ba070d080 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76361 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/cyan: Disable unused devices in devicetreeMatt DeVillier
These devices are not present/used on CYAN boards. Change-Id: I012b49562c2b932822823537032e2265901ddc81 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76799 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-07-31mb/google/rex: Create Ovis4ES variantJakub Czapiga
Ovis4ES variant supports only ESx SoCs. Existing Ovis variant will support QS SoCs. BUG=b:293409364 TEST=util/abuild/abuild -p none -t google/rex -b ovis4es -x -a TEST=util/abuild/abuild -p none -t google/rex -b ovis -x -a Change-Id: Iacf5ef6d3dfee8838fe13e68b254a84e4a6cf200 Signed-off-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76789 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/rex/var/ovis: Simplify the USB-C port mappingSubrata Banik
This patch changes the `EC CONx Mapping` to fix the hot-plug issue where attaching a device to USB-C port C1 can affect the USB-C display over port C2. Note: `PMC MUX Mapping` remains unchanged to reflect the underlying board design where the physical MUX has swapped between C1 and C2 USB-C port. Before: | PMC MUX Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | | EC CONx Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | Physical Mapping between EC and SoC as below: Port C0 - EC CON0 ----> PMC MUX CON0 Port C1 - EC CON1 ----> PMC MUX CON2 Port C2 - EC CON2 ----> PMC MUX CON1 After: | PMC MUX Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | | EC CONx Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 1 | 3 | | USB3-Port | 0 | 1 | 2 | Physical Mapping between EC and SoC as below: Port C0 - EC CON0 ----> PMC MUX CON0 Port C1 - EC CON1 ----> PMC MUX CON1 Port C2 - EC CON2 ----> PMC MUX CON2 Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I59e2630bc0f93321cc4b734fcf3c4cf254882477 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-31mb/system76/addw1: Disable SaOcSupportJeremy Soller
Typically we set SaOcSupport to allow overclocking RAM, but addw2 saw a high rate of errors when using the provided 3200 MHz DIMMs. Disable OC so modules run at the standard 2933 MHz. Change-Id: I469b9c73d2e6bfa0b3c9175bcc87584aeaa95f75 Signed-off-by: Jeremy Soller <jeremy@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-30 05:45:50 +0000