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2022-12-24mb/google/rex: Use GPP_C15 as WWAN_DPR_SAR_ODLSubrata Banik
BUG=b:263413949 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I453fe8e1f4b4b8d4730ade259899d76aec949a44 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71231 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/rex: Rename GPP_D07 to FPMCU_UWB_MUX_SELSubrata Banik
BUG=b:263412235 TEST=Able to build and boot Google/Rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ia444cc8e3666fe15479ece81d068f9e8f1d339ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/71228 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-24mb/google/nissa/var/craask: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I04176fee373e534d42c72506df73a092ad55e65b Reviewed-on: https://review.coreboot.org/c/coreboot/+/71218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/volteer/var/lindar: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib34e6b4f435880d62936ae54f19ba2ec752eced2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/brya/var/taeko: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. WIFI_SAR_CBFS_DEFAULT_FILENAME is not exist, so return the non-exist id has the same outcome. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ib7a764d8cc3160c26abad9c1757812b955bef066 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-24mb/google/nissa/var/pujjo: Use get_wifi_sar_fw_config_filenameEric Lai
Use get_wifi_sar_fw_config_filename to remove the duplicate code. Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: Ifde714c19f7ab9fe08f870060037db190a80dbd0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2022-12-23mb/google/poppy: Use runtime detection for touchscreens/digitizersMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens/digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on all poppy variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I4c1d8ae8c41c1f4283718a86fccbf5ae4fc399b6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70921 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/poppy: Set touchpad/touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: Iee01dac943b6c2955f7af42ce0e9395fc609682f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70920 Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/poppy: Implement touchscreen,digitizer power sequencingMatt DeVillier
For touchscreens/digitizers on poppy variants, drive the enable GPIO high and hold in reset in romstage, then release from reset in ramstage. This will allow coreboot to detect the presence of i2c touchscreens/digitizers during ACPI SSDT generation (enabled in a subsequent commit). TEST=tested with the rest of patch train Change-Id: I90ac4f09c343a28328f7d30254f0448cbe0c78b3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2022-12-23mb/siemens/mc_apl{4,7}: Limit I2C bus speed to 100 kHz on bus 7Werner Zeh
Due to a high I2C bus load on the mainboard I2C frequency of 400 kHz leads to poor signaling. Therefore limit the I2C speed to 100 kHz for this bus. In addition, add a generic I2C device with 100 kHz bus speed to the devicetree so that the OS will not switch to higher clock rates, too. Test= Measure the I2C signals at coreboot and OS runtime and ensure the clock is always at 100 kHz. Change-Id: I6b0a642cd3f5b77331663ac8c76ed0a116ae77ca Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71227 Reviewed-by: Jan Samek <jan.samek@siemens.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/geralt: Pass SD card detect GPIO to payloadsLiju-Clr Chen
1. Add an option for SD card initialization. 2. If CONFIG SDCARD_INIT is configured, pass SD card detect GPIO to payloads for SD card detection and initialize MSDC for SD card configuration. BUG=b:244250437 TEST=build pass Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Change-Id: I2d3683eb673f438c9190c11d4679a3ca97c76a98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/71136 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-23tree: Replace And(a,b) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b)` with `a & b`. Change-Id: Id8bbd1a477e6286bbcb5fa31afd1c7a860b1c7dc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70851 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace And(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `And (a, b, c)` with `c = a & b`, respectively `c &= b` where possible. Change-Id: Ie558f9d0b597c56ca3b31498edb68de8877d3a2f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70850 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace Or(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `Or (a, b, c)` with `c = a | b`, respectively `c |= b` where possible. Change-Id: Icf194b248075f290de90fb4bc4e9a0cd9d76ec61 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70846 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b)` with `a << b`. Change-Id: I812b1ed9dcf3a5749b39a9beb9f870258ad6a0de Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70842 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftLeft(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftLeft (a, b, c)` with `c = a << b`. Change-Id: Ibd25a05f49f79e80592482a1b0532334f727af58 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70841 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23tree: Replace ShiftRight(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `ShiftRight (a, b, c)` with `c = a >> b`. One case was simplified to just `a >> b`. Change-Id: I889012b0a3067138e6f02d3fe8e97151effb5c2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70840 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-23mb,x86/smm: Disable unused IO trapsKyösti Mälkki
Only IO trap #3 for lenovo/x60,t60 and getac/p470 have implemented the IO trap handler. Change-Id: Ibadce174f673e88380f4b6745fd9ed8b73177a13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70367 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/poppy/nocturne: Fix touchscreen reset GPIO configMatt DeVillier
The touchscreen reset GPIO is configured as PAD_CFG_TERM_GPO with an internal pull-down, which puts it in a state of contention when the reset pin is released / set to high. Fix this by changing the reset GPIO to PAD_CFG_GPO like all other poppy variants use for the touchscreen reset. TEST=build/boot nocturne, touchscreen still works. Change-Id: I1ad4bb9d4194485990f54ffa7bae05f5c9a39deb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71185 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/sarien: Add default fmap for non-ChromeOS buildsMatt DeVillier
Test: build/boot google/sarien with non-ChromeOS build, edk2 payload. Linux 5.15, Windows 11 tested. Change-Id: Ibc1857e6b120b0bb827ed610981c4d2bf8f78d1f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/hatch: Use runtime detection for touchscreens/digitizersMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple hatch variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I2eae486eaa5e42cfe42ecc066a58b09fe2bd9138 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71062 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/hatch: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I580348d0aabb24f0241d6e9992c5a17942bd57ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/hatch/*: Add missing enable GPIO for ELAN touchscreensMatt DeVillier
Some ELAN touchscreens were missing the entries for the enable GPIO and associated delays. Add them to variants with ELAN0001 touchscreens missing the entries. TEST=tested with rest of patch train Change-Id: I9ce81ad6ee8183c522d05fbe3f57af87e5895df3 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2022-12-23mb/google/hatch: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on hatch variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I86c5f41b7820eaf5252c276ae854a4206e09385f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71059 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-23mb/google/hatch: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I1939387b5bb98d6d282fd044e9ce8780dbe0d2c5 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71058 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/poppy/rammus: disable USB xDCIMatt DeVillier
With xDCI enabled, the right USB-C port does not work for USB data. Additionally, it was disabled in stock ChromeOS firmware. TEST=build/boot rammus, confirm right USB-C port works for booting, under OS in Windows/Linux. Change-Id: Ie343577d772563fa7d432b62aa8faa41d760102a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/zork: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on berknip/morphius, verify all touchpad functions work correctly. Change-Id: I9d8362719ddbfe523dd83964556b05bb8f1bb1ba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71138 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-23mb/google/volteer: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on lindar, verify all touchpad functions work correctly. Change-Id: If2deedbd572b771c1e7793a3b3c37a3114aa2a48 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/reef: update ACPI HID/CID for Synaptics touchpadMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on coral, verify all touchpad functions work correctly. Change-Id: I161eb953bf8bceb353cf43803ee948c522928892 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/poppy: update ACPI HID/CID for Synaptics touchpadMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on nami, verify all touchpad functions work correctly. Change-Id: I0611da8bbea41565e603a1a1b7cc20226ba21c62 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/hatch: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on bobba, verify all touchpad functions work correctly. Change-Id: I4fd66be21eeff5f37b58a8922c49683a28685064 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/kahlee: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on liara, verify all touchpad functions work correctly. Change-Id: I89ca02629803882e7ed2048a5a26868fc2de41a9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/hatch: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on akemi/kohaku, verify all touchpad functions work correctly. Change-Id: Icb552caa69428908e5e3342139b578a145fa2797 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/guybrush: update ACPI HID/CID for Synaptics touchpadMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot ChromeOS, Linux 5.1x, Windows 10 on dewatt, verify all touchpad functions work correctly. Change-Id: I00efde6f007d57166cd82f76d2f389dedce57466 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/dedede: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=boot Linux 5.1x, Windows 10 on drawcia, verify all touchpad functions work correctly. Change-Id: I43eb5bc394a3fbfd4109f2e6c274ec66fc01d46d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/brya: update ACPI HID/CID for Synaptics touchpadsMatt DeVillier
The currently assigned ACPI HID 'PNP0C50' is not a valid per Windows WHQL validation tests. To ensure compatibility with both Windows and Linux, set the HID to 'SYNA0000' and CID to 'ACPI0C50' as previously done for other boards (eg, google/lulu). TEST=untested on brya, but tested under Windows/Linux on all other boards in the tree using Synaptics touchpads. Change-Id: Ia9351185b918f2d6f2d2be110b88e8310d37a03f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/volteer: Add missing audio codec to HDA probeMatt DeVillier
Audio codec RT1011_ALC5682I_I2S is listed as a fw_config option in the baseboard, but missing from the HDA device probe list in the variant overridetrees, preventing it from being detected at boot. TEST=build/boot lindar, verify audio codec identified and HDA device not disabled by fw_config. Change-Id: Ib40b095688aac5cf4e0a60dcac250023c4f04c9f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/reef: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple reef variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I8c90074515b1c7d3ab742768d7bbd904fec256d4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71154 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/reef: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I1000df10eea5670bf1bc8d04c736150b6a5e26a1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/reef: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on reef variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). As the GPIOs are already correct in ramstage, only the romstage ones need to be set. BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I10d1789c8de23653bac81e1f9604a47f93fa3f7d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71152 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/reef: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Id3ab412183e5c5d534b2e1dea3222c729c25118b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71151 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/google/volteer: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. BUG=b:121309055 TEST=build/boot Windows/linux on multiple volteer variants, verify all touchscreens functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I0448d12a36f522b715e1fbeb8d37eb5a925ebc93 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71183 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Set touchscreen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I269361f90a838d7766ad429afe82ef885f0d9371 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71182 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on volteer variants, drive the enable GPIO high starting in romstage, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: Ie4c3b94594253ced6a875af78e6390cda8dcbc7d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71181 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/google/volteer: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: Ib3c2a0e849006b7bf70cbd0bf6f32aa01ccf1bc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71180 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22mb/starlabs/*: Bind console serial output to EDK2_DEBUGSean Rhodes
Configure the UART port but only enable UART debug for EDK2 debug builds. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I54e1dc5768fd765254c7ede91eaa45842fed3bd6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/69322 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-22soc/intel/xeon_sp: Move codes to support new PCHTim Chu
Different PCHs have different definitions for registers. Here create a lbg folder and move lbg specific codes to this folder so that we can add new PCH code under xeon_sp folder. * Create lbg folder and move lbg specific codes from pch.c to soc_pch.c under lbg folder. * Rename lewisburg_pch_gpio_defs.h to gpio_soc_defs.h and move to lbg folder. * Rename gpio.c to soc_gpio.c and move to lbg folder. * Move pcr_ids.h to lbg folder. * Move lbg specific codes from pmutil.c to soc_pmutil.c under lbg folder. * Create and revise makefile for files under lbg folder. TEST=Can boot into OS on OCP Delta Lake. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I06555ed6612c632ea2ce1938d81781cd9348017a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70009 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-22mb/skyrim/var/frostflow: enable dptc tablet mode switchChris.Wang
add dptc power parameter for tablet mode sustained_power_limit_mW_tablet : 12w BUG=b:257187831 BRANCH=none TEST= validate the parameter changes for each mode by AGT Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I22d3f9c79a1eaaccfbef3766019516edb3523964 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70674 Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
2022-12-22mb/google/nissa/var/yaviks: Extend sd_hold for touchpad/touchscreenWisley Chen
Extend sd_hold to meet touchpad/touchscreen SPEC. touchscreen: tHD > 0.2 us touchpad: 0.3 us < tHD < 0.9 us After applied the change, the tHD meets reqirement. touchscreen: 0.056 us -> 0.28 us touchpad: 0.056 us -> 0.384 us BUG=b:263340540 TEST=build and measure the timing meet SPEC Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I172d2ec8a4b16d8005106f55a37795cc72d69e98 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70195 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-22mb/google/nissa/pujjo: Tuning eMMC DLL value for eMMC initialization errorLeo Chou
Configure eMMC DLL tuning values for Pujjo board Kioxia sku. BUG=b:261676386 TEST=Use the value to boot on Pujjo successfully. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I46991f26571771620dcd94b90e1112484ade63bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/71129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2022-12-21mb/google/brya/var/kano: select SOC_INTEL_RAPTORLAKENick Vaccaro
Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers for FSP as kano is using a converged firmware image. BUG=b:253337338 BRANCH=firmware-brya-14505.B TEST=Cherry-pick Cq-Depends, then "FW_NAME=kano emerge-brya coreboot-private-files-baseboard-brya coreboot chromeos-bootimage", disable hardware write protect and software write protect, flash and boot kano in end-of-manufacturing mode to kernel. Cq-Depend: chrome-internal:5246998, chromium:4119763 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Change-Id: I30ab7d829a6cb45b4e0cd38747501ba0eb6bd6cd Reviewed-on: https://review.coreboot.org/c/coreboot/+/71175 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21soc/intel/skl; mb/google/eve,poppy: Update NHLT methodsMatt DeVillier
Adapted from WIP (and now abandoned) patches CB:25334, 26308, 26309. Update the nhlt_soc_add_*() methods for max98373, max98927, and rt5514 codecs to program the render and feedback slot numbers as appropriate. TEST=boot Windows on google/eve, atlas, nocturne, and rammus. Verify audio functional with both Google project campfire drivers as well as coolstar's AVS audio drivers. Change-Id: Ib8c6e24ba539e205bd5bbd856ecff43b2c016c2e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: CoolStar <coolstarorganization@gmail.com>
2022-12-21mb/siemens/mc_ehl3/devicetree.cb: Remove TSN GbE 0Jan Samek
Remove the PSE TSN GbE device #0 as it's unused on the board and not visible during the PCI enumeration. Change-Id: I4a7d0e437c4f4a12d3a07564cddeafb7c697c6d3 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70700 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/siemens/mc_ehl3/mainboard.c: Remove XIO2001 register tweaksJan Samek
Contrary to mc_ehl2, which this variant is based on, this board doesn't contain the TI XIO2001 PCIe-to-PCI bridge, which makes the attempts to modify the bridge's registers unnecessary. Change-Id: I6597ceb78e4c790c08a0dfa9535dece33a8f95b8 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70854 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Use runtime detection for touchscreens/digitizersMatt DeVillier
Switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens and digitizers. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. Test: build/boot Windows/Linux on various octopus variants, verify touchscreens/digitizers functional, dump ACPI tables and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I67c5bbae42e96ae21d37309e382b635321e6ef01 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63214 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
The GPIOs themselves are configured as level triggered, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE triggering. TEST=tested with rest of patch train Change-Id: I13bc6920a0dfaf769091b1764a7584902d1f85d6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63213 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Implement touchscreen/digitizer power sequencingMatt DeVillier
For octopus variants with a touchscreen/digitizer, drive the enable and reset GPIOs high in romstage, then disable the reset GPIOs in ramstage. Where available, only set the GPIOs for SKUs which have a touchscreen. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). TEST=tested with rest of patch train Change-Id: Ia725b4054069c0a4f60afd7e0bca6e2fd5fdcbba Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/63212 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/octopus: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty weak implementation to allow variants to override as needed for touchscreen power sequencing (to be implemented in a subsequent commit). Call method in romstage to program any GPIOs the variant may need to set. TEST=tested with rest of patch train Change-Id: I4a8e11945ae64b000051989089e0ebae22896c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70905 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/intel/mtlrvp: Enable ChromeOS build for mtlrvpHarsha B R
This patch enables building ChromeOS for mtlrvp. Patch includes, 1. Add cros_gpios for mtlrvp 2. Add chrome OS configuration in Kconfig 3. Add Chromeos.c BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train (CB: 69886) Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: Ia428941bd8269714c3edca6c7b0c2a3fbf08bd75 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70724 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-21mb/google/skyrim: Fix Bluetooth configurationKarthikeyan Ramasubramanian
Power resource for Bluetooth device is not configured correctly in the device tree. Fix Bluetooth devicetree configuration. BUG=b:262785310 TEST=Build Skyrim BIOS image and boot to OS. Ensure that the DUT is able to connect to a Bluetooth headset. Change-Id: Id980424349537be35860dec04cc823d419cefe2f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71068 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20soc/amd/mendocino: add dptc tablet mode supportChris.Wang
add dptc support for different power parameter on tablet/clamshell mode. BUG=b:257187831 BRANCH=none TEST=validate the parameter change for each mode by AGT. Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I96e04d113d18b42f3457056a5e4fa311ceccffb3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20mb/google/skyrim/var/frostflow: Config I2C frequency for touchpad.Rex Chou
1.Config setting for touchpad I2C BUG=b:261159229 TEST=On frostflow, touchpad i2c spec from EE measure Frequencies: 1.I2C0 (Touchpad): 385.7kHz Change-Id: I4ca72ee7fabd4b641eb17451ed8d942c5df52dde Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2022-12-20mb/starlabs/starbook/adl: Set thermal trip based on power profileSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I07be0aa2144b7718e28f1f675978b4b4b92752ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/69492 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Add files required for ramstage and SMMHarsha B R
This patch adds files required for ramstage and SMM. 1. Add file required for ramstage (mainboard.c) 2. Add smihandler.c for SMM BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with the subsequent patches in the train Signed-off-by: Harsha B R <harsha.b.r@intel.com> Change-Id: I377c4ff954a900c7b5193d7cab5554c6c02573ee Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70723 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-20mb/intel/mtlrvp: Enable EC for mtlrvpJamie Ryu
This patch will initialize EC for mtlrvp which includes, 1. Add configuration (& choice) for CHROME_EC and INTEL_EC (WINDOWS_EC) 2. Add respective ACPI configuration 3. Add ec.c required for ramstage 4. Program EC ranges as part of devicetree.cb 5. Enable VBOOT in Kconfig BUG=b:224325352 TEST=Able to build with the patch and boot the mtlrvp platform with CHROME_EC using subsequent patches in the train Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I662d7f79050d35e152d97dc5c2118a4af56223bc Signed-off-by: Harsha B R <harsha.b.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/66101 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-19tree: Replace XOr(a,b,c) with ASL 2.0 syntaxFelix Singer
Replace `XOr (a, b, c)` with `c = a ^ b`, respectively `c ^= b` where possible. Change-Id: Ic5f67684bbd4ea115c4dae8a4417d88bea0d6b77 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70843 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
2022-12-19mb/google/octopus: Add NHLT endpoints for Cirrus Logic codecMatt DeVillier
Add NHLT endpoints for octopus boards using CS42L42 codec. Reuse method to add da7219 endpoint as the routing is identical. TEST=boot Windows, verify audio working with coolstar's audio drivers. Change-Id: Id68997073752f5d90b6fe21f666a6140e22d65eb Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/octopus: update variant VBTsMatt DeVillier
Remove flag in VBTs for 'Use fixed resolution at boot' to allow FSP/GOP display init to use native panel resolution instead. TEST=build/boot multiple google/octopus variants with edk2 payload, verify boot logo not distorted/stretched. Change-Id: Ia31ff28379282619dfa22a955bee1a768bb54bb8 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/hatch/kohaku: set VBT boot resolution to 1080pMatt DeVillier
Boot menus are too small at native 4K res on some panels, so set fixed display resolution to 1920x1090p TEST=build/boot KOHAKU with 4K display, verify boot menu text legible. Change-Id: I82563c83de7ab302151f60d86b8a6824330d03ea Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70370 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2022-12-19mb/google/brya/var/marasov: Configure I2C high and low timeFrank Chu
Adjust I2C speed for codec, TPM, touchpad, touchscreen. BUG=b:260565911 TEST=Built and verified adjusted I2C speed Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Idcec6e401992d30dff01940c50473cba48cffc19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70232 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2022-12-17mb/siemens/mc_ehl3/devicetree.cb: Adapt PCIe root port settingsJan Samek
Based upon hardware differences from mc_ehl2, disable RP7 and enable RP3 and RP5. Change-Id: Iecaa3098c3e4c9ce15254bb8bd1fe6da86d6e706 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70689 Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-17mb/siemens/mc_ehl3: Add board variant based on mc_ehl2Jan Samek
Add a new mc_ehl variant, which is based on mc_ehl2 implementation. This patch uses a copy of mc_ehl2 with changes only in naming as a starting point for the new mc_ehl3 variant. Follow-up patches will introduce the functional changes against mc_ehl3. Change-Id: Ie8c18b4f16d88b175ce576c2ef4c2e6ee0b4c306 Signed-off-by: Jan Samek <jan.samek@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70688 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2022-12-17mb/google/nissa/var/yaviks: Enable wifi SARWisley Chen
Enable wifi sar function for yaviks. Use the fw_config to separate SAR setting for different wifi card. BUG=259199095 TEST=build, enabled iwlwifi debug, and check dmesg Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I3ced65368ee66e084e58d66cff8f75147f665d71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70750 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17mb/google/nissa/var/pujjo: Tunning RegProxCtrl0 register for SX9324Stanley Wu
Update SX9324 RegProxCtrl0 register settings based on tunning value from P-sensor vendor. BUG=b:242662878 TEST=i2cdump -y -f 13 0x28 on Pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: If471a6fee5a3daeac1958709415b2d5e1329b81b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-17mb/starlabs/starbook: Add Alder Lake StarBook Mk VI variantBen-StarLabs
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_202209`: * Windows 10 * Ubuntu 20.04 * MX Linux 19.4 * Manjaro 21 No known issues. https://starlabs.systems/pages/starbook-specification Signed-off-by: Ben-StarLabs <ben@starlabs.systems> Change-Id: Idc0c265a88b19cf9e89cc8ab3e8db9abd8cf8409 Reviewed-on: https://review.coreboot.org/c/coreboot/+/65785 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <inforichland@gmail.com>
2022-12-17mb/google/skyrim: Configure RO and RW SPL filesKarthikeyan Ramasubramanian
This will help to integrate RO SPL table in RO partitions such that it is used before PSP verstage is loaded. After PSP verstage, SPL table in RW partition gets used. BUG=b:243470283 TEST=Build Skyrim BIOS image and boot to OS. Change-Id: Ic2061f66381d7e9a8018e6f28aa0bc2ca6010f6f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70777 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16mb/google/brya/var/lisbon: Use RPL FSP headersKevin Chiu
To support an RPL SKU on lisbon, lisbon must use the FSP for RPL. Select SOC_INTEL_RAPTORLAKE for lisbon so that it will use the RPL FSP headers for lisbon. BUG=b:246657849 BRANCH=firmware-brya-14505.B TEST=FW_NAME=lisbon emerge-brask intel-rplfsp coreboot-private-files-baseboard-brya coreboot chromeos-bootimage flash and boot lisbon to kernel. Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Change-Id: Ie60c357ef0a2af2fec90df4a54e56f51ceb927d3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2022-12-16mb/google/brya/var/marasov: Update gpio table for EVTFrank Chu
BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Id5a73126737a3abbe6f0ef37276ce20f687b47fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/70236 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
2022-12-16mb/google/brya/var/marasov: Disable unused PCIE8 for s0ixFrank Chu
Disable unused PCIE8 for fix system can not enter S0ix completely. BUG=b:261915226 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I06f8bd06e1fe92c03bd5625a41469830ce37a11c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70660 Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2022-12-16mb/google/geralt: Revise the naming of MIPI PWM control GPIOLiju-Clr Chen
Rename the MIPI PWM control GPIO to be consistent with the schematic. BUG=b:244208960 TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB Change-Id: I6a3368d438cb50b257992260d1388f0b7e0f5ace Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70822 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2022-12-16mb/google/geralt: Pass GPIOs to allow backlight control in payloadsBo-Chen Chen
There are two ways to control backlight in geralt: 1. MIPI/eDP panel => control backlight via the GPIOs. (`backlight chip enable` and `PWM dimming control`) 2. eDP OLED panel => enable backlight via `backlight chip enable` and control dimming over AUX. For MIPI/eDP panels(#1), both "backlight enable" and "PWM control" GPIOs will be passed from coreboot. For eDP OLED panel(#2), only the "backlight enable" GPIO will be passed. If depthcharge successfully gets the GPIOs, it will use them to control backlight. BUG=b:244208960 TEST=test firmware display pass for eDP and MIPI panels on MT8188 EVB Change-Id: I866fa219722241008e2b0d566b29edf2f6d9321f Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70744 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-16mb/google/brya/var/marasov: Enable ELAN touchscreenFrank Chu
Correct touchscreen setting to make touchscreen function workable. BUG=b:260565911 BRANCH=firmware-brya-14505.B TEST=Built and verified touchscreen function Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: Ia98deae65ef0e2f501457331144b044e07431a3c Reviewed-on: https://review.coreboot.org/c/coreboot/+/70441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15mb/google/rex: Add support for WWAN over USB3Subrata Banik
This patch connects USB3_PCH_*_WWAN_* to USB32_2 as per Proto 1 schematics dated 12/14/2022. TEST=Able to build Google/Rex. Change-Id: Ie04c79ff5c231527e3d5f63a5cc553ec39c46914 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15mb/google/rex: Modify the PIN name as per schematicsSubrata Banik
This patch updates the GPIO PIN name as per Proto 1 schematics dated 12/14/2022. TEST=Not code change, just updated the comment section. Change-Id: Ic076ab35689fd2afb7c18eff065a90b9464a6b1d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70747 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2022-12-15mb/google/skyrim/var/frostflow: Update SPD file for H9JCNNNFA5MLYR-N6EFrank Wu
Update RAM ID table because H9JCNNNFA5MLYR-N6E is using spd-4.hex instead of spd-9.hex. Reserve RAM ID 3 for it, so the RAM ID table remains the same. BUG=b:261530632 BRANCH=None TEST=FW_NAME=frostflow emerge-skyrim coreboot chromeos-bootimage Then boot devices successfully Change-Id: I1b683168310f74a07d246af8618b977cce32287a Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-15mb/google/nissa/var/pujjo: Modify WWAN warm reset sequenceStanley Wu
pujjo support FM101 WWAN, add delay of FCPO# to meet warm reset toff minimum 500ms requirement. BUG=b:260380268 TEST=Build and boot on pujjo Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I63e599e76bd8a15ca44717823411576fa4df1c26 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org>
2022-12-15mb/google/rex: Add RTD3 support for discrete wifi moduleKapil Porwal
BUG=none TEST=Build and boot to the OS on google/rex. Signed-off-by: Kapil Porwal <kapilporwal@google.com> Change-Id: I2c5bac880e7dbc2ec14376c5cee3c13363bab377 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70444 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-15mb/google/brya/var/zydron: Enable Fast VMode for zydronDavid Wu
Fast VMode nmakes the SoC throttle when the current exceeds the I_TRIP threshold. BUG=b:252966799 BRANCH=firmware-brya-14505.B TEST=Verify that the feature is enabled by reading from fsp log Change-Id: I175f7f39d6115d1f082575393c45734c7b02e346 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70659 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/skyrim: Enable PCIe RTD3 supportJasonNien
Add PCIe RTD3 support for Skyrim BUG=b:245550573 TEST=Boot/Reboot cycles and Suspend_stress_test 10 times Signed-off-by: JasonNien <finaljason@gmail.com> Change-Id: I7f01827613eea2f254bc42c7f5aebeeb969b163a Reviewed-on: https://review.coreboot.org/c/coreboot/+/70740 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/hatch/dratini: increase power enable to reset deassert delayEran Mitrani
With 1ms delay, reset is de-asserted too soon, before power is fully up, causing a glitch to the reset signal. The issue is resolved with 4ms delay. TEST=tested on dratini device and observed the issue is resolved. BUG=b:260253945 Change-Id: I5c3edbc6ac90d5042c2d3c5b01573d4bb1ea676d Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70666 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14mb/google/poppy: Add support for a variant finalize functionTarun Tuli
Add a hook to allow a variant finalize to be called at the end of ramstage. BUG=b:245954151 TEST=Builds successfully Change-Id: I00c091051e3499ca94b286d7fbe0a7a8bd38e635 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70319 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-14mb/google/cyan/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I349d1e7d3027097c5db4da96e2376831fff61b04 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/skyrim/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ib75ccc10c8086086f5db4ced1163b74c9835364b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/slippy/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I950d776a712a104f2caed614886ce2527028ead7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70681 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/kahlee/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ib2ba6b5c14f6699dc6c0734724a6784e3400a467 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/google/jecht/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: If6c37cc2ce51780e0bae007d884d8f77b20847fb Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/aopen/dxplplusu/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: I04f61df6b651058060b88e5f5679a0dd5270e66d Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-14mb/51nb/x210/acpi: Replace Store(a,b) with ASL 2.0 syntaxFelix Singer
Replace `Store (a, b)` with `b = a`. Change-Id: Ic0ae4903546446322c2c47cab00de4c3af6c9d98 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/70634 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2022-12-13soc/amd/morgana: Enable GPP clk req disablingFred Reitberger
Enable GPP clk req disabling on morgana after reviewing against morgana ppr #57396, rev 1.52 Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Id2502137486df7a8b0ac6a4b3e061b25b23e2e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70465 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2022-12-13mb/google/guybrush,skyrim: use gpio.h include everywhereFelix Held
Now that gpio.h will only include the defines in the IASL case, gpio.h can be included instead of soc/gpio.h in the files that will be directly or indirectly included in the DSDT. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ifc8d8fe4e4148e5b5628f32778368d1fc7f44e5b Reviewed-on: https://review.coreboot.org/c/coreboot/+/70510 Reviewed-by: Elyes Haouas <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>