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* Drop PcieRpSlotImplemented on internal slots
* Add PCIe port 15 that connected to CNVi/M.2 E
Change-Id: Iaa05affa760b447fc1725e674b12366684a63720
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Remove unreferenced settings and factor out common settings. Many of
these are not mainboard-specific, and all boards use the same value.
Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This seems to be a debugging option. Since unset devicetree options
default to zero, drop the setting. If it is needed in the future, a
user-visible Kconfig option would probably make more sense.
Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Unset devicetree settings default to zero, so the devicetree setting can
be removed. Looks like no one needs it anyway.
Change-Id: Iad94538c5465347b37a99c6c9f20988168661593
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The value for this setting is not used anywhere. Drop it.
Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The upcoming Librem 14 variant won't use the same SATA HSIO adjustments
as the Librem Mini, so move these settings into a variant-specific file.
Rename existing gpio.h to variant.h, move to board root directory, and
use for all variant-specific declarations; adjust references as needed.
Add newly-created variant.c to Makefile.
Test: build/boot Librem Mini, verify SATA functionality unchanged.
Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48519
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, the option to cache DIMM SPD data in an FMAP region
is closely coupled to a single board (google/hatch) and requires
a custom FMAP to utilize.
Loosen this coupling by introducing a Kconfig option which adds
a correctly sized and aligned RW_SPD_CACHE region to the default FMAP.
Add a Kconfig option for the region name, replacing the existing hard-
coded instance in spd_cache.h. Change the inclusion of spd_cache.c to
use this new Kconfig, rather than the board-specific one currently used.
Lastly, have google/hatch select the new Kconfig when appropriate to
ensure no change in current functionality.
Test: build/boot WYVERN google/hatch variant with default FMAP, verify
FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log.
Also tested on an out-of-tree Purism board.
Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Unset devicetree options already default to zero. Note that this setting
is not referenced anywhere else, and will be removed in a follow-up.
Change-Id: I7bcc1c66caa9167c2327e1dc782f69c5de0fac2e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48579
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Kconfig to remove unrelated configs inheritted from JSL_RVP.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48544
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SMIs and SCIs aren't used before ramstage or the OS, so there should be
no need to already set them up in romstage. Not using this GPIO
configuration functionality allows untangling the GPIO and smi_util code
and only linking smi_util in ramstage in follow-up patches. In romstage
the pins get initialized as inputs with pull-up, so that at least that
part still matches the configuration before this patch.
BUG=b:175386410
Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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1. Make CLKSRC -> 7 and CLKREQ -> 6
2. CLK 6 is using free running CLK
3. Make LAN CLK 7 as unused as GbE is disable
TEST=Able to detect PCIE SD card on 0x1 slot.
Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is a whole bunch of pads being configured by the vendor firmware
that are either unconnected due to unpopulated resistor pads, only
connected to test points for vendor debugging purposes or just used as
strap. Configure them as NC with an appropriate pull to disable the
RX/TX functions.
The pads have been determined by dissecting a dead board.
This patch has been tested thoughroughly on a machine, normally used
productive, to see if any issues arise. No problems occurred at all.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I06b942e3182469f87e41914c893e5b485ccca420
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Updates PCIe registers and GPIO CLKREQ lines to match the schematic.
BUG=b:173566597,b:173567124,b:173566890
TEST=build AP firmware; flash device
BRANCH=none
Change-Id: Ibf519b812022839f749e503436f097d3b48c4383
Signed-off-by: Joe Tessler <jrt@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move the manual calls to fw_config_probe() into the devicetree; the
AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are
already guarded with probe statements in the baseboard devicetree, so
the code in romstage.c was redundant. The variants seem to have their
USB4 probe statements correct as well, so the manual UPD setting in
mainboard.c was also unnecessary.
BUG=none
TEST=abuild google/volteer
Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48512
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In cases when a volteer device is unprovisioned, the safest thing to do
for GPIOs that will normally be used for audio codec buses is to leave
them disabled (configured as PAD_CFG_NC). This patch adds support for
that.
BUG=none
TEST=add debug print to new if branch; remove fw_config from CBI and
see print on console
Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47972
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH
(C621A) by util/inteltool and generate the header file by util/intelp2m.
The DVT and EVT GPIO configurations are the same.
The initial value of GPP_B20 (POST complete) should be high, otherwise
BIC would get incorrect sensor readings and see events like PCH prochot.
Tested=On OCP Delta Lake DVT, dump GPIO configurations
by Intel ITP and verify the results match with the header file.
Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8
Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229
Reviewed-by: Tim Chu <Tim.Chu@quantatw.com>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Correct IOM setting and TCSS AUX setting to fix type C C0 port display can't output after flip.
BUG=b:173093980
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.
Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47785
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs
to be overridden.
port#1
PortUsb20Enable=1
Usb2PhyPetxiset=3
Usb2PhyTxiset=2
Usb2PhyPredeemp=7
Usb2PhyPehalfbit=1
BUG=b:173676539
BRANCH=None
TEST=emerge-volteer coreboot chromeos-bootimage
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset
bluetooth on reset.
BUG=b:171085081
TEST=volteer2 boots; scope shows assertion of the signal
Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a
Signed-off-by: Alex Levin <levinale@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This allows factoring out the common initialization for the integrated
UARTs.
Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently it's not possible to add multiple graphics driver into
one coreboot image. This patch series will fix this issue by providing
a single API that multiple graphics driver can use.
This is required for platforms that have two graphic cards, but
different graphic drivers, like Intel and Aspeed on server platforms or
Intel and Nvidia on consumer notebooks.
The goals are to remove duplicated fill_fb_framebuffer(), to advertise
multiple independent framebuffers in coreboot tables, and better
runtime/build time graphic configuration options.
Add an implementation in edid_fill_fb that supports registering
multiple framebuffers, each with its own configuration.
As the current code is only compiled for a single graphics driver
there's no change in functionality.
Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Remove unused code that appears to be left over from grunt.
Signed-off-by: Mathew King <mathewk@chromium.org>
Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48505
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Commit b0e169ac85 included a few small omissions and typos when
converting 'device pci xx.y' to 'device ref blah' after adding the new
chipset.cb file for TGL. This patch fixes these errors:
1) MIPI camera support requires I2C2 & I2C3 enabled
2) Malefor SAR sensor is on I2C2, not I2C3
BUG=b:175165653
TEST=abuild -p none -t google/volteer -x -a -c max
Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there
isn't anything uncommon with the soc NVS, use the Intel common NVS.
This covers the NVS cases of common code used by xeon_sp. Update
the mainboards for this change.
Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b
Signed-off-by: Marc Jones <marcjones@sysproconsulting.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
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DPM is a hardware module for DRAM power management and for better
power saving in low power mode.
BUG=none
TEST=Boots correctly on Asurada
Signed-off-by: Huayang Duan <huayang.duan@mediatek.com>
Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update memory parameters based on memory type supported by
Elkhart Lake CRB:
1. Update spd data for EHL LPDDR4X memory
- DQ byte map
- DQS CPU-DRAM map
- Rcomp resistor
- Rcomp target
2. Add configurations for vref_ca & interleaved memory
3. Add EHL CRB on board LPDDR4X SPD data bin file
4. Update mainboard related FSPM UPDs as part of memory
initialization
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Update Elkhartlake CRB devicetree devices based on EHL EDS.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I88097ced03f4376f309487b9d5207473f77742ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48124
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Remove JSL specific SMBIOS sku id info as it is not required by
EHL.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48123
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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THis patch removes IPU & MIPI related support from EHL CRB as they
are not supported in EHL.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48122
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Since there is no EC support on EHL CRB, this patch removes board
ID detection via EC (board_id.c & board_id.h) and its related
files. Temporarily removes variant_memcfg_config function in
romstage_fsp_param.c, will be added back when updating memory
configs later.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I40d96285dc05ec5faabc123950b6b3728299e99a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48121
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Since EHL CRB does not support ChromeOS, this patch removes
ChromeOS EC related headers (ec.h & gpio.h) and #includes.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I9c0c3722065c041769081f3d564646ce6a565a9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Since there is no ChromeOS support for EHL CRB, drop smihandler.c
which just deals with ChromeOS support.
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: Id474c3b04a82c03dda6514cc4565b58fb790b9c1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Since ChromeOS is not officially supported for EHL CRB, removing
ChromeOS related codes. Here are the change details:
- Remove ChromeOS related kconfig switches, including
SOC_INTEL_CSE_LITE_SKU which has dependency on ChromeOS flag
- Remove chromeos.c file
- Remove ChromeOS dsdt related codes from dsdt.asl & mainboard.c
- Remove ChromeOS GPIO related codes from variants.h & gpio.c
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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"Die()" needs <console/console.h>, as per this patch:
https://review.coreboot.org/c/coreboot/+/45540
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I0f9fae4a1e43477ca8e78ebbebd8c0729f8b7668
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48116
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a initial mainboard code cloned entirely from jasperlake_rvp
aimed to serve as base for further mainboard check-ins.
This patch is based on TGL_upstream series patches:
https://review.coreboot.org/c/coreboot/+/37868
List of changes on top off initial jasperlake_rvp clone:
1. Replace "Jasperlake" with "Elkhartlake"
2. Replace "jsl" with "ehl"
3. Replace "jslrvp" with "ehlcrb"
4. Remove unwanted SPD file, add empty SPD as placeholder
6. Empty romstage_fsp_params.c, to fill it later with SOC specific
config
7. Empty GPIO configurations, to be filled as per board
8. Empty memory.c configurations, to be filled as per board
9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB
10. Replace jslrvp variant with ehlcrb variant
Changes to follow on top of this:
1. Add correct memory parameters, add SPDs
2. Clean up devicetree as per tigerlake SOC
3. Add GPIO support
4. Update ehl fmd file to replace 32MB chromeos.fmd
Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com>
Change-Id: I2cbe9f12468318680b148739edec5222582e42a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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This patch adds support for loading spm firmware from cbfs to spm sram.
Spm needs its own firmware to enable spm suspend/resume function which
turns off several resources such as DRAM/mainpll/26M clk when linux
system suspend.
BUG=b:159079649
TEST=suspend with command `powerd_dbus_suspend` and
wake up the DUT by powerkey
Signed-off-by: Roger Lu <roger.lu@mediatek.com>
Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Follow vendor and enable Advanced Error Reporting for PCIe root ports.
This enabled the Linux AER driver, which handles PCIe error conditions.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add the subsystem ids to PCI ports and devices, which were dumped on
vendor firmware using `lspci`.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow vendor and enable LTR on all root ports to optimize for devices'
latency requirements and also optimize power management while preventing
failure due to wrongly guessing idle states, which happens without LTR.
Tested successfully. No errors show up in dmesg.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All X11 boards currently supported have Intel SPS without support for
S3/S5. Thus, drop it from Kconfig.
Note: not all X11 boards are server boards. When a X11 desktop or
workstation board should be added, this can be selected by the boards,
where S3/S5 work.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Correct unconnected pads that are configured different currently by
copying vendor configuration while porting the board.
Add internal pull resistors to all unconnected pads, that do not have an
external pull resistor, to prevent floating.
The pads have been determined by dissecting a dead board. This commit
only changes pads, that are not connected at all and don't have any via,
so we can be absolutely sure there is no other connection.
Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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(Re)configure various pads found by dissecting a dead board and vendor
firmware, as well as the BMC firmware:
- GPP_B14: input connected to jumper JBR1 - could be used to implement
"BIOS Recovery" ("Top-Block Swap") functionality; external pull-up
- GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify
the BMC about a thermal throttling event. Not implemented in vendor
firmware.
- GPP_C23: input connected to the CPU's CATERR# output; external pull-up
Not actively used by vendor firmware.
- GPP_D1: output connected to on-board and front panel power LEDs
- GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be
used for testing/debugging only, since it resets both slots at once.
Not actively used by vendor firmware.
- GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be
used for testing/debugging only, since it resets both slots at once.
Not actively used by vendor firmware.
- GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will
be used later in CB:48096 and CB:48097; external pull-up
- GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not
useful, since the IGD is not connected to any ports on this board.
External pulls ensure correct function of a dGPU even without driving
the gpios. Not used by vendor firmware.
- GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls
- GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not
used by vendor firmware.
Also add comments for documentation. While at it, mark ME-owned pads as
reserved.
Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
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add new Synaptics touchpad for volta.
BUG=b:174802144
TEST=emerge-volteer coreboot and check touchpad function work.
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change reorganizes FMAP for volteer to make use of the lower
16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to
RW_LEGACY. This is now possible because TGL supports memory mapping of
BIOS region greater than 16MiB.
Following changes are made in chromeos.fmd as part of this:
1. Move RW_SECTION_A and RW_MISC to lower 16MiB.
2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as
a placeholder in the lower half of the SPI flash.
3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a
larger region for ELOG.
4. Increase WP_RO to 8MiB to allow larger space for firmware
screens. GBB size is thus increased to 448KiB.
BUG=b:171534504
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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AP_PEN_DET_ODL isolated by a diode and need to pull up internally.
BUG=b:160752604
BRANCH=dedede
TEST=Build and confirm waveform by google EE parter.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update telemetry settings.
VDD Slope : 32643 -> 26939
VDD Offset: 208 -> 125
SOC Slope : 22742 -> 20001
SOC Offset: -83 -> 168
BUG=b:171668654
BRANCH=zork
TEST=1. emerge-zork coreboot
2. pass AMD SDLE test report
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48288
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds the PMC MUX and CONx devices for adlrvp for
conn2.
BUG=b:170607415
TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects
in SSDT tables.
Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add Elan and Synaptics touchpad settings.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add HDA,speaker codec and speaker amp settings.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raymond Wong <wongraymond@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This change restricts RW_DIAG region to lower 16MiB to ensure that the
extended BIOS checker for FMAP does not complain about 16MiB boundary
crossing.
I haven't updated any other regions to occupy the newly freed space
but it is fine since this board is dead and should be dropped from
coreboot soon.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This change restricts SI_ME region to live below the 16MiB boundary to
ensure that no regions cross the 16MiB boundary as the extended BIOS
window checker for FMAP complains about it.
Signed-off-by: Furquan Shaikh <furquan@google.com>
Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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disabling DDI port 1 and 2 HPD.
This patch adds the PMC MUX and CONx devices for lindar. Device
specific method contains the port and orientation details used
to configure the mux.
BUG=b:172533907
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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SATA_AHCI is already the default mode for CNL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Align the SATA mode names with soc/skl providing a consistent API.
Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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The PCI devices P2SB and PMC are hidden by the FSP and cannot be
unhidden, because the FSP locks their configuration. Thus, setting them
to `on` is not correct. Therefore, set their state to hidden.
Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48388
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SATA_AHCI is already the default mode for SKL/KBL based mainboards.
Therefore, remove its configuration from all related devicetrees.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: Ib5222c1b0314365b634f8585e8a97e0054127fe9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48378
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Skylake FSP isn't used by coreboot anymore. Therefore, drop the
misleading comment and the "KBLFSP" extension from the names of these
enums.
Also, drop the "MODE" extension to make their names shorter in general,
since it doesn't add any more value.
Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains
identical.
Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I56a905980e5ae382c3488b9fddb9fab382efc1d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48375
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Remove unnecessary device declarations and remove comments where SMBIOS
slot descriptions are used.
Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use proper indents in the devicetree and align `end` keywords.
Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The PCI devices P2SB and PMC are hidden by the FSP. So instead turning
them off, set their state to hidden being able to allocate ressources
for them.
Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48371
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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remove TCC offset setting in overridetree.cb,
use default setting(# TCC of 90) in baseboard.
BUG=b:174547185
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update lindar gpio settings for Synaptics trackpad no function issue.
Update I2C5 bus freq to 400kHz.
Improve Goodix Touchscreen power on sequence.
BUG=b:160013582
BRANCH=firmware-volteer-13521.B
TEST=emerge-volteer coreboot and check system dmesg and evtest can get
device. Verify trackpad function workable.
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48150
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Unique among the Volteer devices, the volteer2_ti50 variant connects to
the TPM via I2C. This CL introduces the proper devicestree declarations
for the Linux kernel to recognize that.
overridetree.cb is shared between "sub"-variants volteer2 and
volteer2_ti50, so both will have two TPM nodes, the I2C being disabled
by default. The odd _ti50 variant then has code in variant.c to enable
the I2C node and disable the SPI node.
BUG=b:173461736
TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x
Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b
Signed-off-by: Jes Bodi Klinke <jbk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48223
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update Power Limit2 (PL2) minimum value to the same as maximum value for
volteer variants like baseboard, delbin, eldrid, terrador and todor.
All other variants uses the DTT entries from baseboard devicetree since
there is no override present for those variants. DTT does not throttle PL2,
so this minimum value change here does not impact any existing behavior on
the system.
BUG=None
BRANCH=volteer
TEST=Build and test on volteer system
Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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refer to cb:45878
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
BUG=b:174735512
BRANCH=volteer
TEST=build and type-c display work
Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48268
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the unused UART_BT_WAKE GPIO as BT is over USB.
Change-Id: I638b4528fa5c4c378a1e8ff7bb88546da1513df2
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48240
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
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Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is
selected by their SoC soc/intel/cannonlake.
Change-Id: I9597746a217575b42f6325998b948e16b452231a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ib4e7ec948ca4d019ad82ebc5abe39fc408281cf4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48299
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add variant_configure_early_gpios() configuring early GPIOs to make the
difference clear.
Change-Id: I6e7c8c32963c9eeab4399947dac511442987cb45
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48298
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: Ibcb6322067285984bad70761fce34cfcb6ed8e0f
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48297
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move mainboard/gpio.h to variant/gpio.h and rename its methods to make
clear that these methods are implemented on variant level.
Change-Id: I1ae9b54ed683000f65323b11747ce3280a1c7f2a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48296
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Allow to specify which signature is to be checked.
Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Create the storo variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174284884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_STORO
Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com>
Change-Id: I5ad41e0b2bc95b44733a2ad3c543267f3f56f9e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Without the EC blob being present in the SPI flash, the board won't even
power up.
Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This is an adapted copy of mainboard/example/min86 that is currently
only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't
expected to reach boot block at the moment. It will be extended in
future follow-up commits.
Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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1. Add VARIANT_HAS_MIPI_CAMERA to Kconfig.name
2. Add mipi_camera.asl
BUG=b:169356808,b:169551066
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47668
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF paramerters form thermal team.
Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W.
BUG=b:174514010
BRANCH=puff
TEST=build image and verified by thermal team.
Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than
APU_DP_BLON.
BUG=b:171954512
BRANCH=zork
TEST=validate the panel sequence with scope.
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Create the copano variant of the volteer reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:174413884
BRANCH=None
TEST=util/abuild/abuild -p none -t google/volteer -x -a
make sure the build includes GOOGLE_COPANO
Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
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According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released.
To ensure this, set the power enable signal in the bootblock GPIO table.
BUG=b:173676531
BRANCH=firmware-volteer-13521.B
TEST=Built and booted into OS, test USB function normally.
Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use a new driver for the SX9324 proximity detector device.
This is first draft settings, will modify it after fine tuning.
BUG=b:172397658
BRANCH=zork
TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Latest HW schematic add LTE_RST pin to control module power sequence.
BUG=b:173490220
BRANCH=zork
TEST=measure the waveform is meet the LTE module spec.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4
which is calibrated value for the board. Other values like PreWake,
Rampup and RampDown are 0 by default.
BUG=b:162192346
BRANCH=dedede
TEST=Correct value is passed to UPD and Acoustic noise test passes.
Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Initiate device tree based on latest schematic.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add implementation of EC smihandler
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Perform EC initialization in bootblock and ramstages. Add associated
ACPI configuration.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Follow latest schematic UART_PCH_DBG is UART 0.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable ACPI configuration and add DSDT ACPI table.
BUG=b:174266035
TEST=Build Test
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Coachz rev1 has changed EN_PP3300_DX_EDP from gpio52 to gpio67.
BRANCH=none
BUG=b:174123578
TEST=emerge-strongbad coreboot chromeos-bootimage.
flash coreboot and boot up normally.
Signed-off-by: yuanliding <yuanliding@huaqin.corp-partner.google.com>
Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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To accommodate also `off`, two spaces are used after `on` to align
comments.
This unifies the devicetree files of the two variants.
Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This reduces the difference with Cereme’s devicetree file.
Change-Id: I1e6ba5891245562d5132307eab224623031e11c8
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since the FMD file isn't parsed any more by a shell script in the SoC's
Makefile.inc, we can use better human-readable numbers for the section
sizes.
TEST=Timeless build results in identical image.
Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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TEST=Timeless build results in identical image.
Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48243
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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This makes it possible to select both the legacy LAPIC AP init or the
newer parallel MP init.
Tested on i440fx with -smp 32.
Change-Id: I007b052ccd3c34648cd172344d55768232acfd88
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48210
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Qemu i440fx does not support an smihandler at the moment.
Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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All four SMI/NMI interrupt inputs have an external pull-up resistor and
get triggered by pulling the line low. Thus, correct the trigger to
active-low.
Also document the signals by adding appropriate comments.
The pads' connections have been determined by dissecting a dead board.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48093
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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