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No need to have separate sections, and will be cleaner when adding
another section in a subsequent patch.
Change-Id: I4ad6be9dd67b5adbc9c5b0fcab51ce0c54351173
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83605
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
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It is a new incoming Protectli product based on Alder Lake-P SoC.
More details and documentation will be added later.
TEST=Boot Ubuntu 22.04 LTS and Windows 11 on VP6670.
Change-Id: If4ae5b14b69806b6b0727d1ca1dcf56f47cfcd8e
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80501
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add mainboard folder and drivers for new reference board 'Rauru'.
TEST=saw the coreboot uart log to bootblock
BUG=b:317009620
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Change-Id: I789b622dcda999635f7aa2ce40adea6db28afa0e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83573
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Xol has a shutdown issue on our reliability test environment:
- High temperature
- No battery condition
It needs to have margin for the PL2 and PL4 values from the adapter
power, this will limit the PL2/PL4 values up to 30W/40W for xol's
45W power adapter. The new values are confirmed by our power team.
BUG=b:353395811
BRANCH=brya
TEST=built and verified MSR PL2/PL4 values.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:18000000 <= MSR PL1 (18W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
[When connected 60W adapter without battery]
Before:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:60000000
After:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:30000000
constraint_2_power_limit_uw:40000000
[When connected 45W adapter without battery]
Before:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:45000000
constraint_2_power_limit_uw:45000000
After:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:30000000
constraint_2_power_limit_uw:40000000
Change-Id: Ic19119042ffdcc15c72764d8c27bcdce9f229438
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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If user continues to use the touchpad for over 3 minutes on Xol, the
pointer movement is stuttering.
Touchpad I2C transaction should appear during the interrupt signal level
is low, but we could see some more I2C transaction after the interrupt
signal(GPP_F14) went to high.
We found experimentally that changing the interrupt type to GPIO_INT
from APIC_IRQ improved this issue. We are still investigating, would
like to apply this change first for Xol's dogfooding.
BUG=b:350609957
BRANCH=brya
TEST=built and verified there's no stuttering issue on touchpad movement
Change-Id: Ie1b59355a694e5a42367a20e03f6c5f93225e79c
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83346
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
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This change adds early and romstage GPIO configurations for the trulo
variant, including:
Early GPIOs:
- GSC (Google Security Controller)
- WP (Write Protect)
- UART0 (for serial debug)
Romstage GPIOs:
- Touch Screen early power sequencing
CrOS GPIOs:
- CROS_GPIO_VIRTUAL
- GPIO_PCH_WP
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ic1b84f61ef62ddbadc2a45758fb3fce90fce0e88
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83568
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds FW Config to the device tree for choosing between the
discrete PD chip.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I0a8fb0225edecb063dede31efaec6f2502476977
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83567
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds power related entries (FIVR and policy to control
lower power c-state transitioning) to the device tree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ib125c91be79a81f3103dcd587dc685134a292e03
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83566
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This patch adds Thermal related entries (like, TDP, TCC and enabling
DPTF config with required sensor configuration) to the devicetree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I32f9219c0ba6b70f847f0752bff8aa2e4fdd0979
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83565
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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The Darter Pro 10 (darp10) is an Intel Meteor Lake-H based board.
There are 2 variants to differentiate them as they have different
keyboards and so use different EC firmware.
- darp10: 16" model with 102 key keyboard
- darp10-b: 14" model with 83 key keyboard
Change-Id: Iaef03a47cf108591ef823bfa779777c7c05c6337
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82609
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Brya/brask devices using NAU88L25 are not recognizing headset buttons
correctly. The reason is we are using wrong reference voltage of
MICBIAS. Use VDDA instead.
BUG=b:352215240
TEST=test with 3.5mm headset with buttons on volume up/down and pause
Change-Id: I0619021c6fd0a196c318aee58e07dc4149f1d64e
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Reorder GPIO pin mapping as per platform documentation:
* GPIO_MEM_CONFIG_0 -> GPP_E2
* GPIO_MEM_CONFIG_1 -> GPP_E1
* GPIO_MEM_CONFIG_2 -> GPP_E12
* GPIO_MEM_CONFIG_3 -> NC
BUG=None
TEST=emerge-nissa coreboot
Change-Id: I4e979686833095a904b114500dc1142def583afa
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83549
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch adds descriptions for Audio device (Speaker, Jack and Mic)
to the device tree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ied531dde856fb7c9a410b5667843c9be759cfc8f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83554
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds descriptions for eMMC device (supported mode and DLL
tuning) to the device tree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I8f1310313b8114731aa417610f245f94c8978ac0
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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1. Add STORAGE_UNKNOWN fw_config to enable all storage devices,
this is used for the first boot in factory.
2. Add fw_config probe to enable/disable devices in devicetree, to
avoid suspend(s0ix) fail issue.
3. Disable eMMC controller incase STORAGE_UFS or STORAGE_NVME fw_config
is enabled.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ifdaa0bf35413981327097c260ab47e757f697e37
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds descriptions for CNVi WiFi and BT device to the device
tree.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I7396917ca7875dcbe1d35a371cc450a9e070b18d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83551
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds descriptions for Low Speed I/O (I2Cx, GSPIx, UARTx)
to the device tree.
It also includes entries that will generate ACPI code at runtime
with LSIO end-point device.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I94a3a7f6f85d84407f32ab4c879b236a80859f2d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83550
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds descriptions for TCSS port, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime
with port definitions, locations, and type information.
Additionally, implement the TCSS PMC MUX programming.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I60de314a92514d153ca039f6eaeb904b117b786c
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83548
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds descriptions for USB2/3 ports, including over-current
(OC) pin configuration, to the device tree.
It also includes entries that will generate ACPI code at runtime with
port definitions, locations, and type information.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: I873810e401c4afdc162036f01bae7247f9b8c749
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83547
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Generate 3 Samsung RAM IDs
K3KL9L90CM-MGCT Samsung
K3KL6L60GM-MGCT Samsung
K3KL8L80CM-MGCT Samsung
BUG=b:331539447,b:333145301,b:333220620
TEST=Run part_id_gen tool without any errors
Change-Id: I4ba0fb409015c24446b2ae8e224fbce3910715e3
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83501
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds minimal device entries and chip configs for Trulo
overridetree.cb to boot.
BUG=b:351976770
TEST=Builds successfully for google/trulo.
Change-Id: Ic8b90dbaaabb439c347a891650d255948d48810a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83546
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves the EC configuration from the orisa variant to the
trulo baseboard, enabling reuse by other variants in the future.
BUG=b:351976770
TEST=Builds successfully for google/orisa.
Change-Id: Ib5611cf67a41950c1c4ce936a5d2bea7fdca5c68
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83544
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change moves the GPIO configuration from the orisa variant to the
trulo baseboard, enabling reuse by other variants in the future.
BUG=b:351976770
TEST=Builds successfully for google/orisa.
Change-Id: If41c1b567a0ed6397bc935183c832a423f43e8b9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83545
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables SKIP_RAM_ID_STRAPS for the TRULO board variant as
this board design won't stuff MEM strap GPIO hence, sets the static
SPD ID to 0 for the MT62F512M32D2DR-031 DRAM part.
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: I1acb4680a143611c55f4fa6e032fde38c62af054
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83543
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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This patch adds key DRAM configuration parameters as below:
- Rcomp
- DQ byte map
- DQS CPU<>DRAM map
- ECT
- CCC Mapping
- SPD Index
Source: Trulo Schematics Rev0.5 (dated June'24)
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: Ie7abc393a71becf26d53ae9e4fc56f66c7117051
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
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This patch adds Micron Technology LPDDR5 DRAM
(part: MT62F512M32D2DR-031) for Trulo.
Make use of spd_tools to generate SPD file after following the below
steps:
1. make -C util/spd_tools
2. ./util/spd_tools/bin/part_id_gen ADL lp5
src/mainboard/google/brya/variants/trulo/memory
src/mainboard/google/brya/variants/trulo/memory/mem_parts_used.txt
Output files are:
1. dram_id.generated.txt
2. Makefile.mk
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: Id35f6b57b716375abb66db187413f0f82361d962
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83539
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure GPIOs according to schematics revision 20240712.
BUG=b:351968527
TEST=abuild -v -a -x -c max -p none -t google/dedede -b awasuki
Change-Id: Ic8f346b788b489f50ab96c0ace8541720a832f72
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83449
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
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Vendor DRAM Part Name Type
SAMSUNG K4U6E3S4AB-MGCL LP4X
SAMSUNG K4UBE3D4AB-MGCL LP4X
MICRON MT53E1G32D2NP-046 WT:B LP4X
BUG=b:351968527
TEST=Run part_id_gen tool without any errors
Change-Id: I9a03c86770101ec70c2ee5d6b914313c1bf23b5f
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83427
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Create the awasuki variant of the waddledee reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:351968527
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_AWASUKI
Change-Id: If18afc92afdbdff5df3f5b034f4357feda6690b0
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dolan Liu <liuyong5@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add socket types for LGA1700, LGA3647_1, LGA4189, LGA4677.
Select the socket type for different boards.
For the socket types which are not defined in SMBIOS type4,
CPU_INTEL_SOCKET_OTHER could be used.
Change-Id: Ida3315694f3ce397b9ad9d676d3195da5f096cb7
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83329
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: Ib84e7804c03f1c0779ab7053a09e397a267a3844
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83523
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set "option WIFI_SAR_ID_1 1" for WIFI_SAR_ID field in fw_config.
BUG=b:347108861
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I179dad5eeabc1d84aa0a2de5359be5848a2ecc39
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83478
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds the necessary Kconfig options to enable support for
the TRULO board, including selecting the appropriate baseboard,
HDA verb table, and TCSS configuration.
Additionally, corrected the TPM_TIS_ACPI_INTERRUPT from `13` to `17`
for Trulo as applicable.
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: I5c1cbd56cf2734058aced35868ae42c1c160f62e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83500
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change adds hda_verb.c to the ramstage build, but only when the
CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB config option is enabled.
BUG=b:351976770
TEST=Able to build google/trulo.
Change-Id: I9b17126ff1493b5714d6ae715ad2863bdff4ed46
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83499
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch sets a default value of 13 (GPE0_DW0_13/GPP_A13_IRQ) for
the `TPM_TIS_ACPI_INTERRUPT` configuration option across most Google
Brya variants. The HADES board uses interrupt 20 (GPE0_DW0_20/
GPP_A20_IRQ), and the ORISA board uses interrupt 17 (GPE0_DW0_17/
GPP_A17_IRQ).
This refactoring simplifies future additions of board-specific TPM
interrupt configurations, improving maintainability.
BUG=none
TEST=The timeless builds with this patch for both Nissa and Brya
devices produce the same binaries.
Change-Id: I9d913bf3da6957ab5c700dd746bc4b5350427d73
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83493
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fixes a pmc_mux port mapping error introduced in coreboot
commit 4fa8354
Mithrax and felwinter do not have sequential mux_conn[X] to connY
mappings which led to the kernel subsystem linking between Type C
connectors and USB muxes to be incorrect. The previous patch
attempted to fix this by changing the custom_pld layout. However
this broke USB usage except for charging.
This patch reverts the custom_pld layout and instead changes the pmc
hidden and tcss_xhci port mappings to match the hardware layout.
BUG=b:352512335 b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
ectool commands below are only for felwinter as a workaround for
devices without a firmware patch to connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
ls -l /sys/class/typec/port0/usb-role-switch (note CONX-role-switch)
echo host > /sys/class/usb_role/CONX-role-switch/role (should succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
ls -l /sys/class/typec/port1/usb-role-switch (note CONY-role-switch)
echo host > /sys/class/usb_role/CONY-role-switch/role (should fail
as no cable attached)
BRANCH=firmware-brya-14505.B
Change-Id: Iebd259842d3affa259069cd776b46759c1c60712
Signed-off-by: Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83472
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also set the vendor default TCC offset temperature
Change-Id: Ia187b67ae28fbcda7d5d0e35ec64a3b21d97a21b
Signed-off-by: Anastasios Koutian <akoutian2@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83280
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Ifc882c2ac9d4e9ce2ed4305bdd6859a5d1e1b09c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83441
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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In order to clean up a bit, drop devices which are equivalent to the
ones from chipset devicetree.
Change-Id: Ief199db47fc529c510709ac37be6014b63244e84
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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The cpu_cluster device is defined in the chipset devicetree. So drop it
from the mainboards.
Change-Id: I65bfeaf0b8771c123c0615531c2cc608b222949b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83440
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Several brya variants were missing VBT files, add and select them in
Kconfig.
Also select in Kconfig for VELL, which already had a VBT but was not
using/selecting it.
TEST=build/boot google/brya (marasov), verify display init functional
/ payload screen shown.
Change-Id: I6848c2b78cf37157299d94bf12c0b6d925ea1432
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83434
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Eliminates the use of a magic number, and the resulting DID entry in
the _DOD method is the same. The first entry was already changed in
commit 1810a1841528 ("mb/google/*: Replace use of gfx/generic addr
field with display type"), this one was missed.
TEST=build/boot google/jinlon w/o privacy screen, dump SSDT and verify
DID entry is unchanged but _ADR is now correct (since the DID flags are
not part of the address field).
Change-Id: Ief22928ea831d4cb5b483406ac388218a97ad98b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Iebe5f8729d463767f5a1b52c375d11bb9d413144
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78840
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I4769f255ce5652a9969ad6535c997ec1ad0be8d2
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Ic33bf07041a8c966dce66109c577621513147609
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78838
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Ide536c74683416b34b0984fe1bddb250e72b045b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
|
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: Id3605e8e05d9d97a73af966459692276265df8bc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78836
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I2b0e19581e0f0111a56bc57185acfcdd70588141
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78835
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Make use of the alias names defined in the chipset devicetree and remove
devices which are equal to the ones from the chipset devicetree.
Change-Id: I290fcfdd7b2cff61c4f6cd153133c5205c6fd6d1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
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Fan control is assign to EC handle now. Remove relate setting on coreboot.
BUG=b:351917517
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Iff0776ce3db6f27e250162357abb3c7e9b1a0dc3
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83380
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Change-Id: I1ffa87eeee521180f37371e5a0d1f9a1a06091aa
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83373
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
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This patch adds FW_CONFIG to accommodate different Lotso BoM
components across various SKUs.
1. Fingerprint sensor - FP Present/Absent
BUG=b:350360162
BRANCH=None
TEST=Boot image on SKU2 and check FP working.
Change-Id: I1ee5fcd1c29099bdbee741ef76c00cf45fcc1189
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83388
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
This commit also updates the USB2 port 10 description and set its type
to the more appropriate `UPC_TYPE_INTERNAL' type.
BUG=b:348345301
TEST=BRDS method is added to the CNVW device and returns the data
supplied by the SAR binary blob
Change-Id: I66c9b75d2aaa1b221313b037defcd2c579fd6b61
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83310
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Cliff Huang <cliff.huang@intel.com>
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1. Add STORAGE_UNKNOWN fw_config to enable all storage devices,
this is used for the first boot in factory.
2. Add fw_config probe to enable/disable devices in devicetree
instead of variant.c, it can avoid suspend(s0ix) fail issue.
BUG=b:328580882
TEST=On riven eMMC and UFS SKUs, boot to OS and run
`suspend_stress_test -c 10` pass.
Change-Id: I518f1a5955fb88f304663112f1e3d4c744bde183
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83405
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bujia does not support Thunderbolt anymore,
therefore disable related TBT setting.
The bujia fit image CL, cf. chrome-internal:7468938.
BUG=b:349923139
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot.
Change-Id: I4301a1f744aa9d4de9f0eba4147c49a4bb3ed922
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83402
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch refactors CSE config options, moving the selection of:
* `SOC_INTEL_CSE_LITE_SKU`
* `SOC_INTEL_CSE_PRE_CPU_RESET_TELEMETRY_V2`
* `SOC_INTEL_CSE_SEND_EOP_ASYNC`
from the generic `BOARD_GOOGLE_REX_COMMON` to individual board models.
This enables finer-grained control over CSE features and sync behavior
on different Rex and variants platforms.
Specifically:
* `google/rex0`: Selects `SOC_INTEL_CSE_LITE_SKU` for CSE sync within
coreboot.
* `google/rex64`: Selects `SOC_INTEL_CSE_LITE_SYNC_BY_PAYLOAD` and
`SOC_INTEL_CSE_SEND_EOP_BY_PAYLOAD` to defer CSE sync
to the payload.
BUG=b:305898363
TEST=Builds successfully for google/rex variants.
Change-Id: Ib5957496b1e1dad8d135b3e10541cb83dd339539
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83397
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Mainboard is identified as 0Y2MRG.
The version tested is with Nvidia dGPU (gfx 560ti).
The flash is a 4MiB Winbond W25Q32BVSIG.
It can be flashed internally with flashrom.
Add a strap on the service mode pin of the mainboard for internal flash.
Tested working:
- SeaBIOS
- All USB ports
- SATA
- dGPU
- Ethernet
- Environment control
- GPIOs
- S3 Sleep mode
- WakeOnLan
Change-Id: I7d394794fec580bc7aed3f6396ceb47d4a6fd059
Signed-off-by: Ronald Claveau <sousmangoosta@aliel.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83104
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Define the PCI I/O base address necessary to use port I/O functions on
the qemu-aarch64 mainboard, so that we can get the VGA display devices
working. The config value is from hw/arm/virt.c [1]:
[VIRT_PCIE_PIO] = { 0x3eff0000, 0x00010000 },
[1] https://gitlab.com/qemu-project/qemu/-/blob/v8.2.3/hw/arm/virt.c#L164
Change-Id: I85439ba68740d64f789983b37d9c95f849ce4f72
Signed-off-by: Alper Nebi Yasak <alpernebiyasak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82059
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib757c0548f6f643747ba8d70228b3d6dfa5182cd
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82752
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Jakub Czapiga <czapiga@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Bujia has 4 thermal sensors, so add two missing sensors settings.
BUG=b:351917517
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot.
check ACPI SSDT table have new TSR info.
$ cat /sys/firmware/acpi/tables/SSDT > SSDT
$ iasl -d SSDT
check SSDT.dsl
Change-Id: Id9a17a22a717faac829e6b5e300351187a62dd43
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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TSEG_SZ_MASK is already defined in "q35.h"
Change-Id: I32ea08c18e1c41d16137ea14a1643f8c8d527722
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83386
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This board has a DVI-I connector, which supports both digital and analog
display outputs. The I2C bus to retrieve the EDID is shared between both
outputs, so `select GFX_GMA_ANALOG_I2C_HDMI_B` to describe this.
Can't currently test this due to lack of hardware.
Change-Id: Ib8239917e2f7ee5bb982621752ec406c2d3ca302
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82753
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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update DTT settings for thermal control,according to b:348285763#comment6.
BUG=b:348285763
TEST=emerge-brox coreboot
Change-Id: I67e16a2596884d501273a5787119406dff7a20f9
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83304
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Orisa uses PDC<->PMC direct connection for USBC mux configuration.
Select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it.
BUG=b:345070027
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I3f740bedc8ff667d15f077fa57d201ab0d42ebf8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83324
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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Add a new fw config field to determine which firmware edition shall be
flashed to the PDC.
BUG=b:334793686
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I817e9415aca1d2f68b484d8e23b581e1a75d6f84
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83353
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83253
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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SKU1 is UFS, SKU2 is NON-UFS, it needs to select this config to disable
the MPHY clock in the SKU2 configuration to ensure that S0ix functions
normally.
BUG=b:350609955
BRANCH=None
TEST=Boot image on SKU1/SKU2 and check S0ix working.
Change-Id: I2fbcc7ffaabf3c085a3345ec94a8d45b225b3450
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83323
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add hid report address for gt7986u.
BUG=b:342932183
BRANCH=None
TEST=Verify touchscreen work normal.
Change-Id: I464c2691505083314528519f608108c8a31e6cc0
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83201
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch creates a new domika variant which is a Twin Lake platform.
This variant uses Yavilla board mounted with the Twin Lake SOC and hence
the plan is to reuse the existing yavilla code.
BUG=b:350399367
BRANCH=firmware-nissa-15217.B
TEST=build, and boot into OS
Change-Id: I42c56770f8b8d6018592253d2bb16b8166eb5719
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Disable VBOOT_EARLY_EC_SYNC for all trulo boards.
BUG=b:345112878
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I10b027d19dedbb190fc960b949017f9e4830d52a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83303
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Domain device objects are created with HID/CID/UID/_OSC/_PXM
Dynamic domain SSDT generation could benefit the support of SoCs with
multiple SKUs, or the case where one set of codes supports multiple
SoCs. One possible side-effect might be the extra performance cost for
generating these tables, which should not bring big impact on high
performance server CPUs.
GNR codes run with dynamic domain SSDT generation to fit for both
GraniteRapids and SierraForest SoCs.
TEST=Build on intel/avenuecity CRB
TEST=Build on intel/beechnutcity CRB
Change-Id: I28bfdf74d8044235f79f67d832860d8b4306670c
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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This is a rudimentary port of this board. It was done with Haswell
Autoport, wherein some adjustments for Broadwell were made
(Thanks to Angel Pons!).
The VBT was copied from /sys/kernel/debug/dri/1/i915_vbt on version
2.20 of the vendor firmware.
Working:
- Broadwell MRC.bin
- S3 suspend and resume
- All DIMM slots
- Libgfxinit
- HDMI-Out Port
- DVI-I Port (including passive DVI to VGA adapter)
- USB 2.0 Ports
- USB 3.1 Gen1
- RJ-45 LAN Port
- SATA3 6.0 Gb/s Connectors
- m.2 PCIe SSD
- mPCIe WiFi slot
- x16 PCIe slot
- USB 3.1 Gen1 Header
- Front Panel Audio Connector
- edk2
Not yet tested:
- SATA Express 10 Gb/s Connector
- HDMI-In Port
- DisplayPort 1.2
- Optical SPDIF Out Port
- PS/2 Mouse/Keyboard Port
- USB 2.0 Headers
Not working:
- Broadwell CPUs, see commit f5105313cf69 (mb/asrock/z97_extreme6:
Add new mainboard)
Special thanks to Angel Pons for guiding me through the process of
porting this board and pushing it to Gerrit!
Change-Id: I3b940e9281814e8360900221714c0dfa3ae39540
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82760
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:348345301
BRANCH=firmware-rex-15709.B
TEST=BRDS method is added to the CNVW device and return the data
supplied by the SAR binary blob
Change-Id: I7f56ab8ac88c1fbc0b223b4286d2a998e424a46e
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83299
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This port was done via autoport and subsequent manual tweaking.
Thanks to Angel Pons for helping me with the misbehaving ASM1061 ASPM!
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection via jumper and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- both RJ-45 Gigabit LAN Ports
- USB 2.0 Ports
- USB 3.1 Gen1 Ports
- both USB 3.1 Gen1 headers
- HD Audio Jack (audio output)
- all six SATA3 6.0 Gb/s connectors by Intel
- all four SATA3 6.0 Gb/s connectors by ASMedia ASM1061
- all three PCI Express 3.0 x16 slots
- PCI Express 2.0 x1 slot
- half mini-PCI Express slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection via jumper
not (yet) tested:
- IR header
- COM Port header
- DisplayPort
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- PCI slots
not (yet) working:
- Front panel audio connector
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
Change-Id: Iae0b73d8e81be90ec3a2d5463df3ed170f603266
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Use FW_CONFIG to differentiate MAX98390 and TAS2563. Since config
GERALT_USE_MAX98390 is no longer needed after using FW_CONFIG,
we remove GERALT_USE_MAX98390 from Kconfig.
BUG=b:345629159
BRANCH=none
TEST=emerge-GERALT coreboot
TEST=Verify beep function through deploy in depthcharge successfully.
Change-Id: Ie9f0cbc30dd950b85581fc1924fa351efe1e0aab
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Add RAM ID for
K3KL9L90CM-MGCT 0 (0000)
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST=Run part_id_gen tool without any errors
Change-Id: Icb84838a6964b9318ded0573ad58a4fd1221867f
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83300
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Before:
I2C0 - 401kHz
I2C4 - 405kHz
After:
I2C0 - 392kHz
I2C4 - 395kHz
HW: Change R8409/R8411 to 33ohm.
BUG=b:349743464,b:349735055
TEST=emerge-brox sys-boot/coreboot
Test pass by EE
Change-Id: I985837b1b80e973f148529b446905580c0f95e98
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83290
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
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Working:
- Both DIMM slots
- All Rear USB 2.0 ports
- Integrated graphics (libgfxinit)
- Realtek RTL8111F GbE
- Flashing internally with flashrom (Note: Works from stock too
due to Gigabyte not following Intel recommendations,
confusing ME)
- SeaBIOS (1.16.3) to boot Arch Linux Installer
- EDK II (uefipayload_202309, MrChromebox) to boot Arch Linux Installer
- Audio output (green jack, rear)
- S3 suspend/resume
- VBT
Untested for now (i.e. should work, will eventually test):
- EHCI debug
- Front USB 2.0 ports
- The other audio jacks
- PCIe ports
- Non-Linux OSes
Untestable (i.e. cannot test due to unavailable hardware):
- PS/2 port
- Serial port
- SATA ports
Not working:
- USB 3.0 ports: The on-board VLI VL805 does not have a flash chip,
so its firmware needs to be loaded on each boot. However,
documentation about the (chip-specific) firmware loading procedure
is nowhere to be found.
- Super I/O automatic fan control: not yet implemented in coreboot.
To control fans, use software fan control methods in the meantime.
Change-Id: I106c195c890823f07227739c6b30133b996f6510
Signed-off-by: PugzAreCute <me@pugzarecute.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83267
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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Change-Id: I3cb1f11beba61afdf2be6188bde9ff135f8ace50
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
|
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This port was done via autoport and subsequent manual tweaking.
Special thanks to Nicholas Chin! This port would have never succeeded
without his help.
The board features two socketed DIP-8 SPI flash chips, as well as a
BIOS selection switch and onboard Power and Reset switches.
Working:
- Haswell MRC.bin
- All four DDR3/DDR3L DIMM slots
- S3 suspend and resume
- Libgfxinit
- HDMI-Out Port
- USB 2.0 Ports
- Vertical Type A USB 2.0
- USB 3.1 Gen1 Ports
- HD Audio Jack (audio output)
- Front panel audio connector (audio output)
- RJ-45 Gigabit LAN Port
- SATA3 6.0 Gb/s connectors
- mSATA/mini-PCI Express slot
- half mini-PCI Express slot
- PCI Express 3.0 x16 slots (both)
- PCI Express 2.0 x4 slot
- PCI Express 2.0 x1 slot
Working (board-specific)
- Power Switch with LED (functional, yet no LED)
- Reset Switch with LED (functional, yet no LED)
- BIOS Selection Switch
- Slow Mode Switch (locks the CPU at 800MHz)
not (yet) tested:
- IR header
- COM Port header
- Power LED header
- eSATA connector
- USB 2.0 headers
- PS/2 Mouse/Keyboard Port
- HDMI-In Port
- Optical SPDIF Out Port
not (yet) working:
- Software fan control: While the Nuvoton chip is correctly discovered,
the numbering of the fan connectors is faulty, resulting in the wrong
fan being controlled.
- Dr. Debug: on vendor firmware, the LEDs turn off after successful
boot. On coreboot, the LED shows two bright zeros after boot.
- Post Status Checker (PSC)
Change-Id: Iaa156b34ed65e66dd5de5a26010409999a5f8746
Signed-off-by: Jan Philipp Groß <jeangrande@mailbox.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82906
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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Add LCE_LMFBX101117480 MIPI panel for Wugtrio.
Datasheet: LMFBX101117480-10.1-TLCM-24.05.20-2.pdf
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: I863e172400ffb26b5c9c240a21d15c6a2240b4ad
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83221
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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Configuring USB2_PORT_EMPTY is equal to just not setting it. So remove
it to clean up a bit.
Change-Id: I6854f4a0d3e7b51b242549556a5838d4183d3473
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Change-Id: I1992c20dcdc5e974143690d44ee199d7c3394cfd
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
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Change-Id: I6d7bcd298408e15677f27d1a9797a490c57c9fc9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83247
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
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Change-Id: Ide5126c6e642ca16249efeaf46321724f2ddce9a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
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Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I9a9eb370e8e9e8874ad8b4b8ac0f43d61c1a4b9b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83250
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
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Configuring them to 0 is equal to not configuring them at all. So remove
them to clean up a bit.
Change-Id: I18134ac784fffb703e1fe513e5914f05faa749c9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83248
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Also, remove superfluous comments from devices which repeat their name.
Change-Id: I009330042b59c9e6e78aa6f3819546b771b26ff0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
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Change-Id: I8ce94c8bc7ed137eaace12d6cb0befa6c0d39a37
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82925
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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When CNVi based Wifi6 is disabled, CNVi based Bluetooth must be turned
off, based on fw_config. Otherwise, when device boots without the cbi
settings for wifi6, boot may fail with assertion error for line 817 &
819 of file 'src/soc/intel/alderlake/fsp_params.c'.
BUG=b:345596420
BRANCH=NONE
TEST=Dut boots fine with both Wifi6 & Wifi7 based cbi settings, along
with enumeration of corresponding BT device.
Change-Id: I03fde02fa4b36f4e47d6f0e95675feddb3bee7cd
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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PCIe based GPIOs of Wifi7 module are enabled based on firmware config.
BUG=b:345596420
BRANCH=NONE
TEST= Based on fw config configured, wifi6 or wifi7 along with
bluetooth ports are detected.
Change-Id: If0584e91b5143c6df742961657d242c046409b3a
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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PCIe based Bluetooth is on port8. This cl enables bluetooth for PCIe
based Wifi7 module.
BUG=b:345596420
BRANCH=NONE
TEST=With proper FW config enabled, BT gets detected on port8
Change-Id: I989cf6122f2555cc89f622e4ce5d21b574d0458e
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83076
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable pcie based, discreete wifi7 on root port4.
BUG=b:345596420
BRANCH=NONE
TEST=Verified Wifi7 module detection based on cbi settings
Change-Id: I8c2f4a750a1cb00c587bce21bc83ee583d0f4341
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83075
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new fw config field for wifi category as WIFI_6, which is CNVi
based and WIFI_7, which is PCIe based. Also, enable WIFI_6 for existing
CNVi based wifi port as well as bluetooth port.
BUG=b:345596420
BRANCH=NONE
TEST=Verified Wifi6 module detection
Change-Id: I4b218f772405bdb1b741b4d5e640d7b4f145cd76
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83074
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Add wake configuration and set 'add_acpi_dma_property'=true for CNVi.
Also, add "set 'add_acpi_dma_property' to true to tell the OS to enforce DMA protection for this device.
BUG=b:345596420
BRANCH=NONE
TEST=SSDT dump showed below:
Scope (\_SB.PCI0.RP01.WF00)
{
Name (_PRW, Package (0x02) // _PRW: Power Resources for Wake
{
0x23,
0x03
})
Name (_DSD, Package (0x02) // _DSD: Device-Specific Data
{
ToUUID ("70d24161-6dd5-4c9e-8070-705531292865"),
Package (0x01)
{
Package (0x02)
{
"DmaProperty",
One
}
}
Change-Id: If04539fe8dceb5c2edfc06a324ede11147b78b6d
Signed-off-by: Poornima Tom <poornima.tom@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83138
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch configures Serial IO UARTs mode as below.
UART0 and UART1 in PCI mode and keep UART2 disable as per hardware design.
BUG=b:338917836
BRANCH=firmware-brya-14505.B
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I5617331aaf505b97e25a717b145fb70dc53f5a38
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83205
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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ALC257 does not supoort built-in digtal buzzer, So use external pwm
to PCBEEP for beep sound.
BUG=b:346956771
BRANCH=None
TEST=emerge-brox coreboot sys-boot/chromeos-bootimage
firmware-shell: devbeep -> can output beep normally.
Change-Id: If924f9f27f229420e78015f418a97b2d5daf62e5
Signed-off-by: Jing Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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This patch adds initial code block required to build google/fatcat
board with Intel Meteor Lake Silicon. Later after the initial board
power-on is successful, we shall switch to Panther Lake silicon to
build the google/fatcat reference design.
BUG=b:347669091
TEST=Able to build the google/fatcat and able to hit power-on reset
using Intel Meteor Lake SoC platform.
Change-Id: Iad78aec51b2f0f240991c9c35842764a60be988e
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83197
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow nissa baseboard setting for storage field.
option STORAGE_EMMC 0
option STORAGE_NVME 1
option STORAGE_UFS 2
BUG=b:333486830
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I75b4b3037c245f7d517cb33d487f71da98f6c4e8
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83207
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
