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eMMC RST pin could reply on PLT_RST so we could keep GPP B3 in VIH.
BUG=b:263548436
TEST=emerge-brask coreboot
Change-Id: I610d53059e86945693bc5b3d7e43462e53640564
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72940
Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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APOB on Phoenix is larger, so expand the reserved DRAM and MRC_CACHE
regions to fit. This requires moving memory addresses around to prevent
overlapping memory linker errors.
TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds
all boards
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I42af7230ca5f09ba66b2b3c4f99ac3feac7feeea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72905
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Glinda and Phoenix have different requirements, so split the birman FMD
files to better apply to each SoC.
TEST='./util/scripts/testsoc -K PHOENIX -K GLINDA' successfully builds
all boards
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Ia2dbaeb8af04fb1d1224c397d728929c50800dfe
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72904
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The EFS must be located at the 128K offset. The combination of EC,
MRC_CACHE, and FMAP push the start of the coreboot CBFS region to 128K,
leaving no room for the CBFS headers for the EFS.
Move the MRC_CACHE region to the end of the image. This matches the
chromeos MRC_CACHE layout.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I3919fba40f22ee84b0a3eee1ac7b6e48c076d713
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The EFS must be located at the 128K offset. The combination of EC,
MRC_CACHE, and FMAP push the start of the coreboot CBFS region to 128K,
leaving no room for the CBFS headers for the EFS.
Move the MRC_CACHE region to the end of the image. This matches the
chromeos MRC_CACHE layout.
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I15e29443d2735342a5a43339f5bb095e5115349c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72902
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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2/5
of split changes of https://review.coreboot.org/c/coreboot/+/58552/28
Change-Id: I18f73462a3995038fe93750320dfc053fec969ba
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
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Add Raptor Lake (RPL) 28W dptf settings for Brya0
BUG=b:235311241
BRANCH=firmware-brya-14505.B
TEST=Built and tested on brya
Change-Id: I5d06c1ace5b481012ea39f2a57570eb6330479cb
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72887
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Add Raptor Lake (RPL) 28W dptf settings for Skolas
BUG=b:235311241
BRANCH=firmware-brya-14505.B
TEST=Built and tested on skolas
Change-Id: I4364ca6a50906c2a6dd0e754238264c680e7ebd0
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Update Power Limit1 (PL1) minimum value to 15W based on the Brya
design.
BRANCH=firmware-brya-14505.B
BUG=b:235311241
TEST=Built and tested on Brya system
Change-Id: Ifd5256221b82eae2cfe8009918f8ff4791751b4d
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72868
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Update Power Limit1 (PL1) minimum value to 15W based on the skolas
design.
BRANCH=firmware-brya-14505.B
BUG=b:235311241
TEST=Built and tested on Skolas system
Change-Id: I1027ca2bf2323ac959474ee6c38e47fa530113da
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72727
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast.
BRANCH=firmware-brya-14505.B
BUG=b:235311241, b:261749371
TEST=Built and tested on Brya system
Change-Id: I58bc7132086b0776ee191a242bd1302554f3854f
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72867
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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Update dptf thermal settings as per suggested by thermal team.
Control fan based on TSR sensors, not based on CPU sensor temperature
which changes too fast. This change is based on the discussion on
bug:235311241 comment#7.
BRANCH=firmware-brya-14505.B
BUG=b:235311241, b:261749371
TEST=Built and tested on Skolas system
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Ibeddce61b0d73d82a85f486e7cb5cbfa9568953c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71692
Reviewed-by: AlanKY Lee <alanky_lee@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
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The keyboard reset is not being used on this board, so disable the
functionality.
BUG=None
TEST=Check register values
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I4a9f8f254dfefcb32a77f558f984bcdd6004d34b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72913
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Enable DPTF functionality for Meteor Lake based mtlrvp board
BRANCH=None
BUG=None
TEST=Built and booted on mtlrvp board
Change-Id: I8d3e1cd43cf67c3f2081be339589a6da358b668c
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Commit bf3c648fa7f6 ("soc/intel/skl; mb/google/eve,poppy: Update NHLT
methods") contained a copy/paste error for rammus, swapping the max98373
entry for the correct max98927 one. Change it back.
TEST=build/boot Windows on rammus, verify audio functional with
coolstar's AVS audio drivers.
Change-Id: Ibcd4b752e01866a3dd54997f1d2a6c079b07b7a3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72473
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: CoolStar <coolstarorganization@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Commit ae20d4c78f9f ("mb/google/volteer: Fix USB4 enabling for volteer
family") reworked the USB4/TBT config for volteer, but drobit variant
was missed for some reason. Add the missing USB4/TBT entries.
TEST=build/boot Windows on drobit, verify USB4/TBT functional.
Change-Id: I43d771eeaf29b4e141b222ccb05af5cb7ceedc6f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72141
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Commit 525c61f74e94 ("mb/google/hatch: Implement touchscreen power
sequencing") contained a copy/paste error; KOHAKU's enable GPIO is set
twice in ramstage, and the reset GPIO not at all, leading the
touchscreen to not be detected.
Correct the copy/paste error by replacing the 2nd instance of GPP_C12
with GPP_D15.
TEST=build/boot Windows/Linux on KOHAKU, verify touchscreen works.
Change-Id: I08d35f1e2a951cdaa463daa34df2134fdc8c65c8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72119
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Enables display backlight control under Windows.
VBT extracted from stock ChromeOS firmware Google_Drallion.12930.543.0.
TEST=build/boot Win11 on drallion, verify OS backlight control
available and functional.
Change-Id: I85065f22b825a7616fa4ac632c42ae7972091e24
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72579
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Under Win11, a longer delay after asserting reset is needed for the
Goodix touchscreen to init properly. Increase the reset delay to match
that used for the Goodix touchscreen by other volteer variants (120ms).
TEST=build/boot Win11, Linux on eldrid variant with Goodix touchscreen,
verify functional.
Change-Id: I489f037f0bbade9567aad2ad64404a5ac66965d9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Constitution will use SOLDERDOWN. Add memory.c to override baseboard.
Add mem_parts_used.txt and generate dram_id.generated.txt and
Makefile.inc
Memory:
SAMSUNG K4U6E3S4AB-MGCL
MICRON MT53E1G32D2NP-046 WT:B
BUG=b:267539938
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
Change-Id: Id879b2a7491f29e9fca903dcf3c022ec8ffffab4
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72775
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add EC_HOST_EVENT_USB_MUX to MAINBOARD_EC_S0IX_WAKE_EVENTS for
brask. Without it EC won't send host event to wake AP when USB
MUX is changed during S0ix. It's there for brya but missing
for brask.
BUG=b:267573651
TEST=emerge-brask coreboot
Signed-off-by: Derek Huang <derekhuang@google.com>
Change-Id: Id08d9aec9ab3566176369f2ca25cd00b9f0a0ca5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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This reverts commit 8e1bb93fb88bc9cc20aab33a1fe09fb4c0c652a0.
Reason: Enabling L.2 breaks some devices on this bridge. Reverting
until a workaround is found and additional testing is done.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I9f721178244e7764e9b08e419db8a8c05ecc29a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72916
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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Hook up the `wake_on_usb` EEPROM setting so that it works as intended.
TEST=Keysmash on a USB keyboard, verify Hermes does not wake from S3.
Change-Id: I81531b90abae6a62754ea66c47e934e1f440bda2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72906
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO 67 is not currently used on skyrim, so set it as no-connect.
Since it's now free for other purposes, make sure that the
SPI-ROM-SHARING functionality is disabled.
BUG=b:268330591
TEST=Examine registers after change
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Id083baf41d25920eca09795453a01aac1d00d0f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72908
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BUG=None
TEST=Verify that DMI type 3 - Chassis Information Type field has changed
from Desktop to Laptop
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I76c8970fe3fdc2ea322a07f114ad03a0373e152c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72907
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Move the missing APCB warning to the end of the build and make it stand
out better. Prior to this patch, the warning would appear as one of the
first build messages and easily be missed due to the rest of the build
messages.
TEST=build with and without proper APCBs being found, warning message
appears only when APCB is not found and stands out more
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: Iabe32636b8e31fe781519533a329a08535bd661a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72901
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Mainboard name is Compal JBL00. This is based on the GM45/ICH9M chipset
and uses DDR2 RAM. The EC is a SMSC MEC5035 which has internal flash, so
there's no issue about making sure to include the EC firmware in the
BIOS region. This only supports the variant with integrated graphics
only, the version with a discrete Nvidia Quadro NVS 160M is not
supported.
This port was based on the Lenovo T400 port.
Working:
- USB EHCI debug (lower USB port on right side)
- Keyboard
- Touchpad/trackpoint
- VGA
- Displayport
- ExpressCard
- Audio
- Ethernet
- mPCIe WiFi
- mPCIe Bluetooth (uses USB)
Not working:
- Brightness hotkeys
- Physical Wireless switch
- SD card slot: Linux outputs an "irq 18: nobody cared" message when
inserting a card, after which it disables the IRQ
Unknown/untested:
- Dock
- Smartcard (slot and contactless)
- Firewire
- eSATA
- TPM
- Battery (my battery is at the end of its lifespan)
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Change-Id: I516ebbf4390a3f6d242050da8d35dc267b8b3a28
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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For Geralt, we use BOE_TV110C9M_LL0 as MIPI firmware display, so add the
power-on sequence for BOE_TV110C9M_LL0.
BUG=b:244208960
TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt.
Change-Id: I3ef0b2e26d8cc0dc35c2985363ee4c3557dac8a9
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72749
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The regulator MT6359P is needed by both firmware display and SD card.
To avoid duplicate initialization in ramstage, publicize init_pmif_arb()
as mt6359p_init_pmif_arb() and call it from mainboard_init(). This would
save 13 ms for boot time on Geralt.
BUG=b:244208960
TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt.
Change-Id: I29498d186ba5665ae20e84985174fc10f8d4accd
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72839
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Move eMMC init from depthcharge into coreboot to remove it from the
critical boot path. Doing so saves us almost 35ms on villager:
before change:
finished storage device initialization 50,783
after change:
finished storage device initialization 16,255
BUG=b:254092907,b:218406702
BRANCH=None
TEST=flash new FW onto villager and make sure can boot from eMMC
Change-Id: I1af1ec162029120332e7f531f75c3780266d322b
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71830
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Remove the commented VBOOT_VBNV_CMOS Kconfig option as well as VBOOT for
emeraldlake2.
BUG=b:235293589
TEST=none
Change-Id: Ie583dcf615573784c657b9d220ad417b05704150
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72890
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for z220_series.
[1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1
BUG=b:235293589
TEST=./util/abuild/abuild -t HP_Z220_CMT_WORKSTATION -a \
# with VBOOT enabled and a custom FMDFILE with RW_NVRAM region
Change-Id: I1c60a44fb12fd093f45cf54ef2f9e0e02afc80bd
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Config GPP_B9 as LAN_CLKREQ_ODL based on latest schematic
BUG=265021899
BRANCH=dedede
TEST=emerge-dedede coreboot
Change-Id: Ia099bd64364b46240e0426aa57dfe8d230e7494d
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
Reviewed-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add SoC config and .early_init = 1 in I2C1
BUG=b:263060849
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I661bdee6c7b9e6ea4cd0ab2006967d7c7ddd0f67
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72872
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
|
|
1. Add fw_config:STORAGE_UFS & STORAGE_NVME to switch storage.
2. rp11 off change to on.
BUG:b:263846075
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I35c02ac9cbb8442d7b4aae57f6c7b576b2b5f77b
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72090
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
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Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz for starting next phase.
BUG=b:267539952
TEST=None
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Id46201351780bb5bc05422ff36dad6972285690e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Chao Gui <chaogui@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
|
Create the aurash variant of the brask reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:263691099
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_AURASH
Change-Id: I595102778071f822c5cf69ceadeed174e5ea4836
Signed-off-by: Zoey Wu <zoey_wu@wistron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72837
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Move get_loglevel_from_vpd from mb/ocp/deltalake to driver
drivers/ocp/vpd/loglevel_vpd.c.
Change-Id: I70af1051f63c527fd8150f5ecbe4765b4aaacd20
Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71936
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This patch enables PCI Express Advanced Error Reporting Capability for
WWAN, WLAN, and SSD root ports. On enabling PCIE_RP_AER, PCIE device
will automatically report (if any error) about the error nature to the
corresponding PCIe root port.
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Iab8619818e2219b41287b895513eb04b0464401e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815
retimer on USB U1/U2 transition. The usb_lpm_incapable config is
used to disable USB U1/U2 transition for these Type-C ports.
This patch add usb_lpm_incapable config for the following variants
with PS8815 retimer:
- kinox MLB: C0
- volmar DB: C1
- osiris MLB: C0/C1
- mithrax DB: C1
- felwinter DB: C1
- taeko DB: C1
- gimble DB: C1
- gimble4es DB: C1
- taniks DB: C1
- marasov DB: C2
- gaelin MLB: C0/C1
- skolas DB: C1
- skolas4es DB: C1
- brya0 DB: C1
BUG=b:253402457
TEST=Plug in device and check LPM sysfs nodes are disabled
localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u1
disabled
localhost ~ # cat /sys/bus/usb/devices/2-X/power/usb3_hardware_lpm_u2
disabled
Change-Id: Ie9246ff7908887404f49ec10ee781c8cba410557
Signed-off-by: Ron Lee <ron.lee@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
|
|
Add regulator VM18 support to supply power for BOE_TV110C9M_LL0.
BUG=b:244208960
TEST=test firmware display pass for BOE_TV110C9M_LL0 on Geralt.
Change-Id: I13bafbe10a18a18e253575fd107c9b415f28ef01
Signed-off-by: Sen Chu <sen.chu@mediatek.corp-partner.google.com>
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72748
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There might be inconsistence between regulator_id[] and
`enum mtk_regulator` when we need to add new regulator IDs for Geralt.
Therefore, we implement get_mt6366_regulator_id() to get regulator IDs.
BUG=None
TEST=build pass.
Change-Id: I3d28ebf2affe4e9464b1a7c1fb2bbb9e31d64a5e
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72838
Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
update EC FW offset location in spirom to 0x81000
For mayan board EC FW is located at offset 0x81000 location,
0th location contains pointer to this EC FW location.
Change-Id: I63c797e12ed131e8411c11379f4db9bcc29b49a2
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
|
|
This patch adds ACPI configuration for USB2/3 ports for mtlrvp as per
schematics. This helps in generating corresponding ACPI code at runtime
that includes port information.
BUG=b:224325352
BRANCH=None
TEST=Able to build and boot MTLRVP. Connect USB device and check if
corresponding enumeration of USB device (14.0) is observed on executing
lspci.
00:14.0 USB controller: Intel Corporation Device 7e7d (rev 01)
00:14.1 USB controller: Intel Corporation Device 7e7e (rev 01)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie150247661322e3944be15dc70f66033266d8aac
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72787
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch describes BB retimer for tcss_dma0 and tcss_dma1 with respect
to GPP_B21 as per schematics.
+--------------+------------+
| tbt_pcie_rp0 | tcss_dma0 |
+--------------+------------+
| tbt_pcie_rp1 | tcss_dma0 |
+--------------+------------+
| tbt_pcie_rp2 | tcss_dma1 |
+--------------+------------+
| tbt_pcie_rp3 | tcss_dma1 |
+--------------+------------+
BUG=b:224325352
BRANCH=None
TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration
of tbt_pcie_rp as part of lspci.
00:07.0 PCI bridge: Intel Corporation Device 7ec4
00:07.1 PCI bridge: Intel Corporation Device 7ec5
00:07.2 PCI bridge: Intel Corporation Device 7ec6
00:07.3 PCI bridge: Intel Corporation Device 7ec7
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie1a0026b064aa4f7fcd27e75c0b0d052ec620dcc
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72786
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch describes the TCSS USB ports for mtlrvp as per schematics.
This patch describes TCSS ports for UPC_TYPE_C_USB2_SS_SWITCH as below,
tcss_usb3_port1: USB3 Type-C Port C0
tcss_usb3_port2: USB3 Type-C Port C1
tcss_usb3_port3: USB3 Type-C Port C2
tcss_usb3_port4: USB3 Type-C Port C3
BUG=b:224325352
BRANCH=None
TEST=Able to build and boot MTLRVP to ChromeOS. Verify the enumeration
of xhci (0d.0) as part of lspci. Also verify the enumeration of Type-C
ports as part of cbmem -c.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I0054ac4e3d1d9b97cfea615831ec8f3d3e00c9e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72785
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables FM350GL 5G WWAN support for mtlrvp.
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module 00:1c.6
is enumerated as part of lspci and cbmem -c in AP console. Also verify
generation of PXSX Device as part of SSDT. Able to connect WiFi and
access internet.
cbmem -c:
\_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3)
\_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL)
SSDT:
Scope (\_SB.PCI0.RP07)
{
Device (PXSX)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I870cc0782fb989f1bdbe369a4a12630a62729d8e
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72779
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
To deprecate VBOOT_VBNV_CMOS [1], replace VBOOT_VBNV_CMOS with
VBOOT_VBNV_FLASH for samsung boards lumpy and stumpy. 0x8000 unused
flash space is allocated for RW_NVRAM.
Previously BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES was selected for
CPU_INTEL_HASWELL, CPU_INTEL_MODEL_{2065X,206AX} and others (see [2]).
However, there seems to be no particular reason on those platforms.
We've dropped the config for haswell. Now drop it for
CPU_INTEL_MODEL_{2065X,206AX}, so that VBOOT_VBNV_FLASH can be enabled.
[1] https://web.archive.org/web/20230115020833/https://issuetracker.google.com/issues/235293589?pli=1
[2] commit 6c2568f4f58b9a1b209c9af36d7f980fde784f08
("drivers/spi: Add BOOT_DEVICE_SPI_FLASH_NO_EARLY_WRITES config")
BUG=b:235293589
TEST=./util/abuild/abuild -a -t SAMSUNG_LUMPY -x
Change-Id: I833edd4f7a328b21e81c971ba8a9aec0aad7d3d3
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
Create the constitution variant of the brask reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:267539938
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_CONSTITUTION
Change-Id: Idb6089561d3aa5aac4448f9d46347c731f027e9c
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72730
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables GSPI [1] interface for mtlrvp based on mtlrvp
schematics.
BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to ChromeOS. (Base patch for CB:71223)
SPI[0].Mode = 0
SPI[0].DefaultCsOutput = 0
SPI[0].CsMode = 0
SPI[0].CsState = 0
SPI[1].Mode = 1
SPI[1].DefaultCsOutput = 0
SPI[1].CsMode = 0
SPI[1].CsState = 0
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I3d4c4f19dd80fefa80c365b5ecac0a234f5af860
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72706
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
This patch enables PCIe port for WLAN as per mtlrvp schematics
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WLAN module gets
is enumerated as part of lspci in AP console.
ae:00.0 Wireless controller [0d40]: Intel Corporation XMM7360 LTE
Advanced Modem (rev 01)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ief3c0eff40ced57d29ce343e569b6b392c27ad74
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72778
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch enables EC_GOOGLE_CHROMEEC_SWITCHES for MTL_CHROME_EC which
helps in mode switch using dut-control power_state:rec.
BUG=b:224325352
BRANCH=None
Test=Able to build and boot MTLRVP to ChromeOS. Check if chroot command
dut-control power_state:rec puts the DUT to recovery mode.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I5de0cd6c9a50bd85238205e09976a8bd8dd7142f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
This patch enables PCIe port for WWAN as per mtlrvp schematics
BUG=b:224325352
BRANCH=None
TEST=Build and boot mtlrvp to ChromeOS. Ensure that WWAN module
gets enumerated with cbmem -c.
\_SB.PCI0.RP07: Enable RTD3 for PCI: 00:1c.6 (Intel PCIe Runtime D3)
\_SB.PCI0.RP07: Enable WWAN for PCI: 00:1c.6 (Fibocom FM-350-GL)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ib372db9642a3c7b3a21a112fa0e6e0b4bc88a9ea
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72777
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch adds ACPI support for Type-C ports.
BUG=b:224325352
BRANCH=None
Test=Able to build and boot MTLRVP. Verify SSDT for the corresponding
entry,
\_SB.PCI0.PMC.MUX.CON0 under Device (CON0)
\_SB.PCI0.PMC.MUX.CON1 under Device (CON1)
\_SB.PCI0.PMC.MUX.CON2 under Device (CON2)
\_SB.PCI0.PMC.MUX.CON3 under Device (CON3)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I8e5957ca7a6c542a64d79b2ceefbed79ead15811
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72789
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
|
|
Found-by: linter
Change-Id: I7c6d0887a45fdb4b6de294770a7fdd5545a9479b
Signed-off-by: Alexander Goncharov <chat@joursoir.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72795
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
ELAN updated the datasheet, the HID/I2C protocol's T3 delay
time is 150ms now. Modify the kano's delay time to follow
the requiremnet.
BUG=b:247944006
TEST=Manually checked touchscreen works after reboot and suspend.
Change-Id: I42a7737060a82c0b27717f1510b8ec64abd1465a
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72784
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paz Zcharya <pazz@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
|
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Mendocino SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I1ed0407826f579eb14169246b7b14ba677c20e8d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Cezanne SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I6953da5e0f1966aa3022364d9a9c72ebafc698cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72184
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Picasso SoC, remove it form the global NVS
and add an ACPI object for this in the DSDT of the mainboards that use
it in their ACPI code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ia265f3eebf5e48c185d2e4bf4ef74f8eab7c9606
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
|
|
Since the LIDS field is only used in the ACPI code and not in the C code
of any mainboard using the Stoneyridge SoC, remove it form the global
NVS and add an ACPI object for this in the DSDT of the mainboards that
use it in their ACPI code. Eventually the LIDS object should probably be
moved to the EC's ACPI code, but that's out of scope for this patch.
TEST=google/liara doesn't show ACPI errors in Linux' dmesg
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I778c4189607035b4765c6cb8b2e74030dcf9069f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
This patch adds below chip configuration for I2C devices for mtlrvp.
+-----------+--------------------+-------------+
| INTERFACE | PCI Number (B:D:F) | DEVICE |
+-----------+--------------------+-------------+
| I2C0 | 0:0x15:0 | CAM1 |
+-----------+--------------------+-------------+
| I2C1 | 0:0x15:1 | CAM0 |
+-----------+--------------------+-------------+
| I2C2 | 0:0x15:2 | NC |
+-----------+--------------------+-------------+
| I2C3 | 0:0x15:3 | HID |
+-----------+--------------------+-------------+
| I2C4 | 0:0x15:4 | NC |
+-----------+--------------------+-------------+
| I2C5 | 0:0x15:5 | NC |
+-----------+--------------------+-------------+
BUG=b:224325352
BRANCH=None
TEST=Able to boot mtlrvp (LP5/DDR5) to ChromeOS. Also verify serial bus
enumeration through lspci.
00:15.0 Serial bus controller: Intel Corporation Device 7e78 (rev 01)
00:15.1 Serial bus controller: Intel Corporation Device 7e79 (rev 01)
00:15.3 Serial bus controller: Intel Corporation Device 7e7b (rev 01)
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ia5964472be902041f961187c0072a89055badd4f
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72647
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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This patch enables display configuration for mtlrvp. The change follows
mtlrvp schematics.
BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump.
Also verify display over eDP and HDMI.
DdiPortAConfig : 0x1
DdiPortBConfig : 0x0
DdiPortAHpd : 0x0
DdiPortBHpd : 0x1
DdiPortCHpd : 0x0
DdiPort1Hpd : 0x0
DdiPort2Hpd : 0x0
DdiPort3Hpd : 0x0
DdiPort4Hpd : 0x0
DdiPortADdc : 0x0
DdiPortBDdc : 0x1
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I05bd7427d6a339ee200731a8dd448e85efc694e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72645
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
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This patch removes the configuration of GPP_A12 for mtlrvp. Garfield
Peak (WLAN) doesn't use GPP_A12 for WAKE_N. Configuring GPP_A12 pin
prevents system entering G3 (reboots) on issuing shutdown -h now. Hence
configuring GPP_A12 as PAD_NC.
BUG=b:224325352
BRANCH=None
TEST=On issuing 'shutdown -h now' system enters G3
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I5e46b8afd3e0055440fd3c3db4aa5a9f1d4aa556
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
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1. Enable Cnvi BT Audio Offload feature and also
configure the virtual GPIO for CNVi Bluetooth I2S pads.
2. According to the SOC_GPIO_Table_20230116,
Change GPIO GPP_D15, GPP_D16 to NC.
BUG=b:264834572
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I4901c8cd660f2d47018e4cccdb67f666f0800423
Signed-off-by: Jamie chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72035
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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This variant was added without a devicetree, so add the board
specific devicetree according to schematic_20230110.
BUG=b:263060849
BRANCH=None
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: Ie05c152a20953e3e2d5f4ba5f9c00160a3e418e1
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
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NVMe PCIe 9-12 using clk_src1 and clk_req2 mapping to hardware design,
Due to inconsistency between PMC firmware and FSP, we need to set
clk_src to clk_req number, not same as hardware mapping in coreboot.
Then swap correct setting to clk_src=1,clk_req=2 in mFIT.
BUG=b:265720813
TEST=build firmware and veirfy suspend function on DUT.
Cq-Depend: chrome-internal:5351299
Change-Id: Ia057dfa98cb9293d9e212edb4e4ac198e94e8985
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72051
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Turn off camera power during S0ix to improve power consumption.
BUG=b:265754302
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie2b300783adfc1cab30bc897d086a3674436724a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72089
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add configuration to bump up the SPI flash bus speed from 66 MHz to 100
MHz starting the board version of the current phase.
BUG=b:260127676
TEST=Build and boot to OS in Frostflow with 100 MHz SPI bus speed.
Observe that the boot time improved by 100 ms compared to 66 MHz SPI
flash bus speed.
firmware log:
SPI fast read speed: 100 MHz
At 66 MHz:
Total Time: 1,563,384
At 100 MHz:
Total Time: 1,462,570
Change-Id: I9435f4ad0d3541b040703dc9a453badbd080dc09
Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72694
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
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Not exactly sure about the usb4_xhci controllers, but for now I assume
those will behave like any other XHCI controller.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I22384f58e245a1486793831d29d22e9c618f646c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72773
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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The PCI Device ID Assignments table from PPRs #57019 Rev 1.65 and
PPR #57396 Rev 1.54 were used as a reference. Some devices will need to
have ops added in future patches. Since the xhci_2 device isn't there
any more, also drop it from the mainboard devicetrees. The actual USB
port configuration on xhci_0 and xhci_1 is updated in the next patch.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I49721bc44fa1e2a0118a8c3ac79a36aee64be687
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72771
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Now that the PCIe ports on device 1 are added, rename the aliases for
the PCIe ports on device 2 to have a common naming scheme. For phoenix
the device alias names are based on the device and function number the
bridge is connected to.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I5f5698408019bb9222b599dd78540ca1b187b56d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72737
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This enables L1.2 for the SSD port.
link_hotplug is unused on Mendocino, so remove it while I'm here, just
as code cleanup. This has no functional difference.
Enabling L1.2 on other devices currently causes problems. Debug is
ongoing.
BUG=b:265890321
TEST=Build & boot, look at states enabled in lspci. Test device
functionality.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: I8940856a127c8a4ba45148cbbf07a08b621beb4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch drops the WFC sensor OV8856 (reused from the Brya chassis)
support for Rex and added support for Rex specific UFC sensor OV13B10.
BUG=b:267264348
TEST=WFC MIPI cameras have been enabled using google/rex Proto 1.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ic785b82db4368f40d91921f29c218cf417938541
Reviewed-on: https://review.coreboot.org/c/coreboot/+/70226
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
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Enabling `SaGv` along with FSP v2473 is causing blank display issue.
Mostly likely we shouldn't enable SaGv yet on Intel MeteorLake.
BUG=b:267446159
TEST=Able to see ChromeOS UI in consecutive boot.
This reverts commit cbca81c5946384843197c08401c4266f45fef4a2.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ifbcc36515f7550c183c40e5af94684f5c3e39a7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72774
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Removing default on/off from mainboard devicetrees is left as a follow-up.
Change-Id: I74c34a97ea4340fb11a0db422a48e1418221627e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69502
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
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Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the
Kernel when an EC panic occurs. If system safe mode is also enabled
on the EC, the kernel will have a short period to extract and save info
about the EC panic.
BUG=b:266696987
BRANCH=None
TEST=Observe kernel ec panic handler run when ec panics
Change-Id: I9b50ab3c0bcef192ef89f173852cda222f1533c7
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72455
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
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Enable the HPD GPIO so that the USB-C port can be used for
DisplayPort.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: If93d08f64cf7b09bb47622bdc7f22280b8a48174
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72431
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp
schematics.
1. Enable CNVi BT Core in device tree
2. Enable CNVi Wifi (pci 14.3) device in device tree
BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to ChromeOS.
CNVi Mode = 1
Wi-Fi Core = 1
BT Core = 1
BT Audio Offload = 0
BT Interface = 1
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Change-Id: I7eaf625e5acfcefdae7c81e186de36b42c06ee67
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72704
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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The patch disables Tccold Handshake to prevent possible display
flicker issue for skolas board. Please refer to Intel doc#723158
for more information.
BUG=b:221461379
BRANCH=firmware-brya-14505.B
TEST=Boot to OS on Skolas, verify upd setting.
Change-Id: Ic184a61c27abd729667cd181d8f9954f58b67856
Signed-off-by: Selma Bensaid <selma.bensaid@intel.com>
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68636
Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add ADL-N 15W CPU thermal settings.
BUG=b:265101768
TEST=emerge-nissa coreboot
Change-Id: I325704d6fc4ddaf56eaddd6a69bc619588df99cd
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71860
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Removed workaround since the latest schematics fixed.
Power Sequencing of ELAN6918 (in ACPI) after this patch
`POWER enabled -> RESET deasserted -> Report EN enabled`
BUG=b:247029304
TEST=Verified ELAN touch panel is working as expected after booting
Google/rex device to ChromeOS.
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: I19629262776f7e0cccbdebb2285890d177a8a8a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72725
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Create overridetree and GPIO config based on latest schematic:
1. Update PCIe ports
2. Update USB ports
3. Remove unused I2Cs
4. Remove unused peripherals (SD card, eDP, speakers)
5. Add LAN
6. Thermal policy for updated temp sensors
BUG=b:260934185, b:260934719
BRANCH=dedede
TEST=build
Change-Id: I4789be2eee1d01288031bc1e8ee5c9d6df71f9fe
Signed-off-by: Liam Flaherty <liamflaherty@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71882
Reviewed-by: Adam Mills <adamjmills@google.com>
Reviewed-by: Sam McNally <sammc@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Contents of the EDID are passed by a reference to an array
of length 0x80, for which the macro 'PTN_EDID_LEN' has already
been around.
This patch makes use of this macro within the driver and mainboard
implementation utilizing it.
BUG=none
TEST=A successful build of mc_apl{1,4,5,7} and mc_ehl3 mainboards.
Change-Id: If7d254aaf45d717133bb426bd08f8f9fe5c05962
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72653
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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This is regarding issues observed on multiple Brya and Nissa
variant such as Skolas and Nivviks. Issue is that once coreboot
sets GPE_EN bit for the GPIO pin and locks it, kernel is not able
to change the control bit. Hence kernel is not able to control the
IRQ on the pin when required.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Ref: commit 38b8bf02d820
("intelblocks: Add function to program GPE_EN before GPIO locking")
This patch skips the locking for GPP_F14 to allow kernel to
configure it later during reboot or shutdown as required.
BUG=b:254064671
BRANCH=None
TEST=Shutdown works on Skolas and Brya board with the patch.
Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: I7e4a6ac4668028bcd5fa400b9aa8eccf36a79620
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72648
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is an existing issue for skolas boards where board wakes up
from shutdown immediately due to touchpad wake signal.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Ref: commit 38b8bf02d820 ("intelblocks: Add function to program GPE_EN before GPIO locking")
Later issue was found to be with GPP_F14 configuration for skolas
boards. While shutting down, kernel is not able to disable IRQ for
touchpad due to GPE_EN register getting locked and it is preventing
shutdown of the board.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later.
BUG=b:254064671
BRANCH=None
TEST=Shutdown works on Skolas board with the patch.
Nissa Bug: 234097956
Signed-off-by: Maulik Vaghela <maulikvaghela@google.com>
Change-Id: I09cf1af1f5ab11b06073755374ee8a306984d557
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72426
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure the rcomp, dqs and dq tables based on the schematic.
BUG=b:264340545
BRANCH=firmware-brya-14505.B
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I82ca8aa9c3535983d5c506c15dbc69e7be926fa0
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Marx Wang <marx.wang@intel.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Omnigul variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
BUG=b:263846075
TEST=FW_NAME=omnigul emerge-brya coreboot
Change-Id: I90ae116ccccde48792aeafaa683c7420a95c9886
Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72509
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After powering on the device, we need to pull USB3_HUB_RST_L up to
enable USB3 Hub.
TEST=boot kernel from USB ok
BUG=b:264841530
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Signed-off-by: Liju-Clr Chen <liju-clr.chen@mediatek.com>
Change-Id: I8df35efb78e90a5b3314840fe2eae81d6e501242
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72594
Reviewed-by: Yidi Lin <yidilin@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently there is a problem, where two Displayports are not working. To
be precise: TCP0 and TCP1 (Type-C Port 0/1) are not working.
Setting the lane count of the TCP0 and TCP1 to x1 works fine.
Setting the lane count of the TCP0 and TCP1 to x2 does not work.
Setting the lane count of the TCP0 and TCP1 to x4 does not work.
The reason for that is currently unknown.
This change sets the lane count of the TCP0 and TCP1 Port to x1 length
in the VBT binary.
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Change-Id: I182b528275152bf5adcb01a56816afd65674aed3
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72610
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the print message to start with uppercase, 'board'
to 'Board'.
BUG=b:224325352
BRANCH=None
TEST=Able to observe proper print message when invalid board id is
configured.
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: Ie82df940cbd1eba9c5d485b48648c2bc8f234aae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72638
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Usha P <usha.p@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow thermal team's request on b/248086651 comment#27. Update the
thermal table setting for each mode and the conditions of temperature
switching.
BUG=b:248086651
TEST=emerge-skyrim coreboot
Change-Id: Ida10d9b10c33dea11440879afda07c04c1eccb9f
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72006
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
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<gpio.h> chain-include <soc/gpio.h>.
Change-Id: I48191064fcee53ca843a537aa36bdbbd57736bf2
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72588
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Id8e1a52279e6a606441eefe30e24bcd44e006aad
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69815
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
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Since the PSE GBE0 MAC has been disabled on this board in
commit 343644006f89 ("mb/siemens/mc_ehl3/devicetree.cb:
Remove TSN GbE 0"), therefore disable the corresponding
GPIOs as well.
BUG=none
TEST=Test link detection and IP assignment on the remaining
ports (PSE GBE1 and PCH GBE0) of mc_ehl3.
Change-Id: Ifa055f58894688471d68b9b93fcb994fdcb2a568
Signed-off-by: Jan Samek <jan.samek@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72449
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The parallel mp code picks up lapics at runtime, so remove it from all
devicetrees that use this codebase.
Change-Id: I5258a769c0f0ee4bbc4facc19737eed187b68c73
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69303
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch adds initial romstage code and spd data for LP5 memory
parts for MTL-RVP. This also configures memory based on the board id.
Memory - x32 LPDDR5
Vendor/Model - Micron/MT62F2G32D8DR-031 WT:B
Board ID -
0b0000 - Empty spd hex file
0b0001 - DDR5 (Empty spd hex file)
0b0010 - LPDDR5 (MT62F2G32D8DR-031 WT:B)
BUG=b:224325352
TEST=Able to boot intel/mtlrvp (LP5 SKU) to ChromeOS
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Change-Id: I15b352eb246aed23da273e56490c7094eae9d176
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/69741
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch selects USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS for
Google/Marasov variant which intends to achieve a unified AP firmware
image across UFS and non-UFS skus.
Note: Enabling this config would introduce an additional warm reset
during the cold-reset scenarios due to the function disabling of the
UFS controller as results we are expecting ~300ms higher boot time
(which might not be user visible because `cbmem -t` can't include
impacted boot time due to in-between resets).
BUG=b:264838335
TEST=Able to enter S0ix on Marasov NVMe sku after disabling UFS
during boot path.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ie8b8814cdb5e0d97a382cebfe82868ada5762341
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71990
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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The current CMOS option causes Linux to not boot, as the GRUB EFI
loader will report an incorrect parameter.
Update the CMOS option so that the corresponding UPD is changed when
the wireless is set to disable, so that the root port for the wireless
is also disabled.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I607d700319d6a58618ec95b3440e695c82dff196
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71896
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the Type-C USB 2.0 interface to a standard port, as the
Type-C macro will not work in Linux (dmesg says the cable is
faulty),
This makes the port work reliably in Linux, tested with:
* Manjaro 21
* Ubuntu 22.04
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I6dbf31b6e4603685297e9e5203b0db6ac1b9e24a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72387
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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