| Age | Commit message (Collapse) | Author |
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Add devicetree settings per the schematic.
Differences to gladios:
1. remove SD reader
2. remove EMMC setting
3. modify USB port distribution
FRONT
-------------------------------------------------------
| A3 A1 |
| C0 A2 A0 |
-------------------------------------------------------
BACK
-------------------------------------------------------
| --------------- |
| | TX25A | |
-------------------------------------------------------
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: Ia010e99c21e8d6088f6bb873f79dc19cadc9e455
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81447
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Refactor the `get_port_b_vref_cfg()` function to only return the
variable bits of the value. The NID itself is not connected, and
the `misc` field in the verb conveys the Vref value.
Change-Id: I5108f5339c5b002403a4e5339da6d52046c8bcbe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82395
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Probe C1 port in devicetree and disable un-used C1/A1 port by FW_CONFG.
BUG=b:339534479
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
flash and check boot log on DUT.
Change-Id: I944ff6f2fa712e7579ed1c9879f75835adc3ac4c
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Remove unused setting for retimer.
BUG=b:328711879
Change-Id: I48d8680d43a07aa3408dfbf5b25b568c2b51b343
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82475
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Beechnut City CRB is the 2 socket reference board for 6th Gen Xeon-SP
SP SoCs (Granite Rapids SP and Sierra Forest SP).
This patch initially sets the code set up as a compilation target with
GNR N-1 FSP, and with basic feature supports (Integrated IO Controller
(IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/beechnutcity CRB
Change-Id: I3f6a0fb97b62baadb438fb9f11fdd78fccb3f89a
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Gang Chen <gang.c.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81322
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Avenue City CRB is the 2 socket reference board for 6th Gen Xeon-SP
AP SoCs (Granite Rapids AP and Sierra Forest AP).
This patch initially sets the code set up as a compilation target
with GNR N-1 FSP, and with basic feature supports (Integrated IO
Controller (IIO) configuration, BMC, UART, HPET).
TEST=Build on intel/avenuecity CRB
Change-Id: I64fdd5388aadf7732f6d3daa600c1455d3672a46
Signed-off-by: Gang Chen <gang.c.chen@intel.com>
Co-authored-by: Shuo Liu <shuo.liu@intel.com>
Co-authored-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81319
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Instead of including stub/mpio/chip.h, include chip/mpio/chip.h that
will include the correct implementation to be able to use the same file
with both the openSIL stub and the actual openSIL implementation glue
code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iaae26a0dfe0ba96842e72582c06f1b0b3f29871c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82472
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch removes VPU enablement code that is no longer needed because
the VPU is already enabled by default in the baseboard devicetree.
BUG=b:332488817
TEST=Able to see VPU PCI device in lspci list after booting
google/screebo to OS
Change-Id: I94de92e970be1548068ed4e19309a95129f041ff
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82423
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch enables the Versatile Processing Unit (VPU) by default for
Rex/Ovis baseboard. VPU is a dedicated AI engine that is included in
the 14th generation "Meteor Lake" Core processors.
The VPU is designed to efficiently run AI models directly on the
system on chip (SoC). There is no power regression observed while
keeping the VPU default enabled to run AI models natively hence, this
patch enables the VPU by default.
BUG=b:332488817
TEST=Able to see VPU PCI device in lspci (0:11:0) list after booting
google/screebo to OS.
Change-Id: I8b3521c8ec613b002f971eaf9d346927fe8cd656
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82422
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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There is no direct way to override CPU default power_limits for
different SKUs.
This CL add structure variant_get_soc_power_limit_config() for
variants to define and configure the values of soc_power_limits_config
for current CPU SKU.
Variants can override these values i.e. pl1, pl2, psyspl2
in variant_devtree_update().
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST=FSP debug emerge-ovis coreboot intelfsp
check overrides setting
Change-Id: Ib60fa4e3fc502d0aeb0c94ad46ba5a55b4dd027c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82199
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematic to update the gpio table.
BUG=b:327549688
TEST= USE="-project_all project_bujia" emerge-brask coreboot
Change-Id: I3d01e3b9eaef72d9e143f5163ee49d8c8f455b5f
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82412
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Phoenix 2 has less PCIe lanes than Phoenix, so some of the lane end
numbers need to be adjusted to take that into account. When the Kconfig
options WLAN01 or WWAN01 are set, either the WLAN or the WWAN card uses
both PICe lanes that are available for those two devices, so the MPIO
descriptor information the devicetree needs to be updated accordingly
and the bridge to the PCIe port that doesn't have any lane left needs to
be disabled. Two other PCIe devices will be disabled when the
corresponding Kconfig options ENABLE_EVAL_CARD and DISABLE_DT_M2 have
the value that results in the device being disabled via some GPIO driven
by the EC. Since the code is specific to the openSIL case, only include
it in the build in the CONFIG_BOARD_AMD_BIRMAN_PHOENIX_OPENSIL case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I23c14cc03980ea1e39f7e5aec551b975c237e487
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82106
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
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Add the stub MPIO chips that contain the PCIe engine configuration for
the external PCIe interfaces to the devicetree. Birman's
port_descriptors_phoenix.c was used as a reference. The static
configuration in the devicetree assumes that the default WLAN0_WWAN0 is
selected; for the other cases we'll still need to fix up things
accordingly in the mutable devicetree. The WLAN01 and WWAN01 cases still
need to be handled in a follow-up patch. Since openSIL currently doesn't
use the info from the gpio_group struct element, but deasserts both PCIe
reset pins GPIO 26 and 27, the gpio_group isn't specified in the chip
configuration in the devicetree.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Icabe60322d46c1195284dd77ec39f9d143e3d2cb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81101
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
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Create the orisa variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:337178014
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_ORISA
Change-Id: I0cd8d763ffd8864b455a7f8909e95f6aee8bb23e
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Iccmax of VccIn_Aux is 25A with MBVR design.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST=Local build successfully and boot to OOBE normally.
Change-Id: I105dc9df53c624fd7fc697408a1097e023a3cd68
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81445
Reviewed-by: Simon Yang <simon1.yang@intel.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add stop pin control for G2 touchscreen refer to
G7500_Datasheet_Ver.1.2.
BUG=b:335803573
TEST=build and verified touchscreen works normally
Change-Id: I4f085c67c0cdb8b9ca3ff03993fda69cca6319ef
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82254
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copy the data.vbt from brox to greenbayupoc
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Change-Id: I1e8101519ab2ecbb4654c20485fbe83c90656e4d
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82108
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematics GREENBAY_0412.SCH update the gpio and
devicetree settings.
BUG=b:326413034
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot on DUT
Cq-Depend:chrome-internal:7218819
Change-Id: I59f25b8abb7dd8a2dff7ff567b231bddc9db8455
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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Currently the Focal touchpad does not work. Based on the Focal touchpad vendor, upadet the HID descriptor address from 0x20 to 0x01.
BUG=b:339756281
TEST=Build and check Focal touchpad can work.
Change-Id: I383ad907e6a23c34ab1bd0f6594a87564e21181d
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82270
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Support Memory of Micron MT53E512M32D1NP-046 WT:B and Hynix
H54G46CYRBX267 in mem_parts_used list, and generate SPD ID for these
parts.
DRAM Part Name ID to assign
MT53E512M32D1NP-046 WT:B 0 (0000)
H54G46CYRBX267 0 (0000)
BUG=b:337173071
BRANCH=firmware-dedede-13606.B
TEST=Run command "go run \
./util/spd_tools/src/part_id_gen/part_id_gen.go \
JSL lp4x src/mainboard/google/dedede/variants/pirika/memory/ \
src/mainboard/google/dedede/variants/pirika/memory/\
mem_parts_used.txt"
Change-Id: I9b1a2a622d0ca1298671b1da58beacc1b4244769
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82094
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add a nvram option for front audio panel type.
If it is set to AC97, reprogram front line out and microphone
pins to match vendor firmware under same configuration.
TEST=On asus/p8z77-m housed in an AOpen H340D case with an AC97
front audio panel, front panel line out port is now available as
headphone port in Fedora 39 with this patch applied and option
set correctly. And it works. Without the patch (or with this option
set to HD Audio), front audio ports are completely inoperable.
Change-Id: I39ccf066d87c5744a697599861719182768e0728
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79734
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
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Change-Id: I3aa669042908b92d7b270df077a352e197071780
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82354
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I2d73f7815e83e8bf0c6d0a402d32bc99c32c7d90
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82243
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I48b833a3727d4b7d7c50371dbe8f090983d80e36
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add data.vbt file for riven recovery image. Select INTEL_GMA_HAVE_VBT
for riven as it has a VBT file now.
The VBT file is copied from the nivviks reference board.
BUG=b:337169542
TEST=build pass
Change-Id: I499c1b3e61581483a1640375270f7707ebe8deeb
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82269
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Disable c1 state auto-demotion support for brox
BUG=None
BRANCH=None
TEST=Boot brox and verify in fsp debug logs
Change-Id: I18d40cd721d46fce4702cf1a943583cd41c03cf4
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82104
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Previous CL misspelling VR domain to IA not GT which cause
FVM Itrip(GT) not set correctly.
This CL corrects it to VR_DOMIAN_GT and confirm FVM Itrip(GT)
has set to 54.
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
check overrides setting
IccLimit[1] = 216 ( 1/4 A)
Change-Id: I99df053869aa11b7c82aa0b7f7ec0acf73467a76
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
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The chip drivers in the devicetree use the path where the corresponding
chip.h file resides both to include this chip.h file in the static.c
generated by util/sconfig from the devicetree and also for the names of
the chip config and chip ops struct. To be able to build a SoC using
either the MPIO chip driver from the openSIL stub or from the actual
openSIL glue code without needing different devicetree files for the
different cases, introduce a common MPIO chip.h file that then includes
the correct MPIO header file. The chip config and ops structures also
need to be renamed to take this change into account.
Thanks to Matt for pointing out how to make the path to the actual MPIO
chip.h file configurable via a Kconfig setting. This allows overriding
this path from site-local without the need to have any reference to
site-local in the upstream code.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Iead97d1727569ec0d23a2b9c4fd96daff4bebcf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82262
Reviewed-by: Varshit Pandya <pandyavarshit@gmail.com>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Also switch configs to use combo v1/v2 FSP
The reason for this change is to simplify configuration - instead of
multiple targets for VP4630 and VP4650 or VP4670, it's now possible to
have one target covering all VP46x0.
Change-Id: I1a6f6e873e4ec35b9777dc17c0495151348d1d88
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81963
Reviewed-by: Maciej Pijanowski <maciej.pijanowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Configure SODIMM settings for greenbayupoc. The SODIMM settings are
copied from mainboard/google/brya/variants/baseboard/brask/memory.c.
BUG=b:336955026, b:332230842
TEST=emerge-brox coreboot chromeos-bootimage, flash and boot to OS
using Hynix HMAG56EXNSA051N 4G and Micron MTA8AFT1G64HZ-3G2R1 8G SODIMM.
Change-Id: I1552cadfa81c48fe561947ded078bcca2e6bc6ad
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82085
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Add supported memory parts in mem_parts_used.txt, and generate
SPD id for these parts.
1. MT62F1G32D4DR-031 WT:B (Mircon)
2. MT62F512M32D2DR-031 WT:B (Mircon)
3. H9JCNNNBK3MLYR-N6E (Hynix)
4. K3LKLKL0EM-MGCN (Samsung)
5. K3LKBKB0BM-MGCP (Samsung)
6. H9JCNNNCP3MLYR-N6E (Hynix)
BUG=b:337169542
TEST=build pass
Change-Id: I0ff3b1e14fb8bb87d8fc9cbe0e177a5bcedef08c
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82255
Reviewed-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Currently EOP message is sent to CSE late in the boot flow. Instead send
it asynchronously to save ~10 ms in boot time.
BUG=b:337330958
TEST=Build Brox BIOS Image and boot to OS.
Change-Id: I229d16a5dcd072958db3f59a9c364bf7508b3047
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82236
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
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Update the pad reset config for WLAN Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.
BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S0ix & S3 and
wakeup successfully using Wake on WLAN.
268 | 2024-05-07 13:56:44-0700 | S0ix Enter
269 | 2024-05-07 13:57:07-0700 | S0ix Exit
270 | 2024-05-07 13:57:07-0700 | Wake Source | GPE # | 3
271 | 2024-05-07 13:59:01-0700 | ACPI Enter | S3
273 | 2024-05-07 13:59:26-0700 | Wake Source | PME - WIFI | 0
274 | 2024-05-07 13:59:26-0700 | ACPI Wake | S3
275 | 2024-05-07 13:59:26-0700 | Wake Source | GPE # | 3
Change-Id: Ie0d6e6c8fefdd081e252ea99d6e3c559a5330b0e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82234
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to Brox HW design, the PsysPmax is supposed to be 208W.
This patch changes PsysPmax setting from 21.5W to 208W.
Change-Id: I43f4b00a54dc0dfe6bd690492f9ef92698c9b903
Signed-off-by: Lawrence Chang <lawrence.chang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82185
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Shelley Chen <shchen@google.com>
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That's an ATX mainboard with a LGA1150 socket and four DDR3 DIMM slots.
Porting was done using autoport and then doing a bunch of manual edits.
This board has two socketed DIP-8 SPI flash chips and a physical switch
to choose which one should the system boot from. As long as one of them
contains a bootable firmware image, it is possible to reflash the other
chip using the internal programmer by flipping the switch after booting
to OS. Even if one somehow manages to flash unbootable firmware to both
chips, they are socketed: one can carefully remove them from the socket
and reflash them externally, which is a relatively safe procedure (when
compared to in-circuit flashing, especially if the board isn't designed
to safely be flashed in-circuit). In short, the board is hard to brick.
Haswell MRC.bin cannot be used because it lacks support for the Z97 PCH
found on this mainboard. Broadwell MRC.bin only works with Haswell CPUs
so far, as raminit fails on Broadwell CPUs for an unknown reason. Maybe
it's something about RcvEn, but it's unlikely it can easily be fixed.
Working:
- All four DIMM slots
- Broadwell MRC.bin for raminit purposes
- Serial port to emit spam
- POST code display
- S3 suspend/resume
- All rear USB 3.0 ports
- Internal USB 2.0 port
- Audio output (green jack)
- Integrated graphics (libgfxinit)
- HDMI
- VBT
- Intel GbE (I218-V PHY and PCH MAC)
- Realtek RTL8111E GbE
- At least one SATA port
- M2_1 slot (Gen3 x4, bifurcated from CPU)
- Flashing internally with flashrom
- SeaBIOS (current version) to boot Arch Linux
- NCT6791D Super I/O software-based fan control
tested using `sensors` and `pwmconfig`, all 6
fan tachometers and 5 PWM outputs work fine.
Untested for now (i.e. should work, will eventually test):
- DVI-I, DisplayPort
- EHCI debug
- Front USB 2.0 and 3.0 ports
- The other audio jacks (as well as SPDIF)
- The other PCIe and M.2 ports
- Non-Linux OSes
- PS/2 combo port (can only test with a keyboard)
Untestable (i.e. cannot test due to unavailable hardware):
- Thunderbolt AIC (Add-In Card) support
Not working:
- Broadwell CPUs, they require more magic to work (working on it).
- Booting from ASM1062 SATA ports with SeaBIOS. Other payloads were
not tested. It seems that the problem is with the controllers.
- Super I/O automatic fan control: not yet implemented in coreboot.
To control fans, use software fan control methods in the meantime.
- Acer B247Y board driving a FHD panel of a Samsung S24E650 monitor,
connected to the board's HDMI output says "Unsupported resolution"
after libgfxinit configured the iGPU outputs in linear framebuffer
mode. HDMI output works fine after Linux's i915 driver takes over.
Not sure if it's specific to the monitor: the HDMI cable is beaten
up, and it is hard to replace (need to relocate the logic board so
that the ports are accessible).
Change-Id: If1d22547725e59f435de36b973e1bf4f334269a9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68188
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Máté Kukri <kukri.mate@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The smbus subsystem ID was inadvertently reversed when added in commit
eb2897b113a0 ("mb/samsung/lumpy: override SMBus subsystem ID"), so
correct it.
TEST=build/boot Win10 on lumpy, verify touchpad driver functional.
Change-Id: I7520041ea113dff8f2abebfc71a1de6d0f9fc91f
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82227
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
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The smbus subsystem ID was inadvertently reversed when added in commit
6974bcd28e74 ("mb/google/parrot: override SMBus subsystem ID"), so
correct it.
TEST=build/boot Win10 on parrot, verify touchpad driver functional.
Change-Id: I93d4812e24a6fc7419887e364974fcfae2465ea3
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82226
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
|
|
The smbus subsystem ID was inadvertently reversed when added in commit
a6076cfcfdbe ("mb/google/butterfly: override SMBus subsystem ID"), so
correct it.
TEST=build/boot Win10 on butterfly, verify touchpad driver functional.
Change-Id: If4a0eae06bbe4dcba893a42797e371bbf9f899b9
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82225
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add a new Kingler follower 'Squirtle'.
BRANCH=corsola
BUG=b:333826091
TEST=emerge-corsola coreboot
Change-Id: I393738fc470ffc907f125647a46bf81c243708d7
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82117
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
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These boards are clones of LiPPERT boards, which are no longer in this
branch (they were AMD AGESA boards). So, drop the ADLINK placeholders.
Change-Id: Idfd77daf4a5b3d1e120ed22f9a48fa1bf884de9e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add data.vbt files for bujia supported by brask recovery images.
Select INTEL_GMA_HAVE_VBT for bujia which currently have a VBT file.
changes:
1. "integrated DisplayPort with HDMI/DVI compatible"
-> "Integrated HDMI/DVI".
2. turn the AUX off.
BUG=b:327549688
TEST=build/boot various brya variants
Change-Id: Id56461708250eaedd288ddbf788d686153df0b96
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81553
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Brox uses PDC<->PMC direct connection for USBC mux configuration. Select
SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION to enable it. This
patch also adds additional dependency on ENABLE_TCSS_USB_DETECTION to be
selected only when PDC<->PMC direct connection and CHROMEOS is not used.
BUG=b:332383540
TEST=USB3 plugged during G3, is detected after system boots from G3.
Cq-Depend: chromium:5484387
Cq-Depend: chrome-internal:7106592
Change-Id: I0f62943f87d8fb6eb494c0aca3ef08c33cd05ffd
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
For Mithrax and Felwinter, port C1 is on the left side and port C2 is on
the right side. Correct the values accordingly.
The board schematics was mirrored, so had to obtain an actual machine and physically check the correct ports.
BUG=b:321051330
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT
Change-Id: I977c3b4081987592a1d46529eb848a07a6c4cb47
Signed-off-by: Won Chung <wonchung@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81363
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
|
|
Within ec_acpi.c, USB-C ports are iterated to be matched with
corresponding mux. The iteration happens from 0 to the number of USB-C
ports. Given iteration index i, the port with PLD group_token of (i+1)
is matched with mux_conn[i].
Mithrax and Felwinter devicetree matches conn1 to mux_conn[1] and conn2
to mux_conn[0]. However, conn1 is for usbX_port2 which has group_token
of 1 and conn2 is for usbX_port3 which has group_token of 2. Thus,
follow the convention to add conn1 to mux_conn[0] and conn2 to
mux_conn[1].
Otherwise, the kernel subsystem linking between Type C connector and USB
mux will be swapped.
BUG=b:329657774 b:121287022 b:321051330 b:204230406
TEST=emerge-${BOARD} coreboot then check ACPI table on DUT.
TEST=Manually check that usb-role-switches are mapped to the correct
port.
Attach USB 3 A to C cable from development machine to left port of
DUT.
Attach nothing to right-hand port.
usbpd lines are workaround for devices without firmware patch to
connect superspeed lines.
ectool usbpd 0 none
ectool usbpd 0 usb
ectool usbpd 1 none
ectool usbpd 1 usb
echo host > /sys/class/typec/port0/usb-role-switch/role (should
succeed)
echo host > /sys/class/typec/port1/usb-role-switch/role (should fail
as no cable attached)
Change-Id: I349682a6fe3fe4848e4e86d9c446530a31b35875
Signed-off-by: Won Chung <wonchung@google.com>, Emilie Roberts <hadrosaur@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81354
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Emilie Roberts <hadrosaur@google.com>
|
|
soc/intel/xeon_sp/acpi/*.asl are actually used only by SKX and CPX
platforms and not forward compatible to later SoC generations.
Move them to soc/intel/xeon_sp/acpi/gen1/ for clean maintenance.
TEST=Build and boot on intel/archercity CRB
Change-Id: Ib060b123ab0fd761f00d9a0573e9b73d600ea9ef
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82033
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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|
Use the default position for ramtop and exclude it from the checksum.
Fixes invalid checksum after caching ramtop causing things like
disabling CSME to not work.
Fixes: 10d2af04e754 ("mb/system76: Add space for ramtop in CMOS layout")
Change-Id: If30df1e6f2735cf767856e42dfede3d17fe494eb
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81641
Reviewed-by: Jeremy Soller <jeremy@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Configure eMMC DLL tuning values for Sundance board Samsung sku.
BUG=b:337741162
TEST=Use the value to boot on Sundance successfully.
Change-Id: I5f1e03c06c9f8567e757fed999730dff2551f1e0
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82173
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.
Change-Id: I49f5fda5628b2ebc76cd8db20c8f7fe85c676c7a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.
Change-Id: I38f46949d36359826317252e8d3434ad1b24382d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82156
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Replace the PCI numbers with the reference names from the chipset
devicetree. Also, remove their comments since they are superfluous now.
Change-Id: Ib873854954e44b3ea370c2574da5db9792a446e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82155
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Clean up the devicetree by removing entries which are equal to the
chipset devicetree. The P2SB device is enabled but it's hidden by the
FSP. So just remove that as well since the chipset devicetree configures
it correctly.
Change-Id: I6186d295427bcd4a3b696f4df59d94a148ced011
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
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Fill GPIO table for pujjoga.
BUG=b:336469694
TEST=emerge-nissa coreboot
Change-Id: I3f633cf99f56d5f855015de805e16c1205c9bc99
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82044
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Update TDP PL1 value for the DTT optimization. The new value 18W is from
internal thermal/performance team.
- tdp_pl1_override: 15 -> 18 (W)
BUG=b:336684032
BRANCH=brya
TEST=built and verified MSR PL1 value.
Intel doc #614179 introduces how to check current PL values.
[Original MSR PL1/PL2/PL4 register values for xol]
cd /sys/class/powercap/intel-rapl/intel-rapl\:0/
grep . *power_limit*
constraint_0_power_limit_uw:15000000 <= MSR PL1 (15W)
constraint_1_power_limit_uw:55000000 <= MSR PL2 (55W)
constraint_2_power_limit_uw:114000000 <= MSR PL4 (114W)
After this patch:
constraint_0_power_limit_uw:18000000
constraint_1_power_limit_uw:55000000
constraint_2_power_limit_uw:114000000
Change-Id: I28c4f099e0169e8389f63083c03023dd8338589f
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82151
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update I2C5 timing parameter values to meet I2C bus spec.
- fall_time_ns: 400 -> 200
BUG=None
BRANCH=brya
TEST=built and measure I2C5 timing parameters
Before:
tLOW : 1.88 us (spec >= 1.30)
tHIGH: 0.57 us (spec >= 0.60)
fSCL : 399.80 KHz
After:
tLOW : 1.60 us (spec >= 1.30)
tHIGH: 0.97 us (spec >= 0.60)
fSCL : 392.1 KHz
Change-Id: I386b2765410fd10b8cd711f54478fb52428de5a3
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Create the riven variant of nissa reference board by copying the
template files to a new directory named for the variant.
The riven variant is a twinlake platform.
BUG=b:337169542
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_RIVEN
Change-Id: I1be2346d87c891cc0e5fbda094e1f6e0dd60df1b
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82132
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Iefe61d3ad51d355806716483248df5b1083b69bc
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82149
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add pujjoga supported memory parts in mem_parts_used.txt, generate
SPD id for this part.
1. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT
2. Hynix H9JCNNNBK3MLYR-N6E, H58G56BK7BX068
3. Micron MT62F1G32D2DS-026 WT:B
BUG=b:337990338
TEST=Use part_id_gen to generate related settings
Change-Id: I39d44fd278474a7375ad1d2d904d14b9463ba86d
Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82135
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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Based on schematic of 500E_GEN4S_ADL_N_MB_0418, generate overridetree.cb
settings for Pujjoga.
BUG=b:337611700
TEST=FW_NAME= pujjoga emerge-nissa coreboot chromeos-bootimage
Change-Id: I279f94044a22f25100a44b1abe2ef5fb6d0dd835
Signed-off-by: roger2.wang <roger2.wang@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82109
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
When in Package C3 or deeper the PSI settings are used to switch the
CPU VR into a low power state. It was found that the voltage regulator
on the Sandy-Bridge series has non-default PSI settings, compared to
Lenovo's Ivy-Bridge series. Apply the same PSI value for PSI2 and PSI3
as the vendor BIOS does to fix a hang when the package is idle.
Since neither the vendor BIOS is open-source, nor datasheet exists for
the used VR it's unclear why those PSI values must be used and how
they influence the regulator.
The X220 already has the correct PSI values configured and is now stable
for more than 24h in Package C7 state.
TEST: Not tested on the affected boards, only checked vendor firmware.
Change-Id: Idf8c3719f19f7bcdab30c543215c8abd2669cfd2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
Adjust setting is from power team.
Change from 172W to 180W
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
check overrides setting
Change-Id: Icc8b12adc9fb9f680b05131c8d41212865223ca9
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
Adjust setting is from power team.
Itrip(GT) FVM 54
Itrip(SA) FVM 27
BUG=b:320410462
BRANCH=firmware-rex-15709.B
TEST= FSP debug emerge-ovis coreboot intel-mtlfsp
check overrides setting
Change-Id: I6d6cf7cecaac650a7b1784833b4afb8dffb3db2c
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82176
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Correct .UserBd field to BOARD_TYPE_ULT_ULX from BOARD_TYPE_MOBILE. This
is from Intel's guidance for MRC to map the memory speed to proper POR
number.
BUG=b:332980211
BRANCH=brya
TEST=Built and compare the results of command 'dmidecode -t 17'
[Before]
(Same values in all of memory device handle)
Speed: 6400 MT/s
Configured Memory Speed: 6400 MT/s
[After]
(Same values in all of memory device handle)
Speed: 5200 MT/s
Configured Memory Speed: 5200 MT/s
Change-Id: Id16bcbc2d0cb4c2cf3008cf2ef1027ed98e93afb
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jamie Chen <jamie.chen@intel.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
The default MT8186 platform is to initialize USB3 port 1.
Use option bit 27 in fw_config to enable initialization of USB2 port 0
to support devices mounted on it.
BUG=b:335124437
TEST=boot to OS from USB-A
boot to OS from SD Card
BRANCH=corsola
Change-Id: I725b80593f5fc498a204bf47f943c36ccbd78134
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82089
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
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Change-Id: I0c4f74c7b27c8bb5599d68305adf369ddc6fcc70
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/67063
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
This patch moves the VPD based settings (FSP log level, et al)
from SoC codes to mainboard codes.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: Iefea72eec6e52f8d1ae2d10e1edbabdebf4dff91
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82090
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.
Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.
TEST=Build and boot on intel/archercity CRB with no significant log
differences
Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch sets different names for different mtlrvp
variants so they can be matched properly at runtime against
unique frids (i.e. firmware read-only identifiers).
BRANCH=firmware-rex-15709.B
TEST=Verified boot functionality on intel/mtlrvp
Change-Id: I5292a0ffcd7524c55cd7aef37c2f59432b2af06a
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82084
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Alderlake and Raptorlake SoCs support DDR4 and DDR5, which have a total
SPD size of 512 bytes. Set this as the default and remove the setting
from mainboard Kconfigs.
Change-Id: I8703ec25454a0cd55a3de70f73d2117285a833ae
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82115
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add GPP_F18 configuration in early_gpio_table.
Without this, DUT cannot get the proper state of this signal on early
phase. It allowed DUT to attempt to enter into dev mode when EC is in RW
currently, it causes the failure of autotest/firmware_DevMode.
BUG=b:337365524
TEST=built and run autotest firmware_DevMode
Change-Id: I2179bb10b431547bc35f332c74915a63495b779d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
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GPP_D14 is floating when ISH is not being used and wasting power. Add
pulldown to prevent this from happening.
BUG=b:336654954
BRANCH=None
TEST=emerge-brox coreboot chromeos-bootimage
make sure OS boots up
HW team validated that power usage is 20 mW lower
Change-Id: I4e19e98fa31022ece66a47402a2a4461b430ef70
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82096
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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The DVI connector on this board is DVI-D (digital only), not DVI-I.
Change-Id: I74c1257efb67cfdff2ae04a42c163dd320c850a4
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82112
Reviewed-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Update the pad reset config for Touchpad Interrupt from PLTRST to DEEP
so that it can still act as a wake source during S3 suspend.
BUG=b:336398012
TEST=Build Brox BIOS image and boot to OS. Suspend to S3 and wakeup
using Trackpad.
246 | 2024-04-25 16:55:18-0700 | ACPI Enter | S3
247 | 2024-04-25 16:55:34-0700 | ACPI Wake | S3
248 | 2024-04-25 16:55:34-0700 | Wake Source | GPE # | 67
249 | 2024-04-25 17:00:38-0700 | ACPI Enter | S3
250 | 2024-04-25 17:00:47-0700 | ACPI Wake | S3
251 | 2024-04-25 17:00:47-0700 | Wake Source | GPE # | 67
Also suspend to S0ix and wakeup using Trackpad.
Change-Id: If1a275e42c6c7ad743eedc9cd3320776008bfd62
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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The Fn key on Xol emits a scancode of 94 (0x5e).
BUG=b:327656989
TEST=Flash xol, boot to Linux kernel, and verify that KEY_FN is
generated when pressed using `evtest`.
Change-Id: I34ed93d9666504bfd4d439e166911e49f58e5ff5
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82069
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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This is a minimal framework that allows the build to compile.
Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ief4b5c75471a2ef5bedaaee9b4737510c2826b6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81978
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
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Remove duplicate config entry CHROMEOS_WIFI_SAR as it is
used at the baseboard.
BUG=None
TEST=emerge-rex coreboot
Change-Id: Iabf0e490103c2097f3f033036839b77b5a0bb1b3
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81226
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.
BUG=b:333494257
TEST=emerge-brox coreboot depthcharge sys-boot/chromeos-bootimage
Change-Id: Idb62e3f37e1480979ae529692455beb533434520
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82056
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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1.Enable CHROMEOS_WIFI_SAR flag to load a SAR table for Intel module.
2.Describe the FW_CONFIG probe for the settings on glassway.
- WIFI_SAR_0 for Intel Wi-Fi module AX211
BUG=336051631
BRANCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I9e43081c93ef17291c5d55cf262a0f4d1497447b
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81781
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Upload initial configuration for nova based on proto schematics.
Memory:
SAMSUNG 2G*4 K4U6E3S4AB-MGCL
HYNIX 2G*4 H9HCNNNBKMMLXR-NEE
BUG=b:328711879
TEST=FW_NAME=nova emerge-constitution coreboot chromeos-bootimage
Change-Id: Ic9ff3ed2fb3a7f0f100385d0a0444d38fcff5c51
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82043
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Add stop pin control for G2 touchscreen
BUG=b:335803573
TEST=build and verified Touchscreen work normally
Change-Id: I7e0bbc7722cdda6bcca0485009fcf8510b1f55e2
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81971
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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Add STA_ER88577 MIPI panel for Wugtrio.
Datasheet: 2081101BH8028073-50E_Pre Spec_240424.pdf
BUG=b:331870701
TEST=emerge-staryu coreboot chromeos-bootimage
BRANCH=corsola
Change-Id: I279d431d80ca0770540d88e213d4aeafe77038ce
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82055
Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are 4 different chassis types specified by vendor firmware, each
with a slightly different HWM configuration.
The chassis type to use is determined at runtime by reading a set of
4 PCH GPIOs: 70, 38, 17, and 1.
Additionally vendor firmware also provides an option to run the fans at
full speed. This is substituted with a coreboot nvram option in this
implementation.
This was tested to make fan control work on my OptiPlex 7020 SFF.
NOTE: This is superficially similar to the OptiPlex 9010's SCH5545
however the OptiPlex 9020's SCH5555 does not use externally
programmed EC firmware.
Change-Id: Ibdccd3fc7364e03e84ca606592928410624eed43
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81529
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add a new GPIO port cbj-sleeve for kernel driver to call. At the same
time, a new rt5645 driver is added to replace the generic driver to
parse gpio. After entering the system, it is pulled high by the kernel
to enable the MIC function.
BUG=None
TEST=MIC function is normal
Change-Id: I093be6a3e357aae389fcbe8291a9701c40b62e15
Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81774
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix custom_pld for USB2-C2 and USB3-C3 with same PLD group.
Update USB2-A4 PLD group token.
USB2/USB3 Type-C Port C2
"ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))"
USB2/USB3 Type-C Port C3
"ACPI_PLD_TYPE_C(BACK, LEFT, ACPI_PLD_GROUP(4, 1))"
BUG=b:320203629
BRANCH=firmware-rex-15709.B
TEST= emerge-ovis coreboot
Change-Id: Ieecf0f7dda671a421e4e4a4adbf83240fadd018d
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82036
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
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Set unused pin to NC internal PU 20K
BUG=b:325674908
BRANCH=firmware-rex-15709.B
TEST= emerge-ovis coreboot
Change-Id: I78eddaa41c14721eeb6ff33a4cb15382853e430b
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82035
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Allow to set board specific CPU voltage regulator settings.
The VR12 compatible voltage regulator for the CPU can be configured
by two MSRs. Currently a default value is applied, which mimics the
Intel reference code and is what the BWG suggest. However most board
vendors fill in the actual VR parameters to support OC or ULV board
variants.
When the mainboard design is too different from the Intel reference
design, not updating the VR settings might result in:
- unstable system behaviour
- limited turbo performance
- excessive battery drain
- no over-clocking capability
This patch adds support to set the board specific current limit for
Icc and Igfx.
It also allows to adjust PSI1, PSI2 and PSI3, which are powerstates
used by the VR, that consume less energy when the system is idle.
Test on Lenovo X220 with full CPU load after 1 minute, compared to
previous code with default settings:
- Limiting PP0 max current below Iccmax results in less CPU performance.
RAPL readings show that less power is drawn over time.
- Limiting PP0 max current to Iccmax results in equal CPU performance.
RAPL readings show that the same power is drawn over time.
- Setting the PP0 max current to a value >> Iccmax results in equal CPU
performance. RAPL readings show that the same power is drawn over
time.
- Updating the MSR at runtime has no effect.
Change-Id: I59edab47fc4fbe0240e1dd7d25647f7549b4def2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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If the ChromiumOS EC indicates that the device has an assistant key,
we should also add it to the generated linux,keymap binding. This
commit simply does so by examining the keyboard capabilities reported by
the EC.
BUG=b:333088656
TEST=With a device that has an assistant key, flash AP FW and verify
that the key is mapped to `KEY_ASSISTANT` in the Linux kernel using
`evtest`.
Change-Id: I217220e89bce88e3045a4fc3b124954696276442
Signed-off-by: Aseda Aboagye <aaboagye@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81996
Reviewed-by: Jonathon Hall <jonathon.hall@puri.sm>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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The DPTF parameters were defined by the thermal team.
Based on thermal table in 330817690#comment33.
Set 6w "tcc_offset" to "15" by fw_config.
BUG=b:330817690, b:290705146
BRUNCH=firmware-nissa-15217.B
TEST=emerge-nissa coreboot chromeos-bootimage
Change-Id: I19100d960919dc3087fd067c24659de467eea276
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81997
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Commit 00b40090aecf ("mb/google/brox: Move hda verb to variant dir")
introduces a variant-specific file for the HDA verb tables, which
commit 1bf0c3f1897c ("mb/google/brox: Create lotso variant") was missing
which caused the build to fail when both patches were submitted. To fix
the tree, add this file to the newly created lotso variant.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8a85115a204d9d9447a58da71eb65b1de963023d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82014
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Create the lotso variant of the brox reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:333494257
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brox -x -a
make sure the build includes GOOGLE_LOTSO
Change-Id: I5939127f9e6abe5b792c0627d9d67e739b27083b
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81817
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Others variant boards might use diff HDA Codec, so move hda verb
to brox variant dir.
BUG=b:314702466
BRANCH=None
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Device list:
cat /sys/bus/hdaudio/devices/ehdaudio0D0/chip_name
ALC256
cat /sys/bus/hdaudio/devices/ehdaudio0D0/vendor_name
Realtek
Headphone detection:
evtest 8
Event: time 1713404716.656768, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 1
Event: time 1713404716.656768, -------------- SYN_REPORT ------------
Event: time 1713404722.802661, type 5 (EV_SW), code 2 (SW_HEADPHONE_INSERT), value 0
Event: time 1713404722.802661, -------------- SYN_REPORT ------------
Change-Id: Id987c248c37dc8bdc63be7a2513fa8997b5ddc33
Signed-off-by: tongjian <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81945
Reviewed-by: Poornima Tom <poornima.tom@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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[ERROR] PNP: 002e.b 70 irq size: 0x0000000001 not assigned in devicetree
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I2231afd67031c963045b6e7930d239368c723aa5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75142
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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One can argue whether or not this is desirable, but disabling this means
you cannot use power from the USB ports when the board shuts down, which
is better controlled from an option, but at the very least disabled so
as to replicate default vendor firmware behaviour.
Disable deep sleep like it is disabled on all other variants.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: I660f2efebf197df055ee7b9c349e4c2b64bda6cf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75139
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Copied this bit from asus/p8z77-m_pro, without it a GRUB2 payload will
get stuck in an endless loop showing
Unknown key 0xff detected
whenever there is an USB device (such as a keyboard) connected.
In this mode GRUB2 is so busy showing this message repeatedly that no
other keypress ever gets handled, and thus no other remedy is possible
than a reset via mb pins and unplugging the USB device.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Iebd433e2762a69241257e1b4f859319536a8d8f5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75138
Reviewed-by: Keith Hui <buurin@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add STORAGE_UNKNOWN, STORAGE_UFS, STORAGE_NVME for storage fw_config
field to prevent depthcharge build break.
BUG=b:333325006
TEST=emerge-brox coreboot depthcharge with no errors
Change-Id: I0e220787d6ac73ec8fa2469ed958981d0801920e
Signed-off-by: Eren Peng <peng.eren@inventec.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ivan Chen <yulunchen@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
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These machines come with a TPM1.2 device by default. It is somewhat
obsolete these days, but there is no harm in enabling it.
Change-Id: Iec05321862aed58695c256b00494e5953219786d
Signed-off-by: Mate Kukri <kukri.mate@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81827
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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WDT1 is currently enabled but gives these errors:
[ERROR] ERROR: Resource didn't fit!!!
PNP: 002e.8 60 * size: 0x8 limit: fff io
[ERROR] PNP: 002e.8 60 io size: 0x0000000008 not assigned in devicetree
Therefore, just disable it, like it is disabled on all other variants.
Signed-off-by: Fabian Groffen <grobian@gentoo.org>
Change-Id: Ie33c219eae60f55d272b261480283a02c2d502e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/75144
Reviewed-by: Keith Hui <buurin@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set GPIO27 of PCH to blink before going to sleep. This blinks the
power LED. Revert after waking up.
Tested on p8z77-m. Power LED blinks in suspend.
Change-Id: Ie1b40ae17fa2ef397585b86ac82730099b611dda
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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According to a boardview, GPIO27 is connected to the front
panel power LED, and should be output.
It will be made to blink before entering S3 suspend in a follow-up.
Change-Id: I7e47f63999e8c0bfbd37e3273d33c00bc035bcbb
Signed-off-by: Keith Hui <buurin@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81921
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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Support Memory for Hynix H58G66AK6BX070 and Samsung
K3KL9L90CM-MGCT in mem_parts_used list, and generate SPD ID for these
parts.
DRAM Part Name ID to assign
H58G66AK6BX070 4 (0100)
K3KL9L90CM-MGCT 5 (0101)
BUG=b:335341310
BRANCH=firmware-nissa-15217.B
TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\
part_id_gen.go ADL lp5 \
src/mainboard/google/brya/variants/glassway/memory/ \
src/mainboard/google/brya/variants/glassway/memory/\
mem_parts_used.txt"
Change-Id: Ic07ec36a8015ce6433196a93e894b818a515b954
Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81955
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com>
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Enable SaGv support for brox
BUG=None
BRANCH=None
TEST=Boot brox with SAGv enabled and verify in fsp debug logs
Change-Id: I80c44e7df1d75732c6982b27e44ecd6060b1b3f1
Signed-off-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81556
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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