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2019-08-27smsc/superio/sio1007: Fix header nameKyösti Mälkki
The file chip.h has a special purpose for defining the configuration structure used in static devicetree. Change-Id: If0289c29ca72768009c1b7166311bc4c3cee4171 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2019-08-26emulation/qemu-x86: Rename memory.c to memmap.cKyösti Mälkki
Change-Id: I311423cb565485236f89bd6043155aaf6296a031 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34974 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26emulation/qemu-x86: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. Change-Id: If0729721f0165187946107eb98e8bc754f28e517 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34973 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26soc/intel: Use common romstage codeKyösti Mälkki
This provides stack guards with checking and common entry into postcar. The code in cpu/intel/car/romstage.c is candidate for becoming architectural so function prototype is moved to <arch/romstage.h>. Change-Id: I4c5a9789e7cf3f7f49a4a33e21dac894320a9639 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34893 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26Split MAYBE_STATIC to _BSS and _NONZERO variantsKyösti Mälkki
These are required to cover the absensce of .data and .bss sections in some programs, most notably ARCH_X86 in execute-in-place with cache-as-ram. Change-Id: I80485ebac94b88c5864a949b17ad1dccdfda6a40 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-26mb/scaleway/tagada: Remove use of car_get_var()Kyösti Mälkki
Board has CAR_GLOBAL_MIGRATION=n and can use .bss for a variable that was previously declared with CAR_GLOBAL. Test for !defined(__PRE_RAM__) can be transformed into ENV_RAMSTAGE here as the warnings about invalid bmcinfo structure do not need to be repeated in SMM console, which is generally disabled anyways due to DEBUG_SMI=n. Change-Id: I6b63213484107fa0eeb0d952d8766916b44a3c4e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-26google/kukui: Enable CHROMEOS_USE_EC_WATCHDOG_FLAGYu-Ping Wu
Kukui AP doesn't remember if the last AP reset was due to AP watchdog. We need to enable CHROMEOS_USE_EC_WATCHDOG_FLAG so that it will query the reset reason from EC. BUG=b:109900671,b:118654976 BRANCH=none TEST=1. run 'mosys eventlog clear; stop daisydog; echo > /dev/watchdog' 2. wait for watchdog reset 3. check 'mosys eventlog list | grep watchdog' Change-Id: I053cc7664bbaf0d3fcae26ba9481a0ad700dca90 Signed-off-by: You-Cheng Syu <youcheng@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31844 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-26mb/facebook/fbg1701/data.vbt: Correct EFP1 configurationFrans Hendriks
EFP1 is configured as 'DisplayPort with HDMI/DVI compatibility'. Using this setting 4K monitor is configured into lower resolution. Change EFP1 setting to 'HDMI/DVI' The next addtional small changes are made in VBT: UEFI GOP Driver Child Device 2 = LFP Child Device 3 = EFP1/LFP LFP Panel configuration Y-Res of Panel #10 = 1920 BUG=N/A TEST=LCD and HDMI on Facebook FBG1701 Change-Id: Idc694b15ff94b83291a8c8252e269b7e6d96f87b Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35043 Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-26google/link: fix detection of dimm on channel 1Matt DeVillier
Changes to the sandybridge memory init code (both MRC and native) now require SPD data on all populated channels in order for dimms to be detected properly, so copy spd_data[0] to spd_data[2], as LINK always has 2 channels of memory down. Test: boot google/link, observe onboard RAM correctly detected on both channels Change-Id: Id01d57d5e5f928dfc1cd9063ab1625c440ef2bbe Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-26mainboard/emulation/qemu-aarch64: Update DRAM_SIZE_MBAsami Doi
DRAM_SIZE_MB should be the maximum size (255GiB / -m 261120M) that’s possible with QEMU on AArch64 virt because it tries to search the DRAM_SIZE_MB range to find the true memory size. Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Change-Id: Id479c0b18d1e1adceecdcca13e36119b95617e6d Reviewed-on: https://review.coreboot.org/c/coreboot/+/35024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2019-08-24mb/google/octopus: Re-assign sku number for vortininjaWisley Chen
Re-assign sku number for vortininja. BuG=b:138177049 BRANCH=octopus TEST=emerge-octopus coreboot Change-Id: I3166a635151fcc7b2e3c0122fa05925cfa5df7d0 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-23mb/google/hatch/var/kindred:: Add enable signal for touch screenPhilip Chen
In the next board version, we will use GPP_D9 as enable control for touch screen. BUG=b:137133946 TEST=build Change-Id: I213d0878bfca1ce4059ec0393f59d8e79e1b274c Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/hatch/variants/kindred: Remove unused devicesPhilip Chen
sx9310 and FPMCU are not used in Kindred. BUG=none TEST=build Change-Id: Ied09d4bdb899d991131a75d7c848ff8637022f53 Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-23mb/google/rambi: update GPIO, RAM config for clapperMatt DeVillier
When upstreamed, GPIO and RAM config for clapper variant was taken from an older branch, leading some boards to fail to boot. Update based on chromium branch firmware-clapper-5216.199.B, commit 362d845 [baytrail: implement baytrail technical advisory 556192] Change-Id: I099ee2cd0833e4b9ab093663c4549c79ec044127 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-23Revert "mb/google/octopus: Disable WLAN prior the entry of S5"Kane Chen
This reverts commit 38dbd6892080c93ccd24fbfa46ed5d9bdb7d9e99. Reason for revert: ODM helped to verify w/ BT runtime suspend disabled + revert this change And issue is gone. so I revert this change see the test result in https://partnerissuetracker.corp.google.com/issues/136039607#comment32 Change-Id: I248e9613cc39247a2bb88270c234c7d36d0ff60f Signed-off-by: Kane Chen <kane.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-23mb/google/drallion: Add two variants - arcada_cml & sarien_cmlThejaswani Putta
These variants are to support the sarien and arcada boards with CML SOC, the drallion variant will be used to support the upcoming drallion board. Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I766bdccb6f8b6924d6ae1abbe57035f4ff1f6f17 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34887 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2019-08-23mb/google/kukui: Add panel for KodamaPeichao Wang
Declare the following panel for Kodama: - AUO B101UAN08.3 BUG=b:139699622 TEST=builds Kodama image and working properly Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I3f688ffd0ece6afac08d353ab5a6cf1cf876b32f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35001 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-22mb/google/kukui: Add flapjack panelsHung-Te Lin
Add panels supported by flapjack. Change-Id: I547bf6f26bdbfed52a00c8cfb268d4e7c17ed889 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-22arch/x86: Add <arch/romstage.h>Kyösti Mälkki
Start with moving all postcar_frame related function declarations here from <arch/cpu.h>. Change-Id: I9aeef07f9009e44cc08927c85fe1862edf5c70dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21mb/google/kukui: Move panel description to CBFS filesHung-Te Lin
The panel description may be pretty large (for example, 1.3k for BOE TV101) due to init commands and we should only load the right config when display is needed. BUG=None TEST=make -j; boots and see display on Krane. Change-Id: I2560a11ecf7badfd0605ab189d57ec9456850f75 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-21mediatek/mt8183: add scp voltage initializationHsin-Hsiung Wang
Add scp voltage initialization. BUG=b:135985700 BRANCH=none Test=Boots correctly on Kukui and scp can boot up normally Change-Id: I5afb60af3c14490e20f28f1c089cfca42ddf7fcf Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34205 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2019-08-21arch/x86: Rename some mainboard_romstage_entry()Kyösti Mälkki
These platforms use different signature for this function, so declare them with different name to make room in global namespace. Change-Id: I77be9099bf20e00ae6770e9ffe12301eda028819 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34909 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-21AMD fam10: Remove HAVE_ACPI_RESUME supportKyösti Mälkki
Change-Id: I62bbba8cfe515b3cae413582ff8d062a20e6741b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/15474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-21mb/google/kohaku: Correct DPTF temp sensor IDsSeunghwan Kim
This change corrects DPTF temperature sensor IDs BUG=none BRANCH=none TEST=none Change-Id: I25c76b0e938b2568da1833a4a5685ed36c00275e Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34985 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21mb/google/octopus/variants/bloog: Add G2Touch touchscreen supportTony Huang
Add G2Touch touchscreen support for blooglet. BUG=b:139725457 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen by evtest. Change-Id: I6ebcc60f58857d8b28446932787742c2740fadd8 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35013 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-21mb/google/kahlee/treeya: Update Raydium TS device ACPI nodesChris Wang
Update I2C irq to EDGE trigger for Raydium TS. BUG=b:135551210 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ic0a00a31eefa756b6e4ee9aac8d25c1be5ac9195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-21mb/google/kahlee/treeya: remove keyboard backlight supportChris Wang
Treeya doesn't support the keyboard backlight. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I02dfc77d3cb7ac00b3f10d577d92775db99c1bdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/34903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Use GPIO_10 for EC_SYNC_IRQChris Wang
Use AGPIO 10 as the EC sync interrupt for MKBP events for sensor data. Reference to Aleena project. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ie0b719ebce90710bca2109b7ff255e19329f9cac Reviewed-on: https://review.coreboot.org/c/coreboot/+/34902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Add EC_ENABLE_TBMC_DEVICEChris Wang
Enable ACPI TBMC notification on tablet mode change to support convertible treeya devices. BUG=b:135551210 BRANCH=grunt TEST=emerge-grunt coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Id0618c8df66267b88008dc5057892de6b530629f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org>
2019-08-21mb/google/kahlee/treeya: Enable Synaptics touchpad andPeichao Wang
Synaptics touchscreen BUG=b:139699619 TEST=emerge-grunt coreboot chromeos-bootimage flash bios image to DUT and make sure the touchpad and touchscreen can work Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I002badd49e678e1c32c802352923ca51efb45cef Reviewed-on: https://review.coreboot.org/c/coreboot/+/35000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-20mb/ocp/monolake: Add IPMI CMOS clear supportJohnny Lin
coreboot would clear CMOS by request via IPMI command, for example BMC can issue "bios-util server --boot_order enable --clear_CMOS" to set the request and reboot the system, then coreboot would clear CMOS on the next boot. Tested on Mono Lake Change-Id: I21d44557896680cfac3c3b6d83e07b755b242cad Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34857 Reviewed-by: Johnny Lin Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb/google/hatch: Skip SD card controller WP pin configuration from FSPAamir Bohra
BUG=b:123907904 TEST=SD WP GPIO PAD retains coreboot configuration and FSP ScsSdCardWpPinEnabled UPD is set to 0. Change-Id: I30367cda09cc8c88abb649f70b4587889083f9af Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34901 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb,autoport: Fix GCC 9 Port_List build errorJacob Garber
Port_List is an array of 8 elements, and GCC 9 is warning that there are no 'others' when all 8 elements are explicitly initialized, which is causing the build to fail. Remove the 'others => Disabled' clause to silence this. Change-Id: Id082e7a76641438f3fb4c4d976dbd254a7053473 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34918 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb/amd/serengeti_cheetah_fam10: Add null pointer checkJacob Garber
Print an error message and die if the PCI device cannot be found. Change-Id: I10c58502658ebf12d1a8fe826ee7d47a618fd1c8 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1403000 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20mb/{asrock,intel,purism}: Copy channel arrays separatelyJacob Garber
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of the first array and overwrite both of them at once. However, FSP_M_CONFIG is not declared with the packed attribute, so this is not guaranteed to work and is undefined behaviour to boot. It is cleaner and less tricky to copy them independently. The same is true for DqsMapCpu2DramCh0 and DqsMapCpu2DramCh1, so we change those as well. Change-Id: Ic6bb2bd5773af24329575926dbc70e0211f29051 Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 136538{8,9}, 140134{1,4} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33135 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-20mb/google/{eve,glados}: Copy channel arrays separatelyJacob Garber
DqByteMapCh0 and DqByteMapCh1 are declared adjacently in the FSP_M_CONFIG struct, so it is tempting to begin memcpy at the address of the first array and overwrite both of them at once. However, FSP_M_CONFIG is not declared with the packed attribute, so this is not guaranteed to work and is undefined behaviour to boot. It is cleaner and less tricky to copy them independently. The same is true for DqsMapCpu2DramCh0 and DqsMapCpu2DramCh1, so we change those as well. Change-Id: If394f14c4a39d6787ae31868241229646c26be7a Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1365730, 14013{38,39,40,42,43} Reviewed-on: https://review.coreboot.org/c/coreboot/+/33066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2019-08-20mb/asus/kfsn4-dre: Return early if CK804 not foundJacob Garber
It probably doesn't make sense to continue if the CK804 isn't found, and doing so would perform uninitialized reads of the busn and io_base arrays anyway, so let's return early. Change-Id: I13c663314496caf51a57da7f27f9ea24e3d7fcbd Signed-off-by: Jacob Garber <jgarber1@ualberta.ca> Found-by: Coverity CID 1370586 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2019-08-20AGESA,binaryPI: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id878fd33ec3d2de640d9a488058a805be3ccd223 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-20mb/google/kohaku: Use level trigger for touchscreen interruptSeunghwan Kim
Level trigger is recommended setting for touchscreen interrupt of kohaku, so we would change it as the recommedation. BUG=b:139179200 BRANCH=none TEST=Verified touchscreen works on kohaku Change-Id: Ibbcdbe3ab555d014048f66ff527e539c5b566187 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-20google/stout: Use MAYBE_STATICKyösti Mälkki
Change-Id: I11027acb11a4656536384134d0caebd14b63770c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-20google/butterfly: Replace use of __PRE_RAM__Kyösti Mälkki
Change-Id: Iae944b589d587b30826e935feae029aa8d07d5d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2019-08-20arch/non-x86: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: Id8918f40572497b068509b5d5a490de0435ad50b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-19google/rambi: Replace __PRE_RAM__ with ENV_ROMSTAGEKyösti Mälkki
Change-Id: I9d86f8475221b52ccdb45cdeaf538e85ab7a17c0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-19mainboard/google: Remove use of __PRE_RAM__Kyösti Mälkki
Change-Id: I2ebeb393e4a5a4bfac8a37a877d067aca484ca2e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34927 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-18cpu/intel: Enter romstage without BISTKyösti Mälkki
When entry to romstage is via cpu/intel/car/romstage.c BIST has not been passed down the path for sometime. Change-Id: I345975c53014902269cee21fc393331d33a84dce Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-18mainboards: Remove floating __PRE_RAM__ commentsKyösti Mälkki
Change-Id: I110e54175a81b6a651213e0f18ddc1e3e71160cf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2019-08-16mediatek/mt8183: Add SAMSUNG 4GB LPDDR4X discrete DDR supportHuayang Duan
BUG=b:80501386 BRANCH=none TEST=Boots correctly and stress test passes on Kukui. Change-Id: I27164f0909edb9d9398835e292fb845f0e342391 Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34532 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Huayang Duan <huayang.duan@mediatek.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-16mb/google/hatch: Create Akemi variantPeichao Wang
This is based on the hatch variant BUG=b:138879565 TEST=FW_NAME="akemi" emerge-hatch coreboot depthcharge intel-cmlfsp chromeos-bootimage look for image-akemi.*.bin generated under the /build/hatch/firmware/ Change-Id: I1a868839e2c598f8052d37c99713bc58b21e887c Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-15mb/google/hatch/var/kindred: Configure GPIOs for eMMC SKUsDavid Wu
Configure GPIOs for eMMC SKUs BUG=b:132918661 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Change-Id: I9f678a40555dbc841487811cc1f680b211a51a89 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34795 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15mb/google/hatch/var/kindred: Disable SATA controller for eMMC SKUsDavid Wu
Disable SATA controller and SATA port 1 for eMMC SKUs BUG=b:132918661 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Change-Id: I6d95ff94b079a564f74c19739370101899843f00 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34789 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/hatch/var/kindred: Configure GPIOs for SSD SKUsDavid Wu
Configure GPIOs for SSD SKUs BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24 Change-Id: Ief48a2fd2fa078aa5d89aec01f99af75510334b2 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34851 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/hatch/var/kindred: Disable eMMC for new SKU ID 23 and 24David Wu
1. Disable eMMC controller for new SKU ID 23 and 24 2. Disable HS400 mode BUG=b:132918661 TEST=Verify eMMC is disabled when SKU ID = 1/3/23/24 Change-Id: I0d893f0f7339e7b1a1e6b56d1598c0a361c8d604 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34788 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-15cpu/x86/smm: Promote smm_memory_map()Kyösti Mälkki
Change-Id: I909e9b5fead317928d3513a677cfab25e3c42f64 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34792 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mainboard/google: Fix indirect includesKyösti Mälkki
Change-Id: Ie79702efab519b16cff45ccad61b95e7d8c2fbac Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34854 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/kukui: Report panel manufacturer nameHung-Te Lin
The src/lib/edid now supports reporting manufacturer name so we should define that in MIPI panels and print out in initialization. BUG=None TEST=emerge-kukui coreboot; boots properly Change-Id: If844da84ecca31307127b14c66bbe17c408699f3 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15soc/mediatek: Change DSI init commands to take flexible length arrayHung-Te Lin
The fixed size of init command in lcm_init_table is wasting lots of space and we should change to packed array since the command buffer already provides length information. With this change, BOE panel init commands have been reduced from 4848 bytes to 1309 bytes. BUG=b:80501386,b:117254947 TEST=emerge-kukui coreboot chromeos-bootimage; Boots properly Change-Id: I359dde8e6f2e1c0983f4677193bb47a7ae497ca6 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34778 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/kukui: Support eDP panels via PS8640Hung-Te Lin
Some Kukui variants may have eDP panels connected via a PS8640 MIPI bridge which we may retrieve EDID dynamically. BUG=b:b:137517228 TEST=emerge-jacuzzi coreboot chromeos-bootimage; boots and see display. Change-Id: I85aac5255e6a3e6019299670486214ecffbf9801 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34516 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/kukui: Add panel for KodamaPeichao Wang
Declare the following panel for Kodama: - BOE TV101WUM-N53 BUG=b:138156559 TEST=builds Kodama image and working properly Change-Id: I129cb6bf084b76da3ad33b7a19e38e884442b1aa Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34505 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-15mb/google/kukui: Add panel for KukuiHung-Te Lin
Support Kukui rev 2 panel (via SSD2858). BUG=b:129299873 BRANCH=none TEST=Build as Kukui and boots on Rev 2 unit. Change-Id: Icc16c4297eb3c6b6a4770a36661a2e3cab418048 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15mb/google/kukui: Add panels for KraneJitao Shi
Declare the following panels for Krane: - BOE TV101WUM-NL6 - AUO KD101N80-45NA The edid info and init command are from: https://crrev.com/c/1565758 BUG=b:129299873 BRANCH=none TEST=Builds krane image and boots properly. Change-Id: Id19c6c2b4c1c728c39aa26301adf7d6fb5046403 Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15mb/google/kukui: Initialize displayHung-Te Lin
Many devices in Kukui family will be using MIPI panels, which needs hard-coded EDID and initialization commands. And because each device may have its own layout and ID, there should be very few devices sharing same panel configuration. As a result, we want to put panel data (EDID and init commands) into board-specific modules, provided by `get_panel_description` function. The panel numeric ID is identified by ADC 2, and is currently available as higher 4 bits of sku_id(). After ID is retrieved, the get_panel_description should return a reference to the EDID and table of init commands. The default implementation is to simply return NULL, and the data for real devices should be provided by panel_*.c in further commits. BUG=b:80501386,b:117254947 BRANCH=none TEST=boot correctly on Kukui Change-Id: I19213aee1ac0f69f42e73be9e5ab72394f412a01 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/32511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-15soc/mediatek: dsi: Support sending MIPI init commandsHung-Te Lin
For systems with real MIPI panels (8173/oak was using PS8640 eDP bridge), we have to send DCS commands to initialize panel. BUG=b:80501386,b:117254947 TEST=make -j # board = oak and boots Change-Id: Ie7c824873465ac82a95bcb0ed67b8b9866987008 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34773 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-13mb/google/hatch/var/kohaku: Change Atmel touchscreen HID to PRP0001Furquan Shaikh
This change updates the Atmel touchscreen ACPI node to use PRP0001 as _HID to allow OF-style compatible string matching for enumeration. Reason for this change: Atmel touchscreen driver in Linux kernel looks for "compatible" property to decide if it is okay to attach to the device. This check seems to be a protection against old firmware in the field that do not have the right properties. BUG=b:129162037 TEST=Verified that touchscreen works on Kohaku. Change-Id: I6d027f8533494e903efd1da8da1fa273a97fe9b2 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-13mb/google/hatch: Kohaku: Enable DMIC1 in device treeMac Chiang
The default is DMIC0 on, but Kohaku is also using DMIC1 BUG=b:133282247 BRANCH=None TEST=arecord -D hw:0,1 -r 48000 -c 4 -f s32 4dmic.wav make sure 4 channels recording work Signed-off-by: Mac Chiang <mac.chiang@intel.com> Change-Id: I2dd573e1634516bcf9876bedb92b7d9148bb0e6a Reviewed-on: https://review.coreboot.org/c/coreboot/+/34692 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-12soc/sifive/fu540: add code for spi and map flash to memory spacesXiang Wang
SiFive's ZSBL has initialized flash, but only 16MB of space is available. 1. add code for spi 2. add code to map flash to memory spaces Change-Id: I106688c65ac7dd70be7479dc4691797b700682d9 Signed-off-by: Xiang Wang <merle@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2019-08-11arch/x86: Flip option NO_CAR_GLOBAL_MIGRATIONKyösti Mälkki
It is easier to track CAR_GLOBAL_MIGRATION which is the approach to be deprecated with the next release. This change enforces new policy; POSTCAR_STAGE=y is not allowed together with CAR_GLOBAL_MIGRATION=y. Change-Id: I0dbad6a14e68bf566ac0f151dc8ea259e5ae2250 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2019-08-11arch/x86: Enable POSTCAR_CONSOLE by defaultKyösti Mälkki
Almost all platforms force it on. Make it enabled by default but under user control to optionally disable it. Change-Id: I6b0f19c8bfd6ffed93023d57a1d28ca6acc06835 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34803 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Martin Roth <martinroth@google.com>
2019-08-11kohaku: add TEMP_SENSOR_3 and TEMP_SENSOR_4 to DPTFPaul Fagerburg
The Kohaku V24 schematic adds two additional temperature sensors to the EC. Add these to the DPTF tables. Cq-Depend: chromium:1742914 BRANCH=none BUG=b:138578073 TEST=Rebuild EC and BIOS, look for new thermal sensors in kernel. 1. Build EC ``cd ~/trunk/src/platform/ec`` ``make -j BOARD=kohaku`` 2. Program EC ``./util/flash_ec --board=kohaku`` 3. Reboot device 4. Rebuild BIOS ``cd ~/trunk/src/third_party/coreboot`` ``FEATURES="noclean" FW_NAME=kohaku emerge-hatch chromeos-ec depthcharge vboot_reference libpayload coreboot-private-files intel-cmlfsp coreboot-private-files-hatch coreboot chromeos-bootimage`` 5. Use flashrom to program the BIOS 6. Reboot device 7. Log into the root console (ctrl-alt-F2 or servo) 8. Example thermal sensor information ``grep . /sys/class/thermal/t*/type`` Look for "TSR0" through "TSR3" in the output. Change-Id: Ib8f38beae6392855927ce1249c229d7a114c72b2 Signed-off-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34765 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-11mb/google/hatch: Fix Kohaku pen GPIO configurationTim Wawrzynczak
Oops, I missed this in the last CL. The pin needs to be configured as owned by GPIO, so that the kernel driver can bind it with an IRQ. BUG=b:139165490 TEST=Ensure kernel nastygram about inability to claim the IRQ is gone Change-Id: I26c08d75d8b4e3b834db6e90868239899605fa5b Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-10mb/facebook/fbg1701: Select SOC_INTEL_COMMON_BLOCK_HDA_VERBFrans Hendriks
HDA is not configured. Enable SOC_INTEL_COMMON_BLOCK_HDA_VERB to configure the HDA using cim_verb_data[] table. BUG=N/A TEST=Boot Embedded Linux 4.20 on Facebook FBG-1701 Change-Id: I9bb542091ad200833894431f5b840f48dd388173 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34655 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-10mb/google/octopus: Add G2touch touchscreen supportWisley Chen
Add G2touch touchscreen support for Dorp/Vortinija/Vorticon. BUG=b:139110164 BRANCH=octopus TEST=emerge-octopus coreboot chromeos-bootimage, and check touchscreen by evtest. Change-Id: Ia42757c881ec78b1c676ac984507732717af94a9 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-09google/drallion: Fix build issue due to recent mergeKyösti Mälkki
One case slipped past the review and rebase of 733c28fa42 (soc/intel/{cnl,icl}: Use new power-failure-state API). Change-Id: Id01df30d10e202e9672bf5be799a84f4f202fe24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34812 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/intel/{cnl,icl}: Use new power-failure-state APINico Huber
pmc_soc_restore_power_failure() is only called from SMM, so add `pmc.c` to the `smm` class. Once all platforms moved to the new API, it can be implemented in a central place, avoiding the weak- function trap. Change-Id: Ib13eac00002232d4377f683ad92b04a0907529f3 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34726 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09soc/mediatek/mt8173: Remove dual DSI modeHung-Te Lin
The 'dual DSI mode' was never used by any real boards running coreboot and is introducing lots of complexity when it comes to refactoring. In order to create a common display stack for MTK SOCs, we want to first drop dual DSI mode so 8173 and 8183 DSI/DDP implementation will be more similar to each other. BUG=b:80501386,b:117254947 TEST=emerge-oak coreboot Change-Id: I357c30cc687803ca8045d0b055dec2e22eef4291 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34693 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-09mb/google/sarien/variants/sarien: Set PCH Thermal Trip point to 77 degree CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Sarien. Change-Id: Ibc336be0523ff4e65a818474907faf20fc417ff4 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09mb/google/sarien/variants/arcada: Set PCH Thermal Trip point to 77 degree CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal shutdown when S0ix is enabled. BUG=None BRANCH=None TEST=Verified Thermal Device(B0: D18: F0) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Arcada. Change-Id: I1915b974b10638b0f6ab97c6fb9b7a58d2cabc59 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-09mb/google/hatch: Refactor override_early_gpio_tableTim Wawrzynczak
There was the potential for misuse of the override early GPIO table, because if the override early GPIO table did not have a corresponding entry in the base table, it would not get overridden, and there was no way to know except manual inspection (this has already happened here), so now all hatch mainboards are required to explicitly list out all of their required early GPIOs. TEST=booted several hatch boards, verified that they can communicate with TPM and successfully train memory Change-Id: I0552b08a284fd6fb41a09fef431a0d006b0cf0bd Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-08mainboard/emulation/qemu-aarch64: Add new board for ARMv8Asami Doi
This CL adds a new board, QEMU/AArch64, for ARMv8. The machine supported is virt which is a QEMU 2.8 ARM virtual machine. The default CPU of qemu-system-aarch64 is Cortex-a15, so you need to specify a 64-bit cpu via a flag. To execute: $ qemu-system-aarch64 -M virt,secure=on,virtualization=on \ -cpu cortex-a53 -bios build/coreboot.rom -m 8192M -nographic Change-Id: Id7c0831b1ecf08785b4ec8139d809bad9b3e1eec Signed-off-by: Asami Doi <d0iasm.pub@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2019-08-07mb/google/hatch: Kohaku: Re-setup dual-routing of EMR_GARAGE_DETTim Wawrzynczak
The pinctrl driver in the linux kernel automatically turns off SCI routing for all GPIOs exported via ACPI, so this patch sets up dual-routing of the EMR_GARAGE_DET signal so that one can be used for IRQs and one for the SCI wake. Change-Id: Iadeb4502c5a98a72ba651bdcad626609656c196f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34780 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07mb/google/hatch: Kohaku: Add touchscreen controller to device treeTim Wawrzynczak
The touchscreen controller was never added to the device tree, and the next board rev will have this IC connected. Set it up in the device tree with conservative power resource timings from the datasheet. BUG=b:138869702 BRANCH=none TEST=compiles; current board rev does not have touch IC Change-Id: I759fb32f31c8eee0e6bd664c6a82308354ef5d08 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2019-08-07mb/google/kohaku: Enable stylus pen deviceSeunghwan Kim
Enabling stylus pen device and pen_eject event. - Adding enable_gpio for power sequencing - Configuring GPP_H4 and GPP_H5 as native function - Adding PENH device node for pen ejection event BUG=b:137326841 BRANCH=none TEST=Verified pen input operation and pen_eject event (pop-up and wake from s0ix on pen ejection) Change-Id: Ic252a1f90c0fc6cb9b1e426d75a8b503824681f3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34581 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2019-08-07opencellular/rotundu: Disable HAVE_ACPI_RESUME supportKyösti Mälkki
FSP1.0 has low memory corruptions below CONFIG_RAMTOP on S3 resume path, as romstage ram stack will be utilised before there is a chance to make the necessary backup to CBMEM. Previously done for intel/minnowmax in commit b6fc727. Change-Id: I2e128079b180f9978e8519b190648d516aaee0dc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34673 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-07mb/google/octopus: Add custom SAR value for VortininjaWisley Chen
Vortininja needs different SAR values than meep. Use sku-id to load SAR values. BUG=b:138261454 BRANCH=octopus TEST=build and verified SAR values by sku id Change-Id: I7b3ab51e1d6cada4faaba1b9d72bd9eacf6b04dd Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2019-08-06src/mainboard/up/squared: Add Support for iTPMChristian Walter
Add support for the integrated TPM in Kconfig and update device tree. Change-Id: I3a51545c493674aeed9aef72db24f77315d033ce Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34443 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-05mb/google/helios: Set SPKR_PA_EN PIN high for boot beepSubrata Banik
This patch makes SPKR_PA_EN PIN output and high for boot beep to work in pre-os environment. BUG=b:135104721 BRANCH=NONE TEST=Boot Beep is working with required ALC1011 depthcharge code changes. Change-Id: I012462f93e9e2bcafe5f18ce7d04e3fcd1db9ffa Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com>
2019-08-05mb/google/octopus: Add EMRight digitizer supportWisley Chen
The device Vortininja uses the variant meep, and supports WACOM/EMRIGHT digitizer. BUG=b:138276179 BRANCH=octopus TEST=verified that WACOM/EMRIGHT digitizer can works. Change-Id: I2bed4edb0261953f122f1d9ccca1fe4fa9406b33 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2019-08-05mb/google/drallion: Add new mainboardThejaswani Putta
Drallion is a new mainboard using Intel Comet Lake SOC. As a starting point, I took mainboard/sarien as the reference code and modified WHL to Comet Lake. BUG=b:138098572 Test=compiles Signed-off-by: Thejaswani Putta <thejaswani.putta@intel.com> Change-Id: I541952a4ef337e7277a85f02d25979f12ec075c4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34497 Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-05mb/google/sarien: Increase Wacom touchscreen reset delay to 120 msCasper Chang
Increase reset delay to 120ms of touchscreen to meet wacom touchscreen T4 specification and resolve re-bind hid over i2c driver failed after touchscreen firmware auto update. BUG=b:132211627 TEST=Stress touchscreen firmware auto update 200 times and not found re-bind driver failed. Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I488660aefdc6df27077efc7fec2f3b99adbaef9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/34665 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mike Hsieh <mike_hsieh@wistron.corp-partner.google.com> Reviewed-by: Nick Crews <ncrews@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2019-08-05mb/cubietech/cubieboard: Remove boardArthur Heymans
The Allwinner code was never completed and lacks a driver to load romstage from the bootblock. Change-Id: I12e9d7213ce61ab757e9317a63299d5d82e69acb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33132 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03mb/google/hatch/variants/helios: Adjust all I2C CLK and I2C0 SDA hold timeFrank_Chu
After adjustment Touch Pad CLK: 383.4 KHz Touch Screen CLK: 381.6 KHz Audio codec CLK: 386.0 KHz TouchPad SDA hold time: 0.325ns BUG=b:137722634 BRANCH=none TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Frank_Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I27dec2f3e00eb6618cc429aff3dae7a5d937d638 Reviewed-on: https://review.coreboot.org/c/coreboot/+/34647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2019-08-03mb/google/octopus: Add custom SAR values for droid/blorbSheng-Liang Pan
droid/blorb needs to use different SAR values than bobba. Use sku-id to load the SAR values. BUG=b:138091179 BRANCH=octopus TEST=build and verify SAR load by sku-id Change-Id: I71b5d69ffbba82018a682202df73b604332dd9e7 Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34542 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-03mb/emulation/qemu-riscv: Add opensbi supportPatrick Rudolph
Tested on qemu-riscv: Boots into Linux until initrd should be loaded. Change-Id: I4aa307c91d37703ad16643e7f8eb7925dede71a8 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2019-08-03mb/google/hatch: Enable PmTimerDisabled config to reduce S0ix power usageSubrata Banik
BRANCH=none BUG=b:138152075 TEST=Build for cometlake board with the PmTimerDisabled policy in devicetree set to 1. With PmTimerDisabled = 0 >> iotools mmio_read8 0xfe0018fc 0x00 With PmTimerDisabled = 1 >> iotools mmio_read8 0xfe0018fc 0x02 Bit 1: ACPI Timer Disable (ACPI_TIM_DIS): This bit determines whether the ACPI Timer is enabled to run. - 0: ACPI Timer is enabled - 1: ACPI Timer is disabled Change-Id: I83f49505a804c99d7978e5d541ea9fe8ead9b88f Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2019-08-02mb/google/hatch: Fine-tune Kohaku I2C CLK frequencyPhilip Chen
Add rise time / fall time to I2C config in device tree to ensure I2C CLK runs accurately at I2C_SPEED_FAST (400 kHz). BUG=b:138258384 BRANCH=none TEST=probe I2C0/I2C2/I2C3 SCL on Kohaku board, verify all of them run at 395-399 kHz. Change-Id: Id98079e717f0db3fdcb88f85e45693925d11d7fd Signed-off-by: Philip Chen <philipchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34559 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/icelake: Make use of common thermal code for ICLSubrata Banik
This patch ports CB:34522 and CB:33147 changes from CNL to ICL. TEST=Build and boot dragonegg Change-Id: I0b983005f16fe182e634eac63fef4f6b22197a85 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34649 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-08-02soc/intel/skylake: Make use of common thermal code for SKLSubrata Banik
This patch ensures skylake soc is using common thermal code from intel common block. TEST=Build and boot soraka Change-Id: I0812daa3536051918ccac973fde8d7f4f949609d Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34648 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch: Initialize SSD GPIOs in bootblockShelley Chen
Moving these to bootblock as we are seeing some instances where devices are rebooting into the recovery broken screen with the 0x5a error (no bootable storage device in system). This needed to be done for KBL platforms and never got transferred to hatch. Please reference https://review.coreboot.org/c/coreboot/+/23647 BUG=b:137681648 BRANCH=None TEST=Run autotest faft_bios and faft_ec suites Change-Id: I8cf09c26d77d890f5d0490709504e9edf485a93f Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34484 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kohaku: Update DPTF parameters and TDP PL1/PL2Seunghwan Kim
Applying first tuned DPTF parameters and TDP PL1/PL2 values for kohaku. More fine-tuning will happen later. BUG=b:1704071 BRANCH=none TEST=build Change-Id: I8a87ff88e8e14ada473f9da59c15cdc779cbb108 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/34397 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/hatch/variants/hatch: Set PCH Thermal Threshold value to 77 deg CSumeet Pawnikar
PMC logic shuts down the PCH thermal sensor when CPU is in a C-state and DTS Temp <= Low Temp Threshold (LTT) in case of Dynamic Thermal Shutdown when S0ix is enabled. BUG=133345634 BRANCH=None TEST=Verified Thermal Device (B0: D20: F2) TSPM offset 0x1c [LTT (8:0)] value is 0xFE on Hatch. Change-Id: Ib20fae04080b28c6105e5a187cc5d7a55b48d709 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33147 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-07-31mb/google/kukui: Enable config for coreboot displayYongqiang Niu
BUG=b:80501386,b:117254947 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I478e06686158dd77b075bcef8a41763ae26c79f9 Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/31521 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 21:26:20 +0000