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This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl4 mainboard will follow in separate commits.
Change-Id: I3dfdccc8198f3a23a45d319ede6080803a46f7f6
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This mainboard variant requires GPIO adaptations to match the hardware.
Change-Id: I16387358d6c6fa15efd16f7ba7f6b89740477e9d
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29318
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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RCBA address numbers in comments looks wrong and confusing. Let's fix
them.
This is a cosmetic change since no actual data is added or removed.
Change-Id: I0e521acdac17959586bc0af7d8a2f7182f1e6721
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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See also commit 4ad1446b with Change-Id
I036208a111d009620d8354fa9c97688eb4e872ad ("Fix non-local header treated
as local").
Change-Id: Idea19b52198e6f46b0da6022558a46246a52f2e7
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29501
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia997c5188aef0c18d871658209c2d5f718ee2a19
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29499
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This structure was defined but never used. Let's use it.
Change-Id: I73baf428a7300e64fa486699e82ef62c6a53ea60
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29498
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Disable I2C7 because there is no device connected.
Change-Id: Ie9877d40b06f4a849163a873fd308ff03995fcdc
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29506
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Enable all PCIe root ports for this mainboard.
Change-Id: I62c7ba5048b4c2288bb502a78b9621edda333f2a
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29505
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There is no device on I2C0 which requires a lower clock rate.
Change-Id: Ib9ad4d9026267d2079e95245994d84c163b28dbb
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29504
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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All PCIe root ports of this mainboard do not have an associated CLKREQ
signal. Therefore the ports are marked with "CLKREQ_DISABLED".
Change-Id: I59c1132c6d273ccefeb1be6243577e1ae5064ef4
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This mainboard variant requires GPIO adaptations to match the hardware.
Change-Id: I4ba475e7d387f46ed5f41b7a691c7933edbc50c5
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29496
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This change adds a sku_id() function that returns a static value to
differentiate the sarien and arcada boards.
Change-Id: I1fecc675573a6aece7188aae9370733068d45dbf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29486
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Refer to CL:1043916
BUG=none
BRANCH=none
TEST=none
Change-Id: I3fbbbcac334646f68b8b9fd38fbb529d9e833581
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29464
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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generation
This changes uses drivers/intel/wifi chip for CNVi device to ensure that:
1. Correct device name shows in ACPI name space
2. Correct wake up shows in cat /proc/acpi/wakeup
3. Remove cnvi.asl from soc/intel/cannonlake
Change-Id: Ic81de2dce6045ced913766790a40ed19119f5118
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/29399
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Some variants of nami will have a fingerprint MCU.
BUG=b:118503113
BRANCH=Nami
TEST=None (build and boot, but no hw yet)
Change-Id: I446dc09cdf7f84a801723cb403d2de80e0997c65
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Marvell is the chip company, Marvel makes comic books.
Change-Id: I437ac0d4fc706fbb62a0a74ca74a197dba4499fb
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/29347
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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WWAN start-up control requires RESET# assert after FULL_CARD_POWER_OFF#
set to high more than 10 ms, so force RESET#(GPP_D21) to low at
bootblock stage to match the sequence.
BUG=N/A
TEST=Boot up Sarien/Arcada board, check WWAN get detected as USB
devices through lsusb.
Change-Id: I36eb841a2e8f2b36771d20577314a7451fbee133
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/29430
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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This change removes the function defintions from variant
so that the weak definition in baseboard can be used.
Refer to CL:813944.
BUG=none
BRANCH=master
TEST=Build and boot on DUT
Change-Id: I561414fcc94e3c812bb88730df9b94e332c61781
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29368
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update GPP_D9 to fix audio jack can't detect issue.
BUG=b:118393646
BRANCH=master
TEST=Verify audio jack can auto detect.
Change-Id: I87d24ed294c1ddc59bbd6ba9194c76d1f66413f3
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Use GPIO_134 as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
BRANCH=none
BUG=crbug:896347, b:118443377
CQ-DEPEND=CL:1298699
TEST=verify sensor events coming in on a reworked board
with companion EC and kernel patches
Change-Id: I41333cabe97bc8b0d59e19d84366f2ea2a59e026
Signed-off-by: Enrico Granata <egranata@chromium.org>
Reviewed-on: https://review.coreboot.org/29278
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add option for Nanya NT6CL256T32CM-H1 part.
Add comments to indicate total memory size for convenience.
BUG=b:118624505
BRANCH=master
TEST=none
Change-Id: I82200e7b3d0a13295cb38f53ab576697ff8d302b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/29341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ic08b191ee4dbcc56eb482601aa268394545936ba
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29292
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib3aafcc586b1631a75f214cfd19706108ad8ca93
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29285
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I0668b73cd3a5bf5220af55c29785220b77eb5259
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29103
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Using a conditional statement to return 0 or 1 depending on a logic
value is unnecessarily complex.
Change-Id: I449ce2b71b72374de5ec4986f9cc9f91a67856ee
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29265
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There are some small mistakes in these recently-added mainboards:
- board_info.txt: Lists board socket incorrectly.
- cmos.default: Loglevel was decreased some time ago.
- devicetree.cb: Spelling mistake.
- Kconfig: Mainboard name does not have a hyphen.
Change-Id: I08d9b06e79683acd3994b84647bce401ed6741e2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/29446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Get board id from AUXIN4 and RAM code from AUXIN3.
BUG=b:80501386
BRANCH=none
TEST=AUXIN4 is 0.074v and AUXIN3 is 0.212v on P0.
AUXIN4 is 0.212v and AUXIN3 is 0.212v on P1.
Change-Id: I50533e851d2fae66ae8c5e4e1aa36708d9058e94
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The Sarien mainboard uses the newly added Wilco EC.
- enable CONFIG_EC_GOOGLE_WILCO
- add the device and host command ranges to the devicetree
- have the mainboard SMI handlers call the EC handlers
- add EC and SuperIO devices to the ACPI DSDT
- call the early init hook for serial setup
Change-Id: Idfc4a4af52a613de910ec313d657167918aa2619
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29411
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add a variant of the Sarien board called Arcada. This is currently
very similar to Sarien with differences in PCIe, USB, and GPIO usage.
Change-Id: I432d2ba99558e960d4e775c809cc8bf6aa1a56bf
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29410
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Sarien is a new board using Intel Whiskey Lake SOC. It also uses
the newly added Wilco EC, enabled in a separate commit.
Sarien is not a true reference board, it is just one variant of
a very similar design. For that reason it is not considered the
baseboard but rather a standalone variant.
Change-Id: I2e38f617694ed2c2ef746ff8083f2bfd58cbc775
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/29409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable the radium touchscreen support
BUG=b:117960394
BRANCH=master
TEST=
1. emerge-nami coreboot chromeos-bootimage
2. boot up on ekko DUT to check touchscreen device by evtest
/dev/input/event3: Raydium Touchscreen
Change-Id: I16167d5d3ce6eac9d64832b52bb1945999a63a90
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29365
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify flash layout to match ICL-IFWI layout for early SoC PO support
Flash Reg 0: Descriptor [0x0 - 0xFFF]
Flash Reg 1: BIOS [0x400000 - 0xFFFFFF]
Flash Reg 2: IFWI (consist of ME primary & secondary partition and PMC FW)
[0x81000 - 0x3FFFFF]
Flash Reg 8: EC (applicable for Intel RVP with internal EC support)
[0x1000 - 0x80FFF]
Change-Id: I462a384739b5972d9a59569ffdcadba7cdef6a81
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29316
Reviewed-by: Shelley Chen <shchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The function `acpi_fill_madt()` is identical among all the Lynx Point
boards and sb/intel/bd82x6x, so share a common function between them.
Earlier Intel platforms have similar implementations of this function.
The common implementation might only need minor alterations to support
them.
Tested on an ASRock H81M-HDS and Google Peppy (variant of Slippy). No
issues arose from this patch.
Change-Id: Ife9e3917febf43d8a92cac66b502e2dee8527556
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29388
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The platform.asl file is copied from sb/intel/bd82x6x, and also matches
the contents deleted from each mainboard's platform.asl.
Tested on an ASRock H81M-HDS and a Google Peppy board (variant of
Slippy). No issues arose from this patch.
Change-Id: I539e401ce9af83070f69147526ca3b1c122f042c
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This patch is based on a8a9f34e9b7b ("sb/intel/i82801{g,j}x:
Automatically generate ACPI PIRQ tables")
Tested on an ASRock H81M-HDS. The generated _PRT object looks correct,
and the system doesn't show any issue when running. The following
assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:16.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1a.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1c.1: pin=1 pirq=1
ACPI_PIRQ_GEN: PCI: 00:1c.2: pin=2 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1c.3: pin=3 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=7
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=1 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=2 pirq=2
Also tested on a Google Peppy board. The following assignments occur:
ACPI_PIRQ_GEN: PCI: 00:02.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:03.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:14.0: pin=0 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1b.0: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1c.0: pin=0 pirq=0
ACPI_PIRQ_GEN: PCI: 00:1d.0: pin=0 pirq=3
ACPI_PIRQ_GEN: PCI: 00:1f.2: pin=0 pirq=6
ACPI_PIRQ_GEN: PCI: 00:1f.3: pin=1 pirq=2
ACPI_PIRQ_GEN: PCI: 00:1f.6: pin=2 pirq=1
A diff of the _PRT object for the Google Peppy board is below. The code
used in the diff has been modified for clarity, but the semantics remain
the same. To summarise the diff:
* The disabled PCIe root ports are no longer included.
* The LPC controller is no longer included, as it has no interrupt pin.
The pins for the remaining LPC devices are each one less. Perhaps the
original _PRT object was incorrect?
* The SDIO device is no longer included, as it is disabled.
* The Serial IO devices are no longer included, but that is due to a
separate issue I am having with this system (the devices don't show up
under Linux regardless of this patch). In short: their omission is not
a fault of this patch.
--- pre/_PRT
+++ post/_PRT
@@ -1,301 +1,157 @@
Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table
{
If (PICM)
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0003FFFF,
Zero,
Zero,
0x10
},
Package (0x04)
{
0x0014FFFF,
Zero,
Zero,
0x12
},
Package (0x04)
{
0x001BFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001CFFFF,
Zero,
Zero,
0x10
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- Zero,
- 0x11
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- Zero,
- 0x12
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- Zero,
- 0x13
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
Zero,
0x13
},
Package (0x04)
{
0x001FFFFF,
Zero,
Zero,
0x16
},
Package (0x04)
{
0x001FFFFF,
One,
Zero,
0x12
},
Package (0x04)
{
0x001FFFFF,
0x02,
Zero,
0x11
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- Zero,
- 0x10
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- Zero,
- 0x14
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- Zero,
- 0x15
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- Zero,
- 0x17
}
})
}
Else
{
- Return (Package (0x12)
+ Return (Package (0x09)
{
Package (0x04)
{
0x0002FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0003FFFF,
Zero,
^LPCB.LNKA,
Zero
},
Package (0x04)
{
0x0014FFFF,
Zero,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001BFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001CFFFF,
Zero,
^LPCB.LNKA,
Zero
},
- Package (0x04)
- {
- 0x001CFFFF,
- One,
- ^LPCB.LNKB,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x02,
- ^LPCB.LNKC,
- Zero
- },
-
- Package (0x04)
- {
- 0x001CFFFF,
- 0x03,
- ^LPCB.LNKD,
- Zero
- },
-
Package (0x04)
{
0x001DFFFF,
Zero,
^LPCB.LNKD,
Zero
},
Package (0x04)
{
0x001FFFFF,
Zero,
^LPCB.LNKG,
Zero
},
Package (0x04)
{
0x001FFFFF,
One,
^LPCB.LNKC,
Zero
},
Package (0x04)
{
0x001FFFFF,
0x02,
^LPCB.LNKB,
Zero
- },
-
- Package (0x04)
- {
- 0x001FFFFF,
- 0x03,
- ^LPCB.LNKA,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- Zero,
- ^LPCB.LNKE,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- One,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x02,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0015FFFF,
- 0x03,
- ^LPCB.LNKF,
- Zero
- },
-
- Package (0x04)
- {
- 0x0017FFFF,
- Zero,
- ^LPCB.LNKH,
- Zero
}
})
}
}
Change-Id: Id3f067cbf7c7d649fbbf774648d8ff928cb752a4
Signed-off-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-on: https://review.coreboot.org/29381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Change the variant name from kalista to karma.
According to the CL:1298319, the baseboard name is kalista
and the board name is karma.
BUG=none
BRANCH=master
TEST=emerge-kalista coreboot chromeos-bootimage
Change-Id: Idea295cc14249721a6dc0fc4e2ef6470d43e16eb
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29314
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Idf10a09745756887a517da4c26db7a90a1bf9543
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
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Confirm with RK, H9CCNNNBKTMLBR-NTD uses this sdram config.
sdram-lpddr3-hynix-4GB.inc
BUG=b:117967129
BRANCH=master
TEST=None
Change-Id: I98afc33fd2cb61343be0dcdc007add75bee9c2af
Signed-off-by: Loop_Wu <Loop_Wu@asus.com>
Reviewed-on: https://review.coreboot.org/29366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
|
|
Move soft_reset() to `southbridge/amd/common/` it's only used for
amdfam10 now.
Drop hard_reset() for good.
Change-Id: Ifdc5791160653c5578007f6c1b96015efe2b3e1e
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
According to syndra thermal table, PL2 need to check cpu id.
Set up syndra PL2 value.
1. KBL_U PL2 is 25w.
2. KBL_R PL2 is 29w.
Refer to b:116836990#comment10.
BUG=b:116836990
TEST=The thermal team verify OK
Change-Id: I766a886121a089683565608252b4c176c70e88a3
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Shelley Chen <shchen@google.com>
|
|
Unfortunately Stoney has an issue where enabling the IOMMU causes
a 10%-50% decrease in the integrated graphics performance. It is
also disabled by default on other stoney platforms.
BUG=b:118612241
TEST=Verify that IOMMU is disabled.
Change-Id: Ia396c7227cb21461ec8afbdf746721d4fb28083d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/29342
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This mainboard is based on mc_apl1. In a first step, it concerns a copy
of mc_apl1 directory with minimum changes. Special adaptations for
mc_apl3 mainboard will follow in separate commits.
Change-Id: I963ec63bccf71296c3fdabfcf9f3009c2febc791
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
|
|
Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Variants of Nami need to accommodate single channel DDR. Will use
GPP_D10 on nami for identification. GPP_D10 will return 1 when device
is using single channel DDR and 0 when using dual channel DDR.
BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
channels gets returned.
Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Looks like we must do it in the same way as in l520, t420, t420s,
t430s, t520, t530, x201, x220, x230 models. No idea why t430 should be
handled differently.
Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29031
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed())
also to the Lenovo T400.
See also commit 42ae0bae with Change-Id
I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88 (mb/lenovo/x200: Use
acpi_s3_resume_allowed())
Change-Id: I9d4ac711375977a979a8b3e5606e2197847e88de
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
|
Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.
Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
|
|
Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
This commit follows up on commit 7dee9745 with Change-Id
I88b5ef8e12ac606751952a493f626e1b146e98f7 ("mb/lenovo/x201: Link gpio
map instead of including a header").
Change-Id: Ibdb96deafbe422bf50fd2e1fc56a57ae53ccd5a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
IGD display handling was rewritten with commit dd2bc3f8 with Change-Id
I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). These
comments were removed as well (with some accidentally left behind).
Let's remove them and those who were introduced later with new ports.
Change-Id: I8d3e12d0c3b03b0de38e65f36b94ed706fbf893c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29271
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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These ifdefs are the remains from the following commits:
* fa1d688a with Change-Id I9909a5b2bdb4b59219db6304fa4332802fe0301c
("sandy/ivy native: dedup romstage.c main()")
* 7dee9745 with Change-Id I88b5ef8e12ac606751952a493f626e1b146e98f7
("mb/lenovo/x201: Link gpio map instead of including a header")
Change-Id: If83189688151f531a05780a87db3409cbacfbeff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Clone entirely from mainboard/intel/cannonlake_rvp
commit id: af89f49b83260a04dece84b34e97560fb85d29ae
List of changes on top off initial cannonlake_rvp clone
1. Rename "Cannonlake" with "Icelake".
2. Replace "cannonlake_rvp" with "icelake_rvp".
3. Rename "cnl" with "icl".
4. Remove unwanted SPD file, will add correct SPD with mainboard
patches.
5. Remove NHLT related implementation.
6. Remove FSP configs, will add once FSP headers are available.
7. Removed smihandler.c, will add later if needed.
Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29164
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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In function write_pirq_routing_table(), the function name is used in a print
string. Use __func__ instead.
BUG=b:117642170
TEST=Build grunt.
Change-Id: Ibf8673c5b2cda1105aae1edb46f6589d55208c50
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add a new variant of fizz for the kalista board.
Key differences from baseboard include:
- GPIO changes
- devicetree.cb changes
BUG=b:117066935
BRANCH=master
TEST=Build (as initial setup)
Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29205
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables override device tree for Fizz to allow variants to
provide their own overrides and also moves I2C5 realtek node to
fizz/overridetree.cb since it doesn't apply to some variants being
added for Fizz.
Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Get recovery mode switch from EC and pass it to payload.
BUG=b:80501386
BRANCH=none
Test: Boots correctly on Kukui.
Change-Id: Ib92afca885e5a97ec4646f55f2279ef56a61af5a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Liara auto restart issue is caused by memory access error and consequent
kernel panic. To solve this issue, revert the CL:1243666 (Disable
NbP-state on Liara) and use 2T mode instead.
BUG=b:116082728
TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run
memtester passed 10 cycle.
Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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1. Update PSV values for cpu and sensers.
2. Change PL1 min value from 3w to 4.5w.
3. Change TSR2 TRT source from charger to CPU.
Refer to 112448519#comment31.
BUG=b:112448519
TEST=Build coreboot for Octopus board
Change-Id: I7c7df0f54374fdaa4cf57d5c255d841d7db38cfc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This change uses CRFP ACPI name for FP device since user space
utilities expect this name for triggering different actions.
BUG=b:112974410
BRANCH=nocturne
Change-Id: I63309227c916b43917e529c223cf738fc3baa209
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29231
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On rammus, set GPIO GPP_C22 to 1 for touchscreen power on.
And add touchscreen device "PNP0C50" to I2C0.
According to touchscreen spec, device power on initialization takes
105 ms, so set "generic.enable_delay_ms" to 120.
We found there is i2c error log pop up when we set delay
time to be 110ms or 105ms. If we set delay time to be
120ms. System will not pop up i2c error log.
BUG=b:115944726
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure touchscreen works.
Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of
part_num_store that holds the number of DRAM part. It ensures that
host advertises the supported size to read part number from the EC.
BUG=b:115697578
Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Before entering the OS, the AP relies on the smi handler to shutdown the
system when the lid closes. Without the smi_events setting, the AP will
not receive the smi handler. As a result, the AP won't shutdown and will
always keep in S0.
This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983
and this patch adds the smi_events back to support the smi handler for
the lid close.
BRANCH=master
BUG=b:115572596
TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown
Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/29191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
|
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Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The file soc/amd/stoneyridge/acpi/smbus.asl has 0 bytes (no content). Remove
the include of this file.
BUG=b:117814641
TEST=Build grunt and gardenia.
Change-Id: I0c48167195a9708afc255490bb1996b6dfc7bdfb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29178
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change uses the newly added macros for configuring the same GPI
pad(GPIO_135) for IRQ (normal interrupt operations) and
wake (interrupt for waking from S3/S0ix) for the trackpad device. The
other pad GPIO_142 is now configured as not connected.
BUG=b:117553222
TEST=Verified that yorp and bobba wake from S3 and S0ix using
trackpad.
Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the
changes from kernel driver. IMX319 has two PLLs and it can be configured
either single or dual. Previous driver implemente dual PLL mode, however
image sensor vendor prefer single PLL mode and calculate the pixel rate
became easier. So the kernel driver changed to use single pll, coreboot
change will match that.
Bug=b:116082248
Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28736
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a cosmetic one. It just removes some board names from comments
since these functions sometimes are very similar, so no need to add
extra difference between them.
Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We didn't have a hard_reset() implementation for these boards. So
select the board_reset() stub for them.
Change-Id: I77651e3844632fb1a347008c96e53d23cc5a2646
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29170
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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And here comes the mess...
This just renames do_hard_reset() to do_board_reset() and keeps current
behaviour. As these are never called from chipset or board code but only
from common code, it's likely that their implementations are untested
and not what we actually want. Also note, that sometimes implementations
for rom- and ramstage differ considerably.
Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29058
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change udpates FMAP to wrap MRC training data in RW_PRESERVE
section so that we don't lose the data when performing full firmware
updates on octopus.
BUG=b:117882029
TEST=Verified that chromeos-firmwareupdate doing full firmware update
preserves training data on octopus.
Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move current NHLT configuration implementation to baseboard so that
variants can leverage it or provide their own configuration.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add support for ChromeOS GPIO ACPI table information by providing weak
implementation from the baseboard.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Provide API for gpio table functionality. Default weak
implementations are provided from the baseboard.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In order to be able to share code across different fizz variants,
provide the concept of baseboard and variants. New directory layout:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/fizz - code
variants/fizz/include/variant - headers
New boards would then add themselves under their board name within
"variants" directory.
This is purely an organizational change.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
CQ-DEPEND=CL:1273514
Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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I didn't change the offsets of all the other regions because I didn't
want to cause all dogfood devices to lose their corp enrollment.
BUG=b:117797131, b:117798830
BRANCH=none
TEST=Ran autotest and made sure the tests were skipped
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache [ PASSED ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal [ PASSED ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.
Change-Id: I5cdbf4139dde80fe6e9d0045139a97841b03bc42
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/29171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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this patch adds following changes
- Select config to initialize codecs in common HDA driver.
- Add audio verb table for coffee lake RVP11 & RVP8.
BUG: None
TEST: boot to yocto linux and windows os on CFL RVP11 & RVP8. verified audio
playback and record functionality over anolog audio jack & HDMI display.
Change-Id: I567e317c0e9ac9f91e159866c7f896e4c101712b
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ib359e4039f87bb87faac040f24f70cc0988c0ea8
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibf23f49e7864c611a3cb32a91891b6023a692e1d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28703
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds.
Use frequency as a proxy to determine SKU. The E3805, E3815,
E3825, and E3826 are all <= 1460MHz while the E3827 and E3845
are 1750MHz and 1910MHz, respectively. This will allow to boot
quad-core Minnowboard Turbot especially.
Change-Id: I5e57dd419b443dfa742c8812cec87274af557728
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27989
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t is deprecated.
Change-Id: I564319506870f75eab58cce535d4e3535a64a993
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I020431ba8eb61f5ce256088b919c049985331d64
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead. Also removed FDD from l520
romstage (original value, 0x3c0c, means that FDD_LPC_EN was also
enabled).
Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This file was extracted directly from the vendor's firmware ver. 2.27.
Change-Id: Ic2d2b259f3b535a791c9dcfdf962c03a0bab87a2
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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- Add new mainboard variant coffee lake RVP8, which is CRB for
coffee lake-s processor, support U-DIMM DDR4 memory module.
- Modify cfl_h devicetree to enable IO devices, configure PCIE root
port clock source, usb over current pin as per board schematics.
- Select cannonlake PCH-H chipset config for both cfl_h & cfl_s.
- Add GPIO table as per board schematics.
BUG= None
TEST= Build and flash, confirm boot into yocoto & windows OS on both
cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA,
display, power functionalities.
Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29066
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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L520 and T420 should also use it - platforms are very similar to t420s
and t530. Z61t is based on T60/X60, X131e is based on X230 so commit
with Change-Id I13c08b8c6b1bf0f3deb25a464b26880d8469c005 should be
applied as well.
All four platforms are using ec/lenovo/h8 embedded controller.
Change-Id: Ib177f024871e82979dd430da86f1551aef14d446
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set up USB host controller.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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There is no need to indent these lines with two tabs.
Change-Id: I2164f4e3ea48db8dc5242a55b0452782dae19a4b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The assignment of header->checksum was in some cases done twice, or
unnecessarily split into two lines.
Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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While these pins were set to a pull-down 20KOhm, NPCX EC consumes
~2.1mW higher power. Becasue there was leakage current on both GPIO67
and GPIO70 from NPCX EC. With the external pull-up 10KOhm for
USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current.
BUG=b:117139495
TEST=Check nxpc EC power to see power improvement
Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/29007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update CPU passive temperature threshold value from 70C to 80C,
to avoid early throttling for spiky workloads. Also, change CPU
throttling interval from 1 sec to 5 sec for CPU temperature.
BUG=b:116400298
BRANCH=None
TEST=Manual performance testing on nocturne.
Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29044
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It always included if ACPI is supported since commit 822bc65 with
Change-Id I372dbd03101030c904dab153552a1291f3b63518 ("ACPI: Remove
CONFIG_GENERATE_ACPI_TABLES").
Change-Id: If17a6f43e368ccf850031b349714fa1ec4d02c1d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since there are two cameras on Nami and only one camera on Syndra.
We need to disable rear camera/DMIC on all Syndra sku.
BUG=b:112876867
Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Tried to build all affected mainboards - still compiles fine.
Change-Id: I385cac1a75cee13453b831bd75b3ecc7a6d229fa
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This define is no longer used by anyone. It was removed everywhere else
with commit with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757.
It seems that these two files were simply mislooked. So let's remove it.
Change-Id: Ifbb62441e16e97c0cae0713968844e296619a880
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This mainboard is quite similar to the p5qc. The main differences being a second
PEG slot, the IDE slot and being DDR2 only.
The following was tested:
- both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the
black slot)
- USB
- Ethernet NIC
- PS2 Keyboard
- COM1
- S3 resume
Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/29102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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