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2017-10-11mainboard/google/fizz: Enable Devslp for SATA port 1Gaggery Tsai
This patch is to enable the support of device sleep for SATA port 1 and disable unused SATA port 0. BUG=b:65808359 BRANCH=None TEST=Ran "suspend_stress_test -c 2500" and passed the test. Change-Id: I33b8f5fd0c51d83e154ef7daac3274ff377bc8b3 Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com> Reviewed-on: https://review.coreboot.org/21765 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2017-10-10mb/google/poppy/variants/nautilus: add nautilus boardChris Wang
Create Nautilus board which derives from Poppy, a KBL reference board. BRANCH=master BUG=b:66462881 TEST=Build (as initial setup) Change-Id: I6ca5ab821a7ba1746b37dfd3ea1ed367094d4f52 Signed-off-by: Chris Wang <chriswang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-09skylake mainboards: Use PAD_CFG_GPI_GPIO_DRIVER instead of PAD_CFG_GPIFurquan Shaikh
Change 1760cd3e (soc/intel/skylake: Use common/block/gpio) updated all skylake boards to use common gpio driver. Common gpio code defines PAD_CFG_GPI without GPIO_DRIVER ownership. However, for skylake PAD_CFG_GPI set GPIO_DRIVER ownership by default. This resulted in Linux kernel failing to configure all GPIO IRQs since the ownership was not set correctly. (Observed error in dmesg: "genirq: Setting trigger mode 3 for irq 201 failed (intel_gpio_irq_type+0x0/0x110)") This change fixes the above issue by replacing all uses of PAD_CFG_GPI in skylake mainboards to PAD_CFG_GPI_GPIO_DRIVER. BUG=b:67507004 TEST=Verified on soraka that the genirq error is no longer observed in dmesg. Also, cat /proc/interrupts has the interrupts configured correctly. Change-Id: I7dab302f372e56864432100a56462b92d43060ee Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-09mainboard/intel/cannonlake_rvp: enable NVMe SSDBora Guvendik
Turn on PCIe express port 9 of PCIe controller 3, to enable NVMe SSD via M.2 socket 3 on RVP board. TEST=Boot to OS using Intel NVMe SSD Pro 6 Change-Id: I2fd1cdcf2d9718bf2042262b0c9813811a706b4a Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21908 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-08google/cyan: fix variant memory/silicon init params overrideMatt DeVillier
The mainboard_memory_init_params() and mainboard_silicon_init_params() methods already have weak definitions in drivers/intel/fsp1_1, so having them declared as weak in the cyan baseboard has the effect of them not being called at all unless overridden at the variant level. Therefore, remove the weak declarations in the baseboard and ensure that each variant has its own init functions if needed. TEST: build/boot google/cyan Change-Id: I1c76cb5838ef1e65e72c7341d951f9baf2ddd41b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21704 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-10-08mb/google/poppy/variants/soraka: Add 10ms reset delay for WCOM deviceFurquan Shaikh
Change 868b3761 (mainboard/google/soraka: Reduce Wacom resume time) removed the delay after taking device out of reset since it seemed unnecessary in system resume case (because there is enough time after taking device out of reset and before communication with device starts). However, without the delay, kernel driver runs into issue while talking to the device during boot-up and runtime suspend/resume. (Observed this error in dmesg: "i2c_hid i2c-WCOMCOHO:00: failed to change power setting."). Thus, add 10ms delay after taking device out of reset. Verified on multiple Soraka system that with 10ms delay, kernel driver does not run into any issue talking to the WCOM device during boot-up, runtime suspend/resume and system suspend/resume. BUG=b:65358919 TEST=No more errors talking to WCOM device in kernel dmesg. Change-Id: I485b753cbae4b653e74337e048aea4d26ffdbb81 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21910 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Rajat Jain <rajatja@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-08ec/google/chromeec: Add library function google_chromeec_events_initFurquan Shaikh
mainboard_ec_init implemented by all x86-based mainboards using chromeec performed similar tasks for initializing and recording ec events. Instead of duplicating this code across multiple boards, provide a library function google_chromeec_events_init that can be called by mainboard with appropriate inputs to perform the required actions. This change also adds a new structure google_chromeec_event_info to allow mainboards to provide information required by the library function to handle different event masks. Also, google_chromeec_log_device_events and google_chromeec_log_events no longer need to be exported. Change-Id: I1cbc24e3e1a31aed35d8527f90ed16ed15ccaa86 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-10-06google/zoombini: adapt to schematic changesNick Vaccaro
Adapt code to latest schematic changes, revision 1.1. Configure GPD2 for EC_PCH_WAKE_ODL, GPP_D5 for EC_I2C_SENSOR_SDA, GPP_D6 for EC_I2C_SENSOR_SCL, GPP_D7 for WWAN_SAR_INT_ODL, GPP_D9 for touchscreen power enable, GPP_D10 for wifi power enable, GPP_D11 for wwan power enable, GPP_D13 change to "No Connect" (was VOL_UP_ODL), GPP_D14 change to "No Connect" (was VOL_DOWN_ODL). BUG=b:66265441 BRANCH=None TEST=None Change-Id: Ic9e76ed3e958c1f96deb6356d6480c6ba7cfe699 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21900 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-06mainboard/google/reef: Override VBT selection in coralPatrick Georgi
Change-Id: I7fd667b1cf0b7c2a5e4ab7ac7748d9636a52ae54 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21725 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-05src/mainboard/Kconfig: Add support for 10240 KiB ROM chipsJonathan Neuschäfer
The Dell Optiplex 790 desktop board has a logical 10MiB flash, so it needs to select BOARD_ROMSIZE_KB_10240. Provide it, so it can be used. Change-Id: I6365b0cda67fa1213c20337890157e5d658094d1 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-10-05mb/google/reef: Cache EC's SKU ID on CoralPatrick Georgi
Change-Id: I1925f51d63290b8d08366b622d5df3aab3a7484e Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/21737 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-10-05AGESA: Re-enable HAVE_ACPI_RESUMEKyösti Mälkki
Note: For some of the boards affected ACPI S3 support was never tested but feature was just copy-paste from reference design. Change-Id: I2a54d605fa267a7501f57efd79a16b3bfa49891e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Damien Zammit <damien@zamaudio.com>
2017-10-04google/fizz: Configure GPP_C23 earlyDaisuke Nojiri
GPP_C23 is read by vboot_handoff to set the WP flag. Thus, it has to be configured in early_gpio_table. BUG=b:67030973 BRANCH=none TEST=Verify by wpsw_boot and wpsw_cur match. Change-Id: I96f2b53d7bc0901ffccce46b2d8ddae80c002fdc Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21876 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-04chromeec: Remove checks for EC in RODaisuke Nojiri
This patch removes checks that ensure EC to be in RO for recovery boot. We do not need these checks because when recovery is requested automatically (as opposed to manually), we show 'broken' screen where users can only reboot the device or request recovery manually. If recovery is requested, Depthcharge will check whether EC is in RO or not and recovery switch was pressed or not. If it's a legitimate manual recovery, EC should be in RO. Thus, we can trust the recovery button state it reports. This patch removes all calls to google_chromeec_check_ec_image, which is called to avoid duplicate memory training when recovery is requested but EC is in RW. BUG=b:66516882 BRANCH=none CQ-DEPEND=CL:693008 TEST=Boot Fizz. Change-Id: I45a874b73c46ea88cb831485757d194faa9f4c99 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21711 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-04mb/asus/kcma-d8,kgde-d16: Don't select SPI_FLASH_WINBONDArthur Heymans
The default for SPI_FLASH_INCLUDE_ALL_DRIVERS is y which already includes this. Change-Id: Ib2de0f384a547240528b18f07327566354164699 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-10-03mainboard/google/soraka: Reduce Wacom resume timeRajneesh Bhardwaj
Currently the WCOMCOHO registers a reset delay of 110ms to execute their _ON_ asl power on method. This seems to be correct as per WACOM product design specifications but it introduces an unwanted delay in overall system resume time. This delay should be removed from ACPI critical path since the entire kernel resume gets blocked on this sleep call unless this is over. In the kernel I2C communication with WACOM driver starts with the resume callbacks of I2C HID driver which gets triggered after display is completely resumed. The display resume process takes at least 230ms so it's safe to reduce the delay from coreboot and unblock the critical ACPI path. BUG=b:65358919 BRANCH=None TEST=manual testing on Soraka board to ensure that touchscreen works at boot and after suspend/resume. Also verify that the overall S3 resume time is reduced by 110ms. Change-Id: I59d070977a95316414018af69d5b43e3147ccf4e Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com> Signed-off-by: Rajneesh Bhardwaj <rajneesh.bhardwaj@intel.com> Reviewed-on: https://review.coreboot.org/21692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-10-03mainboard/intel/cannonlake_rvp: Add smi support in boardLijian Zhao
Include SMI Handler support for Cannonlake RVP platform. Change-Id: I8f363e20a6eb92b3c05e16715aa052a8da18b509 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21542 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02soc/intel/skylake: Use common/block/gpioHannah Williams
Other than switch to use common gpio implementation for skylake based platform, also apply the needed changes for purism board. Change-Id: I06e06dbcb6d0d6fe277dfad57b82aca51f94b099 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/19201 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02google/gru: Fix pmu1833_volsel handlingJulius Werner
RK3399 has a pin that can decide whether GPIO port 1 is driven with 1.8V or 3.0V. We thought this mechanism was disabled by default, but it turns out it wasn't. We want to use that pin as an output GPIO on Scarlet so we need to reconfigure the respective SoC controls before we do that. It seems that we also need to explicitly pinmux the pin away from that special function (to normal GPIO) or weird things happen on some boards. BUG=b:66534913 TEST=Sprinkled several long udelays, poked test points with a multi-meter on Scarlet. Change-Id: Ia02cbb4f3b2f14b0d958b84adcddb0c5f4259efa Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-10-02mainboard/amd: Add required callouts to Stoney BiosCallouts.cMartin Roth
Hook the new required AGESA callout functions into the callouts tables. BUG=b:66690176 TEST=Build and boot Kahlee - see the functions get called. Change-Id: Ife9c2b20e59ede404edb1f700238e425fea35914 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/21708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-10-02google/fizz: Enable wake-on-usb attach/detachShelley Chen
BUG=b:62095784, b:35775024 BRANCH=None TEST=Run powerd_dbus_suspend from kernel. Plug in usb device and make sure wakes up. Change-Id: I214d6557998bdaf1d327c2a45532461b95d56a96 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/20421 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-29AGESA binaryPI: Drop amdlib.h in BiosCallouts.cKyösti Mälkki
Some fam14 boards will need more work on this area, those are to be addressed with followup patches. Change-Id: I14208cf8519a4cf71e4944d08a2dae36b7f1f878 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-28google/zoombini: Add new boardNick Vaccaro
Add zoombini board files using cannonlake and FSP 2.0. Copied most initial files from poppy and cannonlake_rvp. BUG=b:64395641 BRANCH=None TEST=Compiles successfully using "./util/abuild/abuild -p none -t google/zoombini -x -a" Change-Id: I13ebaae403d08f1b2e6881eeba4dc1787c792b4e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/21273 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27mb/google/poppy: Modify HID and add device tree support for VCM deviceV Sowmya
Modify the HID to align with ACPI spec. Add the DSD object for the device tree support in kernel which will probe the DW9714 device based on the HID. BUG=b:65423422 CQ-DEPEND=CL:654383 BRANCH=none TEST=Build and boot soraka. Verified that the VCM device probe is successful. Change-Id: Ic4a59dd2027267fbd3837fcd7dbc00551a69f7d6 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21508 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-27mb/emu/*-riscv: Remove outdated memory mapJonathan Neuschäfer
Change-Id: I8919719865bc7ae8d13f025999caf8b5836b88ab Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21656 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-09-27Coral: Add Synaptics touchpad supportPeggy Chuang
We need support two touchpad for Robo project, so adding Synaptices touchpad to coral. BUG=b:63134907 TEST=Compiled, verified by ODM Change-Id: If5a650338d5a7e6f01e9525d28588b871d390e50 Signed-off-by: Peggy Chuang <peggychuang@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/21696 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-27google/kahlee: Fix GPIO ASLMarc Jones
Use a single define and set the CROS GPIO ASL device to match the Stoney Ridge GPIO HID. Update the GPIO number to 142. Also, add a DDN field in the GPIO ASL. This addresses the TEST indicated below. BUG=b:65597554 BRANCH=none TEST=grep ^ /sys/devices/platform/chromeos_acpi/GPIO.*/* reports AMD0030. Change-Id: I1d6c42c6c9a0eef25e0e99aed6d838c767f5e01f Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21614 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26asus/p2b-f: Move to EARLY_CBMEM_INITKeith Hui
It shares the same northbridge, cpu, romstage with asus/p2b-ls, which is already on EARLY_CBMEM_INIT as of commit e14d7de. Change-Id: I8e7c468f0363a5cb9885020bc116e5ae3480ec17 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21647 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-26asus/p2b-d[s]: Move to EARLY_CBMEM_INITKeith Hui
Boot tested on p2b-ds. Migrate p2b-d as well because they share the same mainboard romstage. Change-Id: I3e4b98cc6191d557325fc5da97744902996673af Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21646 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-26mainboard/google/fizz: Enable EC-EFS supportDaisuke Nojiri
BUG=b:65028930 BRANCH=none TEST=emerge-fizz coreboot. Verify Depthcharge recognize VBSD_EC_EFS. Change-Id: Ie18536982e172a45703600eec6e183c1e7c12746 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/21640 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26mainboard/google/fizz: Enable cros_ec_keyb deviceKevin Cheng
This is required to transmit button information from EC to kernel. BUG=b:65980005 BRANCH=None TEST=Verified using evtest that kernel is able to get button press/release information from EC. Change-Id: I3cd524aec47ca988d6044cb089e7aa7636e64ab2 Signed-off-by: Kevin Cheng <kevin.cheng@intel.com> Reviewed-on: https://review.coreboot.org/21633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2017-09-26Use stopwatch_wait_until_expired where applicableJonathan Neuschäfer
Change-Id: I4d6c6810b91294a7e401a4a1a446218c04c98e55 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-26mainboard/winnet/g170: drop the redundant vendor nameLubomir Rintel
"WinNET WinNET G170" doesn't look too cool :( Change-Id: Iae0a8725645b9d6321b64ccbad10633e0049d477 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/21612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-26mainboard/winnet/g170: disable use of upper memory for SeaBIOSLubomir Rintel
Otherwise the USB init gets unhappy: |3df52000| EHCI init on dev 00:10.4 (regs=0xfd010010) |3df3d000| WARNING - Timeout at ehci_wait_td:515! |3df3d000| ehci pipe=0x3df52880 cur=00000000 tok=00000000 next=3df3ddc0 td=0x3df3ddc0 status=80e80 |3df3e000| WARNING - Timeout at ehci_wait_td:515! |3df3e000| ehci pipe=0x3df52a80 cur=3df3ee00 tok=00000d00 next=3df3edc0 td=0x3df3edc0 status=80e80 |3df3e000| WARNING - Timeout at ehci_wait_td:515! |3df3e000| ehci pipe=0x000ee680 cur=00000000 tok=00000000 next=3df3ecc0 td=0x3df3ecc0 status=1f0c80 Change-Id: I69f1fe38503b0f8d6015b515637d8376726490c0 Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/18905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-09-26mainboard: use SeaBIOS config only when it's the payload of choiceLubomir Rintel
It makes no sense for Das U-Boot which uses the same setting. Change-Id: I1629aecf33cb62bb1e6856ef5627748a7dc74d8a Signed-off-by: Lubomir Rintel <lkundrak@v3.sk> Reviewed-on: https://review.coreboot.org/21611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-26mb/google/*: Use newly added Chrome EC boardid functionFurquan Shaikh
Instead of duplicating code across multiple mainboards, use newly added helper function to read boardid from Chrome EC. Change-Id: I1671c0a0b87d0c4c45da5340e8f17a4a798317ca Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26binaryPI boards: Fix indirect AGESA.h includeKyösti Mälkki
Change-Id: I3f6030879da61168adf42db0a4913d70a737594e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-26AGESA cimx: Move cb_types.h to vendorcodeKyösti Mälkki
This file mostly mimics Porting.h and should be removed. For now, move it and use it consistently with incorrect form as #include "cbtypes.h". Change-Id: Ifaee2694f9f33a4da6e780b03d41bdfab9e2813e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA: Remove heap allocations from OemCustomize.cKyösti Mälkki
We can simply declare these structures const. Change-Id: I637c60cc2f83e682bd5e415b674f6e27c705ac91 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21631 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-26AGESA binaryPI boards: Fix some whitespaceKyösti Mälkki
Change-Id: I150d4a71536137a725f43d900d483e7e35592bb3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21629 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26amd/torpedo: Drop PlatformGnbPcieComplex.hKyösti Mälkki
Copy-paste, was not really used at all. Change-Id: I9a916f6fa0f6a48de6ac62be6f366cee0e406a8f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-26google/snappy: Override SKU ID by VPDKevin Chiu
Since snappy PCB may have over 9 SKU and current GPIO board ID GP16/GP17 is insufficient to use. Using VPD to control could prevent H/W change. BUG=b:65339688 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I55ab741354797e022dd945da9c8499ee5e041316 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21533 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-26mainboard/google/reef: expose sku strapping helper functionAaron Durbin
variant_board_sku() callback exists to allow some of the variants to report the sku id differently based on board implementation. However, there are cases where there are multiple ways to encode the sku id, but the original way should be used as a fallback. As such expose a helper function, sku_strapping_value(), such that there isn't code duplication for the common fallback case. BUG=b:65339688 Change-Id: I1e917733eb89aebc41a483e2001a02acfda31bf4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-26soraka: Ensure I2C5 frequency is less than 400kHzFurquan Shaikh
Update I2C5 bus parameters to obtain clock frequency <400kHz. BUG=b:65062416 TEST=Verified using an oscilloscope that I2C5 bus frequency in factory is ~397kHz. Change-Id: I3d0b0388343d4c6c5e7eabf3e06799d059307517 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/21669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-25mb/lenovo/x2?0/devicetree: Fix regression of BDC detectionPatrick Rudolph
The x220 and x230 do have BDC detection, but it's broken. Disable BDC detection on those two boards, and add a comment why it doesn't work. The issue has been reported and tested on Lenovo X220. Change-Id: Id1ccc2c4387370e284ff8964e1c41d945cefe74c Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/21587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-23mb/intel/dg43gt: Add romstage timestampsArthur Heymans
Change-Id: I0383dd9b582d5c77be66ecd74bcf1a438f874cc7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21635 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-23mb/intel/dg43gt: Set SuperIO gpio correctlyArthur Heymans
Set SuperIO GPIO like vendor firmware. Change-Id: I46a48776382eb0d9be9727691c68912991e14dfe Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21627 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-23mb/*/*: Remove rtc nvram configurable baud rateArthur Heymans
There have been discussions about removing this since it does not seem to be used much and only creates troubles for boards without defaults, not to mention that it was configurable on many boards that do not even feature uart. It is still possible to configure the baudrate through the Kconfig option. Change-Id: I71698d9b188eeac73670b18b757dff5fcea0df41 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/19682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-22mb/asrock/g41c-gs: Fix the SATA clock output on ck505Arthur Heymans
With reset default of the clockgen on this board the SATA clock which needs to be 100MHz depends on FSB BSEL straps. This explains why SATA was originally tested to be working but fails with CPUs operating at different FSB. This change sets a bit in the clockgen configuration which fixes the SATA clock. TESTED on with a 1333MHz FSB CPU. Change-Id: Ic2b8ca91920f015ae3265871bc092023302fefdc Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21257 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-09-22mb/intel/d510mo: Use common ramstage driver to configure the ck505Arthur Heymans
TESTED, the screen doesn't jiggle (caused by wrong clock on reset default clockgen configuration) Change-Id: Icfa22daf90f9e2eff13b4fc5994664e96903dd1e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-22mainboard/intel/cannonlake_rvp: enable SATABora Guvendik
Set sata enable FSP parameters. Change-Id: Ie4723b37f0a2028d22f0a344e45a1ded51deecd0 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21407 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-22mb/purism/librem13v2: Remove redundant MAINBOARD_VENDOR settingJonathan Neuschäfer
Unlike Chromebooks, Purism laptops are only sold under one vendor name, so MAINBOARD_VENDOR only needs to be set in src/mainboard/purism/Kconfig. Change-Id: If0b33df01ff3327272d089b7efb8e64fa1233fdf Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/21591 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Youness Alaoui <snifikino@gmail.com>
2017-09-21google/celes: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/celes (Samsung Chromebook 3) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new celes variant - Add new trackpad I2C device to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-celes-7287.92.B, commit 9f0760a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Id52d3c523bae7745b3dc04da012ab65c1fb37887 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-21google/banon: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/banon (Acer Chromebook 15 CB3-531) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new banon variant Sourced from Chromium branch firmware-strago-7287.B, commit 02dc8db: Banon: 2nd source DDR memory (Micro-MT52L256M32D1PF) Change-Id: If29e95deee88b79522547e16fc80c2d5378da7c7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21571 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-21google/terra: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/terra (Asus Chromebook C202SA/C300SA) as a variant of the cyan Braswell baseboard. - Add board-specific code as the new terra variant - Add code to the baseboard to handle terra's unique thermal management - Add new shared SPD files to baseboard Sourced from Chromium branch firmware-terra-7287.154.B, commit 153f08a: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Ib2682eda15a989f2ec20c78317561f5b6a97483a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21570 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-21amd/gardenia: Fix number of memory channelsMarc Jones
Gardenia (with Stoney Processor) has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. Change-Id: If49b6a9f37b2687ea2f64105fb9e476a89aa87ed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21602 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-21superio/winbond/*: Unify w*_set_clksel_48()Keith Hui
This function is identical throughout all Winbond superios in the tree, so move it into superio/winbond/common/early_init.c, renamed from early_serial.c because it now does more than just early serial. Change all affected mainboards to use the unified function. Change-Id: If05e0db93375641917e538d83aacd1b50fbd033b Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-09-21siemens/mc_apl1: Move SCI to IRQ 10Mario Scheithauer
IRQ 9 is used for different purpose on this mainboard so move SCI away to IRQ 10. Change-Id: I7f055447f5d92bc4696b38e8103a7aebde95d9d3 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-21mb/google/{poppy,soraka}: Enable LTR for Root portRizwan Qureshi
Enable LTR for Root port 0, where wifi card is connected. BUG=b:65570878 TEST=After enbaling LTR on port 0 on the MB devicetree, No errors reported by AER driver for root port 0. Change-Id: I222a87fe2094c8424760ccf578e32b9ac042f014 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21548 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rajat Jain <rajatja@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20vboot: reset vbnv in cmos when cmos failure occursAaron Durbin
There's an occasional issue on machines which use CMOS for their vbnv storage. The machine that just powers up from complete G3 would have had their RTC rail not held up. The contents of vbnv in CMOS could pass the crc8 though the values could be bad. In order to fix this introduce two functions: 1. vbnv_init_cmos() 2. vbnv_cmos_failed() At the start of vboot the CMOS is queried for failure. If there is a failure indicated then the vbnv data is restored from flash backup or reset to known values when there is no flash backup. BUG=b:63054105 Change-Id: I8bd6f28f64a116b84a08ce4779cd4dc73c0f2f3d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/21560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-20google/kahlee: Prevent AGESA memory clearMarc Jones
The Linux Pstore area must not be cleared on a reboot. Set the option to not clear the memory in AGESA. BUG=b:64193190 BRANCH=none TEST=Memory clear isn't called in AGESA. Change-Id: I9b8286ade718fa80bf3badd478ab9a7df643ab98 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21596 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-20google/kahee: Fix number of memory channelsMarc Jones
Kahlee has a single memory channel, not two. This corrects DMI type 17 reporting and the memory clear functions. BUG=b:65403853, b:64193190 BRANCH=none TEST=AGESA DMI reports the correct number of DIMMs. Change-Id: Ic263d2677a480448beaf3850391b1a3d4ed38657 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19mainboard/intel/cannonlake_rvp: Add PCI, PCIE IRQs to DSDT tableBora Guvendik
Change-Id: Id0b2b9e9ae2755ed89cee337a1a085fc4e95b073 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-19AGESA binaryPI: Clean up amdfamXX.h includeKyösti Mälkki
Change-Id: Iba8b8d33e1f10e28745234988d97d4fafd04c798 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21583 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2017-09-16mb/google/poppy: Add lens_focus property for OV13858 camera moduleV Sowmya
Add lens_focus property with reference to VCM device for OV13858 camera module to register the corresponding v4l2 sub-device asynchronously. BUG=b:64133998 BRANCH=none TEST=Build and boot soraka. Dump DSDT and verified that it has the required entries and verified the camera functionality. Change-Id: Ib22403f668dd07d6b9226fe2c22b533223b69473 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/21512 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-16google/lulu,gandof: set kb backlight on bootMatt DeVillier
Set keyboard backlight to 75% on boot, except when resuming from S3. This enables the backlight at a reasonable level prior to the OS driver taking over, providing early proof-of-life and enhanced usability in grub etc. Uses same method as other google boards with a keyboard backlight (chell, link, samus). 75% value determined based on user feedback. TEST: boot google/lulu,gandof boards, observe keyboard backlight enabled in pre-OS environment. Change-Id: I7ed59289419af21764b1b5bd0a534d3b630c6c6b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21330 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16google/reks: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/reks (Lenovo Chromebook N22/N42) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new reks variant - Add new I2C touchscreen device and SPD files to the baseboard for potential reuse by other variants Sourced from Chromium branch firmware-reks-7287.133.B, commit 7d812d4: Revert "Revert "soc/intel/braswell: Populate NVS SCC BAR1"" Change-Id: Iac9e2b5661aa33e12927f4cb84ebaee36522a385 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16google/edgar: add new board as variant of cyan baseboardMatt DeVillier
Add support for google/edgar (Acer Chromebook 14 CB3-431) as a variant of the cyan Braswell basebaseboard. - Add board-specific code as the new edgar variant - Add common code to the baseboard which will apply to all variants other than cyan Sourced from Chromium branch firmware-edgar-7287.167.B, commit 2319742: Edgar: Add Micron MT52L256M32D1PF-107 SPD data Change-Id: I58548cbbc85828f37c0023e8aa9e09bdca612659 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2017-09-16mainboard/intel/glkrvp: Add support for audioHannah Williams
This patch adds the below: 1) Add correct SSP endpoint config for spk and headset 2) Update GPIO config for jack detection 3) Update GPIO config for I2S pins TEST=sound card binds TEST=cross checked SSDT entries from /sys/firmware/acpi/tables/ TEST=Jack interrupt works Change-Id: I32022ddacd79917730080889c040f842e0c9e6b9 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/19799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-15mainboard/intel/cannonlake: Add ec entry into flashmapLijian Zhao
Add EC entries into chromeos.fmd file. BRANCH=None BUG=None TEST=Flash image and confirm system can get out of reset successfully. System will not be able to reach reset vector if flash map described in coreboot does not match intel flash map generated from fit. Change-Id: Ic18ce59941b4ff8171fe661d332e3e521d988341 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-15mb/google/poppy: enable AER for PCIe root port 0Rizwan Qureshi
Enable PCIe Advanced Error Reporting for PCIe root port 0. BUG=b:64798078 TEST="lspci" shows that AER is enabled in the capabilities list. Change-Id: I8a818a9539b8d4f103d551ffd59713c9bbbc13ce Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/21425 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-15google/cyan: convert to variant configurationMatt DeVillier
Setup cyan to be the baseboard for other Google Braswell boards, to be added in subsequent commits: - Keep code common to all Google Braswell boards in the baseboard, and separate out the board-specific bits into the new cyan variant. - Define the I2C ACPI devices such that they can be easily reused for other variants. - Switch the trackpad/touchscreen interrupts from edge to level, for better performance/compatibility, as was done with all previous Google boards. - Add code to the baseboard to allow optional variant-specific parameters to be used for both memory and silicon init. - Remove superfluous includes, replace some hardcoded values with variables, and correct typos/formatting errors. Change-Id: Iabbbad16efa9cfa79338f4e94d0771779900d8d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/21126 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14mainboard/intel/cannonlake_rvp-u: Configure USB portsPratik Prajapati
Configure USB2, USB3 and Type-C ports for CannonLake-U RVP Change-Id: Id875063721ccb62ad4b5187c81f6abf44bf93f74 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14mainboard/intel/cannonlake_rvp-y: Configure USB portsPratik Prajapati
Configure USB2, USB3 and Type-C ports for CannonLake-Y RVP Change-Id: Ic3b6b481cb33bfefb267910a5e649877d900d109 Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-on: https://review.coreboot.org/21481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-14siemens/mc_apl1: Add delay to wait for legacy devicesWerner Zeh
There are old legacy onboard devices which are too slow for a coreboot boot with log level BIOS_ERR. In this case coreboot is so fast that these devices do not have enough time to become visible on the PCI bus and this in turn leads to missing resource allocation for this devices. The most generic way to work around this problem on existing hardware is to introduce a delay right before the PCI enumeration starts. The needed delay time depends on the hardware and will therefore be get from hwinfo. Change-Id: Ia91babc81e3a347bbc498c3def97b2ea70e10922 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/21518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2017-09-13AGESA vendorcode: Move PlatformInstall.hKyösti Mälkki
All thse Option.*Install.h files are about configuring what eventually is referenced in the final libagesa build. It's self-contained so isolate these together with PlatformInstall.h to hide them from rest of the build. Change-Id: Id9d90a3366bafc1ad01434599d2ae1302887d88c Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mb/google/soraka: Update DPTF parametersWisley Chen
Cloned from baseboard/dptf.asl and update the parameters for soraka. 1. Update DPTF CPU/TSR0/TSR1/TSR2 passive/critial trigger points. CPU: passive point:85, critial point:100 TSR0: passive point:55, critial point:65 TSR1: passive point:58, critial point:70 TSR2: passive point:60, critial point:75 TSR3: passive point:60, critial point:75 2. Set PL1 Max to 7W, and PL1 Min 4.5W 3. Change sampling period of thermal relationship table (TRT) setting CPU: 5 seconds TSR0: 30 seconds TSR1: 30 seconds TSR2: 8 seconds TSR3: 8 Seconds BUG=b:65467566 TEST=build, boot on soraka, and verified by thermal team. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I6af93fa358a037df2088213ee4df5e2cfd047590 Reviewed-on: https://review.coreboot.org/21453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13mb/google/soraka: Fine-tune USB 2.0 port4Wisley Chen
Fine tune usb 2.0 strength for port 4 to pass eye diagram. BUG=b:65306272 TEST=build on soraka, measure usb2.0 eye diagram, and result is pass. Change-Id: I2c79e96e2e3dea1364d7b71af19b57f4c9307fcb Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/21403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-09-13asus/p2b-ls,asus/p3b-f: Move to EARLY_CBMEM_INITKeith Hui
These two boards have been boot tested with EARLY_CBMEM_INIT and is good to go. Change-Id: I2e69901ed83502894f6794b3c1d7bab9aab95e51 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/21351 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-13google/snappy: Update EC keyboard backlight flag by SKU IDKevin Chiu
Set AP SKU ID by ec command EC_CMD_SET_SKU_ID to update EC keyboard backlight flag. BUG=b:65359225 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I1153aa0b89250c55f311dd93a01fcef47afd7292 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/21400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mainboard/intel/cannonlake_rvp: Include ChromeOS supportLijian Zhao
Add ChromeOS support for cannonlake_rvp platform. Change-Id: Ia02407da8ab4aac2c2c33a7796fc71aea12e2925 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-13mainboard/intel/cannonlake_rvp: Add dummy DSDT tableLijian Zhao
Add dummy ACPI DSDT table for cannonlake rvp platform. Change-Id: If45c2a7da7f5b20ddd3d56bf9d7f68a85d2f791d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/21427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12mb/intel/dg43gt: Fix smbus IRQArthur Heymans
This board uses the reset defaults for DxxIP and DxxIR. The datasheet "Intel ® I/O Controller Hub 10 (ICH10) Family" mistakenly says in the D31IP register that all function have INTB as default. This is however not true as documented in the reset default value. This fixes the DSDT such that the SMBus device gets a route for the INT C interrupt it uses. Change-Id: I3dd1308fb7acec86b90ecd9d2079cf9a58702c40 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21442 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2017-09-12mb/intel/dg43gt: Select right gmbus port for VGA outputArthur Heymans
TESTED: NGI works on VGA with adapter on DVI-I port Change-Id: I4bd9d451295d26a3e11ded9863f5d45d42c8fead Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-09-12mb/intel/dg43gt: Configure clockgenArthur Heymans
This makes the VGA output on the DVI-I connector usable. This reuses vendor settings. Change-Id: Ib8b6bf33816f7e468a09ff5e2008c2cb9f7c0a8b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/21440 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-09-12AGESA boards: Clean up Ids.h and Filecode.h includesKyösti Mälkki
Change-Id: I9cb63ff58900a39d7cd8e3da2b9a9a95c2a41a69 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Drop heapManager.h includesKyösti Mälkki
Change-Id: I1a96b1c6181cd657d7aee82370ef86acd688cc94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA CIMX: Remove empty set_pcie_(de)resetKyösti Mälkki
For boards with cimx/sb800, mainboards defined only empty stubs. Reset functionality is handled as BiosCallout. For amd/inagua, the defined function was actually initial GPIO programming. For cimx/sb700, function had prototypes but no callers. For cimx/sb900, everything was commented out already. Change-Id: I936feb4fc41d903078620c919a733bb9f39c3efb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21477 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-12AGESA boards: Clean up some includesKyösti Mälkki
Change-Id: I84c70aa04ab556a3898d3525f7b9aab85812f61d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21475 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-11mb/lenovo/*/devicetree: Add BDC detection supportPatrick Rudolph
Add support for BDC detection, based on the schematics for each board. Support for boards without schematics needs further testing. Needs test on all boards. Change-Id: If33ef88fb808f36b050393fa83eb1b541ce936b9 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/19810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2017-09-11mainboard/intel/cannonlake_rvp: enable eMMCBora Guvendik
Set SCS emmc enable FSP parameter. Change-Id: Ib3d7a305c3bede439249204cf14d50e3eb8b6915 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/21409 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2017-09-11kahlee: Add RO_VPD region in FMAPMarc Jones
The RO_VPD region is required for ChromeOS. BUG=b:65408869 TEST=Build and check coreboot.rom with fmap_decode. Change-Id: I9c475acc5e34a3a41f815990fb1f363963c7b9b9 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/21473 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-08siemens/mc_apl1: Disable internal UARTsMario Scheithauer
APL internal UARTs are not used on this mainboard. Change-Id: I39118262fc6f37b45785538a3f2d1d31d42cbe86 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-08siemens/mc_apl1: Set bus master bit for on-board PCI deviceMario Scheithauer
There is one on-board PCI device where bus master has to be enabled in PCI configuration space. As there is no need for a complete PCI driver for this device just set the bus master bit in mainboard_final(). Change-Id: I45202937eba11da3bea14fef6ebed70599804335 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/21405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-09-06google/gru: Re-enable 3V rail GPIO on ScarletJulius Werner
We've decided to move control for the 3.0V rail (technically 3.3V on Scarlet, but who cares about millivolts) back to a GPIO on the AP for Scarlet rev2. This patch adds the necessary code to enable it and make ARM TF aware of its existence. Since the pin had previously not been connected to anything, we shouldn't really need to guard this by board ID... older Scarlets will just be twiddling an empty pin. Change-Id: I6037aa486b50119f2c7b859b966cadc3686e3459 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/21328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Schneider <dnschneid@chromium.org>
2017-09-06AGESA f14: Work around soft-resetsKyösti Mälkki
Vendorcode expects some DRAM controller registers to be writable, but they are actually locked after soft resets if C6 states are enabled. Without the workaround, raminit fails on soft resets. Change-Id: I6b9e275e11b2907d026c13341334983a4d9c8889 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06mainboard/lippert: Refactor SEMA watchdog messageKyösti Mälkki
It's too critical to ignore when sending the message on SMBus fails, so allow for a fair amount of retries. Failure here causes watchdog to do hard reset later. Move it out of mainboard.c as we need to call this early in romstage while we are debugging. Change-Id: I1006b079269d6dd44de630db7a5694124af2f974 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06asus/kgpe-d16: Add romstage_handoffKyösti Mälkki
Fix regression caused by commit 9e94dbf ACPI: Get S3 resume state from romstage_handoff Boards with EARLY_CBMEM_INIT are required to provide romstage_handoff structure to signal S3 resume path. Change-Id: I7c9065ccc48dfbdefade698ed275756f17dff7a0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-09-06asus/kcma-d8: Add romstage_handoffKyösti Mälkki
Fix regression caused by commit 9e94dbf ACPI: Get S3 resume state from romstage_handoff Boards with EARLY_CBMEM_INIT are required to provide romstage_handoff structure to signal S3 resume path. Change-Id: I464feb1655a51a937b6cf53508dd5c7aa0d8f791 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21395 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2017-09-06asus/kcma-d8 kgpe/d16: Fix regression for shutdownKyösti Mälkki
Fix regression caused by commit: 714709f AMD fam10 ACPI: Use common fixed sleepstates.asl Adding common sleepstates.asl got lost in rebase process. Change-Id: I4f22ee950ae5637113db8e79ca238cb1b81002aa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/21413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Iru Cai <mytbk920423@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-15 20:54:15 +0000