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2023-04-18mb/amd/mayan: Correct PCIe bridge for M.2 NVMe SSD0Anand Vaikar
The M.2 NVMe SSD0 device is behind AMD PCIe bridge 0.2.4 (BDF), hence update the correct bridge number in the device tree. TEST: Builds and boots, the device enumerates. [DEBUG] PCI: 00:02.4 [1022/14ee] enabled [DEBUG] PCI: 01:00.0 [144d/a80a] enabled Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Change-Id: I43096beda0405bd392574319d50e7cd6a7f8d291 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-18mb/google/brya/var/omnigul: Adjust I2Cs CLK to be around 400 kHzJamie Chen
Need to tune I2C bus 0/1/3/5 clock frequency under the 400kHz for audio, TPM, touchscreen, and touchpad. Tuning i2c frequency for omnigul I2C0 - Audio CLK : 293.7khz I2C1 - TPM CLK : 388.8khz I2C3 - Touch Screen CLK : 294.8khz I2C5 - Touch Pad CLK : 389.2khz BUG=b:275061994 BRANCH=firmware-brya-14505.B TEST=emerge-brya coreboot, and measure i2c clock. Change-Id: I7c4fdf0e003318a69b870b487a60accefbc0ffed Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74393 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-17Makefiles: Drop redundant VARIANT_DIR definitionsKyösti Mälkki
Change-Id: Ie75ce1eee3179a623da812a6b76c7ec457684177 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74470 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
2023-04-17mb/google/dedede/var/boten: Generate SPD ID for supported memory partkevin3.yang
Add boten supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Samsung K4U6E3S4AB-MGCL BUG=b:278138388 TEST=Use part_id_gen to generate related settings Signed-off-by: kevin3.yang <kevin3.yang@lcfc.corp-partner.google.com> Change-Id: I5f910393847c6494f77c009cb11f50b31bebffb6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-17mb/google/rex: Enable all DDI lanesAnil Kumar
This patch enables all DDI ports on Rex board to support display port tunneling and dual display on TBT dock. BUG=b:273901499 TEST=Boot google/rex and connect two displays over a TBT dock and check the display functionality. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I45ee5334fbb877bd58912c8d24920037f155dc42 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74413 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-17mb/google/brya/variants/hades: Update GPIO configsTarun Tuli
Update GPIO configs based on latest schematics (revision aabe36) Move GPP_D4->GPP_A13 (BT_DISABLE_L) Swap GPP_E3<>GPP_E8 (WIFI_DISABLE_L and PG_PPVAR_GPU_NVVDD_X_OD) Move GPP_A13->GPP_A20 (GSC_PCH_INT_ODL) BUG=b:269371363 TEST=builds Change-Id: I958e45156515cf4ce236084ec823f9329d7a063d Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73909 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-17mb/google/nissa/var/craask: Add GTCH7503 and split TS by SSFCTyler Wang
Add G2 touchscreen GTCH7503 for craaskino. Use SSFC to separate touchscreen settings. Bit 38-41 for TS_SOURCE: (1) TS_UNPROVISIONED --> 0 (2) TS_GTCH7503 --> 1 BUG=b:277979947 TEST=(1) emerge-nissa coreboot (2) Test on craaskino with G2 touchscreen (3) Test on craaskino with elan touchscreen Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: I636f21be39f26a617653e134129a11479e801ea2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-16mb/google/rex: Create screebo variantSimon Zhou
Create the screebo variant of the rex0 reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:276814951 BRANCH=None TEST=util/abuild/abuild -p none -t google/rex -x -a make sure the build includes GOOGLE_SCREEBO Change-Id: I8d05ca7c0fe596378ca15d0734d46ad1dc63a1f9 Signed-off-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74391 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-15sb,soc/amd,intel: Add and use ACPI_COMMON_MADT_LAPICKyösti Mälkki
Boards with SOC_INTEL_COMMON_BLOCK_ACPI_CPU_HYBRID have special handling for the time being. Change of aopen/dxplplusu is coupled with sb/intel/i82801dx. Change of emulation/qemu-i440fx is coupled with intel/i82371eb. For asus/p2b, this adds MADT LAPIC entries, even though platform has ACPI_NO_MADT selected. Even previously ACPI_NO_MADT creates the MADT, including an entry for LAPIC address. Change-Id: I1f8d7ee9891553742d73a92b55a87c04fa95a132 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74316 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-14mb/google/corsola: Add detachable Starmie as variantRuihai Zhou
The 'Starmie' is a mt8186 detachable reference design that will share most of Corsola design. For AP firmware, there will be a few changes, mostly in display (MIPI interface and w/o bridge), so we create it as a variant in Corsola. BUG=b:275470328 BRANCH=corsola TEST=./util/abuild/abuild -t google/corsola -b starmie -a Change-Id: Ic1556ad0031e9a24bf26fa84d7713b7b7928312a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-04-14mb/google/corsola: Add support for VIO18 in regulator.cCong Yang
Add regulator VIO18 support to supply power for STA_HIMAX83102_J02 panel. BUG=b:272425116 TEST=test firmware display pass for STA_HIMAX83102_J02 on Starmie. Change-Id: Ie1dd9226b0c4f05f9c9ce6633b7384aa5eb4c978 Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74342 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14mb/google/dedede/var/kracko: Add G2touch touchscreen supportRobert Chen
Add G2touch touchscreen support for kracko. BOE NV116WHM-T04 V8.0 with G7500 touch panel sensor IC BUG=b:277852921 BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot & test on DUT Change-Id: Ic065d5dc2900c6ccfee09031f7a80cefc391f5dd Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74307 Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-14mb/google/hades: move PCIEXP_SUPPORT_RESIZABLE_BARS to commonEric Lai
All the variant will use the same dGPU, so make PCIEXP_SUPPORT_RESIZABLE_BARS common. BUG=b:277974986 TEST=abuild -a -x -c max -p none -t google/brya -b hades Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: If8618f2da3133c6b52427375c55a69d7014c4881 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74371 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Disable keyboard reset pinJon Murphy
The keyboard reset is not being used on this board, so disable the functionality. BUG=b:277294460 TEST=None Change-Id: If7fb9ab0c9b1260d342313badb65c55bb9f788c0 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74285 Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/brya/acpi: Add support for GPS_REQUESTDXSTATETarun Tuli
Implement the GPS_REQUESTDXSTATE function which forces the current D notifier state to re-report. TEST=verified that notifications are forced out when invoked using acpiexec BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I6dab9b793fe1d0b1c875eddbe6ae324d2894efe6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73890 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: Add support for forcing notifications in DNOT funcTarun Tuli
Currently the DNOT function first checks to see if the current DNOT value has already been reported. Add support to allow forcing regardless if it had been sent already. TEST=confirmed that when enabled, all events notify. When disabled, only events on value change are notified. BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I7a93cca6a8f922574dd46b46572b230755db9aa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: Pass GPS_FUNC_SUPPORT as 8 byte bufferTarun Tuli
Currently the value was being truncated to 4 bytes. Change so that the full 8 byte value is passed. TEST=verified function returns expected value using acpiexec BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: Icfc775de680e328a2b240595223d7098fee3dc3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/73899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: LTOB - Add support for a 8 byte integer to bufferTarun Tuli
This function adds support to convert a integer into a 8 byte buffer TEST=verified returned buffer is as expected using acpiexec BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I89eb50f1452657c26b97eb5609ed956fa8ee8117 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73898 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/brya/acpi: Correct _DSM GPS function for revision checkTarun Tuli
The logic was not equals, rather than the intended greater than or equal to for checking the minimum GPS revision. TEST=version check passes as expected now BUG=b:271938907 Signed-off-by: Tarun Tuli <taruntuli@google.com> Change-Id: I66bf1fc32295e1b9e9c41c661ea8e395a1592a86 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73897 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/dedede: Create taranza variantDavid Wu
Create the taranza variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:277664211 BRANCH=dedede TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_TARANZA Change-Id: Id64e48ff2acd6e827fe586a00376183930ddc7e1 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74295 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/lenovo/x200/blc: Add LTN121AT07-L02 at 750HzBill XIE
Its EDID string is "LTN121AT07L02". The vendor sets BLC_PWM_CTL to 0x31313131. This frequency seems working well on the x200 with this panel, which is said to be LED. Change-Id: I8b0ec04c6f6fcb6d4027a5114698db87d7718191 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74182 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2023-04-13mb/google/nissa/var/yaviks: Update GPIOs to support yavillaShon Wang
Yavilla is a variant of yaviks which is almost identical to yaviks, so is reusing the yaviks coreboot variant. so update the GPIO tables to handle these based on fw_config. BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I831b199055c931e7a4a393eeb9e75e83c8ae3c3a Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74264 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/nissa/var/yaviks: Select VBT based on FW_CONFIG for yavillaTony Huang
Select hdmi vbt bin files based on MB_HDMI field of FW_CONFIG. BUG=b:277148122, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I210003c27c83155dd5a768c1a6cdcfd8c849d256 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74262 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/nissa/var/yaviks: Update devicetree based on FW_CONFIG for yavillaTony Huang
Yavilla will leverage yaviks FW build. It has one additional USB Type-A0 port, support stylus and support WWAN. Here update devicetree based on FW_CONFIG for yavilla's design. -Enable USB2 port3 and USB3 port1 for USB2/3 Type-A0 -Enable USB2 port5 and USB3 port3 for WWAN -Enable pen garage -Enable rear mipi cam -Enable Synaptics touchpad BUG=b:277148122, b:276369170 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I38dbcf5920d12adb1f84885bdfa4c2f2faf2eb9e Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-04-13mb/google/myst: Add initial I2C configurationJon Murphy
Add I2C peripheral reset configuration required during early init. Enabled I2C generic and HID drivers. BUG=b:275939564 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I44668295fb6ed03992df9d9fc075792e181d1a8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74108 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-13mb/google/myst: Enable elogJon Murphy
Enable ELOG for Myst. BUG=b:275938975 TEST=builds Change-Id: I214e2dbaa3bc40c3f4ca68c8ee4b1398446d7090 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74282 Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Add ACPI configuration for USB portsJon Murphy
The USB port configuration was derived from the PPR and schematics. Primary functions are: 2 USB-C ports 1 USB SS+ type A port 2 Cameras (World/User facing) 1 Bluetooth transceiver 1 WWAN BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Iecb256cad7b2daea1fddfc8323e88ff5c38d1e51 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Van Patten <timvp@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Enable XHCI controllersJon Murphy
Enable the XHCI controllers in the devicetree for myst project. BUG=b:275905635 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I05dc5bb157f0ef955e4b37e34d7b32678e42ebc8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-13mb/google/myst: Enable internal graphicsJon Murphy
Enable internal graphics on the phoenix soc for myst projects. BUG=b:275900162 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ia6ef1ca07b9af491c7d937be5cef4f051852e486 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74104 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/amd/birman/port_descriptors_*: use DDI_DP_W_TYPEC type for DDI 2..4Felix Held
DDI 2..4 are the display outputs multiplexed onto the 3 USB type C ports as DisplayPort alternate function, so use the DDI_DP_W_TYPEC connector type for those. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I659d62bfb426e3e47214203490c34e9c200beee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74299 Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12mainboard/google/skyrim: Fix MP2 FW namingMarshall Dawson
Update the blob type for TypeId0x25_Mp2Fw_MDN_AD03.sbin to subprogram 0. Delete the extra MP2FW line. BUG=b:246770914 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Change-Id: I5418b1ed59e1916b971d2eece9f6a2fd0e51b1b3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>
2023-04-12Revert "soc/intel/{tgl,adl}: Hook up D3ColdEnable UPD to D3COLD_SUPPORT"Michael Niewöhner
This reverts commit 6bfca1b689e48be4f72e8fa401f3558d845fc282. Reason for revert: dependency for revert CB:73903 Change-Id: I56bab4d85d04e90cacfe77db59d0cde6a8a75949 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-12mb/google/myst: Enable iommuJon Murphy
Enable iommu in devicetree for myst in order to allow kernel to load and initialize IOMMU. Bug=b:276805280 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I94e93afe775b070253464a9d187ad6c028d1b811 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74177 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/google/myst: Enable console UARTJon Murphy
Enable the console UART for myst devices. Bug=b:275900837 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I52c1b86c46907216d88f98917968b833af0d5d41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74103 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Tim Van Patten <timvp@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12mb/google/myst: Add FW_CONFIGJon Murphy
Add initial FW_CONFIG for the myst program. BUG=b: TEST=builds Cq-Depend: chrome-internal:5674351 Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If74c3649d4e8d174d9fe00a4b896c2351ee3ab19 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12mb/google/myst: Enable eSPI SCI eventsJon Murphy
Enable EC SCI events for eSPI. BUG=b:275894894 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I8fd858c484f6fcf952bcb4f756ba2e4728091d8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74101 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-12mb/google/nissa/var/yaviks: Generate SPD ID for new memory partsTony Huang
Add supported memory parts in mem_parts_used list, and generate SPD ID for these parts. These new memory are added for yavilla. DRAM Part Name ID to assigna H58G66BK7BX067 4 (0100) MT62F2G32D4DS-026 WT:B 4 (0100) K3KL9L90CM-MGCT 4 (0100) H58G66AK6BX070 5 (0101) BUG=b:277148122 BRANCH=firmware-nissa-15217.B TEST=run part_id_gen to generate SPD id Change-Id: I3c48b9763f54e2e69f7c2d494fefbabedab2a389 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74228 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/google/rex: remove weak from cros gpioEric Lai
No need for variant to use _weak. BUG=b:276818954 TEST=new_variant_fulltest.sh rex0 Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Change-Id: I7ad904e06e5d83edf4bc11cafd5060ca409bd4ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74294 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-12mb/google/nissa/uldren: Configure the external V1p05/Vnn/VnnSxDtrain Hsu
This patch configures external V1p05/Vnn/VnnSx rails for Uldren to follow best practices for power savings – untested though. * Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3, S4, S5 , S0 states. * Set the supported voltage states. * Set the voltage for v1p05 and vnn. * Set the ICC max for v1p05 and vnn. BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I3ff8e7db33bfbe4048327825406462262e8d2919 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74335 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12mb/google/skyrim: Remove mainboard LIDS ACPI objectKarthikeyan Ramasubramanian
With EC's lid switch implementation, there is no need to maintain the lid switch state in mainboard. Hence remove LIDS ACPI object from mainboard. BUG=None TEST=Build Skyrim BIOS image and boot to OS. Read the lid switch state correctly through /proc/acpi/button/lid/LID0/state. Change-Id: I0f8dc7216337268c421a475f54ee5b28abf33d08 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-12mb/starlabs/starbook/adl: Enable OverCurrent 3 GPIOSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I9971209539aa7b74e55673141902b6ad0d698e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73985 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12mb/starlabs/starbook/adl: Fix OC pin configSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I1c4bdab44f0d73546f52614917dccbe71f0911a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73984 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-12mb/intel: Add 2 SPR sockets CRB Archer CityJonathan Zhang
Intel Archer City CRB is a dual socket CRB with Intel Sapphire Rapids Scalable Processor chipset. The chipset also includes Emmitsburg PCH. It was tested with LinuxBoot payload on both dual and single socket configurations. The multisocket support depends on Change-Id: I4a593252bb7f68494f4ccce215ac9cf1eb19b190 Change-Id: Ic02634cd615e2245e394f10aad24b0430cf5cd17 Signed-off-by: Jonathan Zhang <jonzhang@meta.com> Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71968 Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11mb/google/myst: Add smihandlerJon Murphy
Add SMI handler code for Myst platform. BUG=b:275858191 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I92e5e6aef7ab0b84a96d976e29ebf96b56f6f1a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74100 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-11mb/google/myst: Enable chromeOS ECJon Murphy
BUG=b:270624655 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id18a311097d575973087eb92fd446a5c511f570e Reviewed-on: https://review.coreboot.org/c/coreboot/+/74099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11mb/google/myst: Enable variants for MystJon Murphy
BUG=b:270618107 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I688e9c2fdf203cecfd5f200dec6cde9dbc0a9aa7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11mb/google/rex: Add DTT thermal settings for thermal controlSumeet Pawnikar
Add DTT thermal settings for thermal control provided by thermal team for rex0 board BRANCH=None BUG=b:262498724, b:270664854 TEST=Built and verified thermal entries in ACPI SSDT on Rex board Change-Id: I00dd97b759c8c68edaeeb4d64422b83c5e86981d Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71166 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/siemens/mc_ehl2: Fix GPIO settings for latest HW revisionMario Scheithauer
With the latest hardware revision, the two GPIOs GPD11 and GPP_C8 are no longer used. BUG=none TEST=Checked output verbose GPIO debug messages Change-Id: Ia06f93aee4eccb0e4230f0c3ef53922d42701f21 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74201 Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2023-04-11util/sconfig: Remove unused ioapic and irq keywordsArthur Heymans
Ioapic information in the devicetree was only used to set up mptables but this generic driver was removed (ca5a793 drivers/generic/ioapic: Drop poor implementation). This removes the unused remainders from mainboard devicetrees. Remove ioapic setup from sconfig. Change-Id: Ib3fef0bf923ab3f02f3aeed2e55cf662a3dc3a1b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2023-04-11mb/google/skyrim: Enable UPD usb3_port_force_gen1 for MarkarthJohn Su
From request, all type C port limit to to Gen1 5GHz. So enable UPD usb3_port_force_gen1 for Markarth. BUG=b:273841155 BRANCH=skyrim TEST=Build, verify the setting will be applied on Markarth. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I9314b67a82ad2993c87f0110db5ec927caaa772b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74087 Reviewed-by: Patrick Huang <patrick.huang@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Chao Gui <chaogui@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-11mb/google/brya/variants/hades: Update GPU power sequencing to add Hades supportTarun Tuli
Add GPU power sequencing changes for the Hades baseboard and variant. Some signals were added, moved or inverted. Based on implementation from Agah. Moved signals: GPIO_1V8_PWR_EN GPP_E11 GPIO_NV33_PWR_EN GPP_E2 GPIO_NV33_PG GPP_E1 New signals: GPIO_NV12_PWR_EN GPP_D0 GPIO_NV12_PG GPP_D1 Inverted signals: GPIO_FBVDD_PWR_EN GPP_A19 ifdef's will be dropped once the Agah variant is retired. BUG=b:269371363 TEST=builds and verified on Agah that DGPU is still detectable (lspci) Change-Id: I0b8efe7a34102cf61d4f784103c4a4f9337213f7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73896 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
2023-04-11mb/lenovo/x200: Read EDID in mainboard_vbt_filename()Bill XIE
mainboard_vbt_filename() used to assume that it is called after a call to get_blc_pwm_freq_value() with a valid parameter, but currently it is the first call of get_blc_pwm_freq_value(NULL), and will return 0, so "data_led.vbt" is always returned, regardless of the actual type of the panel. Combined with the previous commit, in this commit mainboard_vbt_filename() will explicitly read EDID string via gm45_get_lvds_edid_str() and use this string to call get_blc_pwm_freq_value(). Resolves: https://ticket.coreboot.org/issues/475 Tested on my x200s with LTD121EQ3B (LED), and x200 with LTD121EWVB (CCFL). Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I2e080b29321b6989d1f26b6c67876b3d703042f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74181 Reviewed-by: Swift Geek (Sebastian Grzywna) <swiftgeek@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-11mb/intel/mtlrvp: Update Debug Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the MTLRVP debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ie635e3cce1c3fd771e6a17e4b3c1bd700f4729bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/74254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/google/rex: Update Debug Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the Rex debug flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Increase to 7.5MB. RW_LEGACY: Introduce with 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 2MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I4ab69eb24937d58c8bc5d3c0a6e5cb70b843a1ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/74253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/intel/mtlrvp: Update Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the MTLRVP flash layout to optimize WP_RO to 4MB. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot intel/mtlrvp with FSP release and debug image. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ibd1ea7a3a2cd21928b8e33473c7bdddfad17c636 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-11mb/google/rex: Update Flash Layout to fit WP_RO within 4MBSubrata Banik
This patch updates the Rex flash layout to optimize WP_RO to 4MB. The idea is to create more space inside FW_RW_A/B to accommodate multiple blobs to boot google/rex with different Intel MTL SoC stepping. Changes for chromeos.fmd: SI_BIOS: RW_SECTION_A/B: Reduce to 7MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Increased to 1MB. RW_UNUSED: 3MB (reserved) WP_RO: Reduce to 4MB Additionally, ensure RW_SECTION_B region starts at 16MB boundary in the SPI Flash. BUG=b:277143384 TEST=Able to build and boot google/rex with FSP release and debug image. Change-Id: Iccf83b7bb66d0d5503e0ff9e9a819051296c6724 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74229 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-11mb/intel/mtlrvp: Enable PCIe port 6 and RTD3 support for x1 slotCliff Huang
This change enables PCIe x1 slot. In addition, it turns off 3.3v and 12v power and assert PERST# when suspend and turn on the power and deassert the PERST# when resume for the x1 slot. NOTE: Kconfig flag and required GPIO pins are already configured. - /soc/intel/meteorlake/Kconfig select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3 - gpio.c: /* GPP_A18: X1_PCIE_SLOT3_PWR_EN */ PAD_CFG_GPO(GPP_A18, 1, DEEP), /* GPP_A19: X1_DT_PCIE_RST_N */ /* SRCCLKREQ: GPP_C12: SRCCLKREQ3_GEN4_X1_DT_SLOT3_N */ PAD_CFG_NF(GPP_C12, NONE, DEEP, NF1), BUG=b:224325352 BRANCH=None TEST=Insert a SD card or NIC AIC on PCIe x1 slot and the AIC should be detected and enabled at boot. For S0ix, run 'suspend_stress_test -c 1'. The RP6 should not cause any suspend and resume issue. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Id2e92acf754569a22ea76a68c91aafce0075a742 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73054 Reviewed-by: Harsha B R <harsha.b.r@intel.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Jérémy Compostella <jeremy.compostella@intel.com> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/sarien: Use runtime detection for touchscreensMatt DeVillier
Now that power sequencing has been implemented, switch from using ACPI "probed" flag to "detect" flag for all i2c touchscreens. This removes non-present devices from the SSDT and relieves the OS of the burden of probing. TEST=build/boot Windows/linux on drallion, verify touchscreen functional in OS, dump ACPI and verify only i2c devices actually present on the board have entries in the SSDT. Change-Id: I3b91a628cd4a9edb5d5a7521529f39b75935e1d0 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/sarien: Set touchpad/screen IRQs to LEVEL vs EDGEMatt DeVillier
Ensure the GPIOs themselves are configured as level triggered, as well as the devicetree entiures. I2C-HID spec requires LEVEL trigger, and the drivers (both Linux and Windows) work better with LEVEL vs EDGE trigger. TEST=tested with rest of patch train Change-Id: I4fba55c938f401876798c2b32c5922523f32180f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/sarien: Implement touchscreen power sequencingMatt DeVillier
For touchscreens on sarien, drive the enable GPIO high starting in romstage while holding in reset, then disable the reset GPIO in ramstage. This will allow coreboot to detect the presence of i2c touchscreens during ACPI SSDT generation (implemented in a subsequent commit). BUG=b:121309055 TEST=tested with rest of patch train Change-Id: I3ce7bfc0fa4c03c0bb96bebaa3c3d256f886ecc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/sarien: Add method to set GPIOs in romstageMatt DeVillier
Add method variant_romstage_gpio_table() with empty implementation to be used in a subsequent commit for touchscreen power sequencing. Call method in romstage to program any GPIOs that may need to be set. TEST=tested with rest of patch train Change-Id: I11b72a10a4a105385fbcf1d795c020708a7a90d9 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-10mb/google/brya: Compile gpio.c in SMM when neededMatt DeVillier
Without gpio.c compiled in, SMMSTORE will fail to initialize and hang. Add a conditional inclusion so gpio.c is compiled in SMM when SMMSTORE is selected. TEST=build/boot google/banshee with SMMSTORE support enabled Change-Id: If049cba98f13f060807058029306dcad2ada2d49 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tarun Tuli <taruntuli@google.com>
2023-04-10mb/google/poppy/var/nami: Fix stylus runtime detectionMatt DeVillier
Stylus reset GPIO needs to be held low in romstage, released in ramstage for runtime i2c detection to pick it up. TEST=build/boot AKALI360 variant, verify stylus detected in cbmem, functional in OS. Change-Id: I2e7f2a28f6b3a71b0c8fc367168cffbe3f064663 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2023-04-10mb/google/fizz/var/fizz: update VBTMatt DeVillier
Deselect the 'fixed resolution at boot' and 'eFP attached' options via the Windows BMP tool. Fixes HDMI audio output under Windows 10/11. TEST=build/boot Win 11 on Fizz, verify HDMI audio now functional. Change-Id: Iecede735bc1266af837e791e6c024aec2f9a8a80 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74235 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/brya/var/omnigul: Add usb_lpm_incapable for DB Type-C portDtrain Hsu
Intel ADL-P USB Type-C ports are not compatible with Parade PS8815 retimer on USB U1/U2 transition. The usb_lpm_incapable config is used to disable USB U1/U2 transition for these Type-C ports. BUG=b:277149723 BRANCH=firmware-brya-14505.B TEST=Plug in device and check LPM sysfs nodes are disabled localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u1 disabled localhost ~ # cat /sys/bus/usb/devices/2-3/power/usb3_hardware_lpm_u2 disabled Change-Id: I618cd09f45ede0a76cf46b3e467ba87775dd5d9d Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ron Lee <ron.lee@intel.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-10mb/google/geralt: Power on Samsung ATNA33XC20 eDP panelJianeng Ceng
Geralt uses Samsung panel, and Mutto is responsible for bonding the panel and touch, so rename the panel description. Add power-on sequence for Samsung ATNA33XC20 panel. EDID Info: header: 00 ff ff ff ff ff ff 00 serial number: 4c 83 62 41 00 00 00 00 28 1e version: 01 04 basic params: b5 1d 11 78 02 chroma info: 0c f1 ae 52 3c b9 23 0c 50 54 established: 00 00 00 standard: 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 descriptor 1: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 2: 35 36 80 a0 70 38 20 40 30 20 88 00 26 a5 10 00 00 1b descriptor 3: 00 00 00 0f 00 d1 09 3c d1 09 3c 28 80 00 00 00 00 00 descriptor 4: 00 00 00 fe 00 41 54 4e 41 33 33 58 43 32 30 2d 30 20 extensions: 01 checksum: 6f BUG=b:276097739 TEST=test firmware display pass. Signed-off-by: Jianeng Ceng <cengjianeng@huaqin.corp-partner.google.com> Change-Id: Ibd2d05c7eef1360ca954316f2e76b21ed1f85be8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74115 Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: jason-ch chen <Jason-ch.Chen@mediatek.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: Build for chromeOSJon Murphy
Adjust build configs to build Myst for chromeOS. BUG=b:270618097 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: If4b6917fe024067409bfbb3d2691c37759b5cace Reviewed-on: https://review.coreboot.org/c/coreboot/+/74097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-04-10mb/google/brya/var/marasov: Configure Acoustic noise mitigationFrank Chu
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to SLEW_FAST_8 - Set FastPkgCRampDisable VCCIA and VCCGT to 1 BUG=b:271788117 TEST=build FW and system power on. Signed-off-by: Frank Chu <Frank_Chu@pegatron.corp-partner.google.com> Change-Id: I411c91e1e70285afbf31750a56a039d60bbe093f Reviewed-on: https://review.coreboot.org/c/coreboot/+/73491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tracy Wu <tracy.wu@intel.corp-partner.google.com> Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
2023-04-10mb/google/myst: Declare CrOS GPIOsJon Murphy
Declare CrOS GPIOs for Myst, add relevant defines needed by chromeOS for additional control GPIOs. BUG=b:270616013 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ie876883d6ee2e3bc6324c038cefee12d99702dc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74096 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: First pass GPIO configuration for MystJon Murphy
Initial GPIO configuration for Myst. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Ia019704c7b027f14d46281e0de0ffdbc4906a20b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74095 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-10mb/google/myst: Add stubs to configure GPIOsJon Murphy
Add configuration stubs for GPIOs to be implemented later. BUG=b:270596581 TEST=builds Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: I3228f857da7c8c76cf32faf4a23418aedaf40875 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74094 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-10mb/google/myst: Add new mainboardJon Murphy
Myst is a new Google mainboard with an AMD Phoenix SOC. BUG=b:270596106 TEST=util/abuild/abuild -t GOOGLE_MYST --clean Signed-off-by: Jon Murphy <jpmurphy@google.com> Change-Id: Id7d731ce4d6cb6d4e9041f46eb5a799865bb0b9a Reviewed-on: https://review.coreboot.org/c/coreboot/+/74093 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-04-08ec/lenovo/pmh7/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:135:22: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .backlight_enable = 0x01, ^~~~ /cb-build/coreboot-toolchain.0/clang/LENOVO_W500/mainboard/lenovo/t400/static.c:136:23: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .dock_event_enable = 0x01, ^~~~ Change-Id: Icd35224877fee355e1bbb8a8e838cb047604babb Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73810 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-08sb/intel/i82801gx/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:66:19: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .c4onc3_enable = 1, ^ /cb-build/coreboot-toolchain.0/clang/APPLE_IMAC52/mainboard/apple/macbook21/static.c:75:32: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .p_cnt_throttling_supported = 1, ^ Change-Id: I691b51a97b359655c406bff28ee6562636d11015 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-08sb/intel/i82371eb/chip.h: Use 'bool' instead of 'int'Elyes Haouas
This to fix following error using Clang-16.0.0: CC romstage/mainboard/emulation/qemu-i440fx/static.o build/mainboard/emulation/qemu-i440fx/static.c:31:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .ide0_enable = 1, ^ build/mainboard/emulation/qemu-i440fx/static.c:32:17: error: implicit truncation from 'int' to a one-bit wide bit-field changes value from 1 to -1 [-Werror,-Wsingle-bit-bitfield-constant-conversion] .ide1_enable = 1, ^ Change-Id: I36cc19bc2908119fe940941e108ee217a7b26f50 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73794 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2023-04-07mb/google/brya: Enable asynchronous End-Of-PostJeremy Compostella
Set the `SOC_INTEL_CSE_SEND_EOP_ASYNC' flag to request End-Of-Post right after PCI enumeration and handle the command response at `BS_PAYLOAD_BOOT'. With these settings we have observed a boot time reduction of about 20 to 30 ms on brya0. BUG=b:268546941 BRANCH=firmware-brya-14505.B TEST=Tests on brya0 with `SOC_INTEL_CSE_SEND_EOP_ASYNC' show End-Of-Post after PCI initialization and EOP message received at `BS_PAYLOAD_BOOT'. Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Change-Id: Ib850330fbb9e84839eb1093db054332cbcb59b41 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74215 Reviewed-by: Tarun Tuli <taruntuli@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-06mb/intel/mtlrvp: Use `-` over `.` in chromeos-debug-fsp.fmdSubrata Banik
This patch renames debug FMD file (chromeos.debug-fsp.fmd) to chromeos-debug-fsp.fmd in order to match the file path name in `FMDFILE` config. TEST=Able to build intel/mtlrvp with this code change. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: Ic8de07e4befa6b1ab8ab57d593c6939d87c48e9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-04-06mb/google/skyrim: override Markarth PCIe configJohn Su
Because Markarth PCIe port 1 use for eMMc not SD. So we need override PCIe config for Markarth. And also the Markarth have NVMe and eMMC SKU. Follow Winterhold to look at the NVMe CLKREQ signal before initializing the ports allowing us to identify which device is populated and only initialize that device. BRANCH=none BUG=b:275669215 TEST=emerge-skyrim coreboot chromeos-bootimage Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: I0b4e4067a30019d742c7589a52badf93b7091615 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74133 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-05mb/google/skyrim: Remove unused sleep GPIO tableKarthikeyan Ramasubramanian
On Skyrim, there isn't a need for a sleep GPIO table. Remove the TODO and filler table and function to reduce unnecessary function overhead. BUG=None BRANCH=Skyrim TEST=Build Skyrim BIOS image. Change-Id: Ia9d55a5e2295bb2e2c2957c4f5207362f616022c Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jon Murphy <jpmurphy@google.com>
2023-04-05Revert "mb/google/brya: Enable asynchronous End-Of-Post"Nick Vaccaro
This reverts commit 11f2f88a277124713f7b0023f078fcc2e1a98c32. Revert initial change as it was causing a boot failure when transitioning into recovery mode. BUG=b:276927816 TEST='emerge-brya coreboot chromeos-bootimage', flash and boot a skolas SKU1 to kernel, then press Esc-Refresh-PowerButton to try to reboot into recovery mode. Change-Id: I91c8d0434a2354dedfa49dd6100caf0e5bfe3f4c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74206 Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Eran Mitrani <mitrani@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/starlabs/*: Add CMOS entries for the mirror flagSean Rhodes
Add the required CMOS entries for the mirror flag, so that it can be enabled from a defconfig. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I174ac896df050480ee90c8141c5536b628c98432 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73682 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/starlabs/starbook/adl: Add an option to enable Hot PlugSean Rhodes
Some third-party SSDs, from Samsung and WD, such as the 990 Pro and WD Black 850X aren't initialised by coreboot, seemingly as coreboot is too quick; debug builds work, and enabling hotplug does. Add a cmos option `pci_hot_plug`, defaulting to enabled to allow these SSDs to work. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I680211bc87153a5e6005d58040a94725c0973451 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-04-04mb/starlabs/starbook: Disable ASPM in corebootSean Rhodes
ASPM is already configured by FSP so disable it in coreboot to reduce boot time by a whopping 34ms. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I073c68dafa9baa90e253b5230f84b0de6a7e5c47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73982 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-04-04mb/starlabs/starbook/adl: Remove Soundwire workaroundSean Rhodes
This was added to solve Debian 10 not booting. Debian 10, which now isn't the latest stable version works, so remove the workaround that was included in the original port. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ic11f355eb218ff3bad00fff83537c99c1b6985bc Reviewed-on: https://review.coreboot.org/c/coreboot/+/72669 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-04mb/google/brya/var/omnigul: Add ADL and RPL dptf settingsJamie Chen
Add Alder Lake (ADL) and Raptor Lake (RPL) dptf settings for omnigul BUG=b:273415170 BRANCH=firmware-brya-14505.B TEST=FW_NAME=omnigul emerge-brya coreboot Change-Id: I8280f82ff1534ea63bcb448da231712bb4abd6d3 Signed-off-by: Jamie Chen <jamie_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-04Revert "mb/starlabs/*: Remove sleepstates.asl"Sean Rhodes
This reverts commit ac69ce91229dee68d4135c596f49cf9e5efbe1e9. Reason for revert: Removing breaks suspend in kernels > 6.2 and Windows. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I3e90266e66192b328b9af51c5e614774a248ddf0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
2023-04-04mb/google/rex: Enable CSE pre-cpu timestampsBora Guvendik
Enables pre-cpu boot timestamps from cse. 990:CSME ROM started execution 0 944:CSE sent 'Boot Stall Done' to PMC 47,000 945:CSE started to handle ICC configuration 225,000 (178,000) 946:CSE sent 'Host BIOS Prep Done' to PMC 225,000 (0) 947:CSE received 'CPU Reset Done Ack sent' from PMC 516,000 (291,000) 991:Die Management Unit (DMU) load completed 587,000 (71,000) 0:1st timestamp 597,427 (10,427) BUG=b:259366109 TEST=Boot on rex, check "cbmem -t" Change-Id: I68cd53c18af6a400bcd9dc15d428a904b0647495 Signed-off-by: Bora Guvendik <bora.guvendik@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73759 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-04-04soc/intel/alderlake: Add support for CSE timestamp data versionsBora Guvendik
CSE performance data timestamps are different for version 1 Alder Lake/Raptor Lake and version 2 Meteor Lake. This patch moves the current ADL/RPL timestamp definitions to a separate header file. It marks current structure as version 1. BUG=b:259366109 TEST=Boot to OS, check ADL/RPL pre-cpu timestamps. Change-Id: I780e250707d1d04891a5a1210b30aecb2c8620d3 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73712 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com>
2023-04-04mb/google/mtlrvp: Update MTLRVP Flash LayoutUsha P
This patch updates the MTLRVP flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. SI_BIOS: SI_EC: Removed RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:271407315 TEST=Able to enable CSE update on MTLRVP and have free space to add one more PUNIT FW to support different SoC stepping. Signed-off-by: Usha P <usha.p@intel.com> Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762 Reviewed-on: https://review.coreboot.org/c/coreboot/+/73378 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-04-04mb/intel/mtlrvp: Add fmd for debug FSPUsha P
Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for MTL-P RVP flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. BUG=b:271407315 TEST=Build intel/mtlrvp with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: Ief7dd39af018c4c1519ca80d1303085d8298cda6 Signed-off-by: Usha P <usha.p@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74193 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
2023-04-03mb/google/rex: Use FW_CONFIG for generating ACPI code for WIFISubrata Banik
This patch avoids creating runtime ACPI for unused WIFI solutions. For example: if the Rex SKU is with WIFI_CNVI then you don't need to populate ACPI code for WIFI_PCIE. FW_CONIG can be used for making those decisions. TEST=No ASL entries being created for WIFI_PCIE if the FW_CONIG is set to WIFI_CNVI. Also, helped to save the boot time on google/rex (FSP-S API) by 9ms. Change-Id: I60e4332d8d8c360fdf425b30513ff79209979e85 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74147 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-03mb/amd/birman/port_descriptors: split files for phoenix/glindaFred Reitberger
Glinda and Phoenix have different requirements, so split the birman port_descriptors file to betty apply to each SoC. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ia28cf4172b6adada10809e0135b2459077fa3da0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2023-04-03mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_empMorris Hsu
Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2 RX signal integrity issue. BUG=None TEST=build FW and check Type-A USB3 port0/port1 RX pass Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0 Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-04-03mb/google/brya/variants/hades: Add CPU power limitsTarun Tuli
Add CPU power limits support and values for RPL on Hades BUG=b:269371363 TEST=builds Change-Id: I22ef56152abe5a23067c5e923b07d60dc9fac8e7 Signed-off-by: Tarun Tuli <taruntuli@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73895 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-04-03arch/ppc64/rom_media.c: move to mainboard/emulation/qemu-power*Krystian Hebel
CBFS location in memory is different than on the real hardware. Change-Id: Icd806a57f449042c883b624056c05c1ff7e4c17e Signed-off-by: Krystian Hebel <krystian.hebel@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Kopeć <michal.kopec@3mdeb.com>
2023-04-03mb/google/nissa/var/uldren: Add overridetreeVan Chen
Add override devicetree based on schematics(ver. 20230308). BUG=b:272829190 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9cd918c6a48cc6007a18c5aa94afe31fd9608718 Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73974 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: John Su <john_su@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
2023-04-02soc/intel/alderlake: Add ADL-P 4+4 with 28W TDPPatrick Rudolph
Add the 28W TDP version of the ADL-P with MCHID 0x4629. Verified that all 28W SoCs have the same PL1/PL2 defined in Intel document #655258 "12th Generation Intel Core Processors Datasheet, Volume 1 of 2". Fixes the error seen in coreboot log: [ERROR] unknown SA ID: 0x4629, skipped power Limit Configuration Change-Id: Iad676f083dfd1cceb4df9435d467dc0f31a63f80 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74116 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
2023-04-01mb/google/rex: Add FW_CONFIG for FP/UWB/WIFISubrata Banik
This patch adds FW_CONFIG to accommodate different Rex BoM components across various SKUs. 1. Fingerprint sensor - FP Present/Absent 2. Ultra wideband - UWB Absent/Using BITBANG/Using GSPI1 3. WIFI - CNVi/PCIe TEST=Able to build and boot google/rex. Change-Id: I97b0dc25f239103a0a235f14b50008a633e2f88d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com>
2023-04-01mb/google/rex: Update Rex Flash LayoutSubrata Banik
This patch updates the Rex flash layout to allow CSE Lite FW update and accommodate multiple ESx SoC stepping blobs. For default chromeos.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.9MB. RW_LEGACY: Reduce to 1MB. RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections Additionally, moved RW_LEGACY under extended BIOS region. For chromeos-debug-fsp.fmd SI_BIOS: RW_SECTION_A/B: Increased by ~1.2MB. RW_LEGACY: Dropped RW_MISC: Reduce to 152KB. - Drop RW_SPD_CACHE - Optimize other sections BUG=b:262868089 TEST=Able to enable CSE update on google/rex and have free space to add one more PUNIT FW for support different SoC stepping. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I6146b36c4ce2c0141277eeb906d6ad1f503f3c78 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66288 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-04-01mb/google/rex: Add fmd for debug FSPSubrata Banik
Debug FSP is ~920KiB larger than release FSP and we don't have sufficient space for rex flash layout. Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a room for it. Note: This fmd will only used for internal testing/debugging and not for the firmware in released devices. BUG=b:262868089 TEST=Build google/rex with CONFIG_BUILDING_WITH_DEBUG_FSP. Change-Id: I58b0af9c43c5d096dc80084497b39f13f67c25cd Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 07:35:21 +0000