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Remove baseboard gpio.c and rely on variant override.
Change-Id: I4657b1aa2c81a990b750e163e948b8495d8b97c7
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37512
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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ACPI method TEVT is reported as unused by iASL (20190509) when ChromeEC support is not
enabled. The message is “Method Argument is never used (Arg0)” on Method (TEVT, 1, NotSerialized),
which indicates the TEVT method is empty.
The solution is to only enable the TEVT code in mainboard or SoC when an EC is used that uses
this event. The TEVT code in the EC is only enabled if the mainboard or SoC code implements TEVT.
The TEVT method will be removed from the ASL code when the EC does not support TEVT.
BUG=N/A
TEST=Tested on facebook monolith.
Change-Id: I8d2e14407ae2338e58797cdc7eb7d0cadf3cc26e
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Mainboards exist with a 4+1 MiB flash chip combination.
Change-Id: I214553a2c70e1a4a0e4d972fee5e524b609bb1e0
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add VBTs for all rambi variants, extracted from VGA BIOS
from stock firmware images using intelvbttool.
Test: boot several rambi variants using MrChromebox edk2/master
branch with Baytrail GOP driver and extracted VBTs.
Change-Id: I401ae5accd852fc5211092a5944fc85871b642ae
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Add VBTs for jecht variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy.
Use a common VBT for all except tidus, since it differs
from the others.
Change-Id: I570bdb749ef7d49f41539074220bb16c9c100342
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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This impacts boards:
hatch (&variants) and drallion.
Some variants like Puff can have up to 12 cores. coreboot should take
the min() where MAX_CPU is the upper bound.
Further to that, boards themseleves shouldn't be setting the MAX_CPUS,
the chipset should be and so do that.
BRANCH=none
BUG=b:146255011
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: I284d027886f662ebb8414ea92540916ed19bc797
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Shelley Chen <shchen@google.com>
Reviewed-by: Mathew King <mathewk@chromium.org>
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Switching was done by moving a SIO configuration and
a clocks setup from 'romstage.c' to 'bootblock.c'
TEST=Boots into Ubuntu Linux 16.04.6 without a problem.
Change-Id: I7a972b531183b08af7b325bd686cf3eb7558082f
Signed-off-by: Sergej Ivanov <getinaks@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Now RCOMP_TARGET_PARAMS is defined and used once in the definition of
the RcompTarget structure. All other structures in these functions use a
fixed value.
Replace RCOMP_TARGET_PARAMS with fixed value.
BUG=N/A
TEST=build
Change-Id: Ibe7c72c65975354433e9a0c613bda715eb782412
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37658
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add VBTs for beltino variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy. Use
a common VBT for all except monroe, since it differs as
it has a built-in display (being a Chromebase vs Chromebox).
Change-Id: I82afb20a5648695c2cd568384a26839ab28be3da
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37733
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Update VBT using file extracted from VGA BIOS from stock
firmware image using intelvbttool, zero-padded to 0x11ff
bytes to make the Intel BMP editor happy.
Change-Id: I9f53e80305ec8de78a3d5c930224b394b5c8618a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37732
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add VBTs for all auron variants, extracted from VGA BIOS
from stock firmware images using intelvbttool, zero-padded
to 0x11ff bytes to make the Intel BMP editor happy.
Test: boot several auron variants with libgfxinit and Tianocore
payload, ensure both internal and external displays as well as
HDMI audio function properly under Linux (4.x/5.x).
Change-Id: Ibc4eabfa5d02b4c08755cf52835b5df8c1291fea
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Also, don't define the default as this results in spurious lines in the
.config.
TEST: Build all boards with where config.h differed with
BUILD_TIMELESS=1 and remained the same
Change-Id: Ic77b696f493d7648f317f0ba0a27fdee5212961e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/31316
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add an fmd file with a layout that allows configuring the system for
measured boot without enabling verified boot.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: I85fc6bee3f28fa4454d43df0e8bd1e511e1d0caf
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37673
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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cbfstool doesn't support % tag yet while this was in the fmd.
Revert the fmd changes that use the % tag.
BUG=N/A
TEST=build
Change-Id: I2dc8b8f56ee0890e01be3bed939ed922feb15e89
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Update signal names and GPIO configuration.
Remove unused GPE_EC_WAKE and EC_XXX_GPI defines.
BUG=N/A
TEST=tested on facebook monolith
Change-Id: Iae5edb8418894a669ed49c2d78672d8957010f3c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Remove the sarien_cml and arcada_cml subdirectories from the
drallion/variants directory.
BUG=b:140068267
TEST=./build_packages --board=drallion
Confirm that drallion still builds successfully.
BRANCH=none
Change-Id: I9648965ca222d4d68bf73738716ad1c93739b03f
Signed-off-by: Mike Wiitala <mwiitala@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Mathew King <mathewk@chromium.org>
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As per the 4.11 release requirement, C_ENVIRONMENT_BOOTBLOCK=y
is a mandatory feature, which most AGESA and binaryPI boards lack.
Disable such platforms from the build for the time being.
The Kconfig symbol has been flipped, ROMCC_BOOTBLOCK=n is the
same mandated feature as C_ENVIRONMENT_BOOTBLOCK=y.
If a platform does not reach ROMCC_BOOTBLOCK=n within a
reasonable timeframe both the mainboard and the respective
unused platform support code will get removed.
Change-Id: I7fceb0370f7f4f5f52080277c5d21615d3ab3454
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37355
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: I1d7127e2f9bd5bd9677feb2b0e686a854c4e3885
Signed-off-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37727
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ib27c518fb5ce99e17be25b974ff5adc8c6b3f3a6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37570
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ie9918e5114bb880e37680a85eab2bd224b0b082c
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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BRANCH=none
BUG=b:146172098
TEST=./util/abuild/abuild -p none -t google/hatch -x -a
Change-Id: Ib2da3baace9255ef25c0f03390a064fd77ef9ae5
Signed-off-by: Edward O'Callaghan <quasisec@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37696
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Change-Id: Ie14db10b6a72e19ac67254ca8f95bcf6ac8af8d3
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo@cyberdimension.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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No special treatment required for bootblock.
Change-Id: I1a08d4da94ab34bf62fbfdd2cb66f2b44a847916
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37452
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=boot PC Engines apu1 with C bootblock patch and launch
Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I36af6d3871a57f462a7508745663d9759de1c47d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37332
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With LPC decode enables explicitly set in C env bootblock,
this call can be delayed to happen before AMD_INIT_RESET.
Change-Id: I3a28eaa2cf70b770b022760a2380ded0f43e9a6f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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On nocturne, the VBT specifies that the native panel resolution
(3000x2000) is to be used by FSP/GOP init, which makes payload
and grub menus extremely difficult to read. Change the default
POST resolution specified by the VBT to 1500x1000 instead
(200% scaling) which is much more legible.
Test: build/boot nocturne with GOP init and Tianocore payload,
observe menu text is actually readable.
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Change-Id: I767a2b8319c7673e3460acfad534140409bf1d57
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37621
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These entries have no functional purpose, followup work will
disallow chip entries that do not link in the respective
driver.
Change-Id: Ieab695022d0dd2f2671f9058db97bdd6fb29a10d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Confirmed with Goodix team, so increase reset delay time
from 120ms to 150ms.
BUG=b:144267684
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I4ff95ac89314fc031620ca28e4f6e6e26cdef3f9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37544
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. SKU ID 1 and 3 for eMMC
2. SKU ID 2 and 4 for SSD
BUG=b:144815890
BRANCH=firmware-hatch-12672.B
TEST=FW_NAME="akemi" emerge-hatch coreboot
chromeos-bootimage
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I25f0c4142be024ba55f671491601d1f6ec26d68a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37498
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Philip Chen <philipchen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ibe2d92990d0074266aa05ada749e9dad55e609a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37541
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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No special treatment required for bootblock.
Change-Id: I0036614579045b62829577bb2ae94266b2d62310
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37500
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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No special treatment required for bootblock.
Change-Id: Icb673bba1ba210a077e9569de70b6c4f3cbd1e6b
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37499
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I603e6c83d72cf6c1d8f8c6eef652fdf954a3a284
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37453
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add early SuperIO initialization in bootblock to enable early console.
Also, remove some southbridge-specific initialization that has been
moved to southbridge bootblock initialization in previous patch.
The board obtains few additional timestamps: start of bootblock, end
of bootblock, starting to load romstage and finished loading romstage.
TEST=boot apu2 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: If770eff467b9a71d21eeb0963b6c3ebe72a88ef3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36915
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Fix for CB:35086.
Build the Ricoh SDcard driver that is defined in devicetree.
Change-Id: Ib0ac3da088d798c35e2c5ea045ea721c89d9e12f
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37625
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Defines in onboard.h are moved to other files.
Remove this empty and unused file.
BUG=N/A
TEST=build
Change-Id: Ide10b352eadcffad2d4221865124f64466af5a1c
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37615
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Items in onboard.h are related to verified or measured boot.
Move the items to board_verified_boot.h and remove onboard.h.
BUG=N/A
TEST=build
Change-Id: Icfc8d6d8351f0654c277e81c7f3cc2b0a947866a
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37614
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now that we have a CONFIG_NO_FMAP_CACHE to completely configure out the
pre-RAM FMAP cache code, there's no point in allowing the region to be
optional anymore. This patch makes the section required by the linker.
If a board doesn't want to provide it, it has to select NO_FMAP_CACHE.
Adding FMAP_CACHE regions to a couple more targets that I think can use
them but I don't know anything about... please yell if one of these is
a bad idea and I should mark them NO_FMAP_CACHE instead.
Change-Id: Ic7d47772ab3abfa7e3a66815c3739d0af071abc2
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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While Merlin Falcon binaries are not available, make it explicit that it's
compiling for Prairie Falcon (it was being surreptitious about it).
Board Padmelon accepts 3 different SOC, just changing some resistors
(soldered or not): Brown Falcon, Prairie Falcon and Merlin Falcon. Code for
Brown Falcon is not currently available.
BUG=None
TEST=Build with prairie falcon.
Change-Id: I1663e4403a32a7d626dd2fa06763f18f4230457e
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add package and APU selections to mainboards and remove symbols no
longer used in soc//stoneyridge.
Change-Id: I60214b6557bef50358f9ec8f9fcdb7265e04663b
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37225
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Make a new Kconfig symbol for using soc//stoneyridge. This code also
supports Prairie Falcon is backward-compatible with Carrizo and Merlin
Falcon.
Although Bettong uses Carrizo, it does not currently rely on stoneyridge
source, so it is unaffected by this change.
Change-Id: I786ca54b0444cbcf36dc428a193006797b01fc09
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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The stoneyridge code inferred that if Merlin Falcon was built but no
Merlin Falcon binaries were present, the intent must be Prairie Falcon.
The two falcons are Embedded variants, and Prairie Falcon falls within
Family 15h Models 70h-7Fh.
Add a Prairie Falcon symbol that can be used explicitely. Drop
HAVE_MERLINFALCON_BINARIES.
Change-Id: I0d3a1bc302760c18c8fe3d57c955e2bb3bd8153a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37223
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Denary, also known as "decimal" or "base 10," is the standard
number system used around the world. Therefore, make use of it.
Change-Id: Ia22705d7629a322292cfd557add9cfadc649c16c
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37537
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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According to the POSIX standard, %p is supposed to print a pointer "as
if by %#x", meaning the "0x" prefix should automatically be prepended.
All other implementations out there (glibc, Linux, even libpayload) do
this, so we should make coreboot match. This patch changes vtxprintf()
accordingly and removes any explicit instances of "0x%p" from existing
format strings.
How to handle zero padding is less clear: the official POSIX definition
above technically says there should be no automatic zero padding, but in
practice most other implementations seem to do it and I assume most
programmers would prefer it. The way chosen here is to always zero-pad
to 32 bits, even on a 64-bit system. The rationale for this is that even
on 64-bit systems, coreboot always avoids using any memory above 4GB for
itself, so in practice all pointers should fit in that range and padding
everything to 64 bits would just hurt readability. Padding it this way
also helps pointers that do exceed 4GB (e.g. prints from MMU config on
some arm64 systems) stand out better from the others.
Change-Id: I0171b52f7288abb40e3fc3c8b874aee14b9bdcd6
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37626
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: David Guckian
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Fixed value of ACPI_FADT_REV_ACPI_2_0 is replaced by
get_acpi_table_revision().
BUG=N/A
TEST=build
Change-Id: I95b0d886b73f94bc880c0e3e7d512211d2d33e21
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Tuning i2c frequency for dratini:
I2C0: 396 KHz
I2C1: 398 KHz
I2C3: unused
I2C4: 394 KHz
BUG=b:145891557
BRANCH=hatch
TEST=emerge-hatch coreboot chromeos-bootimage
Change-Id: I1431554fbce5f3ce113ef1a934e39448e7ba321c
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37605
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the additional tabs on all lines.
BUG=N/A
TEST=build
Change-Id: I02b1314fe2ae89da3659b198c12df9c30c8a039d
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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SDCARD_CD is defined in onboard.h but required in ASL only, move this
define to dsdt.asl.
Removed the onboard.h file from the ASL files that don use it.
BUG=N/A
TEST=build
Change-Id: I35b75e0ae2e2bc4ce143aaec6df6016774676095
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37610
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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File contains header only.
Remove header leaving an empty file.
BUG=N/A
TEST=build
Change-Id: I8b1c6b38bd7936cc7af11c13744325bed23a6e83
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Make code more readable.
Replace 1 by IGD_MEMSIZE_32MB for PcdIgdDvmtS0PreAlloc.
BUG=N/A
TEST=build
Change-Id: I5d84e575935e9e60610e1805e1402f290672b114
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Follow thermal table for first tuning.
BUG=b:144464314
TEST=Built and tested on drallion
Change-Id: I4546622cdc6efb2bf2eb973cfc5c6f22c40cc6ef
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36860
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: If40fa38e5b249452a6dacf4a4045b6bd00c27cfa
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37580
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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ITE8258_CMD_PORT is used in com_init.c only.
Replace ITE8258_CMD_PORT by fixed value in the c file.
ITE8258_DATA_PORT is removed as this isn't used.
BUG=N/A
TEST=build
Change-Id: I401da3f127db9e65763fd8d115eb274fbadbefbe
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37609
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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This change sets TCC offset to 10 for kohaku.
BUG=b:144532818
BRANCH=firmware-hatch-12672.B
TEST=Checked thermal and performance efficiency internally (b:144532818)
Change-Id: Ia4b53de3a53bc39c1cd0f7626ae23d4c11a7a3db
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37587
Reviewed-by: Kane Chen <kane.chen@intel.com>
Reviewed-by: Grace Kao <grace.kao@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PCIe root port clock gate is already enabled at i945/early_init.c
Also fix comments when only PCIe root port is enabled.
Change-Id: Ica38529dbdd5cc51b19b426999a1d9f0b678b4f5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37576
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These boards currently have no build-testing, so they degrade
fast. Apply some of the build-tested changes we know to be
good from pcengines/apu2 to get them a bit closer to using
POSTCAR_STAGE=y.
Change-Id: Ibc9a15ed5e91c6dd857f2dd02e37d0979dd6ae90
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37373
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I0646b18e823c52109e0fb62c85726622156172b9
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37385
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I70eabc0b03709409d997ccbe8b8e257d68aec338
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: Ifde5d382eb223bd996b9bb909c751e9d5f0a11e5
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37300
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I53e9e1a8381ca51200dc5306eef32442668607a3
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37299
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: I95dbf55b74deca1e035ee1d042f1549d2583e346
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37298
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: Ia9367d03b6f97f1eb8c35045fd7bb79e5f45b535
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37297
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: I90774e22fb7765f44b6cd4fa05b535236b782023
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37296
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
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Change-Id: Ia77f0ce89b2234b9c164bb326d76bef98949832a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37285
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ia321f2b974539ac1684173d767dd9eb64060364a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37284
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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It is an ATX board similar to existing ga-b75* boards. The major
difference is the configuration of pci-e ports on PCH, and on-board
pci-e NIC. (see below)
Tested:
- CPU i5 3570T
- Slotted DIMM 8GiB*4 from Kingston
- usb2 and usb3
- pci and pci-e ports
- sata
- Sound
- S3
- AR8161 NIC connected to 1c.2 with mac address burnt in efuse
- libgfxinit-based graphic init
- NVRAM options for North and South bridges
- tpm 1.2 on lpc (similar to ga-b75m-d3h)
- Linux 4.19.67-2 within Debian GNU/Linux stable, loaded from
SeaBIOS.
Change-Id: I1a969880e4da02abf8ba73aac60ee1296fe0abf2
Signed-off-by: Bill XIE <persmule@hardenedlinux.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This commit creates a foob variant for Octopus. The initial settings
override the baseboard was copied from variant phaser.
BUG=b:144890301
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ibcdda4dd0846612f5e98ab454db7144c1caf0507
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37456
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change the hex values in the VR configuration tables of the Intel Kaby
Lake RVP boards to the same style that is used in the other mainboards.
Also, correct some numbers in the comment tables that did not match the register values.
The values in the tables haven't changed.
BUG=N/A
TEST=build
Change-Id: I77af544d7d88143e19abedb12a13627779c705c6
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37550
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set the SMBIOS system type to detachable for nocturne and
soraka variants, to allow the OS to correctly process events.
Change-Id: Ie0ee5ea6666542c0bca2c264b2ed2e6135b78658
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Because the function is implemented in C, post_code() calls
from cache_as_ram.S and other early assembly entry files may
not currently work for cold boots. Assembly implementation
needs to follow one day.
This effectively removes PORT80 routing from boards with
ROMCC_BOOTBLOCK.
Change-Id: I71aa94b33bd6f65e243724810472a440e98e0750
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37451
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Change-Id: I934830c09f7996e8f5aae5d5abe9fb6014fb478d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mike Banon <mikebdp2@gmail.com>
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Change-Id: If7816992e717b4da585b16e5bbe67610c9af867d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37294
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Change-Id: Iffeb634c73f58aa1cddac5210d75fda75a3d5e92
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37293
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The board is booting Linux and has been briefly tested.
SeaBIOS, TianoCore payload and Linux as payload all seem to work fine.
BUG=N/A
TEST=tested on Facebook Monolith
Change-Id: I65a2e03334af65cfb3f825d43fa0daa6e6c75913
Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37516
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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TEST=Set MAX_CPUS=2 and run qemu with -smp 2
Signed-off-by: Philipp Hug <philipp@hug.cx>
Change-Id: I94fb25fad103e3cb5db676eb4caead11d54ae0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35246
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Xiang Wang <merle@hardenedlinux.org>
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1. No gpio control in bootblock
2. Disable power and assert reset in ramstage gpio
3. Power on and then deassert reset at the end of ramstage gpio
4. Disable power and assert reset when entering S5
On "reboot", the amount of time the power is disabled for is
equivalent to the amount of time between triggering #4 and wrapping
around to #3, which is about 400ms on Kohaku.
Since #2 forces power off for FPMCU, S3 resume will still
not work properly.
Additionally, we must ensure that GPP_A12 is reconfigured as an output
before going to any sleep state, since user space could have configured
it to use its native3 function.
See https://review.coreboot.org/c/coreboot/+/32111 for more detail.
The control signals have been validated on a Kohaku in
the following scenarios:
1. Cold startup
2. Issuing a "reboot" command
3. Issuing a "halt -p" and powering back on within 10 seconds
4. Issuing a "halt -p" and powering back on after 10 seconds
5. Entering and leaving S3 (does not work properly)
6. Entering and leaving S0iX
BRANCH=hatch
BUG=b/142751685
TEST=Verify all signals as mentioned above
TEST=reboot
flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin
TEST=halt -p
# power back on within 10 seconds
flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin
TEST=halt -p
# power back on after 10 seconds
flash_fp_mcu /opt/google/biod/fw/dartmonkey_v2.0.2417-af88cc91a.bin
Change-Id: I2e3ff42715611d519677a4256bdd172ec98687f9
Signed-off-by: Craig Hesling <hesling@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37459
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch moves the common devicetree settings into baseboard and
creates overridetree.cb for each variant. For PCIe root port settings,
SATA, eMMC, I2Cs and GBe, they are in overridetree.
TEST=build an image for each variant
Change-Id: I067bdb3fcf1218b93e52801f6db093e24d7d2b62
Signed-off-by: Gaggery Tsai <gaggery.tsai@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36794
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This removes the weakly linked function to configure the SPI lockdown.
Change-Id: I1e7be41a9470b37ad954d3120a67fc4d93633113
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36007
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I11b2d75dc0d4ff180b03324e5ce3d5590c8169a5
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37356
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
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Change-Id: I126d1d6b582ea95c97ac55784d44d3081aabdae7
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36232
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The PCH uses the SRCCLKREQ# pin to detect PCIe device in the slot in
order to send clock signal to it. However, this logic is not required
for the Realtek LAN device, since this chip is soldered to the board
and always uses clocking. The chipset can't receive the clock request
signal (most likely this pin isn't connected) and doesn't enable the
CLK. For this reason, the device is broken during the initialization
phase. The patch disables clock request logic for the PCH PCIe port 6
to initialize the onboard LAN device correctly.
Change-Id: I5cbce6177c89052eb50959f43903b6f8a607e77f
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36377
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This reverts commit 0bc35af93326ec3232ec73c9b1334241b85f0252.
Reason for revert: This change breaks runtime s0ix.
BRANCH=hatch
BUG=b:141831197
TEST=Check slp_s0 residency increased when system is idle.
Change-Id: Ida80f55b56de7129ed629eb29bd14f2ef300126f
Signed-off-by: Kane Chen <kane.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37088
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This patch changes all existing instances of clrsetbits_leXX() to the
new endian-independent clrsetbitsXX(), after double-checking that
they're all in SoC-specific code operating on CPU registers and not
actually trying to make an endian conversion.
This patch was created by running
sed -i -e 's/\([cs][le][rt]bits\)_le\([136][624]\)/\1\2/g'
across the codebase and cleaning up formatting a bit.
Change-Id: I7fc3e736e5fe927da8960fdcd2aae607b62b5ff4
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Create new variant for Lick that is copied from phaser variant.
Remove unnecessary code, due to not support touchscreen and stylus.
Set to default_override_table.
Remove variant.c.
BUG=b:145181137
BRANCH=octopus
TEST=./util/abuild/abuild -p none -t google/octopus -x -a
Change-Id: If732d94194defb9f5ee9c847ee93dd58aef01174
Signed-off-by: Hash.Hung <hash1.hung@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37247
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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After adjustment on Drallion
Touch Pad CLK: 393 KHz
Touch Screen CLK: 381 KHz
H1 CLK: 391 KHz
BUG=b:144245601
BRANCH=master
TEST=emerge-drallion coreboot chromeos-bootimage
measure by scope with drallion.
Change-Id: Id669d7199bc6ed4b55d7542f095c6c8baf00f984
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37230
Reviewed-by: Mathew King <mathewk@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All serial I2C bus frequencies should not be over 400KHz in kohaku,
but the measurement showed frequencies of I2C1 and I2C4 were over
400KHz. (b:144885961)
This change adjusts I2C speed settings to limit that frequencies to
400KHz.
The new setting values have been from other projects using same I2C
components, and verified I2C1 and I2C4 frequencies < 400MHz internally.
BUG=b:144885961
BRANCH=firmware-hatch-12672.B
TEST=Verified I2C1 and I2C4 frequency not over 400KHz
Change-Id: I9614fb39b6e55cb2ce1b0879a9f5204e55002f8d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37313
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Tune DPTF to ensure compliance with Akemi thermal design
requirements
BUG=b:144195069
TEST=FW_NAME="akemi" emerge-hatch coreboot chromeos-ec
chromeos-bootimage
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: Ie0e6d93e1fc0c684e067d1450eb119a53cfefaed
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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(Auto-Generated by create_coreboot_variant.sh version 1.0.0).
BUG=b:145101696
TEST=util/abuild/abuild -p none -t google/hatch -x -a
make sure the build includes GOOGLE_STRYKE
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Iea6f8a1c6c24a1e3545c364551cb623debdc4a1a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37229
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I17dc2fed6c6518daf5af286788c98c049088911e
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37366
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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BUG=b:144002424
TEST=Ensured no TPM time out issue and system can boot to OS
Change-Id: I7282e6c2d9627846039638bdc0db3ee7ebba5f12
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37320
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: I9db1147c5e112e5e6832eeece2214fece8aa6b83
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37409
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
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Enable ACPI methods to control privacy screen on Drallion devices.
Drallion devices may not have a privacy screen and it is up to the
EC to determine if the privacy screen is present on the system.
BUG=b:142656363
TEST=emerge-drallion coreboot chromeos-bootimage
Change-Id: I79d02bb1b25f0deb49ae4bb852b7ed8c21fd31c7
Signed-off-by: Mathew King <mathewk@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36045
Reviewed-by: Simon Glass <sjg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I9b2cc1bb58922d9e32202ea4c20b9aacfe308bad
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: I19040cca064c2ce063aab77391e0577271c6e9dc
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37354
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
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Drop the redundant cimx_util, remove the includes when appropriate and
replace the implementation with amdblocks/acpimmio where needed.
TEST=boot PC Engines apu1 and launch Debian with Linux kernel 4.14.50
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I66b1f82926372b6ebb570893b6eb73c7f2935b9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37328
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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configuration
The methods generally tested OP region settings and only changed them if
they were not in their desired values. Instead, assign them directly
without checking them.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I3ceca4bd51c4410c7020431f4fd682c4ca925110
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36746
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The mutex is only used in one method and that method is serialised. Remove
the mutex.
BUG=chromium:959232
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: Ic173d557f4b49cc9e860d13b782fc4940fd80869
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36745
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In particular:
- Set voltage before enabling regulators
- Enable regulators and the clock without any sleeping in between. There's
no need to wait there.
- Sleep 1 ms in order to wait for regulator voltages settling before
lifting xshutdown.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I0f8857ae369d5038f293a0e2c48c681df535ad86
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36744
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In particular:
- Enable regulators *after* configuring the voltage
- Allow 1 ms for the voltages to settle
- Enable clock after powering on regulators
- Remove extra delays between enabling things. The sensor requires 8192
clock cycles after the reset is lifted before I²C access, so 1 ms is
enough.
- Make the delay after lifting xshutdown 10 ms. This guarantees that
streaming will only start once the sensor has had enough time to settle
after lifting the reset.
BUG=chromium:959232
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I4589a7d7ec324f4520572a406cc11ad3feec8b21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36723
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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The PMIC opregion is used to change the direction of two GPIOs for I²C
daisy chain operation. Do this after the PMIC is powered on, not before.
BUG=chromium:959232
Reported-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Tested-by: Jacopo Mondi <jacopo@jmondi.org>
Change-Id: I923987ef21a971df9e32ca03f2da4dccdac07843
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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