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2017-02-17mainboard/poppy: select SOC_INTEL_KABYLAKERizwan Qureshi
poppy is based on Kabylake SoC hence select the appropriate config. Change-Id: Ie339a3991eeccb8a7dba983a2b5ab5d1c996ce9d Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18313 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-17mainboard/google/poppy: Generate digitizer node in SSDTFurquan Shaikh
Add support for generating digitizer node in SSDT using wacom i2c driver. BUG=None BRANCH=None TEST=Verified that the node shows up in SSDT. Change-Id: If7e1e2463778c2ff7263eff995def149457edcde Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18373 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-16mainboard/google/eve: Generate FPC device using SPI SSDT generatorFurquan Shaikh
Use the newly added SPI SSDT generator for adding FPC device. BUG=chrome-os-partner:59832 BRANCH=None TEST=Compiles successfully. Verified that the SSDT entry matches the entry in mainboard.asl Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18343 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-15siemens/mc_apl1: Make basic settings for booting the mainboardMario Scheithauer
This commit makes a basic adjustment for GPIOs, device tree, flash map and MRC settings. With these basic settings the mainboard boots into Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow. Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18292 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-02-15mainboard/google/reef: add sand variantYH Lin
Create the initial Sand variant which refers to the Reef. Sand is APL board that derives from reference board Reef. BRANCH=master BUG=chrome-os-partner:62200 TEST=Build (as initial setup) Signed-off-by: YH Lin <yueherngl@chromium.org> Change-Id: Iba8c5653b6176676c759d2b48063f0c0c6cde625 Reviewed-on: https://review.coreboot.org/18324 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-14google/eve: change touchpad HIDWei-Ning Huang
Change touchpad HID to use with the Google Centroiding Touchpad driver. BUG=chrome-os-partner:61088 TEST=`emerge-eve coreboot` Change-Id: I199ff46f1a93d3eccc8c694742585dcf37b2373f Signed-off-by: Wei-Ning Huang <wnhuang@google.com> Reviewed-on: https://review.coreboot.org/18359 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-14google/rambi: add explicit pull-down for ram-idMatt DeVillier
Some variants need the internal pull resistor on GPIO_SSUS_40 set explicitly to pull down rather than disabling the pull, in order for the ram-id to be read correctly via GPIO. Correct this by adding a function to enable and set the internal pull and define its use as needed in the board's variant.h. Chromium source: branch: firmware-gnawty-5216.239.B /src/soc/intel/baytrail/baytrail/gpio.h#418 /src/mainboard/google/gnawty/romstage.c#60 Test: boot 4GB Candy board and observe correct RAM id, amount detected Change-Id: I8823c27385f4422184b5afa57f6048f7ff2a25ab Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18309 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-14google/poppy: select NO_FADT_8042Jenny TC
Poppy doesn't support 8042 keyboard. Select NO_FADT_8042 to disable 8042 in FADT header. Kernel will not try to access 8042 region if 8042.FADT=0 BUG=chrome-os-partner:61858 TEST=Boot OS and verify FADT 8042 flag Change-Id: I00182eb4b059d4d9f0705d349dc98651e3955f0d Signed-off-by: Jenny TC <jenny.tc@intel.com> Reviewed-on: https://review.coreboot.org/18311 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-13mainboard/google/snappy: Update DPTF settingsWisley Chen
Update DPTF parameters based on thermal team test result. 1. Update TSR2 trigger points. TSR2 passive point: 70, critical point: 90 2. Set PL2 Max to 15W. BUG=chrome-os-partner:61383 BRANCH=reef TEST=build, boot on snappy, and verified by thermal team Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-11mainboard/google/reef: Increase PL1 sampling periodSumeet Pawnikar
Performance degradation seen with current PL1 throttling rate as 8 seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1 throttling rate to 15 seconds, fps score improved. BUG=chrome-os-partner:60038 BRANCH=reef TEST=Built and tested on electro system Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/18317 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
2017-02-11google/gru: add scarlet variantphilipchen
There will be more follow-up changes. BUG=chrome-os-partner:62377 BRANCH=None TEST=emerge-scarlet coreboot libpayload Change-Id: I9ca45598ff0ab12bf8063d16a86be564cf509390 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a020a9ba1228b15599e202972df0096f58b1b31c Original-Change-Id: I4804239483f8b35bc3703aa62c2a8fd642e0234a Original-Signed-off-by: philipchen <philipchen@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/433039 Original-Commit-Ready: Philip Chen <philipchen@chromium.org> Original-Tested-by: Philip Chen <philipchen@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18296 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2017-02-10ddr3 spd: move accessor code into lib/spd_bin.cPatrick Georgi
It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18265 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-10ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()Patrick Georgi
Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18264 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-10device/dram: use global DIMM_SPD_SIZE Kconfig variablePatrick Georgi
Also make sure that no board changes behaviour because of that by adding a static assert. TEST=abuild over all builds still succeeds (where it doesn't if DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the device/dram code). Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18254 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-07mainboards/google/reef: Add support for tablet mode switch.Gwendal Grignou
Reef is a convertible add support for sending Tablet mode switch changes from EC to AP. Change-Id: I6dfddbfdb5a2ffbdfd77c5f49602bf68e9693a06 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/18277 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-07google/eve: Add support for tablet mode switch.Gwendal Grignou
Eve is a convertible add support for sending Tablet mode switch changes from EC to AP. Change-Id: I35133ebc1439852d0ceb88d7d679b37356b0869d Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/18276 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-02-05google/eve: Fix keyboard backlight enable in wake from G3Duncan Laurie
The WAK_STS bit is not set in a wake from G3, so the check for this bit needs to only be done when checking for a wake from S3. This change correctly enables the keyboard backlight in wake from G3 and only does not enable it during a wake from S3. BUG=chrome-os-partner:58666 TEST=Use Refresh+Power to issue hard reset and ensure that the keyboard backlight turns on like it does when waking from S5. Also force enter hibernate with Alt+VolumeUp+H and then power back up and ensure that the keyboard backlight is enabled when booting. Change-Id: I44045950e38aa5e5ae96a79385d604791852c7e6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18280 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-04google/jecht: Fix LED for guado/rikku variantsMatt DeVillier
When guado/rikku/tidus were rolled into jecht, an error was made in set_power_led() as guado/rikku set the polarity differently than tidus. Fix the power LED for guado/rikku by setting the polarity correctly. Test: boot guado/rikku and observe proper function of power LED under S0, S3, and S5 power states. Change-Id: I23072ac60bc9683776f748ca1326d98257c3c54f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18249 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-04lenovo/x60: use correct BLC_PWM_CTL valueFrancis Rowe
Bit 16 in BLC_PWM_CTL enables brightness controls, but the current value is generic. Use the proper value, obtained by reading BLC_PWM_CTL while running the VBIOS. Change-Id: Ib273359e1c285b405a9bb26fc217c2f7e255b99f Signed-off-by: Francis Rowe <info@gluglug.org.uk> Reviewed-on: https://review.coreboot.org/10624 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-02-04Revert "google/pyro: remove Wacom touchscreen probed flag"Kevin Chiu
Reason for revert: Pyro has two touchscreen sources: WACOM/ELAN. It will not have both touchscreen IC in one system at the same time. So the "probed" property of WACOM i2c device is mandatory to set for kernel to know whether it exists before driver initializes it. Otherwise in ELAN case, when driver fails to init WACOM i2c device, ACPI _OFF will be invoked to set GPIO#152 low to cut off power. BUG=chrome-os-partner:62371 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I30f467bd8720d959686dc14f7877e6bc11ea6213 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2017-02-04google/eve: Fix DRAM DQS mapDuncan Laurie
This change fixes the two sets of pins that were swapped in the map of DQS signals from CPU to DRAM for channel 1. Although this does not appear to have any impact to the system it does result in different register values for DQS pin mapping that are programmed inside FSP. BUG=chrome-os-partner:58666 TEST=This fix was verified against the current schematic and using FSP debug output. Change-Id: I45b821071ba287493b3b13204b7f5b38e06eee75 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18279 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-04google/poppy: Set GPIO GPP_D22 highRizwan Qureshi
same change as I49935e659bf67225d3f5db1b06acc2cd046dcd74 this is required for poppy board as well. GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=None BRANCH=None TEST=play test sound in OS over internal speaker Change-Id: I1695e9198f8f78e9c5ad6df6c1ac073ac1762c6b Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/18282 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-02-04google/eve: Set GPIO GPP_D22 highDuncan Laurie
GPIO GPP_D22 controls the I2S buffer for isolating the I2S signals when doing GPIO-driven I2S. This needs to be high by default so the DSP can drive these signals, instead of low where it is enabled for GPIO-driven I2S and the DSP cannot drive these signals. BUG=chrome-os-partner:58666 TEST=play test sound in OS over internal speaker Change-Id: I49935e659bf67225d3f5db1b06acc2cd046dcd74 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18281 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-02-03mainboard/google/snappy: Set PL2 override to 15000mWHarry Pan
This patch sets PL2 override value to 15W in RAPL registers. BUG=chrome-os-partner:62110 BRANCH=reef TEST=Apply new firmware to evaluate Octane benchmark score. Change-Id: I51734051586753677129314b5273fb275c74f5d2 Signed-off-by: Harry Pan <harry.pan@intel.com> Reviewed-on: https://review.coreboot.org/18283 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-02-03mb/lenovo/x60,t60: Move EC CMOS parameters in checksummed spaceArthur Heymans
This allows for defaults to be applied to CMOS parameters when cmos checksum is incorrect. This probably results in changed cmos settings for current users of these targets. Change-Id: Ifec0093f4b0dbaa51b96812a041f0eaf5c58ee86 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-03asus/f2a85-m_le: Activate IOMMU supportTobias Diedrich
Activate the IOMMU for the ASUS F2A85-M LE board. Enable the IOMMU in `devicetree.cb` and build AGESA IOMMU code by enabling the option in `buildOpts.c`. ACPI and MPTABLES interrupt routers are already present since they are syminks to the F2A85-M version. ``` $ uname -a Linux nukunuku 4.8.5 #35 SMP Sun Oct 30 19:34:55 CET 2016 x86_64 GNU/Linux $ lspci -s 0.2 00:00.2 IOMMU: Advanced Micro Devices, Inc. [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg | grep -i IOMMU ACPI: IVRS 0x00000000BFFAFF70 000070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) AMD-Vi: Applying erratum 746 workaround for IOMMU at 0000:00:00.2 iommu: Adding device 0000:00:01.0 to group 0 [...] iommu: Adding device 0000:00:18.5 to group 9 iommu: Adding device 0000:03:00.0 to group 8 AMD-Vi: Found IOMMU at 0000:00:00.2 cap 0x40 AMD IOMMUv2 driver by Joerg Roedel <jroedel@suse.de> ``` Change-Id: I6049fcfad53d16a99495d7a8fbc584c71e371d73 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: https://review.coreboot.org/18259 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-02-02siemens/mc_apl1: Add new mainboardMario Scheithauer
This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with minimum changes. Special adaptations for MC APL1 mainboard will follow in separate commits. Change-Id: If0b8a2bc21c99c3be4e6043e8febfb1b91ff0a63 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/18272 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Brenton Dong <brenton.m.dong@intel.com>
2017-02-01Add Baytrail ChromeOS devices using variant schemeMatt DeVillier
Add new ChromeOS devices banjo, candy, clapper, glimmer, gnawty, heli, kip, orco, quawks, squawks, sumo, swanky, and winky using their common reference board (rambi) as a base. Chromium sources used: firmware-banjo-5216.334.B 32ec493 [chromeos: vboot_loader: Set...] firmware-candy-5216.310.B 519ff11 [baytrail: Preserve VbNv around...] firmware-clapper-5216.199.B 80d55e3 [baytrail: add code for...] firmware-glimmer-5216.198.B fae0770 [baytrail: add code for...] firmware-gnawty-5216.239.B 952adb7 [Gnawty/Olay: Add 2nd source...] firmware-heli-5216.392.B f1f3604 [helis: Lock ME / TXE section...] firmware-kip-5216.227.B db3c5d9 [kip: update spd for for MT41K256M16*] firmware-orco-5216.362.B 76f1651 [Orco: Adjust rx delay for norm.] firmware-quawks-5216.204.B edb60c9 [Quawks: Update SPD data] firmware-squawks-5216.152.B c6573dc [Squawks: Update SPD data] firmware-sumo-5216.382.B c62b6f23 [Ninja, Sumo: Add SPD source...] firmware-swanky-5216.238.B 233b2a7 [Swanky: update SPD table] firmware-winky-5216.265.B ce91ffc [Add to support HT Micron...] The same basic cleanup/changes are made here as with the initial BYT variant commit: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) - Micron 2GB SPD file for kip with updated values renamed to distinguish from same file used by other boards Change-Id: Ic66f9b539afb5aff32c4c1a8563f6612f5a2927c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18164 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-31google/veyron*: mark GPIO array non-staticPatrick Georgi
That status isn't needed and making it non-static helps gcc 4.9.2 (or any compiler that insists on "standard C" behaviour with global const initializers) Change-Id: Ib1fbd5213d262e653f31564b106095b4a28292f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/18266 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-31asus/m2v,m2v-mx_se: Unify KconfigPaul Menzel
Reorder the items to minimize the differences. Change-Id: I745ec70a990f997d87c2a0b6164ae127eb694ddf Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17438 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-31mainboard/google/reef: remove NHLT DMIC 1ch and 2ch configurationSathyanarayana Nujella
Apollolake boards should use DMIC-4ch configuration in Kernel side and use CaptureChannelMap in userspace to distinguish boards with different number of DMIC's. So, NHLT DMIC 1-ch & 2-ch endpoint configuration will not be required and hence removed. BUG=chrome-os-partner:60827 TEST=Verify internal mic capture TEST='arecord -Dhw:0,3 dmic_4ch.wav -f S16_LE -r 48000 -c 4 -d 10' works Change-Id: Ibe81290906c9e379ae49e437648ee9cd6f123ff8 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/18252 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-31mainboard/google/reef: Set edge triggered interrupt for GPIO_22Vaibhav Shankar
EC sets the logic level based on outstanding wake events. When GPIO_22 is configured as a level triggered interrupt, the events are not cleared from the interrupt handler. Hence, we'd just be re-signalling over and over causing an interrupt storm upon lid open. So, GPIO_22 needs to be configured as EDGE_SINGLE instead of LEVEL. BUG=chrome-os-partner:62458 TEST=Lid close/open. check CPU usage using top. It should not show 70% CPU usage. Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Change-Id: I710a690578c6e5b63be34b7fbcb21c703ef56e3a Reviewed-on: https://review.coreboot.org/18267 Tested-by: build bot (Jenkins) Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-29mainboard/google/snappy: Update WDT touchscreen deviceFurquan Shaikh
Export PowerResource for WDT touchscreen device. BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Compiles successfully. Change-Id: Icc5be170353753201d3571c39b50e29424d4d6d3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18240 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29mainboard/google/pryo: Update touchscreen device ACPI nodesFurquan Shaikh
1. For ELAN, export reset GPIO as well as PowerResource 2. For WCOM, export PowerResource BUG=chrome-os-partner:62311, chrome-os-partner:60194, chrome-os-partner:62371 BRANCH=reef TEST=Verified that touchscreen works on pyro with WCOM device on power-on as well as after suspend/resume. Change-Id: I0306e24e19bf821cd3e08fdacc0d78b494c9a92f Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18239 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-29i2c/generic: Allow GPIOs to be put in _CRS and PowerResource in ACPIFurquan Shaikh
Linux kernel expects that power management with ACPI should always be handled using PowerResource. However, some kernel drivers (e.g. ELAN touchscreen) check to see if reset gpio is passed in by the BIOS to decide whether the device loses power in suspend. Thus, until the kernel has a better way for drivers to query if device lost power in suspend, we need to allow passing in of GPIOs via _CRS as well as exporting PowerResource to control power to the device. Update mainboards to export reset GPIO as well as PowerResource for ELAN touchscreen device. BUG=chrome-os-partner:62311,chrome-os-partner:60194 BRANCH=reef TEST=Verified that touchscreen works on power-on as well as after suspend-resume. Change-Id: I3409689cf56bfddd321402ad5dda3fc8762e6bc6 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18238 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2017-01-29mainboard/google/reef: Set IOSSTATE for trackpad I2C GPIOsVaibhav Shankar
I2C data (GPIO_132) and Clk (GPIO_133) lines are pulled low during standby states S3/S0ix. This causes leakage of power. To reduce the leakage, we have to pull these lines high during S3/S0ix. This is done by programming the IOSSTATE to HIz. Also note that we are using the internal pull ups to keep at SOC at 1.8V and the I2C lines are not floating. BUG=chrome-os-partner:62428,chrome-os-partner:61651 TEST=Enter S3/S0ix. Measure trackpad power. It should be less than 4mW. Also I2c lines should be pulled high in S3/S0ix. Change-Id: I5570ac37ec3cc41f6463dd6b858fdb56a20a1733 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/18251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-26google/pyro: Add USB2 phy setting overrideKevin Chiu
In order to pass type A USB2 eye diagram, USB2 port#0/#1 PHY register will need to be overridden. port#0: PERPORTPETXISET = 7 PERPORTTXISET = 1 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 port#1: PERPORTPETXISET = 7 PERPORTTXISET = 2 IUSBTXEMPHASISEN = 3 PERPORTTXPEHALF = 0 BUG=chrome-os-partner:59491 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8e67a6f0192d1c0abf6ec4926c2a17e44c818948 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18229 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-26google/pyro: Disable Wacom touchscreen probedKevin Chiu
Wacom touchscreen is i2c hid device and it's the device that always exists. So no need to set "probed" property for it. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I27fe18ceadd03029b826e0237f80132eda1089b0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-25mb/intel/d510mo: Add cmos.layout and cmos.defaultArthur Heymans
Change-Id: I877d4470b697d6a6d4652ed1c60028cdcbe8df98 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18143 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-25google/pyro: Modify Wacom touchscreen IRQ type to level-triggeredKevin Chiu
Follow i2c-hid spec definition, level trigger interrupt is required for i2c-hid device. BUG=chrome-os-partner:61513 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: Ia825bd0c898e71e2ee2bf411f117a49a8fb411b6 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18217 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-24arch/x86: do not define type of SPIN_LOCK_UNLOCKEDPatrick Georgi
This fixes building coreboot with -std=gnu11 on gcc 4.9.x Also needs fix ups for asus/kcma-d8 and asus/kgpe-d16 due to the missing type. Change-Id: I920d492a1422433d7d4b4659b27f5a22914bc438 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: https://review.coreboot.org/18220 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2017-01-24google/eve: Enable PD MCU deviceDuncan Laurie
In order for PD charge events to properly notify the OS when a charger is attached we need to enable the PD MCU device and event source from the EC. Without this change the charging still happens, but the OS does not notice and update the charge state icon in the Chrome OS UI. BUG=chrome-os-partner:62206 BRANCH=none TEST=plug in a charger to either port and see charge status updated to indicate charging in the power_supply_info tool and the Chrome OS UI. Change-Id: Ia6f63ac719b739326d313f657a68005c32f45b8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18209 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-24mainboard/lenovo: Add new port L520Patrick Rudolph
Add support for Lenovo Thinkpad L520. The files are generated by autoport, and are successfully tested on the board. L520 has got 4MiB flash chip, that contains a "slim" ME with 1.2MiB only. The flash IC has to be desoldered, as it won't be accessible in circuit. It is located on top of the mainboard right under the touchpad. Test-setup: Extract the following blobs from vendor BIOS: * Intel Flash Descriptor * Intel Management Engine * Intel VBios The laptop has been externaly flashed. It was able to turn on the display and load SeaBIOS. Latest debian has been booted from harddisk. Latest fedora has been booted from USB flash drive. The following hardware has been tested and is working: * Display using Option Rom * PCIe wifi * Ethernet * Keyboard, trackpoint and touchpad * Some Fn functions keys * Volume Keys (except mic mute) * Status LEDs * Audio (headphone jack only) * USB ports * Native raminit dual channel (2 DDR3-1333 DIMMs tested) * SATA cdrom * SATA harddrive Broken: * Some Fn functions keys * Microphone mute button * Speakers (but headphone jack gives sound) Untested: * Expansion slot * SD card slot * Docking station * Native gfx init The EHCI debug port is the first one on the right side. Change-Id: Ic8943799b953bde09ff1daf8427ce5125a0778ca Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/18003 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2017-01-24mainboard/intel/leafhill: initial leafhill board changesBrenton Dong
This commit makes the initial changes to support the Intel Leaf Hill CRB with Apollo Lake silicon. Memory parameters and some GPIOs are set. The google/reef directory is used as a template, and the same IFWI stitching process as reef is used to generate a bootable image. Apollo Lake silicon requires a boot media region called IFWI which includes assets such as CSE firmware, PMC microcode, CPU microcode, and boot firmware. Change-Id: Id92f0458548e3054d86f5faa8152d58d902f4418 Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18039 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-24mainboard/intel: add leafhill board directoryBrenton Dong
This commit adds the initial scaffolding for the Intel Leafhill CRB with Apollo Lake silicon. The google/reef directory is used as a template. This commit only makes the minimum changes to Kconfig and Kconfig.name needed for the build bot to not have issues. Change-Id: I088edee0e94ecfb4666fa31e08dbcfd24a81891b Signed-off-by: Brenton Dong <brenton.m.dong@intel.com> Reviewed-on: https://review.coreboot.org/18038 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-23google/pyro: Update DPTF settingsKevin Chiu
1. Update DPTF CPU/TSR1 passive trigger points. CPU passive point: 80 TSR1 passive point: 46 2. Update DPTF TRT Sample Period TSR1: 8s BUG=chrome-os-partner:62133 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I8fcf750ac17b8894ed3c8704eec62f5071d9cf24 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18174 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22gru: kevin: define GPIOs used on both platformsVadim Bendebury
The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: I54ef3e8dd79670bdb037baeec91430113d11bcc1 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c58788026f28af52c650da0159b93d97269ca4a9 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/18176 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-22mainboard/google/reef: Increase TSR1 trigger pointTim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT2_v0.4_20170120.xlsx) 1. Update DPTF TSR1 passive trigger point. TSR1 passive point: 46 BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: If35e4cf2dbf7c506534c52a052598f6204d5315a Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18183 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Fixes for devicetree settingsDuncan Laurie
The devicetree settings were incorrect in a few places with respect to the SOC and board design: - IMVP8 VR workaround is for MP2939 and not MP2949 on Eve - IccMax values are incorrect according to KBL-Y EDS - USB2[6] is incorrectly labeled - I2C touch devices do not need probed as they are not optional - PCIe Root Port 5 should be enabled - I2C5 device should not be enabled as it is unused BUG=chrome-os-partner:58666 TEST=manually tested on Eve board Change-Id: I74e092444ead4b40c6d8091b80a691d44e2c6c7d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18200 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Enable separate recovery MRC cacheDuncan Laurie
In order to get quick boot speeds into recovery enable the feature that allows for a separate recovery MRC cache. This requires shuffling the FMAP around a bit in order to provide another region for the recovery MRC cache. To make that shuffling easier, group the RW components into another sub-region so it can use relative addresses. BUG=chrome-os-partner:58666 TEST=manual testing on eve: check that recovery uses the MRC cache, and that normal mode does too. Check that if cache is retrained in recovery mode it is also retrained in normal mode. Also check that events show up in the log when retrain happens. Change-Id: I6a9507eb0b919b3af2752e2499904cc62509c06a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18199 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-22google/eve: Enable keyboard backlight in bootblockDuncan Laurie
Enable the keyboard backlight as early in boot as possible to provide a indication that the BIOS is executing. Since this is bootblock it can't use the convenience function for checking for S3 resume so just read the PM1 value from the SOC and check it directly. Use a value of 75% for the current system as that is visible without being full brightness. BUG=chrome-os-partner:61464 TEST=boot on eve and check that keyboard backlight is enabled as soon as the SOC starts booting Change-Id: I9ac78e9c3913a2776943088f35142afe3ffef056 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18197 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21mainboard/google/reef: remove internal pullups on PP1800_S railAaron Durbin
The PP1800_S rail is turned off in S3. However, enabling internal pullups on the pins which are connected to PP1800_S results in leakage into the P1800_S rail. Fix this by disabling the internal pullups on PP1800_S rail pins. BUG=chrome-os-partner:61968 BRANCH=reef TEST=measured leakage on PP1800_S rail. Gone with this patch. Change-Id: I5ae92b31c1a633f59d425f4105b8db1c9c18c808 Signed-off-by: Aaron Duribn <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/18189 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-21pcengines/apu2: Add serial number in SMBIOSKyösti Mälkki
Change-Id: Ic8149b1dd19d70935e00881cffa7ead0960d1c78 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18154 Tested-by: build bot (Jenkins) Reviewed-by: Piotr Król <piotr.krol@3mdeb.com>
2017-01-21pcengines/apu2: Add SKU in SMBIOSKyösti Mälkki
Installed memory only, PCB revision cannot be detected. Change-Id: Ib6224018db3de4a7ddd9e6f7f30edc438c3f0702 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18153 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Refactor reading memory strapKyösti Mälkki
Change-Id: Ie4f80619d9417200a007fc65154b97a5bc05f2f8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18152 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Change SMBIOS part numberKyösti Mälkki
This string should not include manufacturer name. Change-Id: I63793b16129334ea4930b8b0264a39d7f9849bba Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18151 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-21pcengines/apu2: Remove DDI configurationKyösti Mälkki
Assembled SoC part does not have integrated graphics. Change-Id: I5d157063cd850d343df73d448e6904c188a09730 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/18150 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-20google/snappy: Add weida touchscreen supportWisley Chen
Add weida touchscreen as 2nd touchscreen source BUG=chrome-os-partner:61865 BRANCH=reef TEST=emerge-snappy coreboot, and verified that touchscreen works on snappy. Change-Id: If76312a62e97da9d5de18ad895e90ee6b0f0c6ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18166 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20google/snappy: Use exported GPIOs and ACPI regulator for touchscreenWisley Chen
ELAN touchscreen device expects firmware to export GPIOs and ACPI regulators for managing power to the device. Thus, provide the required ACPI elements for OS driver to properly manage this device. BUG=None BRANCH=None TEST=Verified that touchscreen works properly on boot-up and after suspend/resume. Change-Id: I78e0c35f60289afe338d140d90784a433ca534ae Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18163 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-20google/eve: Adjust DPTF parametersDuncan Laurie
- Remove the 0mA entry for the charger performance table - Slightly raise the passive limit for TSR2/TSR3 to 55C BUG=chrome-os-partner:58666 TEST=manual testing on P1 system Change-Id: I75c66afe04afbbdb64a45833eb938e57ff21b392 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18172 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20google/eve: Enable ACPI keyboard backlightDuncan Laurie
Enable the ACPI interface to EC driven keyboard backlight. BUG=chrome-os-partner:61464 TEST=manual testing on P1 system Change-Id: I13d96c13d7db726b1e8289131db65104bd302efe Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18171 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-20google/eve: Enable pull-up on ACPRESENTDuncan Laurie
Enable an internal pull-up on ACPRESENT signal. BUG=chrome-os-partner:58666 TEST=manual testing on P1 Change-Id: I0bb86f4547272e021ffd10998faa0e2f103b0808 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/18170 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-19mainboard/google/snappy: Disable unused devicesWisley Chen
The following devices i2c6, i2c7, spi1, spi2, uart3 are not used. BUG=none BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I9bacdbdd194ce21686c1618494d113402f2bef6c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/18140 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-19mainboard/google/reef: Ignore Audio DMIC IOSSTATEVaibhav Shankar
Audio DMIC PLL needs to be ON in S0ix to support Wake on Voice. This requires GPIO_79 and GPIO_80 to be configured as IGNORE IOSSTATE. So DMIC CLKs will be ON in S0ix. Change-Id: If91045a8664ce853366b670b9db38d620818fbab Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/18155 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-17Revert "mainboard/google/snappy: Add PowerResource for ELAN touchscreen"Martin Roth
This reverts commit 01ba8cf7 (mainboard/google/snappy: Add PowerResource for ELAN touchscreen) Change was out of date and broke the build. Change-Id: Id47631ece1172c3f93bf6f40b8686dfd728842a9 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18158 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-17mainboard/google/reef: Ignore SPI IOSTANDBYLijian Zhao
SPI controller need to access flash descriptors/SFDP during s0ix exit, so all fast SPI IO can't be put into IOSTANDBY state. For reef, that will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and GPIO_106. BUG=chrome-os-partner:61370 BRANCH=reef TEST=Enter s0ix state in OS, after resume run flashrom to read SPI content. Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/18137 Tested-by: build bot (Jenkins) Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-17mainboard/google/snappy: Add PowerResource for ELAN touchscreenWisley Chen
Define reset_gpio and enable_gpio for touchscreen device so that when kernel puts this device into D3, we put the device into reset. PowerResource _ON and _OFF routines are used to put the device into D0 and D3 states. BUG=chrome-os-partner:59034 BRANCH=master TEST=emerge-snappy coreboot chromeos-bootimage Change-Id: I08c05d06b2812a33b3fdff9b42b2a8e0653dd8b4 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17366 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17Combine Baytrail ChromeOS devices using variant schemeMatt DeVillier
Combine existing boards google/enguarde and google/ninja using their common reference board google/rambi as a baseboard. Variants contain board specific data: - DPTF ACPI components - I2C ACPI devices - RAM config / SPD data - devicetree config - GPIOs - board-specific HW components (e.g., LAN) Additionally, some minor cleanup/changes were made: - remove unused ACPI trackpad/touchscreen devices - correct I2C addresses in SMBIOS entries - clean up comment formatting - remove ACPI device for unused light sensor - switch I2C ACPI devices from edge to level triggered interrupts, for better compatibility/functionality (and to be consistent with other recently-upstreamed ChromeOS devices) The existing enguarde and ninja boards are removed. Variant setup modeled after google/auron Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18129 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-17google/enguarde,ninja: Prep for variant mergeMatt DeVillier
Minor cleanup for enguarde and ninja devices: - enguarde: correct trackpad I2C slave address - enguarde: remove unused trackpad ACPI devices - ninja: remove unused PS2 keyboard ACPI device Change-Id: I1beb34059ba318e2d496a59e4b482f3462faf232 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/18128 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-16intel: Fix copy/paste error in license textMarshall Dawson
Change all instances of "wacbmem_entryanty" to "warranty". Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/18136 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-16riscv/spike: Remove obsolete DRAM_SIZE_MB settingJonathan Neuschäfer
Change-Id: I4077739ac2be09107d8c5a3e4ae7ebd0da3cb876 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/18147 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2017-01-16mainboard/google/poppy: SD card changesFurquan Shaikh
1. Disable WP 2. Pass SD card detect info in ACPI BUG=chrome-os-partner:60713 BRANCH=None TEST=Verified that OS is able to detect SD card and read/write to it. Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18138 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-16mainboard/google/poppy: Update DQS and DQ Byte mappings for poppyRizwan Qureshi
poppy schematics have undergone change after review, update DQS and DQ Byte mappings based on the new schematics. BUG=chrome-os-partner:61856 BRANCH=None TEST= Build and boot all the poppy proto SKUs to OS. Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18133 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-13aopen/dxplplusu: Switch to 2MiB flashKyösti Mälkki
Change-Id: Iedc15823dc24b3211fe7954cdf4302934a517afb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/17919 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13mainboard/google/poppy: Disable EC SW syncFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that EC SW sync is disabled Change-Id: I399b26aa64084f5d5e91a2e585281dc48fa81c89 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18114 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13mainboard/google/poppy: Enable touchscreen in ACPIFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Verified that touchscreen works on poppy. Change-Id: I0fd605048b91b126ca5b5f8c1c4d6d3f46f866a3 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18113 Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Martin Roth <martinroth@google.com>
2017-01-13mainboard/google/poppy: Correct the index for SPD binariesFurquan Shaikh
BUG=chrome-os-partner:60513 BRANCH=None TEST=Picks up correct SPD for index. Change-Id: Iac683ab3b8151747940b0ad7e257da3d9b0ac622 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18112 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13mainboard/google/poppy: Enable SD cardFurquan Shaikh
BUG=chrome-os-partner:60713 BRANCH=None TEST=sdcard is detected. Change-Id: I9ec0cabff0ed7973f5e7dd2c1eae346ae6a1aa99 Signed-off-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: https://review.coreboot.org/18111 Tested-by: build bot (Jenkins) Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-13fsp_baytrail: Enable graphic init per defaultWerner Zeh
Baytrail SoC has a bug where in some cases the DisplayPort can hang leading to a non-working display (it just stays black). To avoid this hang, a patch was introduced in 02/2016 (1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort) but per default not switched on so that each mainboard can decide if it wants to use this patch or not. Recently a new case of this bug was reported by Benoit Sansoni (benoit.sansoni@kontron.com) and he requested to enable this fix per default as it costs him a lot of time to find the cause and even the already available fix in coreboot. To avoid this effort for someone else in the future we can enable this fix per default as no negative side effects are known and it is now tested at Siemens and at Kontron on different mainboards with success. As the goal is to enable this code permanently the config switch is not longer needed and is removed. Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/18109 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13gru: Tuning USB 2.0 PHY0 and PHY1 host-portWilliam wu
The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase compatibility") bypass ODT to set the max driver strength for the Type-C otg-port, it works well on otg-port when connected with USB2.0 devices. Unfortunately, because the Type-C otg-port and host-port are consisted in one USB2 PHY, so bypass ODT will have an effect on both host-port and otg-port. I have tested the host-port eye-diagram, the result shows that if we bypass ODT, the host- port eye-diagram height will become to high, more than 500mv, this may cause USB 2.0 high-speed enumeration failure. This patch bypass ODT for host-port separately, and then we can reduce the host-port driver strength without affecting the otg-port driver strength. BRANCH=gru BUG=chrome-os-partner:60727 TEST=Boot system, run 'lsusb' command and check if the usb camera and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are on usb 1.1 hub, the issue happens. If not, try to run camera app and then close camera app, repeat until find that the usb camera is on the usb 1.1 hub. Change-Id: Ib693e2a6f2113c06692a7bfee22d85b67ee3b165 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5ea7660b7b05080b76fc5ca5af3fa18552a03491 Original-Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a Original-Signed-off-by: William wu <wulf@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/425739 Original-Commit-Ready: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Tested-by: Inno Park <ih.yoo.park@samsung.com> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/18126 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-13mb/lenovo/t400,x200,x201: Do not select DRIVERS_ICS_954309Arthur Heymans
This driver to configure the clock generator is not used. Change-Id: I156a42dfc336ff45acdcb6d8618bbd12671b66a7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18104 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-13google/pyro: Add ELAN touch screen supportKevin Chiu
Current fw does not create ACPI device for OS to recognize ELAN touchscreen. List the touch screen in the devicetree so that the correct ACPI device are created. BUG=chrome-os-partner:61803 BRANCH=reef TEST=emerge-pyro coreboot Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/18086 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-12fsp 1.0 systems: Check for NULL when saving HobListPtrMartin Roth
Die if cbmem_add can't allocate memory for the hob pointer. This shouldn't ever happen, but it's a reasonable check. - fsp_broadwell_de already had a check, but it returned to someplace inside the FSP. Just die instead. Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623 Found-by: Coverity Scan #1291162 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/18092 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2017-01-10mb/lenovo/t400: Increase MAX_CPUS to 4Arthur Heymans
The Lenovo T400 has a CPU socket that can fit quad cores. Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18059 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2017-01-06Kconfig: Remind users to delete .config when switching boardsMartin Roth
Because Kconfig default values *ONLY* get set when they are first configured, if you switch mainboards with an existing .config, the values will not be set as expected for the new board. This seems to confuse most users, so put a warning in a visible location to let them know. Change-Id: Ie6a9c2d139ecd841d654943f14c119ebafd632f2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/17939 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2017-01-06mb/asus/p5gc-mx: Use common/gpio.hArthur Heymans
Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to set up GPIOs", which was not rebased on addition of this board. Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/18047 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins)
2017-01-06sb/ich7: Use common/gpio.h to set up GPIOsArthur Heymans
This is more consistent with newer Intel targets. This a static struct so it is initialized to 0 by default. To make it more readable: * only setting to GPIO mode is made explicit; * only pins in GPIO mode are either set to input or output since this is ignored in native mode; * only output pins are set high or low, since this is read-only on input; * blink is only operational on output pins, non-blink is not set explicitly; * invert is only operational on input pins, non-invert is not set explicitly. Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17639 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-05src/amd: Add common definition of AMD ACPI MMIO addressTimothy Pearson
The bare ACPI MMIO address 0xFED80000 was used in multiple AMD mainboard files as well as the SB800 native code. Reduce duplication by using a centrally defined value for all AMD ACPI MMIO access. Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/18032 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-05mb/ga-m57sli-s4: Fix early uart outputArthur Heymans
The console output is garbled until it is fixed in ramstage by devicetree which sets the uart clock predivider correctly. Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17969 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-01-04google/auron: Fix omitted ACPI KB backlight for variantsMatt DeVillier
Restores KB backlight functionality for auron variants gandof, lulu, and samus. TEST: boot Lulu and observe KB backlight functional Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/17960 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-04amdfam10: Perform major include ".c" cleanupDamien Zammit
Previously, all romstages for this northbridge family would compile via 1 single C file with everything included into the romstage.c file (!) This patch separates the build into separate .o modules and links them accordingly. Currently compiles and links all fam10 roms without breaking other roms. Both DDR2 and DDR3 have been completed TESTED on REACTS: passes all boot tests for 2 boards ASUS KGPE-D16 ASUS KFSN4-DRE Some extra changes were required to make it compile otherwise there were unused functions in included "c" files. This is because I needed to exchange CIMX for the native southbridge routines. See in particular: advansus/a785e-i asus/m5a88-v avalue/eax-785e A followup patch may be required to fix the above boards. See FIXME, XXX tags Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/17625 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
2017-01-04intel/i945 boards: Add romstage time stampsPaul Menzel
Currently, some Intel 945 boards miss some or all of the time stamps *1:start of rom stage*, *2:before ram initialization*, and *3:after ram initialization*, so add them. Use the same formatting as used for the board Lenovo X60, which already has code for all the time stamps. Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/17993 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2017-01-03Revert "google/oak: increase the driving strength for 4GB DRAMs"Nicolas Boichat
This reverts commit 34a6537512d412363bf56428b7ae284e6dd80fb3, which appears to cause random stability issues on some elm units. BRANCH=oak BUG=chrome-os-partner:60869 BUG=chromium:673349 TEST=None Change-Id: I5ce9e2673db1bc7a1f487a3c3bcce4651a5e3567 Reviewed-on: https://chromium-review.googlesource.com/419862 Commit-Ready: Nicolas Boichat <drinkcat@chromium.org> Tested-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18005 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2017-01-03mb/asus/p5gc-mx: Remove extra BSEL strap checkArthur Heymans
This extra check is based on comparing CPU BSEL pins and reports in MCH configuration. This gives false positives in the case of 1333MHz CPUs which automatically get downgraded to 1067MHz by the northbridge (max supported frequency by 945gc). TESTED with Intel Xeon 5460 (does not boot but completes raminit) Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17997 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-03mb/intel/d945gclf: Fix resume from S3 suspendArthur Heymans
Checking for dram self refresh in MCHBAR8(SLFRCS) generates false positives. Change-Id: I25afd565cae0269616e38ecbcdf385281bae5d1f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17996 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-03mb/ga-m57sli: Add cmos.defaultArthur Heymans
If the cmos checksum is incorrect it should fall back to sane defaults. Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17968 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2017-01-03google/snappy: Update DPTF settingsWisley Chen
1. Update DPTF TSR1/TSR2 passive/critial trigger points. TSR1 passive point:53, critial point:80 TSR2 passive point:90, critial point:100 2. Update PL1 Min to 4W and PL1 Max to 12W 3. Update thermal relationship table (TRT) setting. BUG=none BRANCH=master TEST=build, boot on snappy dut and verified by thermal team member. Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17955 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-01-03mainboard/google/reef: Update DPTF parameters EVT1_v0.3Tim Chen
Update the DPTF parameters based on thermal test result. (ZHT_DPTF_EVT1_v0.3_20161227.xlsx) 1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points. CPU critical point:103 TSR1 passive point:45 TSR2 passive point:55, critical point:90 2. Change thermal relationship table (TRT) setting. Change CPU Throttle Effect on CPU sample rate to 3secs Change Charger Effect on Temp Sensor 2 sample rate to 60secs Change CPU Effect on Temp Sensor 1 sample rate to 8secs BUG=chrome-os-partner:60038 BRANCH=master TEST=build and boot on electro dut Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Reviewed-on: https://review.coreboot.org/17975 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-12-28mb/asus/p5gc-mx: Fix and complete SIO devicetree optionsArthur Heymans
The devicetree lacks the 'chip' option for the Super I/O, which causes the Super I/O related entries to be ignored. This also adds other LDN that are present on this Super I/O. Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/17965 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-12-26google/eve: Enable internal pull-up on PWRBTN#Duncan Laurie
Enable an internal pull-up on the power button input as a quick press is resulting in power button override being asserted. BUG=chrome-os-partner:61312 TEST=tested on eve P0b to ensure quick power button press does not result in a shutdown due to power button override. Change-Id: I3028cf7faef309cf4d60c3585b48adab6e1549d4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/17962 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-19 18:40:16 +0000