summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2014-08-12gm45: Allow coexistance with ME firmware.Vladimir Serbinenko
Change-Id: I08ca5eec94c70b43789122266d68af149772385c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6626 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12Haswell: Lower TJ_MAX to 100C. Adjust critical temps to match.ChromeOS Developer
Change-Id: I3326b6e3c412b6360af37030cefd13d95b704e70 Signed-off-by: Dave Parker <dparker@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/180750 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1978b0f91b2e91d2251721c7c6981d51a6930b61) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6615 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-12exynos5420: minor clean-up memory related stuffDavid Hendricks
This cleans up a few minor things (mostly #defines) of the memory code for exynos5420, pit, and kirby. Specifically: - CONCONTROL.empty is read-only, so don't try to set it and also get rid of the unneeded DMC_CONCONTROL_EMPTY_ENABLE #define. - MEMBASECONFIG* overlaps members of the mem_timings struct and are mainboard-dependent anyway, so get rid of 'em. - DMC_MEMCONTROL_TP_DISABLE corresponds to a reserved bit. It may have been deprecated. - Same with TIMING* #defines. - Clarify DDR_MODE_* usage and use mem->mem_type when appropriate. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ideb21efcc97b24f7e115e90051c20daef4480f17 Reviewed-on: https://chromium-review.googlesource.com/167500 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 650dba32cb217414c422907398f68e784e5720e8) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6614 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-08-12exynos5420/pit: re-factor membaseconfig0/1 usageDavid Hendricks
membaseconfig0/1 are utterly dependent on the mainboard's particular DRAM setup. This defines their values in the mem_timings struct for pit. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0 Reviewed-on: https://chromium-review.googlesource.com/167488 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 80eebd5bc0dbb9fabf81f46c25dcd5c5d5747579) exynos5420: necessary updates for DRAM This updates DRAM usage for Exynos5420 so that we can actually use 3.5GB: - Memory chips used with Exynos5420 may have 16 row address lines. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2 Reviewed-on: https://chromium-review.googlesource.com/167489 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 04bbaf5d8e125166dd689f656d5b37776be01fb1) Squashed two related commits. Change-Id: I4e45bc8a446715897ec21b0160701152fa6b226b Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6613 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: ddr3: Switch from 4G setup to 2G setup on exynos5420David Hendricks
This changes the number of chip selects that we configure from 2 to 1. On current setups with (x16 memory 4Gbit chips) that means that we're at 2GByte. Technically we should add a second setting in the ares_ddr3_timings and select between the two of the based on board strappings. That would make the CONFIG_RUN_TIME_BANK_NUMBER work properly. I've changed the ddr3_mem_ctrl_init() so it should handle that, but I'm not actually doing the board strapping read right now. This change means that accesses to 0xA0000000 - 0xFFFFFFFF on 2G systems will no longer put the system in a messed up state (leading to a hang). It also prevents some of the weird boot behavior that we've seen that comes and goes depending on U-Boot alignment. See <http://crosbug.com/p/20577>. This patch was ported from: https://gerrit.chromium.org/gerrit/66117 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Ib4cfe420aac30bd817438f06d01e8671afc4a27d Reviewed-on: https://chromium-review.googlesource.com/167210 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: ron minnich <rminnich@chromium.org> (cherry picked from commit 0ea574243058068702e3f6bc7355098745d16880) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6612 Tested-by: build bot (Jenkins)
2014-08-12Exynos5420: ddr3: fine tuning the DDR3 timing valuesDavid Hendricks
Fine tuning DDR timings value for better stability * Changed Data Driver Strength from 34 ohms to 30 ohms, expected to enhance signal integrity. * Changed DQ signal from 0xf to 0x1f000f, to keep default value safe. * Changed mrs[2] and added new mrs direct command for setting WL/RL without resetting DLL. * Added explicit reset value write in phy_con0 instead of just setting a bit, to ensure that reset happens. * Added DREX automatic control for ctrl_pd in none read memory state. This is ported from: https://gerrit.chromium.org/gerrit/61405 Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I59e96e6dede7b49c6572548aca664d82ad110bb1 Reviewed-on: https://chromium-review.googlesource.com/66995 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ec34b711c6d270672c56d45c370ca14c0aa27ca3) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6611 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-12exynos5: Refactor board-specific parts out of USB PHY codeJulius Werner
This patch moves around some of the existing Exynos5 USB 2.0 PHY code to make it cleaner in preparation of the 3.0 PHYs. It moves the VBUS GPIOs (which are completely board-specific) into the mainboard code and makes sure to only initialize PHYs on the boards that actually need them. It also removes the USB 3.0 PLL hack that was needed on Snow from the Pit and Kirby boards (which do not have that PLL anymore). Change-Id: Ia35f47a765acff60481f0907f7448ec4f78e0937 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66887 Reviewed-by: Stefan Reinauer <reinauer@google.com> (cherry picked from commit c3b1a8b687b535f4d5ac1b3bd2a4760151698fdb) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6609 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12exynos5420: Make USB A-A booting work with early data cacheJulius Werner
Apparently the IROM doesn't like data caches... the recently added dcache-in-bootblock makes A-A booting fail, and flushes/invalidations alone don't seem to fix it. It's pretty fast anyway, so we just disable the cache again for the duration of the IROM call. Also removes a superfluous invalidation line from the bootblock code... dcache_mmu_enable/disable already take care of that. Old-Change-Id: I35580d15664c7b4197d4ed14028720147adbf918 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66602 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit e9c28a6a7a88c8286e62764ee5ad2694da2e822f) exynos5: Implement booting from SDMMC media This patch augments the alternative CBFS media source implementation for Exynos5250 and Exynos5420 to allow booting from SDMMC devices (such as an SD or uSD card reader, if available). It also moves MMC initialization for the Snow, Pit and Kirby boards from romstage to ramstage (mainboard_init) to prevent it from interfering with the IROM during SDMMC boot. Old-Change-Id: Ic4adef80c28262d084a53c28ec59aa7ac3af50c8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66154 (cherry picked from commit 08de13b72432c076e3327c048df93d89d52b0ecc) snow and pit: turn on FET4 (for SD card) at bootup Explictly enable FET4 on Snow and Pit. Historically we haven't needed to do this because: * On snow there's a bypass around FET4 which effectively eliminates it. Even if we don't turn on FET4 the SD card is still powered. Turning on FET4 doesn't hurt though and is technically correct. * On pit the EC turns on FET4 on cold bootup. On pit we run into a problem if the kernel turns off FET4 like in <https://gerrit.chromium.org/gerrit/#/c/65332/> and then we get a software reset or warm reset. In this case the EC won't know to turn it back on. This was ported from: https://gerrit.chromium.org/gerrit/#/c/65673 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I57337f12b38889e6afee8577cf8807ec4c41e91c Reviewed-on: https://gerrit.chromium.org/gerrit/66786 Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit e910117047d898b6b1d0dc965ef2ec0237d17646) Squashed three commits for alternate cbfs SD support. Change-Id: Idbd1fd4776cbf8cb20d03e6b691104cd8540a1ec Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6530 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-08-12Kconfig: do not set SB_HT_CHAIN_ON_BUS0 twice to the same valueDaniele Forsi
Change-Id: If7286abf91f758cfbac2c85dcad336f38f70d843 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6579 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-08-12mainboard/intel/minnowmax: clean up includes & whitespaceMartin Roth
Clean up as requested in commit e6df041b. No functional changes. Change-Id: Iec3f7ee25fd8351c7e13d660e2df6461f7745478 Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6597 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-11bayleybay_fsp: Add bakersport board variantMartin Roth
The Bakersport board is a variant of the Bayley Bay mainboard that uses one ECC DIMM instead of two non-ECC dimms. This commit uses the Bayley Bay mainboard directory and modifies the required pieces to add the Bakersport board variant. It disables the second DIMM, points to an ECC version of the FSP, and sets the board name to be Bakersport instead of Bayley Bay. All of the code is still contained in the bayleybay_fsp directory. It seems like duplicating the whole directory for the one line of code that's actually different between the two platforms. Change-Id: Ia31e9ee927a6810a01a1ae143fcb00cfb7d8a7aa Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/5983 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-08-11mainboard/intel/minnowmax: Add MinnowMax mainboardMartin Roth
MinnowMax board using Intel's Bay Trail FSP Working: - Booting from SATA / USB / (USB3 with latest SeaBIOS) Not working: - Boot from SD - S3 Suspend / Resume ***** To configure the FSP ***** Download the Bay Trail FSP and the binary config tool: Modify the standard Bay Trail FSP: run the bct tool with the command line options: bct --bin <Bay Trail FSP Binary> \ --absf src/vendorcode/intel/fsp/baytrail/absf/minnowmax_Xgb.absf \ --bout <path to save the updated FSP to> Here are the required changes for modifying the FSP manually: Enable Memory Down: Enabled DRAM Speed: 1066 MHz DIMM_DWidth: x16 DIMM_Density: 4 Gbit (2GB Minnow Max) / 2 Gbit (1GB Minnow Max) tCL: 7 tRP_tRCD: 7 tWR: 8 tRRD: 6 tRTP: 4 tFAW: 27 Other FSP values can remain the same. ***** To configure the vbios ***** The vbios is in the Bay Trail FSP package. Download Intel's "Binary Modification Program" (BMP) Use it to disable all ports except HDMI on port B. Change-Id: I00d90e0d838d70c9d25c69f5115d0c9d6d19855c Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6429 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-11soc/intel/fsp_baytrail: set up for including irqroute.h twiceMartin Roth
irq_helper.h intentionally gets included into irqroute.asl twice - once for pic mode and once for apic mode. Since people are used to seeing guard statements on the .h files, add the guards to irqroute.h and add a comment to irq_helper.h explaining why they aren't there. Add a time. Change-Id: I882cbbff0f73bdb170bd0f1053767893722dc60a Signed-off-by: Martin Roth <martin.roth@se-eng.com> Reviewed-on: http://review.coreboot.org/6572 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-10bolt: Set GPIO29 as input in S0, output+high in S3/S5Duncan Laurie
This resolves WiFi issues after suspend/resume. It needs related SPI descriptor soft strap change to enable SLP_WLAN as a GPIO instead of owned by the ME. Change-Id: I03f4458d1e52a913770d391061baa6cfa41e8558 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/170577 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit cf1fe0524ad4793c8c422dc3fed3007b7fc96038) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6533 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-10falco: Add support for Samsung memoryDuncan Laurie
New SPD and update to the SPD map. Add both a 4GB and 2GB option. 4GB = RAM_ID{1,1,0} 2GB = RAM_ID{1,1,1} Original-Change-Id: I37318c1b5a6ee84b7c55da00d326f10fe8af6f1e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit 7eb5a4ef1062a34e883c3f356ab0dc00ba07910d) Change-Id: I0f35a7f5191fefeb5910a2d28aea153516d9a11d Reviewed-on: https://chromium-review.googlesource.com/171693 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit b02fa777aa5935021b2c69f7345dffd111cbd118) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6545 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-10Falco/Slippy: Patch to remove redundant graphics initializationsFurquan Shaikh
gma_fui_init repeats the initializations already performed in gma_setup_panel. These redundant initializations reset any gtt settings done before this call. Hence, they had to be done again after call to gma_fui_init. However, the call gma_fui_init is not required at all. Does not affect the behavior of suspend/resume. Old-Change-Id: Idfb9f9930624694b878ddc0fe8648b3c8dd80e55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65997 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit c376aea1b89c9a829874d5c657693993a3bb1f13) Falco/Slippy: Patch to fix garbage on screen during graphics initialization in normal mode Depending on the init_fb parameter: 1) For normal mode, first page is filled with zeroes and setgtt is used make all GTT entries point to this same page 2) For developer/recovery mode, we init the gtt to consecutive pages Old-Change-Id: I281b0b7efe01f7892e98b19ff9a63c04b087bd2c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 97c99dfe52ef3a87d387fdbf27ad3a28ad81c722) Squashed two graphics related commits for Falco/Slippy. Change-Id: I7ddb92672c026fe66f9fb0caba9d8fdc3f8a9d0a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6536 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-09lenovo/x201: Enable wake on LID and Fn key.Vladimir Serbinenko
Change-Id: I485da5b8e9084c73f16b5df1c42879697fc0ac3d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6528 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-09intel/eagleheights/Kconfig: Do not set twice MMCONF_BASE_ADDRESSDaniele Forsi
Remove the lines added in an apparently unrelated commit 53ad9f58 (Make CONFIG_HAVE_HIGH_TABLES consistent in where and how it is set.) which touched the symbol HAVE_HIGH_TABLES in all files except this one and keep those added the same day in commit 6842c029 (Remove MAINBOARD_OPTIONS, which is a relic from early kconfig development.) Change-Id: Ib055c25a0a0795a50a36e65218c8f31e921f1502 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6417 Tested-by: build bot (Jenkins) Reviewed-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08falco: Remove RTD2132 chip and setup from devicetreeDuncan Laurie
This disables the spread spectrum clock and avoids errata. Old-Change-Id: I04eb767f1587bb64a215a92b66cd05e099d29964 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66673 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a7bf0d818c431221f4d014e3a0130bec8db7406e) falco: Remove RTD2132 driver from kconfig Original-Change-Id: I89ad9fbfbc58878602ed85ada918524426b5bc77 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66946 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit 1d732eb5e4743546b8ed50c8c44965a687f61ab2) Conflicts: src/mainboard/google/falco/Kconfig Old-Change-Id: I317a0741779e272ad72b7272ef6f4a67abd66698 Reviewed-on: https://chromium-review.googlesource.com/167311 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit ffa6c89fbac04b4b6fceafd4ba97d39a285c4aa3) Squashed two commits and corrected the subject line from 2312 to 2132. Change-Id: If4f1e59999b70efe2de45522ba78051d9ed88dd7 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6527 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-08-08Falco/Slippy: remove unwanted scratchpad writesFurquan Shaikh
Register range 0x4f000 - 0x4f08f includes scratchpad registers. Fastboot works fine with these registers removed and graphics is initialized properly Change-Id: Ic57c526a90619f4a073690440f6c5ac6ca96bf10 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65755 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> (cherry picked from commit 7e7befdc3956cbc28d346545669cb55c566cf3ea) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6525 Tested-by: build bot (Jenkins)
2014-08-08qemu-armv7/media.c: fix coding styleStefan Reinauer
Change-Id: I01a11923fc1b250afeed36acc20793fd072421ba Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/168574 Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 46b5f64096c55d0d9627cb9537fc4910e1bddcd9) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6520 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08falco: Add double function reset to ALC283 verb tableDuncan Laurie
The ALC283 needs a double function reset to ensure that all settings are reset and the firmware beep is functional. Original-Change-Id: Id9ddc6f4914957f39c5f9cdfaaac354808929146 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@google.com> (cherry picked from commit c59865ac464af308baedcd69aa662f46ff3a04d3) Change-Id: Ie6f3a8179376bc97a6d22712dd965f5e0e6ec5d6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/167313 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit b31d7a31b838e67a4b7f33119a3baea049d30a36) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6518 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2014-08-08Pit: remove backlight delayRonald G. Minnich
Change-Id: Ia2e5427fec1bfff9babb9c59a3878323277f4f4c Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66555 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 2b96235123d55db3ff5ae5c2454b65de831a1c18) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6524 Tested-by: build bot (Jenkins)
2014-08-08exynos5420: Implement support to boot with USB A-A firmware uploadJulius Werner
This patch ports the USB A-A firmware upload functionality from exynos5250 over to exynos5420. Essentially just like a conflictless cherry-pick of 9e69421f5f0eebf88c09913dee90082feab2856c. It also fixes the exact same bug with SPI initialization for Pit and Kirby. Old-Change-Id: Ief0ed54c0beb2701e51201041f9bc426b2167747 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65751 Reviewed-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 5dff43f929478f83939221df13b961a69f89b132) exynos5: Fix trivial style nits A few curly braces on the wrong line. Old-Change-Id: I4ddac4476c6509dc1716e8c1915fbdb67d346786 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66153 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 41e3fd9eaafe36433723f4e96a6d94c04e5fbafb) Squashed two related commits. Change-Id: I22d579693b5e7270aacb45bbe3557e40893dd1f8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6500 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-08lenovo/x230: Enable wake on LID and Fn key.Vladimir Serbinenko
Change-Id: Ifc7208400b0bdfa2b9b70773bd24e9f9df7f8048 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6526 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-07exynos: Set up caching in the bootblock.Gabe Black
This improves firmware boot time substantially. Because cbmem isn't available yet, we need to allocate some space in sram for the ttb. Doing cache initialization in the bootblock means we can implement this once per CPU instead of once per mainboard. Old-Change-Id: Iad339de24df8ec2e23f91fe7bf57744e4cc766c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65938 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> (cherry picked from commit c32b9b32ad933e627b9ea98434b392239b1fea73) exynos5420: flush caches and disable MMU in resume path This patch flushes the caches and disables the MMU before resuming. c32b9b3 ("Set up caching in the bootblock.") had a bug where the dcache and MMU remained enabled in the resume path. This caused the machine to hang on resume. However, other bugs were preventing us from testing this properly earlier on so it went unnoticed until now. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ib1774f09d286a4d659da9fc2dad1d7a6fc1ebe5e Reviewed-on: https://chromium-review.googlesource.com/67007 Reviewed-by: ron minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 4fdf9763d25f70fd1e3591f6ff9785f78dd6170d) Squashed two related commits. Change-Id: Ibd42b28bb06930159248130e5ceaddb3b4b6cc2a Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06slippy/flaco/peppy: setup beep verbsMarc Jones
Add verb setting for beep during recovery and dev mode. Requires depthcharge CL. Change-Id: I13cbb4e889ebc4c27bb4ab9fa49601b03e872d09 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66519 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Dylan Reid <dgreid@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit c072543946b317192a8e80a744c1515deb414456) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6502 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-06lenovo/x201: Enable pcie lanes in wwan slot.Vladimir Serbinenko
Change-Id: I7332eeed244877252074e661f1c256a69a9b428a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6482 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-06mainboard/amd: De-ASCIIartify AGESA board headersEdward O'Callaghan
As was done for the reference boards in: cd30951 mainboard/amd: De-ASCIIartify reference boards Change-Id: Ie34aa5269388b771daa6934f8aff0314ac6778d5 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6290 Tested-by: build bot (Jenkins) Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
2014-08-06gizmosphere/gizmo: Change the PCIe GPP to two x1 portsDave Frodin
Gizmo sends two southbridge GPP PCIe lanes to its high speed edge connector. This change will allow developers to create two x1 slots on an extender card. Change-Id: Iba6c1a4caf7846d12e3960775d7bc906ca8ff385 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/6499 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-06lenovo/t530/mainboard.c: Include header `h8.h` for prototypeEdward O'Callaghan
Change-Id: I05cea020e77051bd3bc0e93b0c70e12b9b985d05 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6398 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-05exynos5420: get rid of old exynos5420_config_l2_cache()David Hendricks
We set up L2 cache early in romstage now so the old function is now redundant. Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Icec93810ddd7feb48286d4b600cb2d58af38b7ef Reviewed-on: https://gerrit.chromium.org/gerrit/65428 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit bb91f1078ea55a7c8bdc19336cef2ec9a5f4511f) exynos: stack size: Increase the stack size to 16KB. The lzma decoding function in the RAM stage allocates nearly 16KB on the stack which is shared between the bootblock, rom stage, and ram stage. The stack had been much too small and needed to be expanded. Old-Change-Id: I1b74fff9b54e506320d58956b779b3a102e66868 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65937 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> (cherry picked from commit 243d8a80f68dd257ecc5b4e19614bc7f0f5d398b) exynos: gpio: add a bigger delay when reading board strappings Z-state pins were not reading reliably with a 5us delay, so increase it to 15us. This is ported from https://gerrit.chromium.org/gerrit/64338 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: Ife6ea2ef5989e1a4c17913278ab972f0fd7f7f35 Reviewed-on: https://gerrit.chromium.org/gerrit/65727 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 76f0f8203f1af3f461745cefcc94e97c422d9084) exynos5420: enable DMC internal clock gating lets enable memory controller internal clock gating for ddr3. with these bits enabled we save some power out of ddr3. This is ported from https://gerrit.chromium.org/gerrit/#/c/60774 Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I2f9b0d78483b3ea7441f54a715c7c1e42eda3f7f Reviewed-on: https://gerrit.chromium.org/gerrit/65728 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 022a81c44e655a9f81e974e730c0cecc1f048781) exynos5420: Correct the 600MHz PMS value In UM ver0.02, 600MHz clock PMS values differs from what is programed currently. Though this also results in 600MHz clock, but it is better to match what UM says. This patch chnage this as per UM This is ported from https://gerrit.chromium.org/gerrit/#/c/65106/3 (Note: we already used the correct 600MHz value for KPLL) Signed-off-by: David Hendricks <dhendrix@chromium.org> Old-Change-Id: I6786815ab33427a23436e6ee37295f6c37dcd3d5 Reviewed-on: https://gerrit.chromium.org/gerrit/65726 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit ceabf57ca78449fa6e9cfd212bdf4774706de92f) Squashed five commits pertaining to exynos. Change-Id: I3fd894aed15b8cd161c30904a46dac7e07eb8992 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6425 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04lenovo/t520/mainboard.c: Include header `h8.h` for prototypeElyes HAOUAS
Change-Id: I5ac6608ebf78f2d48bc7f68bce9eae7a2be82332 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6424 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04peppy: Force enable ASPM on PCIe Root Port 1Shawn Nematbakhsh
(Clone of Falco change Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8) Old-Change-Id: I5feba8fdbafba6d2de9f7d3de6170defc0d45a32 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66536 Reviewed-by: Dave Parker <dparker@chromium.org> (cherry picked from commit b78a872a6647d7bb82f6c06a75e4075e451a1622) peppy: Disable unused clocks CLKOUT for PCIE ports 2-5 and CLKOUT_XDP are not used and can be disabled. This change was modled after the change made in Falco: Falco-Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b The only difference per schematic for Peppy was PCIe 1 supports a NGFF interface. PCIe 0 is connected to WLAN. Old-Change-Id: Ib4871cb2655316cb260ab33ada6b9d81f271377f Signed-off-by: Steven Sherk <steven.sherk@se-eng.com> Reviewed-on: https://gerrit.chromium.org/gerrit/66693 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> (cherry picked from commit 8f12335013a510dee3c21b55251ab00c0fbac609) Squashed two related commits. Change-Id: Ibc5b902018eec07fdccaa8c6cb066ce918f6a6b5 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6419 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-08-04falco: Re-read critical temperatures in ACPI _TMPDuncan Laurie
There seem to be a significant number of shutdowns during suspend resume tests related to critical temperatures. It is possible that we are getting a bad reading from PECI and shutting down prematurely in some cases. If we get a reading that is above critical then wait for the EC to re-poll and then re-check the temperature in case it was just a bad reading. Also add some ACPI debug messages when this happens. Original-Change-Id: I0ab7bdcc50d133981c0f36fc696b06d4a1d939a7 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/66937 Reviewed-by: Aaron Durbin <adurbin@chromium.org> (cherry picked from commit a39d7b11dd7b2af37fc2658542d56b32e3966ed4) Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Ib612266511d90749ec6507f8467c71523ee8fb95 Reviewed-on: https://chromium-review.googlesource.com/66939 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> (cherry picked from commit e98da983dca7819490464bddf08b9c53f28d2712) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6457 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-08-03nehalem: Make UMA size configurable in CMOS.Vladimir Serbinenko
All modes tested on X201. Change-Id: I23df81523196ea3f5fdb10eb04f4496c00aaeb9f Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6481 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-08-03sandy/ivybridge: Make UMA size configurable.Vladimir Serbinenko
Change-Id: I9aa3652d1b92cece01d024e19bdc065797896001 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6470 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-31armv7/exynos5420: Configure CPU cores for kernel to enable SMP.Hung-Te Lin
The SMP on Exynos 5420 requires setting a special page and entry wrappers in firmware side (SRAM) so kernel can start cores (and to switch clusters). Change-Id: I77ca98bb6cff5b13e95dd29228e4536302f0aee9 Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64770 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> (cherry picked from commit 4a11c7ab78cc0811df0f88763b0af8b9f24e5433) Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6405 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000Martin Roth
Add the Mohon Peak CRB. Updates to come. Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6371 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-30i82801ix: Allow configuration of SATA mode in CMOS.Vladimir Serbinenko
Change-Id: Ice0f0273b16a946143c038a90b61978269c1c56e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6409 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-30artecgroup/Kconfig, linutop/Kconfig: Add comment to endifDaniele Forsi
All other Kconfig files at the mainboard vendor level have a comment on "endif" matching the corresponding "if", except these two. Change-Id: Ib03c4552c670178d6b09a2ca3037ee29e3524a2f Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6396 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-30Kconfig: Fix comments on endif to match the corresponding ifDaniele Forsi
Change-Id: I5c40de41a01d9c558f6c2795e19e643009804e70 Signed-off-by: Daniele Forsi <dforsi@gmail.com> Reviewed-on: http://review.coreboot.org/6397 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-07-29gm45: Move spd address map to board-specific config.Vladimir Serbinenko
Change-Id: I8f45a821ecd414dbd0129ae6d583d4e7dc06bc5a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5931 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-07-29pit: setup voltage rails before system clocksDavid Hendricks
This moves the call to setup_power() before system_clock_init(). This causes the PMIC to set up the voltage rails earlier so that the CPU clock can be set up at a faster rate (in the follow-up patch). After system clock init, we re-initialize the PMIC's I2C bus since the input clock rate will have changed. Old-Change-Id: Ieb828ac25daad7ee95bfa4823aaaf161028c9c92 Reviewed-on: https://gerrit.chromium.org/gerrit/64744 Reviewed-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 6c133a84ef4a32c35577a266905e02af8c2d9278) pit: save setup_power() status and die later if needed Since system clock and console initialization now happen after power setup, we cannot print error messages in setup_power(). This patch re-factors the code a little bit to save the status of setup_power() so that if we get an error during setup_power() we will wait until we can actually print something before dying. Old-Change-Id: Id7ff477224b104b3c7e221c1d2df460ca9125f3b Reviewed-on: https://gerrit.chromium.org/gerrit/65009 Reviewed-by: Gabe Black <gabeblack@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> (cherry picked from commit 0c89f922b20bc1291ac7ba7b2c22bdce911be7a4) Squashed two closely related commits. Change-Id: I3efe29412738959e698c89d26e682536ceabdff8 Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com> Reviewed-on: http://review.coreboot.org/6403 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-07-29lenovo/x201 & x230: Add EC info to SMBIOS.Vladimir Serbinenko
Based on X60 counterpart. Change-Id: I1556f75db08edf47c9313dae91072335240d46ad Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4780 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29ec/lenovo/h8: Apply ME workaround on X230 on S3 resume.Vladimir Serbinenko
This makes S3 work. Change-Id: Ife14372f5f9bb151d7e6e98c6069eb99d5369baf Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/6392 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29nehalem: Remove fake_vbt copying.Vladimir Serbinenko
Instead generate simple VBT in code. Tested on X201. Change-Id: I2244053edd24c22694161d9bf5f7f2f3eb4e2f57 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5895 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins)
2014-07-29ivybridge: LVDS gfx init.Vladimir Serbinenko
Change-Id: If71e9c94922cd4283d5e175dfd8757d398a72be1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5285 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-29sandy/ivybridge: Native raminit.Vladimir Serbinenko
Based on damo22's work and my X230 tracing. Works for my X230 in a variety of RAM configs. Also-By: Damien Zammit <damien@zamaudio.com> Change-Id: I1aa024c55a8416fc53b25e7123037df0e55a2769 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: http://review.coreboot.org/5786 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA boards: Drop get_bus_conf.c filesKyösti Mälkki
The only remaining purpose for get_bus_conf() was to fill in obscure bus_sb800 (etc.) arrays containing partial PCI bus enumeration. Complete enumeration is available in devicetree and PCI configuration space so discard these arrays. Change-Id: I733115940afba3a50c58aedb9a04ecf5082b1234 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6360 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA f14 f15tn 16kb: Move IOAPIC ID setup out of get_bus_conf()Kyösti Mälkki
Change-Id: I7fd14c17242cd3deb7a784fc918ad6fe1191bd13 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6359 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA boards: Use devicetree for PCI bus enumerationKyösti Mälkki
Previously MP table contained PCI_INT entries for PCI bus behind bridge 0:14.4 even if said PCI bridge function was disabled. Remove these as invalid, indeterminate bus number could cause conflicts. PCI_INT entries with bus_sb800[2], bus_hudson[2] and bus_yangtze[2] were invalid as there is no PCI bridge hardware on device 0:14.0. Remove these as invalid, indeterminate bus number could cause conflicts. Change-Id: Ie6a3807f64c8651cf9f732612e1aa7f376a3134f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6358 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA: Have IRQ routing in mptablesKyösti Mälkki
MP table should be complete with IRQ routing information even when we have ACPI tables. Change-Id: Ieeaed442aea6217f4477b7ac7e06a1926eec8996 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6361 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA fam16kb: Move NB config fam16kb out of get_bus_conf()Kyösti Mälkki
Change-Id: Iedb5e1c72afe70f63f39c2dbce4896863d1d275f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6357 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-28AGESA: Drop some excessive agesawrapper.h includesKyösti Mälkki
Change-Id: I3807912b1dc68fae8248a66e37bbe642fb92d3ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6262 Tested-by: build bot (Jenkins)
2014-07-25AGESA f15tn f16kb: Fix HUDSON_XHCI_ENABLEKyösti Mälkki
Control for XHCI was split to handle AMD_INIT_RESET in agesawrapper while AMD_INIT_ENV was already handled as part of BiosCallouts. OEM configuration is supposed to be implemented as part of BiosCallouts, leaving agesawrapper agnostic of platform details. TODO: S3 resume for XHCI1. Change-Id: Id5e9c25a227db4d821f1be4b176470547ca4ea84 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6241 Tested-by: build bot (Jenkins) Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-07-24AGESA hudson yangtze: Move IMC firmware init out of get_bus_conf()Kyösti Mälkki
Change-Id: I5b3cbc4d25f06a5f916760d4474621abbf826ee4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6355 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA: Drop offset on PCI device enumerationKyösti Mälkki
Integrated PCI devices in southbridge silicon have static BDFs, no need to have variables to store the parent bus or an offset with constant zero. Change-Id: I37d3794d36b5e5775da9215574ddc199696646d0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6333 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA: Drop unused extern declarationsKyösti Mälkki
Change-Id: I7f681b40251f49ff717589ed5e7d7e00ee36c7c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6332 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA fam15: Drop code that was commented outKyösti Mälkki
Only references to bus_rd890, bus_sp5100 and bus_sr5650 were in code sections that had been commented out. Change-Id: If5552c409ce948c494345f49dbaad790b398bff8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6331 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA boards: Drop global bus_isaKyösti Mälkki
Only ever used as lvalue (except when incrementing) so this global is unused. Change-Id: I616721f937eb0bfdb28f356284efd70f99ccd2dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6330 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24AGESA fam15: Use local bus_isa storageKyösti Mälkki
Do not use a global as the value gets discarded anyway. Change-Id: I86aac304e073f0d74b011548d079e139891ec140 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6329 Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24amd/dinar & torpedo: Remove trailing whitespaceElyes HAOUAS
Change-Id: I4ac14c4f511eb6d56480e5167ce98b861cbed775 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6322 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24src/mainboard: Remove trailing whitespaceElyes HAOUAS
Change-Id: I14a9dc99acb5d5365a3d7e99a3964120bb611b05 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6308 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24mainboard/msi/ms7135/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: I4151e8ac8903d0daa1e7b12ecadbab8ff7adaaeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6349 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24mainboard/msi/ms9185/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ifea7c078b5246d4f48da2da1d58d4a5b2b05e6f5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6350 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24msi/ms6156/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ib2c08b58ab98d681f34a435c5ddcb4a9cbab65c1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6348 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24lippert/spacerunner-lx/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: I1a5b5d19ff72b028bbf5bb1c1414eebbf9827a2b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6351 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24lippert/literunner-lx/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: Ib71e25a33e7fe6d43f2ebac0494c263318fa243e Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6352 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24thomson/ip1000/devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: I79c1d1187b1fb44337c1a82bfd9b5871cd43e3e3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6354 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24mainboard/lippert's devicetree.cb: Remove trailing whitespaceElyes HAOUAS
Change-Id: I995b7946b56ed759dc2abac34797fa4747ea9f34 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6353 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24mainboard/msi/ms9282: Remove trailing whitespaceElyes HAOUAS
Change-Id: I93808f7798a18ab0993401af556fbb65dbcee32a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6347 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24siemens/sitemp_g1p1: Remove a trailing whitespaceElyes HAOUAS
Change-Id: I88366c7cb80d65d84c9f4ea5d287639a9de95a2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6323 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24supermicro/h8qgi & h8scm: Remove a trailing whitespaceElyes HAOUAS
Change-Id: I9d44679f32b917dae42b9a6920c3d3c54626dcda Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6324 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24tyan/s8226: Remove a trailing whitespaceElyes HAOUAS
Change-Id: Ic47cf1b55fc0d8b22d30d822b1744847e84d5a43 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6326 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-24broadcom/blast/devicetree.cb: Remove a trailing whitespaceElyes HAOUAS
Change-Id: I76e54669a0e129adf6c7873585c62f692a5d509f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: http://review.coreboot.org/6346 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-19nehalem: Move cbmem_recovery call to raminit.Vladimir Serbinenko
Currently cbmem_recovery is done in raminit only on non-S3-resume path do it on both paths to reduce confusion. Change-Id: I16161ad449b9802a855fcf834aa721f4f65c0bb4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5954 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins)
2014-07-19lenovo/x60: Support digitizer on X60t and X201t.Vladimir Serbinenko
Change-Id: I5b0399a8edca3b73aa7d515d2c446c31b3239fa5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5239 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-07-18mainboard: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: If29a70be4fb56ebb0dbf6d510412cbe2f34480ef Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6291 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-18src/superio/smsc/lpc47m15x: Avoid #include early_serial.cEdward O'Callaghan
Provide proper header and function type-signatures for Super I/O romstage component. Fix mainboard's bogous romstage component to match. Change-Id: Icd02199690d0c428b2daadf702d50714dc367692 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/5924 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2014-07-18google/panther: general cleanup, file organization (non-functional)Matt DeVillier
acpi_tables.c: consolidate/organize headers chromeos.c: consolidate/organize headers; move header, #defines outside of #ifdef fadt.c: organize headers gpio.h: rename include guard; add comment to trailing #endif had_verb.h: add include guard; replace manual array size calculation with std header macro lan.c: remove conditional header inclusion; organize headers; remove pre-processor directive indentations mainboard.c: remove conditional header inclusion; organize headers; replace spaced indentations with tab(s); add comment to trailing #endif onboard.h: move fn prototype after #defines; add comment to trailing #endif romstage.c: consolidate/organize headers smihandler.c: organize headers; remove commented-out/dead code; add comment to trailing #endif thermal.h: add comment to trailing #endif Change-Id: Iadafdd1092108c3f52435831fa0103f2457066f1 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6270 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-18src/superio/ite/it8772f: Separate mainboard from SIO at obj levelEdward O'Callaghan
Remove #include early_serial.c and rename to early_init.c as no actual UART configuration is done here. Note that this SIO component still hard codes its base address to 0x2e. Change-Id: Ieef32ac7285246717f0519ffed4314ba28cd47dc Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6271 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-18mainboard: Make use of ARRAY_SIZE in buildOpts.c on AGESA platformsEdward O'Callaghan
Found using coccinelle. Change-Id: I406de6cfe25d3b471dbb6f98d9c62addae008de3 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6195 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-17AMD get_bus_conf(): Drop bus_type arrayKyösti Mälkki
Only ever used as lvalue, so no point creating the array. Change-Id: I6699dfae9377a895e9bc4a52579d00ddcfa60a9f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6277 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
2014-07-17mainboard,Makefile.inc: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: I6a95debbe86fddcaf94270dd380bc73ce3172e58 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6283 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-17mainboard,ASL: Trivial - drop trailing blank lines at EOFEdward O'Callaghan
Change-Id: Ib531a54db7df6b49a6218f689dcaab712e9dfb01 Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-on: http://review.coreboot.org/6292 Tested-by: build bot (Jenkins) Reviewed-by: Idwer Vollering <vidwer@gmail.com>
2014-07-14AGESA Hudson: Fix typecasts in Fch_Oem_config()Kyösti Mälkki
Like many other (but not all) BiosCallouts, StdHeader is also passed as ConfigPtr argument. Use that instead to make no assumptions of the real type of FchData as it changes depending of the StdHeader. Change-Id: Ibdf01d08e63b9e1b8e99ac16abb7f807d37a056e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6240 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA boards: Use IS_ENABLED() for HUDSON_LEGACY_FREEKyösti Mälkki
Change-Id: Ib2a015dac82cec8538f8b1a1c2d45b20b05747bc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6239 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Martin Roth <gaumless@gmail.com>
2014-07-14AGESA CIMx: Move late init out of get_bus_conf()Kyösti Mälkki
Followup deals further with Fam15 case. For unknown reasons calls were commented out for amd/dinar and they remain that way. Change-Id: Ie0a25fbb6f5378019fbf0f19a02acf024d79817e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6237 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA: Trace execution with AGESAWRAPPER()Kyösti Mälkki
Implement logging just once to have uniform output. Change-Id: I8db694a3bf6b1af459bdf98f7acb99edf4dd07f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6180 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2014-07-14AGESA: Fix error status code return type to enum from UINT32Edward O'Callaghan
AGESA correctly uses the enum AGESA_STATUS type whereas boards use a mess of UINT32 typecasts. Also no need to shout VOID. We are not that careful on changing all cases of VOID->void or whitespace issues as these files will get merged with follow-ups. Change-Id: I16ccfcc73cda6b917c7ff5fd42ee2cd04e7dc0dd Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6182 Tested-by: build bot (Jenkins)
2014-07-12libpayload: find source of input charactersLuigi Semenzato
This change makes it possible for vboot to avoid an exploit that could cause involuntary switch to dev mode. It gives depthcharge/vboot some information on the type of input device that generated a key. BUG=chrome-os-partner:21729 TEST=manually tested for panther BRANCH=none CQ-DEPEND=CL:182420,CL:182241,CL:182946 Change-Id: I87bdac34bfc50f3adb0b35a2c57a8f95f4fbc35b Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://chromium-review.googlesource.com/182357 Reviewed-by: Luigi Semenzato <semenzato@chromium.org> Tested-by: Luigi Semenzato <semenzato@chromium.org> Commit-Queue: Luigi Semenzato <semenzato@chromium.org> Reviewed-on: http://review.coreboot.org/6003 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: adjust critical tempMatt DeVillier
Set critical temp to match newer devices Change-Id: I11f32297a9b8c9a3554821b5d1cd723d8d9e2b69 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: http://review.coreboot.org/6023 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Force enable ASPM on PCIe Root Port 4Stefan Reinauer
BUG=chrome-os-partner:21535 BUG=chrome-os-partner:25990 BRANCH=panther TEST=manual: Boot on Panther and look in /sys/firmware/log for the string "PCIe Root Port 4 ASPM is enabled" Change-Id: I294571c113a8909adb2e97afca92aef9a1af917c Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/187153 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6007 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: acpi: Fix unstable fan behavior on boot + resumeStefan Reinauer
FLVL is used to keep track of which thermal zones are active, but it is not initialized upon boot / resume. An initial value of zero corresponds to all zones being active, which causes the fan to spin at max speed until the OS changes zones. Fix this annoyance by initializing FLVL to the lowest temperature zone. Also, fix a related bug where FLVL may jump to an undesired value. For example, if FLVL=3 (zones 3 + 4 active), and zone 0 is set to off (it's already off!), FLVL would previously become 1 (zones 1 + 2 + 3 + 4 active!). Fix this by not taking zone ON / OFF actions if our zone is already ON / OFF. BUG=chrome-os-partner:25766, chrome-os-partner:24775 TEST=Suspend / resume on Panther 20 times, verify that thermal zone after resume matches expectation based upon temperature. Also, stress system and verify thermal zones become active according to temperature increase. Change-Id: Ic60686aa5a67bf40c17497832b086ba09d56111a Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186455 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186669 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6006 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Fix RW ramstage indexStefan Reinauer
Without this patch coreboot will always use the read-only version of ramstage, even if there is a read-write version available. BRANCH=panther BUG=chrome-os-partner:25870 TEST=Install different RO and RW version, check in cbmem log that coreboot's romstage and ramstage have different timestamps in their banners. Change-Id: I723a3d4479d59534660728d891a9f40a077b4ef0 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186664 Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/6005 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Add new thermal valuesMohammed Habibulla
Based on latest thermal report BUG=chrome-os-partner:24532 TEST=boot tested on panther BRANCH=panther Change-Id: I4b8639f926fc3cf57eb5329818b9b912bfbe222d Signed-off-by: Mohammed Habibulla <moch@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/186113 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6004 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Avoid shutdown when thermal sensor is unavailableStefan Reinauer
When the thermal sensor on Panther is unavailable (early on resume) it will return 0x80 which causes our AML thermal code to overflow, which causes the system to shut down. Instead, return a reasonable value in those cases so that the system will continue running until the sensor gets back on its feet. BUG=chrome-os-partner:24918 BRANCH=panther TEST=suspend_resume_test survived more than 100 iterations on Panther Change-Id: Ib2d714c39d353ce2415361bc6590784a3f6837d2 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182369 Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6002 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Re-read temperature if current reading would cause power-offStefan Reinauer
Sometimes the SuperIO seems to provide wrong readings, especially early on after a resume from suspend. This will cause the system to power off. If that happens, wait for 1s and read again, to make sure the high temperature value was not just a flaky read. BUG=chrome-os-partner:24918 BRANCH=panther TEST=Boot tested on Panther. Change-Id: Ib3768528d90e34448e96ad587b2503d8d8b1a775 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182188 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6001 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-07-12google/panther: Disconnect speaker and mic in verb tableStefan Reinauer
There is no speaker and no builtin microphone in this system, hence disable them in the verb table. BRANCH=panther BUG=chrome-os-partner:24230 TEST=Boot Panther, see Microphone and Speaker disappear in Audio Settings Change-Id: I32bacec38ba3ba0c2359a8fc94e12af64f576012 Signed-off-by: Stefan Reinauer <reinauer@google.com> Signed-off-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: https://chromium-review.googlesource.com/182006 Reviewed-by: Dylan Reid <dgreid@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/6000 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 21:04:27 +0000