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don't use non-volatile pointers for MMIO access
Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: http://review.coreboot.org/12081
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The reintroduction of cougar_canyon2 crossed beams with the
moving the GMA display brightness data in ACPI into individual
mainboards.
Make things build again by having the board use the same default values
that it used to use automatically. They may be wrong, but no worse than
what was there before.
Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: http://review.coreboot.org/12132
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Those are actually board specific. Keep the old value as defaults,
though. The defaults are included by all affected boards.
Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11705
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
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Please don't remove chipsets and mainboards without discussion and input
from the owners. Someone was asking about cougar canyon 2 just a couple
of weeks ago - there's obviously still interest.
This reverts commit fb50124d22014742b6990a95df87a7a828e891b6.
Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9
Signed-off-by: Martin Roth <martinroth@google.com>
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: http://review.coreboot.org/12128
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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With the introduction of these options in commit b26156e
(bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.)
the default regressed to disable these capabilities. Maybe other boards
regressed too. I didn't check.
Change-Id: I220896e656d00145618e61d55b74904517c7d855
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: http://review.coreboot.org/11287
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Merge artifact -- don't check spd_index twice.
BUG=None
TEST=Build only
BRANCH=Auron
Original-Change-Id: I0cc372fec415646854aa931949ed0f57b473cb01
Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/234421
Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org>
(cherry picked from commit 850125141b52886c845161434a1320676e59534d)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I0070e3f26ebddba716905ebb934bcec4715c4b05
Reviewed-on: http://review.coreboot.org/11912
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Part of the following patch was lost in the merge from chromium.
This patch fixes up the spd_index for the copy from the SPD file.
In spd.c "spd_index *= SPD_LEN" will change the original spd_index
from gpio and let the following if(spd_index>3) to misjudge and
disable channel 1 incorrectly. So we calculate the index for spd file
memcpy when calling memcpy().
BUG=chrome-os-partner:32879
TEST=Can get total memory 4G on yuna 4G SKU
BRANCH=Auron
Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf
Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/234420
Original-Reviewed-by: Shawn N <shawnn@chromium.org>
Original-Commit-Queue: Shawn N <shawnn@chromium.org>
Original-Tested-by: Shawn N <shawnn@chromium.org>
(cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Change-Id: I03f9d63623e083c99d349d938fd802d828858f70
Reviewed-on: http://review.coreboot.org/11911
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Georg Wicherski <gw@oxff.net>
Tested-by: build bot (Jenkins)
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Serial number is derived from the MAC address of first NIC.
Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11901
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins)
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Do this to wipe error message and hexdump of SPD from console log.
Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11900
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Value of tRFCmin was incorrectly using 2 Gigabit chip data.
There was no observed instability or bug reports because of this.
Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/11899
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This chip is still being used and should not have been deleted. It's
a current intel chip, and doesn't even require an ME binary.
This reverts commit 959478a763c16688d43752adbae2c76e7764da45.
Change-Id: I78594871f87af6e882a245077b59727e15f8021a
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: http://review.coreboot.org/11860
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its
internal USB EHCI controller broken, with no assigned IRQ.
PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive
for the GPIO to use. They cannot be used for PCI devices at the same time.
Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/9993
Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
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In order to build stand alone verstage the chromeos.c
file needs to be part of the verstage target.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Change-Id: Id2b05548e4e10cd12002286913f2228b84802e63
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11828
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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In order to introduce a verstage which performs vboot
verification the cache-as-ram environment needs to be
generalized and split into pieces that can be utilized
in romstage and/or verstage. Therefore, the romstage
pieces were removed from the cache-as-ram specific pieces
that are generic:
- Add fsp/car.h to house the declarations for functions in
the cache-as-ram environment
- Only have cache_as_ram_params which are isolated form the
cache-as-ram environment aside from FSP_INFO_HEADER.
- Hardware requirements for console initialization is done
in the cache-as-ram specific files.
- Provide after_raminit.S which can be included from a
romstage separated from cache-as-ram as well as one that
is tightly coupled to the cache-as-ram environment.
- Update the fallout from the API changes in
soc/intel/{braswell,common,skylake}.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados.
Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302481
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Eliminate unused parameters from the console initialization.
BRANCH=none
BUG=chrome-os-partner:44827
TEST=Build and run on kunimitsu
Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/301204
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437
Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11814
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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board_id() returns an integer which is platform-specific. 0 for one port
is different from 0 for another port. So there is no default board_id()
and hence enabling it on boards other than urara would cause build failure.
Not enabling it on urara or just setting id to "(none)" as is default results
in board_id() = 0 which means urara and an error message on console.
Change-Id: I94618f36a75e7505984bbec345a31fe0fa9cc867
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/10379
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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MBa doesn't have a usable usbdebug port.
Change-Id: Ia8459daa5c9b9405c289954b28ecf1423b1f076c
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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Tested on T60 with intel graphics.
Change-Id: Id74d0a1315749052e7313135242e6b64862aa5e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/5345
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Only one value would work with corresponding gma code currently (which one
depends on board). Going forward, it's possible to compute which number can
be used, so there is no need to keep this info around.
Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11862
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Based on the info by Felix Held.
Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11857
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: Iff1864982f2f3337c33e56976a0d4eb36f171e66
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11854
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I036c2c300b2aac38b2c30ab86623c9c46b3c5c98
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11850
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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MBA has eDP and not LVDS, so it's not supported by our native init.
Change-Id: I489b7a98163b648f0e8000202117593c6b1aaf31
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11842
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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MBA has a soldered RAM without SPD, so you need to use stored SPD.
Change-Id: I0205e6c65ccbfe7764c12c815e60801a3c3623a5
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11841
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Just ran autoport on the data from MacBookAir4,2
Change-Id: Iba2a56a6846d81d29e6b090a9a31253ce240914d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/11840
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a
mess of it, by forcing a build-time error when CONFIG_POST_IO was not
being set. fsp 1.0 boards ended 'select'ing this in their Kconfig.
Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the
"select POST_IO" from boards that have it. Instead of implementing an
ad-hoc changing post code display and a delay based on port 0xed, just
encode the FSP failure code in the POST code. Since FSP failure codes
are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble.
Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/8485
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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mohonpeak is the reference board for Rangeley. I doubt anyone uses it
or cares about it. We jokingly refer to it as "Moron Peak". It's code
with no known users, so we shouldn't be hauling it around for the
eventuality that someone might use it in the future.
Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11790
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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We already have two other code paths for this silicon. Maintaining the
FSP path as well doesn't make much sense. There was only one board to
use this code, and it's a reference board that I doubt anyone still
owns or uses.
Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11789
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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This is a sad story. We have three different code paths for
sandybridge and ivybridge: proper native path, google MRC path, and,
everyone's favorite: Intel FSP path. For the purpose of this patch,
the FSP path lives in its own little world, and doesn't concern us.
Since MRC was first, when native files and variables were added, they
were suffixed with "_native" to separate them from the existing code.
This can cause confusion, as the suffix might make the native files
seem parasitical.
This has been bothering me for many months. MRC should be the
parasitical path, especially since we fully support native init, and
it works more reliably, on a wider range of hardware. There have been
a few board ports that never made it to coreboot.org because MRC would
hang.
gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so
the effort was abandoned at first. Once the native path became
available, the effort was restarted and the board is now supported.
In honor of the hackers and pioneers who made the native code
possible, rename things so that their effort is the first class
citizen.
Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11788
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
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Remove dummy data from hwinfo.hex as it is not needed
anymore in the system.
Change-Id: I4f328a4ef61741039eb2c030e23fea33f539c2bb
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11763
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Since microcode was moved to 3rdparty/blobs, we need to select
USE_BLOBS in Kconfig to get the submodule 3rdparty/blobs automaticaly.
Change-Id: I25e574fd90b830448cacccd16d01a5a2dbc8517d
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11764
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Inspired by the Sage source code (itself from coreboot).
Change-Id: I4864923166efb200882d895c572d1ee060c71951
Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com>
Reviewed-on: http://review.coreboot.org/11730
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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The thermal sensor interface exposed in function 3 of the northbridge is
a more convenient and faster way to access the processor-internal
thermal sensor than using the SMBus/SB-TSI interface from the FCH, see
the Family14 BKDG: "Tctl is a processor temperature control value used
for processor thermal management. Tctl is accessible through SB-TSI and
D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the
processors cooling requirements"
Also on at least some of these boards the existing thermal zone is
broken and always returns 40C (the default value if the SMBus read
failed) because the SMBus muxing register (SmBus0Sel) is not set up
correctly.
Case in point: The fallback "smbus read failed" temperature is 40 C and
the the logs taken from the board status repository for the Asrock
E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)"
e.g.
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-5054-gf584218/2013-12-20T20:56:20Z/kernel_log.txt#l390
and
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-7030-g6d7de4f/2014-10-16T15:34:19Z/kernel_console.txt#l404
and
http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-9989-gf2dfef0/2015-06-13T00:22:49Z/kernel_log.txt#l425
Example lm-sensors output with this patch on the pcengines APU1, on
Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and
CONFIG_SENSORS_K10TEMP enabled):
acpitz-virtual-0
Adapter: Virtual device
temp1: +54.0 C (crit = +100.0 C)
k10temp-pci-00c3
Adapter: PCI adapter
temp1: +54.0 C (high = +70.0 C)
(crit = +100.0 C, hyst = +97.0 C)
Change-Id: Id9c5b783ba424246816677099ec6651814e59f21
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Reviewed-on: http://review.coreboot.org/10940
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Add some missing devices to device tree and header.
Remove the obsolete devices.
Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11378
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The vboot verification in a stage proper is unified
replacing duplicate code in the tegra SoC code. The
original verstage.c file is renamed to reflect its
real purpose. The support for a single verstage flow
is added to the vboot2 directory proper.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built glados.
Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11744
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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BUG=chrome-os-partner:41280
BRANCH=none
TEST=Audio jack insert/eject detection and headset buttons work
on glados with the nau8825 driver in chromeos-3.18 and the
staging kernel skl2.
Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb
Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80
Original-Signed-off-by: Ben Zhang <benzh@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/293610
Original-Reviewed-by: Anatol Pomazau <anatol@google.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11720
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fix the typo of _DDR to be _DDN.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build kunimitsu with iasl-20150717
Change-Id: I1e7c20d450ea897bfd24506d10a5f466b03610e4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f136581b653bfb63aac24065c8837307e3fc5432
Original-Change-Id: I3358e6d3d05bcfc291199e8ef12ff92c66f5b74f
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302165
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11718
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Fix the typo of _DDR to be _DDN.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=build glados with iasl-20150717
Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad
Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/302164
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11717
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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While the romstage code flow is not consistent across all
mainboards/chipsets there is only one way of running ramstage
from romstage -- run_ramstage(). Move the
timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage().
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built and booted glados. TS_END_ROMSTAGE still present in
timestamp table.
Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11700
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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When building for ChromeOS, it is expected that Coreboot will only occupy the
first MiB of the SPI flash, according to the veyron fmap description.
Otherwise, it makes sense to use the full ROM size.
Change-Id: I168386a5011222866654a496d8d054faff7a9406
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Reviewed-on: http://review.coreboot.org/11117
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of reaching into src/include and re-writing code
allow for cleaner code sharing within coreboot and its
utilities. The additional thing needed at this point is
for the utilities to provide a printk() declaration within
a <console/console.h> file. That way code which uses printk()
can than be mapped properly to verbosity of utility parameters.
Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11592
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This is a follow-up patch to
https://chromium-review.googlesource.com/#/c/286877, after fsp support
is landed in v1.5.
BUG=chrome-os-partner:42975
BRANCH=none
TEST=execute "mosys memory spd print all" on glados and kunimitsu
Change-Id: I949e287372b190affac36a0efde8a30402eecdc8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa
Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/298967
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11657
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Assign GPE DW0 to GPP_B block
- Enable GPP_B16 as ACPI_SCI for wake
- Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
Note that current designs cannot wake from Deep S3 via wifi.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529
Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298232
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11651
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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- Assign GPE DW0 to GPP_B block
- Enable GPP_B16 as ACPI_SCI for wake
- Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW
Note that current designs cannot wake from Deep S3 via wifi.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=tested on glados:
1-disable deep s3 in devicetree.cb
2-enable magic packet with "iw phy phy0 wowlan enable magic-packet"
3-powerd_dbus_suspend to go to S3
4-wake system with magic packet
Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2
Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298231
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11650
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The EC doesn't support these commands so sending them is
not working. We have had a default policy of wake on USB
for a long time now and this runtime config isn't really
needed any longer.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I547d92b4e852664567792060bf1f7b60976bb9a6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 4a929eb9ec422e145006505ea4d5fbd1ef3950be
Original-Change-Id: I01e80de65e6e1cdcabb24edb43bc671f5a8aa437
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298234
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11653
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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The EC doesn't support these commands so sending them is
not working. We have had a default policy of wake on USB
for a long time now and this runtime config isn't really
needed any longer.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655
Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298233
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11652
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Existing memlayout code placed sections in overlapping areas, and would
overwrite the payload if it was large enough. Update memlayout.ld in
src/mainboard/emulation/spike-riscv to represent the spike emulator, and
add sbi interface which now has room into src/arch/riscv/bootblock.S.
Add utility code to qemu-riscv, but emulator itself has yet to be
updated to new ISA and as such should not be used.
Update Makefile to include all the files necessary for sbi interface.
Clean up unused include in src/arch/riscv/include/atomic.h and
whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld
Fixed whitespace issues in spike_util.c
Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11370
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Kunimitsu has an ambient light sensor connected to the EC which
is presented to the OS as a standard ACPI0008 device.
BUG=chrome-os-partner:43493
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2
Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298252
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11645
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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Glados has an ambient light sensor connected to the EC which
is presented to the OS as a standard ACPI0008 device.
BUG=chrome-os-partner:43493
BRANCH=none
TEST=test ALS functionality on glados P2 board
Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054
Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/298251
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11644
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
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This patch will reset Deep S3 flag, hence S3 will work.
BUG=chrome-os-partner:40635
BRANCH=None
TEST=Build and Boot Kunimitsu and verify S3 is working.
Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5
Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/297903
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11643
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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RISCV requires the bios/bootloader to set up an interface by which it
can get information about memory, talk to host devices, etc. Put
implementation for spike in
src/mainboard/emulation/spike-riscv/spike_util.c, and
src/arch/riscv/trap_handler.c
Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11368
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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Remove the acpi_tables.c functions so these functions can move to
SOC init code. The file itself is included by x86/arch code and
must exist for the build to succeed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 93ae87f2429af5cb9d497f8b5ef8b8dffe370df4
Original-Change-Id: Ifc2f64dc1693e7bd3f5a43144d84ff033b2cfe8b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297759
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11580
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove the acpi_tables.c functions so these functions can move to
SOC init code. The file itself is included by x86/arch code and
must exist for the build to succeed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I18e6a0be5eac053598b613b30b622c4963417919
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2
Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297758
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11579
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove thermal.h as it is not used by this board.
Remove functions from acpi_tables.c so they can move to SOC.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-sklrvp coreboot (does not compile due to GPIO changes)
Change-Id: I934fcc451a722f853034c0970074ee3259cc704f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7e3b5c0ed8295091d3d5761b8456f3c13c6bd8bc
Original-Change-Id: If855f598e895e38c58657af17130158b2f73de81
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297757
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11578
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Clean up the intel/kunimitsu mainboard code to match the code
and cleanups in glados. Many of these are trivial changes that
do not impact things in a meaningful way but will make it easier
to diff the code and keep the mainboards in sync.
- use relative path for mainboard includes to make porting easier
- fix trivial style issues to match glados so diffs are clean
- pull GPIO configuration into gpio.h and use from there
- remove thermal.h as it is not used on this board
- make info message BIOS_INFO instead of BIOS_ERR
- add support for SPD manufacturer and part number in SMBIOS
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be
Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297752
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11576
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Select the EC PD and software sync kconfig options so they are
supported by the mainboard and call the EC early init function
to reboot into RO in recovery mode.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I48316df99b796c568c2481c72588b41f7147bec0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: c7507470f82848062bc98da809d3c5fe1ca31998
Original-Change-Id: I822aac9c24718f226819e5d3fcc82a4024b7c5a7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297751
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11575
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Select the BOARD_ID_AUTO kconfig option to have the coreboot
tables populated with the board ID and print it early in
romstage as well. Also clean up the code for it.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I90bd85ef14543717287cbeaaab77e6c54b94df97
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1fed7de4a0650a497a240b091fd2eb99d59e1433
Original-Change-Id: I82e9d17ab618b1aae1fd874d9247b7d52b42334d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297750
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11574
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Add support for reading board id and populating it in the
coreboot tables so it is exposed to payloads.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=boot on glados and look for reported board ID
Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004
Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297746
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11570
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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- Add ACPI code for DPTF support with placeholder thresholds
- Do not have custom PDL for mainboard
- Do not have enable charger control for DPTF as there is
already a complicated charge profile in the EC. We may still
want to enable this but it would need to be tuned to work
well with the EC profile.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a
Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297745
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11569
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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- romstage.c is using gpio_configure_pads so it should really
include soc/gpio.h instead of relying on it to come from "gpio.h"
- consistent formatting of array initializers in pei_data.c
- remove pei_data->ec_present flag as this is unused in skylake
- fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR
- clean up acpi_slp_type usage in ec.c, remove unnecessary post
codes, and cleaner console output message.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b
Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297744
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11568
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The constants defined in thermal.h are never used since there
is no defined thermal zone. Remove it to result in less code
to worry about in board ports.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10
Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297743
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11567
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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To make it easier to port glados to a new board name change
the include headers to use relative path name instead of
including the mainboard name.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90
Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297742
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11566
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Select the EC PD support in kconfig and call the EC early init
code that will reboot into RO for recovery mode.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=boot on glados in recovery mode
Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e
Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297749
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11573
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the new kconfig entry to select the EC PD chip and have it
be rebooted before the EC automatically insetad of being done
manually by the board.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-samus coreboot
Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199
Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297748
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11572
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This changes the API to rkclk_configure_cpu() such that we can pass
in the desired APLL frequency in each veyron board's bootblock.c.
Devices with a constrainted form facter (rialto and possibly mickey)
will use this to run firmware at a slower speed to mitigate risk
of thermal issues (due to the RK808, not the RK3288).
BUG=chrome-os-partner:42054
BRANCH=none
TEST=amstan says rialto is noticably cooler (and slower)
Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb
Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631
Original-Signed-off-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297190
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: http://review.coreboot.org/11582
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch removes a lot of code duplication between the virtually
identical Veyron Chromebook variants by merging the code into a single
directory and handling the different names solely within Kconfig. This
also allows us to easily add all the other Chromebook variants that have
only been kept in Google's firmware branch to avoid cluttering coreboot
too much, making it possible to build these boards with upstream
coreboot out of the box.
The only effective change this will have on the affected boards is
removing quirks for early board revisions (since revision numbers differ
between variants). Since all those quirks concerned early pre-MP
revisions, I doubt this will bother anyone (and the old code is still
available through the Google firmware branch if anyone needs it). It
will also expand a recent fix in Jerry that increased an LCD power-on
delay to make it compatible with another kind of panel to all boards,
which is probably not a bad idea anyway.
Leaving all non-Chromebook boards as they are for now since they often
contain more extensive differences.
BRANCH=None
BUG=None
TEST=Booted Jerry.
Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9
Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296053
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11555
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Modify DQ Byte Map and DQS Byte Swizzling to match up with design
BUG=chrome-os-partner:44647
BRANCH=none
TEST=System boot up and pass memory initialization
Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com>
Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de
Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78
Original-Reviewed-on: https://chromium-review.googlesource.com/295518
Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11551
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fix the PCI device list comments to be consistent between
mainboards and remove unused and incorrect register settings.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: Ib1c0eb80c57661502a4d4cfb4622a34effaa1c4a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 17c4f0d306194e7086f39f7ab560841999c318d8
Original-Change-Id: Ia1c138e52cbc3e81c0d12aa97d7f564e723d61f9
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297339
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11562
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Clean up the PCI device list comments to be consistent between
the skylake mainboards.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I0080ab21db006365f34995db06480dae68ac547d
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: fa21f77cbaafbc9ca0b98d6951df92c4349fa28d
Original-Change-Id: Ie70f94dcc12da141d82b4445643cc0cbe08bb766
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297338
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11561
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove devicetree.cb settings that do not apply to skylake so
they can be removed from chip.h and clean up the pci device
comments and add missing devices.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-sklrvp coreboot
Change-Id: I232bd62853685bdcda771e3cbaba2d8ee7437b81
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a22e1fa56c68b06192acbeeb5c76862d84b8f509
Original-Change-Id: I61f0581069d87ab974b0fffa6478b44a71bdd69b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/297337
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11560
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #. Due to a last minute formatting
change in my commit to enable USB ports this broke the kunimitsu
build.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-kunimitsu coreboot
Change-Id: I7a77f0f51345f779fcae43338cdc078bc91bb51c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 6454b377f865ec3d4e426fce3259f4df5d513ef5
Original-Change-Id: I19bde397018890db37257b55d0481e0c9f3a41f2
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296302
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11554
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The devicetree.cb compiler can't handle C style /**/ comments,
they need to be shell-style #. Due to a last minute formatting
change in my commit to enable USB ports this broke the glados
build.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: I46ee4e5a94d61eefbd2c9a1ba3cafcb6a9e7d71b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 8fa92f77b3ef13ede1029292d886351ab5ed87d2
Original-Change-Id: Ibff02a4fd6132def81006a2c6502d34bd4b72823
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296301
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11553
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable only the USB ports that are connected on-board or to an
external port, all others will be disabled.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=emerge-kunimitsu coreboot, change verified in schematic but not tested
Change-Id: I909a6fab553bba829349dd08fa9cc3f26e5adeb2
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1b0ce28d093e3b12273d7e0f56b47fb5b13d712f
Original-Change-Id: I0c4b7de6e559595efa97d756e43f8398feccdffd
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296036
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11549
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable only the USB ports that are connected on-board or to an
external port, all others will be disabled.
BUG=chrome-os-partner:44662
BRANCH=none
TEST=build and boot on glados, ensure expected USB ports still work
Change-Id: I8c999e3b17478effc39cf078f8420f63413d091b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b86268c70f86991f8c2cdd6763f8efe2ce7f9163
Original-Change-Id: I2fce2c401d07639892c4a0c01527173d3f0b2557
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/296035
Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11548
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable 1866 timings in the 4GB Hynix SPD.
BUG=chrome-os-partner:44394
BRANCH=none
TEST=emerge-glados coreboot
Change-Id: Ibb84f77565d46894afe2153f5951e17a450413fc
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f64d76a5f0b0095be96317674caf8542c3155423
Original-Change-Id: Ic5312176c21afc4569f723f5b7f00283b09262d7
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295174
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11528
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The reason for hardcoding the position of the MRC cache was to satisfy
the alignment to the erase size of the flash chip. Hardcoding is no
longer needed, as we can specify alignment directly. In the long term,
the MRC cache will have to move to FMAP, but for now, we reduce
fragmentation in CBFS.
Note that soc/intel/common hardcoding of mrc.cache is not removed, as
the mrc cache implementation there does not use CBFS to find the cache
region, and needs a hardcoded address.
Change-Id: I5b9fc1ba58bb484c7b5f687368172d9ebe625bfd
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11527
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The #include path during compilation already has '-I src'.
Don't encode the src part of a path.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built amd/thatcher while compiling romstage.c with C compiler..
Change-Id: If4fb1064a246b4fc11a958b07a0b76d9f9673898
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11512
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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When building up which files to include in romstage there
were both 'cpu_incs' and 'cpu_incs-y' which were used to
generate crt0.S. Remove the former to settle on cpu_incs-y
as the way to be included.
BUG=chrome-os-partner:44827
BRANCH=None
TEST=Built rambi. No include file changes.
Change-Id: I8dc0631f8253c21c670f2f02928225ed5b869ce6
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11494
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Some of the Chrome OS boards were directly calling vboot
called in some form after contorting around #ifdef preprocessor
macros. The reasoning is that Chrome OS doesn't always do display
initialization during startup. It's runtime dependent. While
this is a requirement that doesn't mean vboot functions should be
sprinkled around in the mainboard and chipset code. Instead provide
one function, display_init_required(), that provides the policy
for determining display initialization action. For Chrome OS
devices this function honors vboot_skip_display_init() and all
other configurations default to initializing display.
Change-Id: I403213e22c0e621e148773597a550addfbaf3f7e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11490
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Adjust gpio settings due to hardware change.
Change-Id: I4f493e5f46cbb9919c5b1a8ba294f8c34a07069a
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11489
Tested-by: build bot (Jenkins)
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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1. Update hwinfo.hex (add dummy data and update checksums).
2. Delete version.hex from mainboard directory. It can be added
in site-local if needed.
Change-Id: I7af9c4a5f606b96177a8ed4e3edf52535f2f1ec7
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: http://review.coreboot.org/11484
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Since more boards are starting to use the EC provided keyboard
backlight interface move the code to a common place and allow
it to get included in mainboards.
Change-Id: I3f307bbce1a96cdd1c8224b1e89a63d6fedef738
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/11478
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Change-Id: Ieaed5cf76c6f0a6a121e6add731d5c1e1528dfc7
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11375
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Without this change, if one USB3 device is attached when
the board is power up, the USB3 port can not be used.
Change-Id: I98628975000c7d56b1540c2b321d580ace1ef70e
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: Zheng Bao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/11377
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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This is just wrong. PAYLOAD_SEABIOS tells us nothing about whether
or not the payload will actually be SeaBIOS:
1. PAYLOAD_SEABIOS, but payload changed with cbfstool
2. !PAYLOAD_SEABIOS, but an elf payload was added which is SeaBIOS
et. cetera.
Change-Id: I4c17e8dde20bf21537f542fda2dad7d3a1894862
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/11293
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
Reviewed-by: Damien Zammit <damien@zamaudio.com>
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Reference CL:294712
BUG=chrome-os-partner:43072,chrome-os-partner:43707
BRANCH=none
TEST=build coreboot and boot on Kunimitsu Fab3.1
Change-Id: Ic89f3bcad1f4b4b1dfe39025a51bfcb97ad87158
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 1c73c1a345bb3ac397f2da2d14b25d688cc00a92
Original-Change-Id: If38fb37c092cbf4aaa339da6a777f2ba80e8cd2a
Original-Signed-off-by: Zhuo-hao Lee <zhuo-hao.lee@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295514
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11437
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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switch and SPI write protect for fill_lb_gpios() to coreboot table.
BUG=chrome-os-partner:43707
BRANCH=none
TEST=build and boot on kunimits
Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Change-Id: I82cd3f74d0ac26e369ee4274b2c65f4f93c1fd3b
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 804a8a60951321e1b5b1d7ddacb97ddbe0cd7680
Original-Change-Id: I31ed6c0e48089b84ef9d52753484253a091d5aa5
Original-Reviewed-on: https://chromium-review.googlesource.com/295580
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Commit-Queue: Wenkai Du <wenkai.du@intel.com>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11436
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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mainboard_ec_init() wasn't getting run due to an invalid
Kconfig symbol. This check isn't required as the Kconfig
option for the EC is forced to be enabled, and the function
should always be run.
BRANCH=none
BUG=none
TEST=Rebuilt glados mainboard.
Change-Id: I2c4a33d80533a19b02b83b3aaa6a3386e927f1c7
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: edd8c7a0666208b35ee81f57ec2626390958dfb7
Original-Change-Id: I2a92fd28347455c09ecf2119788ca9b6a97a11de
Original-Signed-off-by: Martin Roth <martinroth@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295143
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11435
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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recovery mode.
BUG=chrome-os-partner:43683
BRANCH=none
TEST=build and boot on kunimits and successfully enter recovery mode
by pressing “Esc + refresh + Power” keys.
Change-Id: Id25b9f2195f1caaa8b46967b4b5d4abdab48d6cc
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 96b1c295448b412a5662afc729fdd37294d3cb61
Original-Change-Id: I9f650b28b0a86b631ffdfe6de5d58d18e48a0a22
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295138
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11434
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=chrome-os-partner:44470
BRANCH=None
TEST=Builds and Boots on FAB3 (Kunimitsu)
Change-Id: I479fe60dcbdd51f4fa5bca857b4a166f958a54d5
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: e88efdd8766e2846a650eb75709b29035c406bf8
Original-Change-Id: I9fe5697d31e188fca48b14fb76e71631f2974c2d
Original-Signed-off-by: pchandri <preetham.chandrian@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295218
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11433
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Ported below patch from glados to kunimitsu:
glados: Abstract board GPIO configuration in gpio.h
Original-change-Id: I3f1754012158dd5c7d5bbd6e07e40850f21af56d
Originally-signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Originally-reviewed-on: https://chromium-review.googlesource.com/293942
BUG=chrome-os-partner:40828
BRANCH=none
TEST=Verify that acpi interrupts are incrementing on kunimitsu.
Change-Id: Ifeddb34289b6e62c936cf6c542906d6e7ef96ddd
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 8ff0dd2dcdf6485f0171fb967f7de3015cf4e4ad
Original-Change-Id: I1f270a03a241d2285639f79854d04059d2c2c99f
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295048
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com>
Reviewed-on: http://review.coreboot.org/11432
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The patch was ported from commit: glados: fix kepler probing
BUG=chrome-os-partner:44326
BRANCH=None
TEST=Built and booted kunimitsu. lscpi shows the device on bus 2.
Change-Id: I423e5d8414cb9864f6ff2f2ce7cd925baeb242eb
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 37bf5b7594a6784b3acb65410c670300e582e7aa
Original-Original-change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e
Original-Originally-signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Originally-reviewed-on: https://chromium-review.googlesource.com/294810
Original-Change-Id: I2fb620ebff5b477a1a457a354c65229ad1092cae
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295164
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11431
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch includes the DPTF specific ASL files in the main
DSDT definition and enables the CPU thermal participant device
in the device tree. It also enables the DPTF flag in the global
NVS table.It also adds the ASL settings specfic to the mainboard.
BRANCH=None
BUG=chrome-os-partner:40855
TEST=Built for kunimitsu board. Tested to see that the thermal devices
and the participants are enumerated and can be seen in the
/sys/bus/platform/devices. Also checked the temperature readings of the
cooling devices and the thermal zones enumerated in the /sys/class/thermal.
Change-Id: I5fb28e4480648eab39cc9b13ed55eae1d3db4d42
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 54f7f33a12eb5744d6108e362fa1d078fe838b3c
Original-Change-Id: I82527989919bd4f3c49fb58dfc9463f1c1bd3353
Original-Signed-off-by: Shilpa Sreeramalu <shilpa.sreeramalu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/284821
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294650
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Original-Commit-Queue: Naveenkrishna Ch <naveenkrishna.ch@intel.com>
Reviewed-on: http://review.coreboot.org/11429
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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forward port of "glados: make EC_SMI_L functional",
commit 50ed38feba58f
BUG=None
BRANCH=None
TEST=Built and booted kunimitsu.
CQ-DEPEND=CL:295012
Change-Id: I41daeb8b729f2de117b5d57c460925437460e50a
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: d9308c0b8eb05c756d88dc0c3d761c9e76d07e08
Original-Change-Id: Ia90c70d21af75d0f0da2af2b4437ccf26659a157
Original-Signed-off-by: robbie zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295045
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11428
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use the macro for GPP_E22_IRQ instead of the ACPI code so it
can be removed.
BUG=chrome-os-partner:40635
BRANCH=none
TEST=emerge-sklrvp coreboot
Change-Id: I09bea748fea34072d4f8ad7470d37e423b7f63de
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 89069f5f318329182390cad679511547b7d2a6d5
Original-Change-Id: Iad181b4ce1c557ce8d17645431d8ba6f558bb837
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/295171
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11427
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=chrome-os-partner:44336
BRANCH=None
TEST=Built and booted kunimitsu. Validation shows no regressions.
CQ-DEPEND=CL:294757
Change-Id: If4207e87cf22982162a8d5d47fa9e0509a2b2ab1
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 2f43fd6b7afc426d041a242a7e03dbf5800e1eee
Original-Change-Id: Id8ce1bd2f28d32898e99008e2a602d99a5c1098c
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/295012
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Reviewed-on: http://review.coreboot.org/11425
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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This is needed to fix error in depthcharge:
src/vboot/util/flag.c:38 flag_fetch(): Don't have a gpio set up
for flag 3.
BUG=chrome-os-partner:44214
TEST=Verify depthcharge prints EC ID on boot up
BRANCH=None
Change-Id: Ia2d88b8427e54e2dc9e6c9abecc95fd7656abb66
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 142b156c72ceedfbd4bf3f54c0cb1128c0fad5a3
Original-Change-Id: I7e7a7d1b92bc1ee2c5ebac8de6946550ddd68a68
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/294715
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11421
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move the gpio pad configuration prior to SiliconInit()
in case there are dependencies of the pads being configured
in prior to SiliconInit().
BUG=chrome-os-partner:43522
BUG=chrome-os-partner:43492
BRANCH=None
TEST=Built and booted glados.
Change-Id: I84f8e965bf205a4945b14a63fa8074953750f785
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 5cce5347449f69ac6cf7030ea3b91d3f8b4cc7f9
Original-Change-Id: I18cd33a455d5635a866abb76142cab516b04f446
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294642
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11420
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On proto2 boards the kepler device has its reset line pulled up
to one of its IO rails with a zener in between. This results in the
device not being visible at MemoryInit() time because for some
reason FSP is doing PCIE configuration/probing in that path. Hack
around the broken FSP logic by configuring the pads for kepler's
power and clkreq.
BUG=chrome-os-partner:44326
BRANCH=None
TEST=Built and booted glados. lscpi shows the device on bus 2.
Change-Id: I543eb3ccd3ab5ffacd6efc959e6e2f7a88de78b3
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: 67f6b57487e8724b469f74870e0083d4e1dac4d2
Original-Change-Id: I7fe4a707f9321b7bdec4b4be729c5d0dcce65f6e
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294810
Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/11419
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Export the proper GPIO for EC_IN_RW so it can be picked up and
used by depthcharge/vboot.
BUG=chrome-os-partner:43072
BRANCH=none
TEST=build and boot on glados P2
Change-Id: I32d338ef424086ec9701900e976bd0dffe4637a0
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Original-Commit-Id: dd983c84de0c3b896b20d38438a3285cfcaf7e56
Original-Change-Id: I77f7d3a0c0d733302b81273d96026d39b001ed19
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/294712
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11418
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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