Age | Commit message (Collapse) | Author |
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We define a mechanism to pass board specific parameters to BL31. The
idea is BL31 doesn't need to have the board revision knowledge, it
only needs to process the board specific parameters to initialize and
control specific hardware. In this way, we can support different boards
with same BL31 binary.
BRANCH=none
BUG=none
TEST=booted on oak-rev2 and oak-rev3 boards, and confirmed they got
different board arguments in ARM TF
Change-Id: I0df2c6d7d1ffac7d443511c3317c142efeb5701e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 0f9a4a2776110c5ddc113f0d605d4337d5773ace
Original-Change-Id: I985d9555238f5ac5385e126479140b772b36bac8
Original-Signed-off-by: Jimmy Huang <jimmy.huang@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292678
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13101
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BUG=none
TEST=emerge-oak coreboot
BRANCH=none
Change-Id: I3ed8bad1bdc7d17e334e0136f92a51c8e7ba4e67
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b614eeb1bba5660438c214e82225832809caca8e
Original-Change-Id: I0f7b0a426dae1548b34114a024c92befdf6002f6
Original-Signed-off-by: Peter Kao <peter.kao@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292692
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13106
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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BRANCH=none
BUG=none
TEST=boot oak to kernel on rev1
Change-Id: I0773c81398df445aec16bcfcd0c5a8fe5a588b5c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: ae15c42c2f7d9c2a716e5b6098d85e17279f5eae
Original-Change-Id: I65abf810d35ae5e7156cf6f5730117e690183d18
Original-Signed-off-by: mtk05962 <bayi.cheng@mediatek.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/292693
Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com>
Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13102
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add configuration in accordance to "PCI Configuration Matrix".
Change-Id: If1f60486d802a6595aed03d95e0d20fc7db21bd2
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13926
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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Use UDELAY_IO selected by CPU_VIA_C7, so no manual inclusion
(or secondary UDELAY implementation) is needed
Change-Id: Ib086a1bfe8ffca5757bf553c5a62a45da7a410b6
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13782
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Instead of manually including udelay_io.c in each romstage,
select UDELAY_IO for all i440BX boards in the chipset.
Change-Id: I411191927f3fba1d0749edcf79378e8013fb195a
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13781
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add a port of Auron_Paine based on upstream Auron and the Auron_Paine
code originally from commit bd61dfd in Google branch
firmware-paine-6301.58.B .
Change-Id: I3a1faec3195a81bb3a6496b8bd610fc8a89e66aa
Signed-off-by: Georg Wicherski <gwicherski@gmail.com>
Reviewed-on: https://review.coreboot.org/11907
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Pass memory training information to MemoryInit, so memory
training can be completed.
Change-Id: Icb1bf308b77a1c8481313c259c3f3dd1d8379863
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13870
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Nyan is an old board that was committed before several core code
modernizations to timestamp and CBFS code. Not all of those later
patches were correctly integrated with old boards like this, and the
core code has evolved to a point where it doesn't actually boot anymore.
This patch fixes that issue and brings the Nyan boards more in line with
how later ARM platforms look.
BRANCH=None
BUG=None
TEST=My Blaze boots again.
Change-Id: I3277a2f59ad8ed47063f7f6b556685313b1446f8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a1679e342a7adc2b2371b6e3f69a898a7a5c717
Original-Change-Id: I2a0a2abbd79b4b5f756125dcbb6cbd9441016d4e
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/328543
Original-Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: https://review.coreboot.org/13832
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Include the code to add the WRDD method to the existing
WiFi Device in the mainboard ACPI code.
BUG=chrome-os-partner:50516
BRANCH=glados
TEST=boot on chell with 'region'='us' in VPD and see that it is
properly read out by calling WRDD method on the WiFi device.
Compile for the other platforms that are modified.
Change-Id: Ibcff7585744071ba9018d0ba50e274e63365b150
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: b74bb553415f7ce224ddcb0c2c5ae509b8fed516
Original-Change-Id: Ieb24e0e64974ee3686d14a234e148f5d07fc8b12
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329296
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13840
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Set the UPD values for MemoryInit.
* Update the FspUpdVpd.h file which specifies the parameters for
MemoryInit.
* Add the necessary values to chip.h to enable values to come from
the mainboard's devicetree.cb file
* Add the parameters to the mainboard's devicetree.cb file
* Locate the platform configuration database file (pdat.bin)
* Copy the data values from the chip_info structure into the UPDs
* Display the UPD values
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_DISPLAY_UPD_DATA=y
* Testing successful when the UPD data is displayed before the call to
MemoryInit
Change-Id: Ic64f3d97eb43ea42d9b149769fc96bf78bf804f5
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13896
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)
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UDELAY_IO is defined in src/cpu/x86/Kconfig, so it does
not need to be redefined in the AMD cpu or board Kconfigs.
Change-Id: I6676881c0ba5d1634230fc3d3c37da3afbc6fceb
Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://review.coreboot.org/13780
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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On Apollo Lake SPI flash is memory mapped. The mapping is different
to previous platforms. Only "BIOS" region is mapped in contrast to
whole flash. Also, the 128 KiB right below 4 GiB are being decoded by
readonly SRAM. Fail accesses to those regions, rather than returning
false data.
Change-Id: Iac3fa74cd221a5a46ceb34c2a79470290bcc2d84
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13706
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Also re-organize some of the superio code in order
to succesfully compile the rom.
Change-Id: I85a6f1352ae3b91c3c98e4d3fa0b90b87e02babc
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13925
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Turn on the SD controller to allow it to claim resources.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful when at the UEFI shell prompt:
* After issuing:
* "connect -r"
* "map -r"
* The "dir" command displays the contents of the SD flash card
* The "drivers" command shows an SD host and SD media connection
Change-Id: I883dc87270045786ddb931bea83fc36646a128e6
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13894
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Remove dependency on early_serial.c and instead use the
Super I/O's header to access the functions needed.
Change-Id: I9edf7fc2501aa832106dda9213e702dbcc1200b4
Signed-off-by: Antonello Dettori <dev@dettori.io>
Reviewed-on: https://review.coreboot.org/13887
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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Sandy and Ivy Bridge processors use the same socket, and a mainboard
with the socket can support both types of CPUs. However, they use
different native graphics init code for LVDS and cause a crash if
running the wrong code.
This change detects the CPU type and then selects the right code to
run. It will add some more code in ramstage. It also merges the
{SANDY,IVY}BRIDGE_LVDS symbol to one SANDYBRIDGE_IVYBRIDGE_LVDS.
Tested on a Lenovo T520 with i7-2630qm and i7-3720qm
Signed-off-by: Iru Cai <mytbk920423@gmail.com>
Change-Id: I4624759f9c92d56d547db1ab4b9a1d611a182a91
Reviewed-on: https://review.coreboot.org/12087
Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
Tested-by: build bot (Jenkins)
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This patch provides config options to enable/disable Intel SST
(Speed Shift Technology).
BUG=chrome-os-partner:47517
BRANCH=None
TEST=Booted kunimitsu/lars, verified HWP driver load successfully.
CQ-DEPEND=CL:313107
Change-Id: I9419a754384f96d308a5ac2ad90bbb519edc296e
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 5efb7978e9d3ca9a709a4793ad213423a1c3c45d
Original-Change-Id: I328b074b4f56ebe3caa8952ce3df7f834c1cf40f
Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com>
Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/326650
Original-Tested-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Benson Leung <bleung@chromium.org>
Reviewed-on: https://review.coreboot.org/13843
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Update the DPTF configuration for the chell mainboard:
1) Enable DPTF charger control, set max current to 1975mA
according to the battery specification.
2) Enable charger effect on charger temp sensor in TRT
3) Set PL2 to 15W which is the same value configured in the CPU.
BUG=chrome-os-partner:49859,chrome-os-partner:50306
BRANCH=glados
TEST=build and boot on chell
Change-Id: I644256b9596cc5295513c48f5e3a18e6ce8b0a6b
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: c19740a227f932bf80e9243341ec81763779719c
Original-Change-Id: Icff5edc9d659bea6370ff8de1334ebf0983340da
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329187
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13842
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Add new GPIOs for touchscreen enable and reset pins and define
the one missing unconnected pin for GPP_E10.
BUG=chrome-os-partner:50518
BRANCH=glados
TEST=build and boot on chell DVT1
Change-Id: I565a742ff266ee65a5d33f052606fe77c24b6ac8
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 32a890af8c32aa30adac256d2c4ceaeefa30bd0d
Original-Change-Id: I16546d38cc4e926e169f61ae1843106d1e14936b
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/329297
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13841
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Instead of relying on power-on-reset values provide configuration
for all pads. PAD_CFG_NC() was used for all pads which had no nets
routed on the board. PAD_CFG_GPO(0) was used for pads which had nets
routed on the board in order to terminate them.
BUG=chrome-os-partner:50301
BRANCH=glados
TEST=Built and booted chell. Suspended and resumed on EVT.
Change-Id: I7960442d5c06f58a1b671cdefac71ef0bc3b0cd5
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 6a167cd0a747402bfc3cc9b6fbaaceceda766ee9
Original-Change-Id: I519011b049235dc2a960939c0bed274252dbffa8
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/327835
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13831
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Enable the EHCI and OHCI controllers.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful when at the UEFI shell prompt:
* After issuing:
* "connect -r"
* "map -r"
* The "dir" command displays the contents of the USB flash drive
* A USB keyboard can issue shell commands
* The "drivers" command shows an EHCI and OHCI connection
Change-Id: Iad9abced98d9b645e8b12fa0845c97260cf62a72
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13857
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Now that the SoC is configuring the UART pads there's no need to
implement bootblock_mainboard_early_init(). Remove it and
bootblock.c.
Change-Id: I2ae7ea38351733e1c9757cde20b79e1d19d0c1e5
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13794
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
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The used Baytrail-M SoC on TCU3 tend to have issues
with DisplayPort if the graphic power gate is not set up
in coreboot. To avoid this error, use the graphic init
code on this board.
Change-Id: I973bbaa7d86c1ede1f2884b3a08ccb31f7d85087
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/13774
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Use shared gpio code from common folder.
Remove the now unused bd82x6x/gpio.c.
Needs test on real hardware !
Change-Id: Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13616
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Use shared gpio code from common folder, except for
INTEL_LYNXPOINT_LP, which has it's own gpio code.
Needs test on real hardware !
Change-Id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13615
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable the minimal ACPI tables. Initialize the FADT header and provide
an empty DSDT.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file:
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Build EDK2 CorebootPayloadPkg/CorebootPayloadPkgIa32.dsc to generate
UEFIPAYLOAD.fd
* Edit .config file and add the following lines:
* CONFIG_PAYLOAD_ELF=y
* CONFIG_PAYLOAD_FILE="path to UEFIPAYLOAD.fd"
* Testing successful if:
* Outputs multiple lines of debug serial text
Change-Id: I2e30c8af2994c9f56d9ba4fe6bc35e133b1d2d6b
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13759
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I04c0cfea5d49eb70969d6ad38d5cb81d70eeaf9b
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13753
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Old map does not work on recent qemu. New map puts coreboot to ROM, so
it behave more like most real machines would.
For details on this map see comment in memlayout.ld
Change-Id: If1f3328b511daca32ba93da5a6d44402508b37e9
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13748
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
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This builds and produces an image.
The next step is to get a 'halt' instruction into the boot block and then attach with qemu.
I can't get the powerpc64le-linux-gnu-ld.bfd to recognize any output arch but
powerpc. That makes no sense to me.
Change-Id: Ia2a5fe07a1457e7b6974ab1473539c7447d7a449
Signed-off-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-on: https://review.coreboot.org/13704
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Enable HSUART1 for debug serial output. Specify the fixed resources in
the UART driver. This keeps debug serial output flowing during the rest
of the device initialization.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* Debug serial output stays enabled after BS_DEV_RESOURCES state
Change-Id: Ica02e5fece156b21d4a3889284ca467d55c7880d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13730
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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The GPIO USB_A0_ILIM_SEL & USB_A1_ILIM_SEL should be low to enable 2A
charging from the USB Type-A port.
BUG=chrome-os-partner:50212
BRANCH=glados
TEST=Build CB & booted kunimitsu, verified that USB_A0_ILIM_SEL &
USB_A0_ILIM_SEL are at logic zero.
Change-Id: I989987eaaa2015720bbb1403caf20b97a996e168
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 640834506ad749359104e24fdb664044d499fd5f
Original-Change-Id: I741f79a69b78dbb7d4f8cb9718355d802b94b96d
Original-Signed-off-by: Naresh G Solanki <Naresh.Solanki@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/327121
Original-Commit-Ready: Naresh Solanki <naresh.solanki@intel.com>
Original-Tested-by: Naresh Solanki <naresh.solanki@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13722
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Use shared gpio code from common folder.
Bd82x6x's gpio.c and gpio.h is used by other southbridges
as well and will be removed once it is unused.
Change-Id: I8bd981c4696c174152cf41caefa6c083650d283a
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-on: https://review.coreboot.org/13614
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Enable PCIe root port 0
Testing on Galileo:
* Add a 802.11 wireless card in the mini-PCIe slot
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing successful if:
* After PCI 00:17.0, memory addresses are assigned to the 802.11
wireless card on PCI 01:00.0 during BS_DEV_RESOURCES state
Change-Id: I68ea25b8e594480fe5146ffad75e293e346e9517
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13723
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Add additional lines to the devicetree.cb file to disable the PCI
devices in the Quark SoC.
Testing on Galileo:
* Edit the src/mainboard/intel/galileo/Makefile.inc file
* Add "select ADD_FSP_PDAT_FILE"
* Add "select ADD_FSP_RAW_BIN"
* Add "select ADD_RMU_FILE"
* Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
* Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
* Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
* Testing is successful if:
* Devices show up as disabled in BS_DEV_ENUMERATE state or ramstage
Change-Id: I1edbbcb88cef29ce972ef054c82e37bf07c3761d
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13720
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Otherwise the image is simply unusable.
Change-Id: I1e2562ba17279d14dc73b05e4f8fa493e06fbcd2
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13699
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Change-Id: Ic90d3aa714e5681c5021e2b05275d57dce428de0
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13664
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Having two separate memlayouts is an unnecessary complication.
Contributors need to make sure that their code fits into the vboot one
(with smaller stage sizes) either way, and the Tegras have plenty of
SRAM anyway. Let's just make the vboot layout the default (as it was
done on other SoCs) to keep things easier to maintain. The empty SRAM
holes on non-vboot systems where the verstage and work buffer would've
been won't hurt them.
BRANCH=None
BUG=None
TEST=Ran abuild with and without --chromeos on Foster, Rush, Ryu and
Smaug.
Change-Id: If37228facb4de1459cc720dca10bf03e04eb9930
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13667
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
|
|
Some spaces crept in where there should be tabs.
Change-Id: Ie70469f5a16e8a2d5933ac632d13551b19761064
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13698
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
Change-Id: Id695fb6e759b90cd91bb9760bb4fe2a459480b21
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13663
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Change-Id: Ibbb056ae209a16533757af925c8c833c94803834
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13662
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Change-Id: I95173c06d334a340fa2157511a1d69f38877b264
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13665
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Change-Id: I808a739c91cb52782db46fd4897b6b913224d93f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13666
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
|
|
This makes the test IDs the default, taken from depthcharge
master (board/*/fmap.dts, hwid property).
Change-Id: I25793962ac16f451f204dbba6ede6a64c847cfd5
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13634
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
Change-Id: I7b1e046d5895750d350dfa851a6f51c3a3a1613f
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13659
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
|
|
Change-Id: If64607d40a64ada8cfe4c3ad054be9d6571fc221
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13660
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Tested by making lenovo x230 configurable despite pretty MRC bugs.
Change-Id: Ia2a123f24334f5cd5f42473b7ce7f3d77c0e65b7
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13658
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Those aren't used anymore.
Change-Id: If7baf2d03c47bcc6f69d63a349bbf9d5e749aeac
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13685
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
This was copied from mrc structure despite them having fields in different
order.
Change-Id: If10ffa3316c5fdc538a6fabf2409512bc8c3e676
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13661
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
|
|
Change-Id: Ic9d8c2a4e5125eca20eb692ac7ed070fda6cbe32
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13657
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: I11e09804ed1d8a7ae8b8d4502bd18f6be933f9fa
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13656
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Early UART driver is for bootblock and romstage. It is supposed to be used
when BOOTBLOCK_CONSOLE is enabled. This also adds few configuration bits
in bootblock requiered for serial to be set up.
Change-Id: I15520d566f107797e68d618885d4379e73d0fa45
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13677
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
|
RVP1 board comes with DDR3 SODIMMs and discrete VRs.
RVP2 board uses LPDDR3 and PMIC.
Change-Id: I3e47c157c49ad55ff1ba824672ac2630a64a6037
Signed-off-by: Alexandru Gagniuc <alexandrux.gagniuc@intel.com>
Signed-off-by: Andrey Petrov <andrey.petrov@intel.com>
Reviewed-on: https://review.coreboot.org/13298
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
|
|
veyron_speedy was deduplicated as sub-board into google/veyron, so the
addition of chromeos.fmd (identical btw) wasn't useful.
Change-Id: Ic4eb6f5fefb0812cae1b9c0475e3a296d7fa65b6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13646
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
|
|
Change-Id: I4b0a3073815ec8d98c2d23cd745f027517b6fa42
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13619
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Tested during FOSDEM.
Change-Id: Id095364d6e4735256e54a68ea9ae677355dd386a
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13532
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
In the same time remove few native gfx options which were improperly set
and only added dead code to the binary.
Change-Id: I4ed3fec03a1655ae0a779c3aa3845de273cb12e1
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13649
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
|
This is needed for stout EC init.
Change-Id: I5c73499c17763229840152a473a2d820802ee2f6
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13535
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
For devices with Chrome EC, state the "board" name(s), so they're built
as part of the image.
A number of EC boards aren't supported in the Chrome EC master branch,
they're brought along but commented out, waiting for a port to master
in the Chrome EC code base.
Change-Id: Ic6ab821de55cf9b4e8b48fe5ebc603adeb8bb28b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13548
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
|
|
Change-Id: I0a0c925509027f98f724d0a4347146f21ac06c02
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13624
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Otherwise it triggers a IASL warning with new IASL.
Change-Id: I090ee18df78ea779137ee6797c55b96ea27e6d27
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13623
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Store (HPBA, HPBA) had no effect. Rename one of HPBA to avoid shadowing.
Change-Id: I54bfa7bcb3e05c28fe8a257825af56527dbf663e
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13622
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
PBIF is package and so a scalar can't be stored instead of it.
What was meant is probably Index(PBIF, 0)
Change-Id: Iddd18e1f165e0f48fd91124200aba5c6b4a5b4bd
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13621
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Ifcbb6916b718d41fb9cda537ffdc3e652e13cbbf
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13620
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
The ThinkPad X220i is essentially identical to the ThinkPad X220 but it
has a Sandybridge i3 (instead of a Sandybridge i5/i7) CPU and the
VGA_BIOS_ID differs. Thus, support is added by using the X220 mainboard
directory and setting the VGA_BIOS_ID in Kconfig.
Change-Id: I33345a099c617e8c87a1de64b7254b7e7716ca90
Signed-off-by: Christopher Spinrath <christopher.spinrath@rwth-aachen.de>
Reviewed-on: https://review.coreboot.org/13594
Tested-by: build bot (Jenkins)
Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
|
|
Some of the pins are not connected/used on kunimitsu board,
this patch will make them "Not connected".
Un-used PINS will controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.
BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu.
Change-Id: Iaf0d4806836648808fb91cfc7807c4c1595a5167
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7c25ad8ee0d189178124cff20569152b1053488
Original-Change-Id: I3add625b2bf01223cd389c6a5585827ac62dd0c0
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316700
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/13629
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
While the board configuration still works without this,
It's nicer to have the device statically defined since
the NIC is hardwired to the board.
Change-Id: Ic6682865dd17672c3782bfba9511cd120d1657c1
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/13455
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
As the audio card needs 1.8V I2C operation. This patch adds
entry into devicetree.cb to set I2C port 4 operate at 1.8V.
TEST=Built & booted lars board. Verified that I2C
port 4 is operating at 1.8V level
Change-Id: Ia77841a26d024785d53251ca4b17afcf77f36a5b
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e431e7acd85f6d7bf9d47f54ed41c48b8276071c
Original-Change-Id: Iccc85a5e3bbf2b5362665036e1294a6635e38fbe
Original-Signed-off-by: David Wu <David_Wu@quantatw.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/321000
Original-Commit-Ready: David Wu <david_wu@quantatw.com>
Original-Tested-by: David Wu <david_wu@quantatw.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13627
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Enable the option to back up Vboot non-volatile data from CMOS
to flash as these boards have the necessary nvram fmap region
and are using vboot2 which does not backup to the TPM.
BUG=chrome-os-partner:47915
BRANCH=glados
TEST=manually tested on chell
Change-Id: I7bfe88f2cb7826f3315987aaf56f77df708896ce
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 35df03c5ef24406129cba920ee9af6d55458cd45
Original-Change-Id: Ia7c014fe2768c55941a65ec5605ef4fbc986151c
Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324123
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13601
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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The developer mode gpio switch on rialto is always hardcoded (through a
resistor) as developer mode. We need to ignore it to allow transitions to
verified mode with the virtual developer mode stuff.
TEST=We can now exit dev mode on rialto
Change-Id: I94a949f0973132de5fd008224af79cf612151193
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e78bb8f81eaa9c082e47ad818b64843c2565d00b
Original-Change-Id: If11d752d58a5f26fc270ef01b529dad18b4cce46
Original-Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/325861
Original-Commit-Ready: Alexandru Stan <amstan@chromium.org>
Original-Tested-by: Alexandru Stan <amstan@chromium.org>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/13626
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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kunimitisu platform updated these two fields if maxim codec
is detected.
BUG=chrome-os-partner:49570
BRANCH=glados
TEST=Build & Booted kunimitsu board. Verified that kernel
can read new strings.
Change-Id: Icbe0d87f0b46da794db36191b0e12948fe6a2fe6
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: f3d07ef07c382a2df140b457273feb3899228e10
Original-Change-Id: Ia6a111d15b851ae3fa918816e13b54ace215a09a
Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/324631
Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com>
Original-Tested-by: Yang Fang <yang.a.fang@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13603
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Add missing file to fix complaints by git commit script.
TEST=None
Change-Id: I4aac63821a7208fb86fa6c0dda16b7537e49a69a
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13610
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
|
Change-Id: Idefa304a27823c741fab72ff5c2f20fed1aa5a39
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13523
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Also updated KGPE-D16 strings to KCMA-D8 throughout the copy to work
around Jenkins failures caused by an unmodified clone.
Change-Id: I943e81c8c2987a8333fc2a1cdb3675abf2d90cf1
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13521
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Change-Id: I28ad2298ad4dfb428dcd41a4f00db88c5e817cd7
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13173
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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- Stop blinking when coming out of standby.
- Remove code to set blink when going into S3. This never
worked correctly.
Change-Id: I958990f3203d3cbe7ae64833800d631c1034327f
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13171
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Add the files to build soc/intel/quark and mainboard/intel/galileo for a
minimal coreboot image. Please note that this configuration does not
run. Include HTML documentation for the Galileo Gen 2 board.
Testing is successful if build completes successfully.
TEST=Build for Galileo
Change-Id: Idd3fda1b8ed9460fa8c92e6dcaa601c3c9f63a36
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13507
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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These devicetree patches set the ACPI PM Disabled variable to 1.
This will disable the ACPI PM timer and remove from FADT table.
BRANCH=none
BUG=chrome-os-partner:48646
TEST=Build for skylake board with the PmTimerDisabled policy in
devicetree set to 1.
iotools mmio_read32 0xfe0000fc should return 0x2.
cat /sys/devices/system/clocksource/clocksource0/available_clocksource
should list only "tsc hpet". acpi_pm should be removed from this list.
Change-Id: Ia66f37e13f0f2f527651418b8b5c337b56c25c7f
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: db3e8130495038850c7034b89701b4a5fcf88dce
Original-Change-Id: Ib1b876cfa361b8cbdde2f9e212e3da4fd724e498
Original-Signed-off-by: Archana Patni <archana.patni@intel.com>
Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/319362
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/13589
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=None
Change-Id: I331f25ad4764cab972af7198f6154f604d2dbeae
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 2c1cb04645cbf34696e6adf48acec9d396e87ca9
Original-Change-Id: I8d14ea16b2d07bbf04c5c33e4205a85d9f21847b
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324075
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13585
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built kunimitsu w/ separate verstage.
Change-Id: If34cae5516a6df7f72f1f57cab495db70787177e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 543155665e1b05efe82c7440c124a5c83c656aa6
Original-Change-Id: I7281c4373fcbaaf0beedaa63dcf0dedb5316349f
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324074
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13584
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built glados w/ separate verstage and booted.
Change-Id: I626a500c183d21f94d976e24f09af15a242fba9c
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: b564514a8b93f53a919fcdac3589e30dbac82124
Original-Change-Id: Icc989ec5700b3f1a144a6b41198b7dd2c2aac6f7
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324073
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13583
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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In order to support both separate verstage and a verified boot after
romstage one needs to ensure the proper GPIO and EC configuration
been complete. Therefore, move that logic to
car_mainboard_post_console_init() in car.c file which gets called
in the early flow of a CAR stage (either verstage or romstage).
BUG=chrome-os-partner:44827
BRANCH=glados
TEST=Built chell w/ separate verstage and booted.
Change-Id: Ic728c2904006376fdc2b27b512f72173a2260be3
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 42d190af8996fea894305ebe686afbfda5f2b8a5
Original-Change-Id: I95aeb97737d0ddfa6c53269c9d14db16ed5e47cc
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/324072
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/13582
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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This fixes some spelling and whitespace issues that I came across
while working on various things in the tree.
There are no functional changes.
Change-Id: I33bc77282f2f94a1fc5f1bc713e44f72db20c1ab
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13016
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: I67271f2a209fc96eea6181f8875a5e69cf98d8c4
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/13511
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I8996f8ab739a07014a4189738b5624485d752d9d
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13540
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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- Add CONFIG_ prefix to two symbols.
- Remove the use of the third symbol as it will never be matched.
Change-Id: Ifa7f6884001cb05fb8397f193c4b08a0161f498c
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13539
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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Under certain conditions when the APs are still executing during
MCT setup the system can hang. This was the root cause of most
of the S3 resume failures on this platform; waiting for AP stop
before MCT setup allows for reliable S3 resume.
Change-Id: I329eea9a8912d7b57efe6aae327d24fd6c3fd782
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13169
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I5a4e223b2e247decd30d8fb2a083be4cff6500a4
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13166
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I15fedb067f1911799f7528b60b8754f2984b38ec
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13161
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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On certain Winbond SuperIO devices, when a PS/2 mouse is not
present on the auxiliary channel both channels will cease to
function if the auxiliary channel is probed while the primary
channel is active. Therefore, knowledge of mouse presence
must be gathered by coreboot during early boot, and used to
enable or disable the auxiliary PS/2 port before control is
passed to the operating system.
Add auxiliary channel PS/2 device presence detect, and update
the Winbond W83667HG-A driver to flag the auxiliary channel as
disabled if no device was detected.
Change-Id: I76274493dacc9016ac6d0dff8548d1dc931c6266
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13165
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ic4b68a032068208d56b2a04150f7fc7d61b38eba
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13164
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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The IOMMU/HT device was not routed correctly; add the proper APIC
mappting to the mptable generation code. Also clarify comments
surrounding the pin mappings.
Change-Id: I72ceb0f22dabdfa71a1f6231ccb841face08ff7a
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13163
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: Ib4f46944f076f1e696cf16a1e532eb8635b603c9
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13162
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: If67999098fbe2831eeb30cb8b362c558db5d2688
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13157
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I7dcde170d0f59ea9886342c0d2c09b70b9d0d84d
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: https://review.coreboot.org/13537
Tested-by: build bot (Jenkins)
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
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since commit f1e321001d5954096f06f9a43138219a9a46536e, the UART init
should be in bootblock_mainboard_early_init() which runs before
console init. (see src/lib/bootblock.c)
Change-Id: Ib00afdd6e81e7689fbd743c8a5f547d424896d71
Reviewed-on: https://review.coreboot.org/13448
Tested-by: build bot (Jenkins)
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
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Move the default select of "Use native graphics initialization" for
Peppy to the ChromeOS section as SeaBIOS (default payload) requires a
vBIOS and takes twice as long to load with this option enabled. For the
same reasons, this option shouldn't be enabled by default (def_bool y).
Change-Id: I1f2163e0a1e4bf8e5041dad150bdf7de804fb4db
Signed-off-by: Jean Lucas <jean@4ray.co>
Reviewed-on: https://review.coreboot.org/13493
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Some trivial cleanup.
Change-Id: I866efc4939b5e036ef02d1acb7b8bb8335671914
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/13427
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Iad724e9e1d3e64e2af3f74fed9dec30aa34e2af5
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13153
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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The KGPE-D16 supports an optional MIO audio card, which connects
to the on-board HDA interface of the SP5100.
Enable the HDA interface for use with the MIO card.
Change-Id: Idfe069f4bce7b94a7460bc7fcdd378eb57e51fda
Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
Reviewed-on: https://review.coreboot.org/13152
Tested-by: build bot (Jenkins)
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
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