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2020-12-10mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devicesMichael Niewöhner
Add the subsystem ids to PCI ports and devices, which were dumped on vendor firmware using `lspci`. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: enable LTR for all root portsMichael Niewöhner
Follow vendor and enable LTR on all root ports to optimize for devices' latency requirements and also optimize power management while preventing failure due to wrongly guessing idle states, which happens without LTR. Tested successfully. No errors show up in dmesg. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUMEMichael Niewöhner
All X11 boards currently supported have Intel SPS without support for S3/S5. Thus, drop it from Kconfig. Note: not all X11 boards are server boards. When a X11 desktop or workstation board should be added, this can be selected by the boards, where S3/S5 work. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure unconnected padsMichael Niewöhner
Correct unconnected pads that are configured different currently by copying vendor configuration while porting the board. Add internal pull resistors to all unconnected pads, that do not have an external pull resistor, to prevent floating. The pads have been determined by dissecting a dead board. This commit only changes pads, that are not connected at all and don't have any via, so we can be absolutely sure there is no other connection. Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure and document various padsMichael Niewöhner
(Re)configure various pads found by dissecting a dead board and vendor firmware, as well as the BMC firmware: - GPP_B14: input connected to jumper JBR1 - could be used to implement "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up - GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify the BMC about a thermal throttling event. Not implemented in vendor firmware. - GPP_C23: input connected to the CPU's CATERR# output; external pull-up Not actively used by vendor firmware. - GPP_D1: output connected to on-board and front panel power LEDs - GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will be used later in CB:48096 and CB:48097; external pull-up - GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not useful, since the IGD is not connected to any ports on this board. External pulls ensure correct function of a dGPU even without driving the gpios. Not used by vendor firmware. - GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls - GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not used by vendor firmware. Also add comments for documentation. While at it, mark ME-owned pads as reserved. Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-09mb/google/volteer/variant/volta: add Synaptics touchpad.Sheng-Liang Pan
add new Synaptics touchpad for volta. BUG=b:174802144 TEST=emerge-volteer coreboot and check touchpad function work. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/volteer: Reorganize FMAPFurquan Shaikh
This change reorganizes FMAP for volteer to make use of the lower 16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to RW_LEGACY. This is now possible because TGL supports memory mapping of BIOS region greater than 16MiB. Following changes are made in chromeos.fmd as part of this: 1. Move RW_SECTION_A and RW_MISC to lower 16MiB. 2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as a placeholder in the lower half of the SPI flash. 3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a larger region for ELOG. 4. Increase WP_RO to 8MiB to allow larger space for firmware screens. GBB size is thus increased to 448KiB. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-09mb/google/dedede: Update Boten GPIO setting for PEN detection.Stanley Wu
AP_PEN_DET_ODL isolated by a diode and need to pull up internally. BUG=b:160752604 BRANCH=dedede TEST=Build and confirm waveform by google EE parter. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/zork/var/vilboz: Update telemetry settingsJohn Su
Update telemetry settings. VDD Slope : 32643 -> 26939 VDD Offset: 208 -> 125 SOC Slope : 22742 -> 20001 SOC Offset: -83 -> 168 BUG=b:171668654 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE test report Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48288 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2V Sowmya
This patch adds the PMC MUX and CONx devices for adlrvp for conn2. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpadTim Chen
Add Elan and Synaptics touchpad settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-09mb/google/dedede/var/metaknight: Add audio related settingsTim Chen
Add HDA,speaker codec and speaker amp settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-08mb/google/deltaur: Restrict RW_DIAG to lower 16MiBFurquan Shaikh
This change restricts RW_DIAG region to lower 16MiB to ensure that the extended BIOS checker for FMAP does not complain about 16MiB boundary crossing. I haven't updated any other regions to occupy the newly freed space but it is fine since this board is dead and should be dropped from coreboot soon. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-08mb/intel/tglrvp: Restrict SI_ME region to lower 16MiBFurquan Shaikh
This change restricts SI_ME region to live below the 16MiB boundary to ensure that no regions cross the 16MiB boundary as the extended BIOS window checker for FMAP complains about it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-08mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration and ↵Kevin Chang
disabling DDI port 1 and 2 HPD. This patch adds the PMC MUX and CONx devices for lindar. Device specific method contains the port and orientation details used to configure the mux. BUG=b:172533907 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-12-08mb/*: Remove SATA mode config for CNL based mainboardsFelix Singer
SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08soc/intel/cannonlake: Align SATA mode names with soc/sklFelix Singer
Align the SATA mode names with soc/skl providing a consistent API. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I54b48462852d7fe0230dde0c272da3d12365d987 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48390 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08mb/siemens/chili/base: Fix state of PCI devicesFelix Singer
The PCI devices P2SB and PMC are hidden by the FSP and cannot be unhidden, because the FSP locks their configuration. Thus, setting them to `on` is not correct. Therefore, set their state to hidden. Change-Id: Ib7c019cd7f389b2e487829e5550cc236ee5645b7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48388 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/*: Remove SATA_AHCI config from SKL/KBL based devicetreesFelix Singer
SATA_AHCI is already the default mode for SKL/KBL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: Ib5222c1b0314365b634f8585e8a97e0054127fe9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48378 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08soc/intel/skylake: Shorten SATA mode enum value namesFelix Singer
The Skylake FSP isn't used by coreboot anymore. Therefore, drop the misleading comment and the "KBLFSP" extension from the names of these enums. Also, drop the "MODE" extension to make their names shorter in general, since it doesn't add any more value. Built clevo/n130wu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: If37d40e4e1dfd11e9315039acde7cafee0ac60f0 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48377 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/clevo/l140cu: Use lower-case hex valuesFelix Singer
Change-Id: I56a905980e5ae382c3488b9fddb9fab382efc1d6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48375 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/siemens/chili: Remove unnecessary device declarationsFelix Singer
Change-Id: I193aea7c92f340bd80a41a3777bcddc3f1339620 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-08mb/clevo/l140cu: Remove unnecessary device declarationsFelix Singer
Remove unnecessary device declarations and remove comments where SMBIOS slot descriptions are used. Change-Id: I3aa3f72de764889becdb0afeb2dac522385d70ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48373 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/clevo/l140cu: Use proper indentsFelix Singer
Use proper indents in the devicetree and align `end` keywords. Change-Id: Id6e6f4ad648a9bed35305b7a446744c6ed06a150 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48372 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/clevo/l140cu: Make PCI devices P2SB and PMC hiddenFelix Singer
The PCI devices P2SB and PMC are hidden by the FSP. So instead turning them off, set their state to hidden being able to allocate ressources for them. Change-Id: Ie6e12f99b0a7ffb1c4831b3aa8705e911b677e88 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48371 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/volteer/var/voxel: Update DPTF parametersSheng-Liang Pan
remove TCC offset setting in overridetree.cb, use default setting(# TCC of 90) in baseboard. BUG=b:174547185 BRANCH=volteer TEST=emerge-volteer coreboot Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Iaac1fae12ccaa8a623bc2dc3105262918523d440 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48264 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/volteer: Update I2C5 bus freq and devicetree.Stanley Wu
Update lindar gpio settings for Synaptics trackpad no function issue. Update I2C5 bus freq to 400kHz. Improve Goodix Touchscreen power on sequence. BUG=b:160013582 BRANCH=firmware-volteer-13521.B TEST=emerge-volteer coreboot and check system dmesg and evtest can get device. Verify trackpad function workable. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I8c1ab6bab1f9de187e2a78ead7b5bbaf758f5fcf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48150 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-08mb/google/volteer: ACPI nodes for volteer2_ti50Jes Klinke
Unique among the Volteer devices, the volteer2_ti50 variant connects to the TPM via I2C. This CL introduces the proper devicestree declarations for the Linux kernel to recognize that. overridetree.cb is shared between "sub"-variants volteer2 and volteer2_ti50, so both will have two TPM nodes, the I2C being disabled by default. The odd _ti50 variant then has code in variant.c to enable the I2C node and disable the SPI node. BUG=b:173461736 TEST=abuild -t GOOGLE_VOLTEER2{_TI50,} -c max -x Change-Id: I5576a595bbabc34c62b768f8b3439e35ff6bcf7b Signed-off-by: Jes Bodi Klinke <jbk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48223 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-08mb/google/volteer/variants: Update Power Limit2 minimum valueSumeet R Pawnikar
Update Power Limit2 (PL2) minimum value to the same as maximum value for volteer variants like baseboard, delbin, eldrid, terrador and todor. All other variants uses the DTT entries from baseboard devicetree since there is no override present for those variants. DTT does not throttle PL2, so this minimum value change here does not impact any existing behavior on the system. BUG=None BRANCH=volteer TEST=Build and test on volteer system Change-Id: I568e87c87ef517e96eaab3ff144b1674d26ae1e6 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-07mb/google/volteer/var/elemi: use devtree aliases for PMC MUX connectorsWisley Chen
refer to cb:45878 Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:174735512 BRANCH=volteer TEST=build and type-c display work Change-Id: I0bf84e2691856c9760d8fa9b6d853b04be10390a Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48268 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-07mb/intel/adlrvp: Remove GPP_E0Meera Ravindranath
Remove the unused UART_BT_WAKE GPIO as BT is over USB. Change-Id: I638b4528fa5c4c378a1e8ff7bb88546da1513df2 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-06mb/*: Remove unnecessary selectsFelix Singer
Remove SOC_INTEL_COMMON_BLOCK_HDA from mainboards Kconfig since it is selected by their SoC soc/intel/cannonlake. Change-Id: I9597746a217575b42f6325998b948e16b452231a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48289 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-06mb/siemens/chili: Move mainboard/gpio.h to variant/gpio.hFelix Singer
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make clear that these methods are implemented on variant level. Change-Id: Ib4e7ec948ca4d019ad82ebc5abe39fc408281cf4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48299 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-06mb/clevo/kbl-u: Add a seperate method for early GPIOsFelix Singer
Add variant_configure_early_gpios() configuring early GPIOs to make the difference clear. Change-Id: I6e7c8c32963c9eeab4399947dac511442987cb45 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48298 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-06mb/clevo/kbl-u: Move mainboard/gpio.h to variant/gpio.hFelix Singer
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make clear that these methods are implemented on variant level. Change-Id: Ibcb6322067285984bad70761fce34cfcb6ed8e0f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48297 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-06mb/clevo/cml-u: Move mainboard/gpio.h to variant/gpio.hFelix Singer
Move mainboard/gpio.h to variant/gpio.h and rename its methods to make clear that these methods are implemented on variant level. Change-Id: I1ae9b54ed683000f65323b11747ce3280a1c7f2a Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48296 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/prodrive/hermes: Generalise `check_signature` functionAngel Pons
Allow to specify which signature is to be checked. Change-Id: Ica874b1c4283fdb8dbd702c34ccb3315a2cf160d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-12-05mb/google/dedede: Create storo variantTao Xia
Create the storo variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:174284884 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_STORO Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: I5ad41e0b2bc95b44733a2ad3c543267f3f56f9e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
2020-12-05mb/amd/majolica: add functionality to add EC blob to buildFelix Held
Without the EC blob being present in the SPI flash, the board won't even power up. Change-Id: Ia3c50e86414bbc707bc33e28c636196c1be2f1e6 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/amd/majolica: add skeleton of Cezanne reference boardFelix Held
This is an adapted copy of mainboard/example/min86 that is currently only used for Jenkins to test the SoC code in soc/amd/cezanne and isn't expected to reach boot block at the moment. It will be extended in future follow-up commits. Change-Id: I6806955952fbfa3227294cfc44fdf9156140e933 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-05mb/google/volteer/var/voema: Add MIPI camera supportDavid Wu
1. Add VARIANT_HAS_MIPI_CAMERA to Kconfig.name 2. Add mipi_camera.asl BUG=b:169356808,b:169551066 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I63d133246dbdc6aff7bf97d98f95052edf53bac9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47668 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/puff/var/dooly: Update DPTF parametersTony Huang
DPTF paramerters form thermal team. Set PL1 Min/Max 15/25W, PL2 Min/Max 40/49W. BUG=b:174514010 BRANCH=puff TEST=build image and verified by thermal team. Change-Id: I9e6c4bae181e87f87f2e92337bb9d989f5b7d955 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-05mb/google/zork: set APU_EDP_BL_DISABLE to low as defaultChris Wang
set APU_EDP_BL_DISABLE(GPIO_85) to low to avoid the VARY_BL fast than APU_DP_BLON. BUG=b:171954512 BRANCH=zork TEST=validate the panel sequence with scope. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ia6d3f4335583bb2d91a6bce96d89cff84247d0ad Reviewed-on: https://review.coreboot.org/c/coreboot/+/48203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-12-05mb/google/volteer: Create copano variantFrankChu
Create the copano variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:174413884 BRANCH=None TEST=util/abuild/abuild -p none -t google/volteer -x -a make sure the build includes GOOGLE_COPANO Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ib06625f492f68a6a6f5c6b382772b68f1eb681ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48136 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
2020-12-05mb/google/volteer/variant/lindar: Correct SD card reader power sequenceKevin Chang
According to the spec provided by Bayhub, the 3.3V power rail must be enabled at least 100ms before reset is released. To ensure this, set the power enable signal in the bootblock GPIO table. BUG=b:173676531 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I0c536f36c138ace93766f3024f6ec5d47b38269f Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47799 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/zork: Replace generic driver with sx9324 driverEric Lai
Use a new driver for the SX9324 proximity detector device. This is first draft settings, will modify it after fine tuning. BUG=b:172397658 BRANCH=zork TEST=run "i2cdump -y -f 0 0x28" and checked all registers are expected. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I869d0b6640247099ca489e96ed94e03811a04bf4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47867 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-05mb/google/zork/var/vliboz: Add LTE_RST power sequenceEric Lai
Latest HW schematic add LTE_RST pin to control module power sequence. BUG=b:173490220 BRANCH=zork TEST=measure the waveform is meet the LTE module spec. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0f0a35a905d711dd8d17dea2ae82a8dfa1fa05ed Reviewed-on: https://review.coreboot.org/c/coreboot/+/47912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-05mb/google/dedede/var/drawcia: Configure Acoustic noise mitigation UPDsMaulik V Vaghela
Enable Acoustic noise mitigation for drawcia and set slew rate to 1/4 which is calibrated value for the board. Other values like PreWake, Rampup and RampDown are 0 by default. BUG=b:162192346 BRANCH=dedede TEST=Correct value is passed to UPD and Acoustic noise test passes. Change-Id: Iadcf332d59dac2ba191b82742a18a1ab326940d1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48231 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-04mb/google/brya: Initiate device treeEric Lai
Initiate device tree based on latest schematic. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia94119cb6d7eff6ea13c7d6a7dfd6ce891f706fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/48139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Add EC smihandlerEric Lai
Add implementation of EC smihandler BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I211f5755ff44514ab7ab4083f684ddd88c23fe48 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48115 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ECEric Lai
Perform EC initialization in bootblock and ramstages. Add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ie1305706134ca7cc58b8a9941231d1ee14f80949 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Enable building for Chrome OSEric Lai
Enable building for Chrome OS and add associated ACPI configuration. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I5311879a127a2c8da1bbb086449019d932d57b72 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04mb/google/brya: Set UART consoleEric Lai
Follow latest schematic UART_PCH_DBG is UART 0. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8e334fee1adcd79d058b7ab07127f8ecf1735202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48070 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/google/brya: Enable ACPI and add ACPI tableEric Lai
Enable ACPI configuration and add DSDT ACPI table. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I08513ec159b69535f742a1fd70cdec9ec845d414 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-04Coachz: change EN_PP3300_DX_EDP from gpio52 to gpio67yuanliding
Coachz rev1 has changed EN_PP3300_DX_EDP from gpio52 to gpio67. BRANCH=none BUG=b:174123578 TEST=emerge-strongbad coreboot chromeos-bootimage. flash coreboot and boot up normally. Signed-off-by: yuanliding <yuanliding@huaqin.corp-partner.google.com> Change-Id: I32a721d0d725bf217debe35a5cdc01aa8f5d5daf Reviewed-on: https://review.coreboot.org/c/coreboot/+/48224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2020-12-04mb/amd/mandolin: Unify devicetree formatting for 00:14 devicesPaul Menzel
To accommodate also `off`, two spaces are used after `on` to align comments. This unifies the devicetree files of the two variants. Change-Id: I7908fe2313ddccb6a4448a6338d6cd4938264f62 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: mandolin: Fix typo in *Coprocessor* in commentPaul Menzel
This reduces the difference with Cereme’s devicetree file. Change-Id: I1e6ba5891245562d5132307eab224623031e11c8 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46559 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-04mb/amd/mandolin: use more readable size formats in FMAP filesFelix Held
Since the FMD file isn't parsed any more by a shell script in the SoC's Makefile.inc, we can use better human-readable numbers for the section sizes. TEST=Timeless build results in identical image. Change-Id: I2117064a694f67767284f6fd4ac3604b254a2734 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/amd/mandolin: removed unused MANDOLIN_MICROCHIP_FW_OFFSETFelix Held
TEST=Timeless build results in identical image. Change-Id: Ifa5c14add555b382f74ba1165131b1569bbef123 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-04mb/emulation/x86: Add optional parallel_mp init supportArthur Heymans
This makes it possible to select both the legacy LAPIC AP init or the newer parallel MP init. Tested on i440fx with -smp 32. Change-Id: I007b052ccd3c34648cd172344d55768232acfd88 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04cpu/qemu-x86: Add the option to have no SMMArthur Heymans
Qemu i440fx does not support an smihandler at the moment. Change-Id: I5526b19b8294042a49e5bca61036e47db01fd28a Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48208 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-12-04mb/supermicro/x11ssm-f: correct trigger for SMI/NMI interrupt inputsMichael Niewöhner
All four SMI/NMI interrupt inputs have an external pull-up resistor and get triggered by pulling the line low. Thus, correct the trigger to active-low. Also document the signals by adding appropriate comments. The pads' connections have been determined by dissecting a dead board. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Id1a8c1e0b9fe723a15d04a88d565a53eeba9b085 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48093 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-04mb/supermicro/x11ssm-f: drop NMI overridesMichael Niewöhner
Drop the NMI overrides, since NMI now gets configured in gpio common code. Also remove the variant init mechanism, which is unused now. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I02e0c679f9aafe33108320a8dfc62dcb278202ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48092 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03mb/google/zork: Set S0IX_SLP_L high in S0, low in S3Martin Roth
This is used as a signal to show the system state. It hadn't been used up to this point as we're not currently using S0i3, but the fingerprint sensor will use it to go into a low power mode, so set it appropriately on Trembyle. Dalboz devices don't use the FPMCU, but set there as well so that the state matches. BUG=b:174695987 TEST=Verify GPIO state in S0 and S3 with the EC BRANCH=Zork Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ibc725905909830d44f77c2498a26edf6d7a3dc05 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48255 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Vincent Palatin <vpalatin@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03mb/hp/z220_sff_workstation/Kconfig: Select MAINBOARD_USES_IFD_GBE_REGIONAo Zhong
Select MAINBOARD_USES_IFD_GBE_REGION to make CONFIG_HAVE_GBE_BIN (Add gigabit ethernet configuration) selection available. Without that onboard Ethernet won't work. Signed-off-by: Ao Zhong <hacc1225@gmail.com> Change-Id: I9fe138363fc47254285ebaa4a7dbe5b94a0a8784 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48007 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03src: Remove redundant use of ACPI offset(0)Elyes HAOUAS
IASL version 20180927 and greater, detects Unnecessary/redundant uses of the Offset() operator within a Field Unit list. It then sends a remark "^ Unnecessary/redundant use of Offset" example: OperationRegion (OPR1, SystemMemory, 0x100, 0x100) Field (OPR1) { Offset (0), // Never needed FLD1, 32, Offset (4), // Redundant, offset is already 4 (bytes) FLD2, 8, Offset (64), // OK use of Offset. FLD3, 16, } We will have those remarks: dsdt.asl 14: Offset (0), Remark 2158 - ^ Unnecessary/redundant use of Offset operator dsdt.asl 16: Offset (4), Remark 2158 - ^ Unnecessary/redundant use of Offset operator Change-Id: I260a79ef77025b4befbccc21f5999f89d90c1154 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43283 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Jason Glenesk <jason.glenesk@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-03cbfstool: Use cbfs_serialized.h and standard vboot helpersJulius Werner
This patch reduces some code duplication in cbfstool by switching it to use the CBFS data structure definitions in commonlib rather than its own private copy. In addition, replace a few custom helpers related to hash algorithms with the official vboot APIs of the same purpose. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I22eae1bcd76d85fff17749617cfe4f1de55603f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-12-02mb/google/brya: Add GPIO stubsEric Lai
Add stubbed out GPIO configuration and perform GPIO initialization during bootblock and ramstage. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia658ab4b466242cf8658abb239f19a9c0a03849a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/brya: Add entry stubs of each stageEric Lai
Add entry point stubs of each stage for Brya. More functionalities will be added later. BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I44934c05ee32090b6e34648ee02f004c83e93d57 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48063 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/brya: Add flashmap descriptorEric Lai
BUG=b:174266035 TEST=Build Test Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ia1ba8c997680c60ee1eabfae82459e127f664117 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48062 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Simplify load/map API names, remove type argumentsJulius Werner
This patch renames cbfs_boot_map_with_leak() and cbfs_boot_load_file() to cbfs_map() and cbfs_load() respectively. This is supposed to be the start of a new, better organized CBFS API where the most common operations have the most simple and straight-forward names. Less commonly used variants of these operations (e.g. cbfs_ro_load() or cbfs_region_load()) can be introduced later. It seems unnecessary to keep carrying around "boot" in the names of most CBFS APIs if the vast majority of accesses go to the boot CBFS (instead, more unusual operations should have longer names that describe how they diverge from the common ones). cbfs_map() is paired with a new cbfs_unmap() to allow callers to cleanly reap mappings when desired. A few new cbfs_unmap() calls are added to generic code where it makes sense, but it seems unnecessary to introduce this everywhere in platform or architecture specific code where the boot medium is known to be memory-mapped anyway. In fact, even for non-memory-mapped platforms, sometimes leaking a mapping to the CBFS cache is a much cleaner solution than jumping through hoops to provide some other storage for some long-lived file object, and it shouldn't be outright forbidden when it makes sense. Additionally, remove the type arguments from these function signatures. The goal is to eventually remove type arguments for lookup from the whole CBFS API. Filenames already uniquely identify CBFS files. The type field is just informational, and there should be APIs to allow callers to check it when desired, but it's not clear what we gain from forcing this as a parameter into every single CBFS access when the vast majority of the time it provides no additional value and is just clutter. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: Ib24325400815a9c3d25f66c61829a24a239bb88e Reviewed-on: https://review.coreboot.org/c/coreboot/+/39304 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Mariusz Szafrański <mariuszx.szafranski@intel.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02cbfs: Enable CBFS mcache on most chipsetsJulius Werner
This patch flips the default of CONFIG_NO_CBFS_MCACHE so the feature is enabled by default. Some older chipsets with insufficient SRAM/CAR space still have it explicitly disabled. All others get the new section added to their memlayout... 8K seems like a sane default to start with. Change-Id: I0abd1c813aece6e78fb883f292ce6c9319545c44 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-02soc/amd: factor out common SMI/SCI enums and function prototypesFelix Held
At least a part or the remaining definitions in the soc-specific smi.h files are also common, but those have to be verified more closely. Change-Id: I5a3858e793331a8d2ec262371fa22abac044fd4a Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-12-02mb/google/volteer: Add fw_config entries for boot deviceDuncan Laurie
Add the fw_config entries for the newly added boot device fields. These are added as separate fields since a board may have more than one selected. BUG=b:173129299 TEST=abuild google/volteer Change-Id: I2af9ffcf0b90d4f4b7f2f31613ee110d8f350454 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48160 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/google/volteer: Add additional SD cards to device listDuncan Laurie
The initial commit only focused on GL9755S and RTS5261, but there were recently other cards added to the fw_config and those also need to be added to the probe lists. BUG=b:173207454 TEST=abuild google/volteer Change-Id: Ic27074a016ffbd4c4dd86104a6d85437357c4b82 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-02mb/intel/adlrvp: Replace tab by white space in devicetreeMeera Ravindranath
Change-Id: I928b4528fa5b4c378a2e8ff7bb88547da1413df2 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48213 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-02mb/google/dedede/var/drawcia: Support VBT for DrawmanKarthikeyan Ramasubramanian
Default VBT supports only integrated Display port. Drawman supports a HDMI port and hence support a separate VBT for Drawman. BUG=b:161190931 BRANCH=dedede TEST=Build and boot to OS in Drawlat and Drawman. Cq-Depend: TBD Change-Id: I8895cc67d87428eddb31328f1e3a90c346b54533 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-12-02mb/google/dedede: Add Daughter-board FW_CONFIG in devicetreeKarthikeyan Ramasubramanian
Add daughter-board ports bit field and mask in devicetree. BUG=b:161190931 BRANCH=dedede TEST=Build and boot to OS in drawlat & drawman. Change-Id: Ibbd86fc8c3e44a7d1703b8ce75c48881226545c9 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-12-02mb/google/zork: Update SPD table for ShubozKane Chen
Add memory table to "mem_parts_used.txt", and command to generate files: go build gen_part_id.go ./gen_part_id ../../../src/mainboard/google/zork/spd ../../../src/mainboard/google/zork/variants/shuboz/spd/ ../../../src/mainboard/google/zork/variants/shuboz/spd/mem_parts_used.txt Shuboz memory table as follow: value Vendor Part number 0x00 MICRON MT40A512M16TB-062E:J 0x01 HYNIX H5AN8G6NCJR-XNC 0x02 MICRON MT40A1G16KD-062E:E 0x03 SAMSUNG K4AAG165WA-BCWE BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I5f5f875daab58343f1cc8a9327ea128ba5e1f050 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2020-12-02mb/google/dedede/var/lantis: Configure IRQs as level triggered for HID over I2CTony Huang
Config HID-I2C device to level trigger. As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:171546871 TEST=emerge-dedede coreboot Change-Id: If8be25f591715765a99920b79482c862b1cc7079 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-01mb/intel/jslrvp: Modify the flash layout for fsp debug buildV Sowmya
Current flash layout doesn't support the fsp debug builds since the FW_MAIN_A/B doesn't have enough space to hold the fsp debug binaries along with ME RW binaries. This patch reduces the SI_ALL size to 3.5MiB and increase the SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries. BRANCH=dedede TEST=Build and Boot jslrvp with fsp debug enabled coreboot. Cq-Depend: chrome-internal:3425366 Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-01mb/google/zork: Mark RW_MRC_CACHE as "Preserve"Martin Roth
AGESA checks to make sure that the firmware version reading the MRC cache is the same version that wrote it, so it doesn't need to be erased during a firmware update. BUG=b:173724014 TEST=Flash firmware to DUT, update firmware, check RW_MRC_CACHE was not erased BRANCH=Zork Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: Ice3d1d467c25366b7ef678cd6481d043f62644ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/47776 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-01mb/kontron/mal10: Use the system library for headersFelix Singer
Use the system library for header files instead of relative filesystem paths. Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: I0b356d0188f104d7c49571ce5c8fe65e79589123 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48141 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-01mb/kontron/mal10/Kconfig: Reorder selects alphabeticallyFelix Singer
Built with BUILD_TIMELESS=1, coreboot.rom remains the same. Signed-off-by: Felix Singer <felixsinger@posteo.net> Change-Id: Id78c478a1252099cd1aa42c62efd406e7e1c5ef8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-01mb/ocp/deltalake: Update SMBIOS type 8 informationTim Chu
Update port connector information for Delta Lake. Tested=Execute "dmidecode -t 8" to check all the information of SMBIOS type 8 is correct. Signed-off-by: Tim Chu <Tim.Chu@quantatw.com> Change-Id: I880bb9a5a41077172423f78b56c19aadd93e001f Reviewed-on: https://review.coreboot.org/c/coreboot/+/47893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-01mb/intel/adlrvp: Remove unused EC_SYNC_IRQ GPIO on ADLRVPSubrata Banik
As per latest schematics GPP_A15 is not used for EC_SYNC_IRQ hence remove the unused GPIO. Wrong GPIO configuration is causing platform reboot issue on ADLRVP with Chrome SKU. Change-Id: I704cd722683258c80197d8872d3bdaafb7c923dc Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mb/intel/adlrvp: Add ASL support for WFC annd UFCVarshit Pandya
1. Add 2 ports and 2 endpoints 2. Add support for OVTI5675 WFC Cam is on I2C5 and UFC is on I2C1 BUG=None BRANCH=None TEST=Build and Boot adlrvp board and able to capture image using camera. Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I6d2a4fdca99354d1b6977233c70ccd950c99d8a2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47497 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mb/intel/adlrvp: Configure Camera related GPIO as per schematicsVarshit Pandya
Configure RST and PWR_EN signals for both WFC and UFC Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: Ie416da373756b1c73472b8572f87930965a3d6ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/47496 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mb/intel/adlrvp: Update GPIO configuration as per schematicsVarshit Pandya
Configure I2C related GPIO as per ADL-P schematics. This is based on Revision 0.974 of schematics. Signed-off-by: Varshit Pandya <varshit.b.pandya@intel.com> Change-Id: I76e1207cb31bed10b6e9fbeb2456b6feec42f97e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slotSubrata Banik
List of changes: 1. Enable Root Port 8 aka 0:0x1c:7 2. Assign free running clock for RP8 3. Apply W/A to get card detected on x1 slot - Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low TEST=Able to detect PCIe SD card over x1 slot localhost ~ # dmesg | grep mmc [ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA [ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8 [ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB [ 3.849158] mmcblk0: p1 Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-01mainboard/intel/adlrvp/spd: Update SPD for LP4x SKUSubrata Banik
List of changes in SPD: 1. SPD Revision (of JEDEC spec) 2. SDRAM Maximum Cycle Time (tCKAVGmax) (MTB) 3. MSB -> CAS Latencies Supported, First Byte 4. CAS Latencies Supported, Second Byte 5. CAS Latencies Supported, Third Byte 6. LSB -> CAS Latencies Supported, Fourth Byte 7. Minimum CAS Latency Time (tAAmin) 8. Fine Offset for SDRAM Maximum Cycle Time (tCKAVGmax) 9. Fine Offset for SDRAM Minimum Cycle Time (tCKAVGmin) 10.Cyclical Redundancy Code (0- 125 byte) TEST=Able to build and boot with updated SPD. Change-Id: Iae7f2693e87bffb2dfa20bd07b22f4a4768c56cb Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mb/intel/adlrvp: Add support for LPDDR5Sridhar Siricilla
This patch adds LPDDR5 memory configuration parameters to FSP. TEST=Able to pass FSP-M MRC training on LPDDR5 RVP. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2020-12-01mb/intel/adlrvp: Refactor lpddr4_mem_config structureSubrata Banik
List of changes: 1. Initialize dq_map array in a single line 2. Make dqs_map array also in a single line TEST=Able to build and boot ADLRVP LP4 SKU. Change-Id: I64f2b38492934c8ede301f4b252c8700060ed4ac Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48077 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/siemens/chili: Configure GPIOs in gpio.cFelix Singer
Get rid of variant_gpio_table() and configure GPIOs in gpio.c instead of passing data around. Change-Id: Ib158d6bdbcbceb3c1dc4f47fc7c3e098b9c7e5c4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47974 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/siemens/chili: Introduce include folder for header filesFelix Singer
Use include folder for header files allowing proper includes. Change-Id: I80066fb925b918d040062397e633c5d499a50dbe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47973 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/kontron/bsl6: Configure GPIOs using mainboard_opsFelix Singer
Hook up the mainboard_ops driver and configure the GPIOs using .init, since mainboard_silicon_init_params() is meant for the configuration of the FSP, not the GPIOs. Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47850 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30soc/amd/picasso: remove PICASSO_LPC_IOMUX Kconfig option from SoCFelix Held
PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in the corresponding SoC code, so remove it from the SoC's Kconfig and reanme it in the mainboard's Kconfig to MANDOLIN_LPC. Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2020-11-30mb/google/volteer: Create drobit variantFrank Chu
Create the drobit variant of the volteer reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:171947885 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-11-30mb/google/dedede: Update Imon slope and Offset Value for DrawciaMeera Ravindranath
Updating Imon slope and offset values as per recommendation of ODM based on calibaration. Updating Imon slope to 1.0 and offset to 1.4 BUG=b:167294777 BRANCH=dedede TEST=Boot dedede platform and confirm values in FSP. Change-Id: I3eb32218040163f0abef9b8dd4c52efb16289fe7 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Vinay Kumar <vinay.kumar@intel.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-11-30mb/google/dedede: Create sasuke variantRaymond Chung
Create the sasuke variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:172104731 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKE Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>