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2016-08-11intel/amenia: Add MAINBOARD_FAMILY for ameniaBora Guvendik
BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: I66178cc75872f14941434081d9650a569a084d04 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16135 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-11intel/amenia: set default value for BOOT_MEDIA_SPI_BUSBora Guvendik
BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: I60d411482812d98cb8dd11d66b0fc96ea9bae895 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16134 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-11intel/amenia: Select UART_FOR_CONSOLE for ameniaBora Guvendik
Set default value for UART port BUG=chrome-os-partner:51844 TEST=Boot to chrome and check console Change-Id: I5e76066e0ff531303595dcd5a99f2f8db379e89b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16133 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11intel/amenia: Update flash size to 16MBBora Guvendik
Update flash image size to 16MB and update image layout in flashmap descriptor file. BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: Ibdfb2949d06aedc38ddcef1078c2d14abcfa2dac Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16083 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10google/reef: Add mainboard handler function for gpio SMIShaunak Saha
This patch adds mainboard_smi_gpi_handler which handles the SMI event. This can happen in situations like lidclose and system goes to shutdown. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15834 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-09google/gru: Fix rk3399-gru write protectDouglas Anderson
The write protect GPIO is active high, not active low. After fixing I can see this after removing the write-protect screw: $ crossystem | grep wpsw_boot wpsw_boot = 0 Putting the screw in shows: $ crossystem | grep wpsw_boot wpsw_boot = 1 Caution: this CL contains explicit material. It explicitly sets the pullup on the WP GPIO even though that's the boot default. BRANCH=None BUG=chrome-os-partner:55933 TEST=See desc. Change-Id: I23e17e3bbbe7dcd83e81814de46117491e61baaa Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e6969f4be42c00c6e88bbb14929cf0454462ad21 Original-Change-Id: Ie65db9cf182b0a0a05ae412f86904df6b239e0f4 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/366131 Original-Tested-by: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-09gigbyte/ga-g41m-es2l: add cmos.layout and cmos.defaultArthur Heymans
This adds a cmos.layout and a cmos.default to ga-g41m-es2l. This allows to set things like baud_rate, debug_level, etc. from cmos. Change-Id: I25df7a1f3a0ce486b96cfe05bda628f604b0baec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15493 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-09mainboard/google/rush_ryu: remove rush_ryu mainboardAaron Durbin
The rush_ryu board was a development platform that never made it into a product. Remove it as it's not available to anyone. BUG=chrome-os-partner:55932 Change-Id: Ia3836ff8cade3009730543177a66736ae197572b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16107 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-09mainboard/google/rush: remove rush mainboardAaron Durbin
The rush board was a development platform that never made it into a product. Remove it as it's not available to anyone. BUG=chrome-os-partner:55932 Change-Id: I0f77bb791491509da7bd9cf25050e01c2f734a2f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16106 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-09google/gru: Update board/RAM ID ADC valuesJulius Werner
Looks like our hardware guys have decided to change some voltage ranges in the Gru/Kevin ADC IDs since we last wrote a table. This patch updates it to the latest values from the Spreadsheet of Truth. Also adds further values up to rev15. BRANCH=none BUG=none TEST=none Change-Id: I1aa093ca3abe952afd658eb7da01b325f798eaa0 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e42b4685c91f01ce1cff61638b17042be9d575fd Original-Change-Id: I646fd03dc385df1a8f0af8cb85ff3128cc31f8d8 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/365111 Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16053 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08supermicro/h8scm: Remove last unused chip.h fileMartin Roth
Change-Id: I84d61c8ade6e42e314a31e1155b4d5628b16199a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16081 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-08skylake/devicetree: Add PIRQ Routing programmingBarnali Sarkar
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08google/reef: Configure SDIO D1 to enable SCS Power GatingJagadish Krishnamoorthy
SDIO D1 pin needs to be configured as Native mode to enable SCS Power Gating. BUG=chrome-os-partner:54251 TEST=Verify SCS Power Gating Change-Id: Ic33b26443203217678e11d195eb965a7e628ad82 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/16062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-06google/reef: Enable I2C2 for use in bootblockDuncan Laurie
Enable I2C bus 2 for early init so it can be used by vboot for TPM communication for verifying the memory init code. BUG=chrome-os-partner:53336 BRANCH=none TEST=build and boot on reef Change-Id: Id4940ab01d8ccf288ab0a7a9a2f19867ed464e8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16059 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05google/reef: Correct SD card pins configChiranjeevi Rapolu
SD CLK and CLK_FB needs to be pulled down by 20K. SD CD_N is active LOW, needs to be pulled up by 20K SD WP pin is not connected for uSD cards, enable writes by default by pulling low by 20K. BUG=chrome-os-partner:54866 BRANCH=None TEST=Test with uSD cards. Change-Id: Ia4bbd966ffb21e276dfc31a74f4ea54718900d66 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://review.coreboot.org/16057 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05soc/intel/quark: Add FSP 2.0 romstage supportLee Leahy
Add the pieces necessary to successfully build and run romstage using the FSP 2.0 build. Because romstage is using postcar, add the postcar pieces so that romstage can attempt to load postcar. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15866 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05soc/intel/quark: Add FSP 2.0 boot block supportLee Leahy
Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Build and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-04chromeec: Chrome EC firmware source selection for EC and PD firmwaresPaul Kocialkowski
In some cases, we don't want the Chrome EC firmwares (both EC and PD) built directly by the coreboot build system or included in images at all. This is already supported with EC_EXTERNAL_FIRMWARE but it does implement a binary (build and include) or (neither build nor include) policy. Some cases require the ability to separately control whether the EC and PD firmwares should be built and included by the coreboot build system, only included from externally-built images or not included at all. This introduces config changes implementing that behaviour, renaming options to make it clear that they are specific to the Chrome EC. Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04google/reef: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: If5a6a1cb8f065a8c3a6a19d9441a21d60b39e579 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16031 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-03lenovo/x60: Fetch 16 bits when trying to parse bit 13Patrick Georgi
I'm not sure if that's the right fix here, but assuming the bit mask is right, the inb is wrong. Change-Id: I7e33019af088780a09be12513200bec63734bf97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229556 Reviewed-on: https://review.coreboot.org/16026 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-08-03google/gale: Add more board ID variantsKan Yan
EVT1 has two board IDs. Use binary first mode of base3 encoding for board ID. BUG=chrome-os-partner:55320 TEST=None. BRANCH=None Change-Id: I1cac1f74207f42616111d39db5c0494b7d1a0fb2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2b16cc74c4c147315b7db345678bbaf536ab4a7b Original-Change-Id: I6e95c7be4a6d28a0aae38b0838bd2ab71d288ba1 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364623 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Reviewed-on: https://review.coreboot.org/16030 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add code to support I2C TPM for KevinJulius Werner
Coming Kevin revisions will switch back to an I2C TPM. This patch adds the required configuration options and code to support that. Since the TPM type can currently only be changed at compile time, we can no longer support older Kevins with the same image. In order to build for Kevin revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2. BRANCH=None BUG=chrome-os-partner:55523 TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage binary had the appropriate code differences. Change-Id: I1b2abe0f331eb103eb0a84f773ee7521d31ae5d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3245bff937154f0f9f39894de9c98a75631d59d9 Original-Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364222 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16029 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add support for Gru rev1Julius Werner
This patch adds support for the Gru rev1 board. This board differs from rev0 by no longer relying on the I2C backlight booster and requiring the same ODT SDRAM settings as newer Kevin boards. BRANCH=None BUG=chrome-os-partner:55087 TEST=None Change-Id: I1428760540a0aaaa0c02c6cb5b0981294ba4df33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8de7bcc78c6c48c251c85185e238cea7812f7a28 Original-Change-Id: I3cb49bc644190f35300e6c618b2934956fa88e5b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364624 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16028 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03mainboard/intel/galileo: Add FSP 2.0 Kconfig supportLee Leahy
Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0 builds for Quark. TEST=Build and run on Galileo Gen2 Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15864 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03mainboard/intel/galileo: Remove use of EDK-II macros & data typesLee Leahy
Add assert.h to use coreboot's ASSERT macro. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2. Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15859 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-02google/lars & intel/kunimitsu: Disable EC buildMartin Roth
The Chrome EC codebase no longer supports the google/lars and intel/kunimitsu boards. Disable the build in those platforms. Change-Id: Ic4f5a1a34bb19ee31632c1ad8430c30f7154f138 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15869 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02google/reef: Add pull up 20K for LPC SERIRQKane Chen
per hw team's check and info from EDS, this pin needs to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating. BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory verified the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a Reviewed-on: https://review.coreboot.org/15951 Tested-by: build bot (Jenkins) Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-02intel/amenia: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/15777 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01siemens/sitemp_g1p1: Fix typoPatrick Georgi
Change-Id: I1c9af223d3598c4822905acce0cf9b1dca6ad1b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287066 Reviewed-on: https://review.coreboot.org/15981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-07-31mainboard/bap/ode_e20XX: Enable UART 3/4 in devicetreeFabian Kunkel
This patch adds IO and IRQ information for UART 3/4 to the devicetree. Patch with Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e is needed. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: I1d8fa16950079a47775f48166486415bd5d24f42 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15621 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard/bap/ode_e20XX: Add different DDR3 clk settingsFabian Kunkel
This patch adds two SPD files with different DDR3 clk settings. The user can choose which setting to use. Lower clk settings saves power under load. SoC Model GX-411GA supports only up to DDR3-1066 clk mode. Both SPD settings were tested with memtest for several hours. Power saving is around half a watt under heavy memory load. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Ibb81e22e19297fdf64360bc3e213529e9d183586 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard/bap/ode_e20XX: Change PCIe linesFabian Kunkel
This patch binds PCIe lanes 2 and 3 to one PCIe device. PCIe device 2.4 becomes x2. Tested with the connected FPGA on PCIe 2.4. FPGA doubles transfer rate from/to the AMD. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Icee567272312a7df4c3b5a6db5b420a054ec3230 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15905 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31sunw/ultra40m2: Fix handling non-existence of a devicePatrick Georgi
This probably never happens, but since we already test for the presence of the device, it makes no sense to try to configure it after its absense was determined. Change-Id: I9877dcd15819fb7949fa08a0954b05780df66316 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347362 Reviewed-on: https://review.coreboot.org/15982 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31google/reef: Update chromeos.fmd RO_SECTIONFurquan Shaikh
Update RO_SECTION to match the changes in depthcharge: https://chromium-review.googlesource.com/#/c/364261 BUG=chrome-os-partner:55713 Change-Id: I7238856cf73a62345778ea87e191a11190b7fb38 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31intel/amenia: Enable DPTF in mainboardShaunak Saha
This patch enables DPTF support for Intel Amenia platform, adds the ASL settings specific to Amenia boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Amenia board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I400e2312a20870058f3a386004fad748d3ee4460 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15094 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31google/reef: Enable DPTF in mainboardShaunak Saha
This patch enables DPTF support for Google Reef platform, adds the ASL settings specific to Reef boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Reef boards. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15640 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31gigabyte/ga_2761gxdk: Remove comment *endif*Paul Menzel
After the indentation is fixed in commit *mainboard: Format irq_tables.c* [1], the comment is redundant. So remove it. [1] Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Change-Id: Iebbcf10ee3cef1b4cf60ea34a6b3ad51e2208671 Reviewed-on: https://review.coreboot.org/15933 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31mainboard: Format irq_tables.cPaul Menzel
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31google/gale: Change board ID definition.Kan Yan
Change EVT3 board id to 5. BUG=chrome-os-partner:55320 TEST=None. BRANCH=None Change-Id: I020be47e1fdbf886c7c471d7fdcace1537875b6d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 63bd6541055172765c31a9b1220a24d4e3604cdc Original-Change-Id: I21a8764ff95892430944778f4898d2f1d4c97fd7 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362391 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/15949 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31Update degree symbol to utf-8 encoding in commentsMartin Roth
Almost all of the places where we have the degree symbol '°', it's encoded as 0xc2 0xb0 (utf-8 encoding). There are a few places where it is encoded as just a high ascii byte: 0xb0. Editors that support the high ascii 0xb0 seem to support the utf-8 0xc2 0xb0 encoding as well, but the opposite does not seem to be true. Change the high-ascii degree symbols to utf-8 encoding. Change-Id: I3d06289b802f45e938dc72b4c437fca56235b62b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15978 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31intel/wifi: Include conditionally in the buildKyösti Mälkki
Keep this enabled by default as most x86 platforms could have PCI-e slots equipped with one of these Intel WiFi adapters. The Kconfig entries under google boards had no function previously, the variable was never referenced. Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15931 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30mainboard/bap/ode_e21XX: Add board supportFabian Kunkel
Add next generation of BAPs (https://www.unibap.com/) SOC module, called ode_e21XX. Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini), but it includes a new AMD G-Series GX-412HC (Steppe Eagle) and an updated Microsemi FPGA. Changes to Olivehillplus: - Add SuperIO Fintek F81866D - Soldered down DDR3 with ECC - User can choose between different DDR3 clk settings (lowest setting can save up to 1.2W) - Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3 Tested with: - Payload SeaBIOS 1.9.1 - Lubuntu 16.04, Kernel 4.4.0 - Windows 10 (UART functionality) Known problems: - S3 not working - IOMMU not working Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15918 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30mainboard/bap/ode_e21XX: Add copy of amd/olivehillplusFabian Kunkel
Initial copy of olivehillplus. Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15917 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30google/reef: Use GPE0_DW1_15 as wake signal for touchpadFurquan Shaikh
Due to GPE routing, raw GPIO cannot be used for indicating the wake signal for touchpad. Instead we need to reference GPE pins. BUG=chrome-os-partner:55670 Change-Id: Ie5d8473df4301c7beef0cae8fe84e71b2838261b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28google/gru & kevin: Update DRAM configurationLin Huang
We need to enable DRAM ODT on kevin/gru board to improve the DRAM signal. Note, if the DRAM ODT is enabled and set to 120ohms, the sdram VREF need to adjust to 840mv. This patch also makes following changes: 1. For compatiblity with the old board, add the "sdram-lpddr3-hynix-4GB-666-no-odt.inc" and "sdram-lpddr3-hynix-4GB-800-no-odt.inc" files which do not enable sdram ODT. 2. Delete the 300MHz dram inc file. The 300MHz sdram config just reduced 666MHz to 300MHz based on the 666MHz config file, and it is not stable, so delete it. 3. Delete the 928MHz dram inc file, 928MHz sdram config still in debuging, delete it for now. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: If0248e1bc4cef2c298762080f1ca018653af0521 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 78d8a28e2d3489c99c9bba2c1c9aa76812e2e33f Original-Change-Id: I35f0685782d6fb178a95780ec77c45f565dd2194 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358763 Original-Commit-Ready: Dan Shi <dshi@chromium.org> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15813 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28google/reef: Write protect GPIO relative to bank offsetSusendra Selvaraj
Update the write protect GPIO reported in ACPI to GPIO_75. Also update the controller ID to "INT3452:01" which will point at the goldmont device and includes write protect GPIO. BUG=chrome-os-partner:55604 BRANCH=none TEST=verify crossystem output for wpsw_cur. Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab Signed-off-by: Susendra Selvaraj <susendra.selvaraj@intel.com> Reviewed-on: https://coreboot.intel.com/7929 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28skylake/devicetree: Add LPC EC decode rangeSubrata Banik
Define LPC decode ranges for EC communication. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu to ensure no EC timeout error Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15898 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28chromeos: Clean up elog handlingFurquan Shaikh
1. Currenty, boot reason is being added to elog only for some ARM32/ARM64 platforms. Change this so that boot reason is logged by default in elog for all devices which have CHROMEOS selected. 2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that want to add details about watchdog reset in elog. This requires a special region WATCHDOG to be present in the memlayout. 3. Remove calls to elog add boot reason and watchdog reset from mainboards. BUG=chrome-os-partner:55639 Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28google/urara: Provide dummy implementations of rec/dev functionsFurquan Shaikh
This is required to enable elog support in ChromeOS by default. BUG=chrome-os-partner:55639 Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28qualcomm/gale: Add required files to enable elog in ramstageFurquan Shaikh
BUG=chrome-os-partner:55639 Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15895 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28qualcomm/storm: Add required files to enable elog in ramstageFurquan Shaikh
BUG=chrome-os-partner:55639 Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15894 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28bootmode: Get rid of CONFIG_BOOTMODE_STRAPSFurquan Shaikh
With VBOOT_VERIFY_FIRMWARE separated from CHROMEOS, move recovery and developer mode check functions to vboot. Thus, get rid of the BOOTMODE_STRAPS option which controlled these functions under src/lib. BUG=chrome-os-partner:55639 Change-Id: Ia2571026ce8976856add01095cc6be415d2be22e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15868 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28vboot: Separate vboot from chromeosFurquan Shaikh
VBOOT_VERIFY_FIRMWARE should be independent of CHROMEOS. This allows use of verified boot library without having to stick to CHROMEOS. BUG=chrome-os-partner:55639 Change-Id: Ia2c328712caedd230ab295b8a613e3c1ed1532d9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15867 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-27mainboard/google/slippy: remove unobtainable mainboardAaron Durbin
The slippy board was a proof of concept device that has never made it out in the wild. Moreover, I don't think any of these boards exist any longer. Change-Id: I24fb08d9be35b2367e7aa64520ce5778ab861535 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15902 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-27mainboard/google/bolt: remove unobtainable mainboardAaron Durbin
The bolt board was a proof of concept device that has never made it out in the wild. Moreover, I don't think any of these boards exist any longer. Change-Id: I5ca055d448659a2b8e2eafcfc2114a6b8f8a56a4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15901 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-27soc/nvidia/tegra124: remove cache_policiy optionAaron Durbin
All mainboards (nyans) utilizing the cache_policy option has it set to DCACHE_WRITETHROUGH. This option is for setting the framebuffer's cache attribute. However, this option is reliant on an architecture-specific enumeration. Just remove the option and use DCACHE_WRITETHROUGH across the board. If someone wants to reconfigure it at a later date one can introduce a non-architecture specific option. Change-Id: I6a0848231f5e28d36ec2d56b239bed67619fe5a7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15838 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2016-07-26google/oak: dsi: set mipi pin driving control onMartin Roth
We set this driving control to prevent signal attenuation caused by LVDS DRV termination. When DA_LVDSTX_PWR_ON is not set, LVSH has no power and LVDS DRV termination status is unknown(floating). This creates a chance that MIPI output would be influenced. The DSI's LP signal will be half voltage attenuation. There will be no display on panel. When DA_LVDSTX_PWR_ON is set, LVSH and LVDS DRV termination are effective and termination is fixed OFF. The DSI won't be influenced. We only need to set this register once, so we set it here to prevent repeat setting in the kernel when the system goes to recovery mode. BUG=chrome-os-partner:55296 BRANCH=none TEST=build pass elm and show ui The original commit in the cros repo combined the chipset and mainboard code changes. This has been split for the push to coreboot.org Change-Id: I733bdd115950b71493856220414ac0dd75d28122 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0d25a27f300acc4b65a894110d3ee0cc9676cd12 Original-Change-Id: Ie71f9cc41924787be8539c576392034320b57a49 Original-Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/360850 Original-Commit-Ready: jitao shi <jitao.shi@mediatek.com> Original-Tested-by: jitao shi <jitao.shi@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15808 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25google/gru: Change UART _Static_assert() condition to #ifJulius Werner
_Static_assert() gets evaluated even when the code path it's in is unreachable (e.g. inside an if (0) block). Unfortunately, Kconfigs that depend on a disabled Kconfig are always 0, meaning that CONFIG_CONSOLE_SERIAL_UART_ADDRESS on Gru cannot evaluate to UART2 when CONFIG_CONSOLE_SERIAL (which it depends on) is disabled. Switch the condition it is wrapped in to a preprocessor #if so that the _Static_assert() is not evaluated when building without serial support. BRANCH=None BUG=None TEST=Built and booted Kevin without serial Change-Id: I391325fcc4b7d64b4866a7fce4444e2f28365b7d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f5e5cf0644154eca5b347ea381df3f6b28287524 Original-Change-Id: I33d51d4ef09b218c14173d39a12795f0cef6bb40 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/361581 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15810 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25google/gale: Fix board ID and GPIO config.Kan Yan
Fix the board ID handling. Recovery switch and WP status GPIO has been reassigned in board rev3. Configure related GPIOs based on Board ID. BUG=chrome-os-partner:55320 TEST=Verified GPIO assignment for Rev.1 board. BRANCH=None Change-Id: Id8e1ba1c039f8b5b503f0da038e5cfc84b72678f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d295ab514e31d9ebd1b77e0af9b769e64cbf567e Original-Change-Id: I6d3d5df2e9017f7845edc3cd0b2c19ad7c58a97c Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/361393 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/15809 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-25vboot: Clean up vboot codeFurquan Shaikh
1. Remove unused functions/structures. 2. Add checks for NULL return values. 3. Change prefixes to vb2 instead of vboot for functions used internally within vboot2/ 4. Get rid of vboot_handoff.h file and move the structure definition to vboot_common.h 5. Rename all functions using handoff structure to have prefix vboot_handoff_*. All the handoff functions can be run _only_ after cbmem is online. 6. Organize vboot_common.h content according to different functionalities. BUG=chrome-os-partner:55431 Change-Id: I4c07d50327d88cddbdfbb0b6f82c264e2b8620eb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15799 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-25skylake: Move CHROMEOS config to SoCFurquan Shaikh
All the mainboards share the same config options for CHROMEOS. Instead of duplicating those in every mainboard, move the CHROMEOS config to SoC and make it dependent on MAINBOARD_HAS_CHROMEOS. BUG=chrome-os-partner:55431 Change-Id: Iafabb6373dfe16aaf0fe2cbc4e978952adeb403e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15822 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-25apollolake: Move CHROMEOS config to SoCFurquan Shaikh
All the mainboards share the same config options for CHROMEOS. Instead of duplicating those in every mainboard, move the CHROMEOS config to SoC and make it dependent on MAINBOARD_HAS_CHROMEOS. BUG=chrome-os-partner:55431 Change-Id: I2d54ff6beac9fca7596a8f104e3c1447cada5c05 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15821 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-25intel/amenia: Add chromeos.c to verstageFurquan Shaikh
BUG=chrome-os-partner:55431 Change-Id: I94fe54c12d7438a71f81a9053cc9785c0aa1e6cf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15823 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-25google/jecht: Increase RO coreboot size on flashDaisuke Nojiri
Bitmap images have been moved to CBFS from GBB. This patch adjusts the flash size accordingly for jecht. BUG=chromium:622501,chromium:628494 BRANCH=none TEST=emerge-jecht chromeos-bootimage CQ-DEPEND=CL:361380 Change-Id: I941df04b4999d35bd652e4ee1664c032cb550b29 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c859ce04d2df5f21c47a164cabbc9ef6dec61818 Original-Change-Id: I50a9ade2e90237b0a7c277bffd7b540132415f13 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/361370 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15806 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-24google/reef: Enable PS/2 keyboard driver by defaultDuncan Laurie
This device has a built-in keyboard that should be enabled by default or it will not work in firmware. This was tested to ensure that TAB (display info) and Ctrl+D (enter developer mode) are functional at the Chrome OS recovery screen. BUG=chrome-os-partner:55549 Change-Id: I60156f1fc001b88deac69e03e02e9d8277fbc38d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15782 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-22intel/amenia: Write protect GPIO relative to bank offsetsselvar2
Update the write protect GPIO reported in ACPI to GPIO_75. Also update the controller ID to "INT3452:01" which will point at the goldmont device and includes write protect GPIO. BUG=none BRANCH=none TEST=verify crossystem output for wpsw_cur. Change-Id: Id6b172e289976072836746c1814e0300544a06cb Signed-off-by: sselvar2 <susendra.selvaraj@intel.com> Reviewed-on: https://coreboot.intel.com/7771 Reviewed-by: Sparry, Icarus W <icarus.w.sparry@intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15496 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22google/reef: Update gpio config for audioSathyanarayana Nujella
This changelist updates gpio config for speaker SDMODE pin. It disables speaker by default. Audio kernel is expected to enable this when audio rendering starts. Change-Id: Id33ad29e637bf1fe6b02e8a4b0fd9e220e8983e7 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15433 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-22soc/intel/apollolake: clarify meaning of LPDDR4 density meaningAaron Durbin
The 'dram density' is a misnomer because the memory initialization code treats that input parameter as a per rank density. Therefore, update the variables to further clarify how it's actually being used. BUG=chrome-os-partner:55446 Change-Id: Ie4c944f35b531812205ac0bb1c70f39ac401495e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15773 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-22mainboard/google/reef: indicate dual rank LPDDR4 skusAaron Durbin
The 16Gb devices use two ranks per channel within the DRAM module. However, the density settings are really on a per rank basis so indicate dual rank with a device density of 8Gb. BUG=chrome-os-partner:55446 Change-Id: Ib5dba6f9ed248750d68b726996c71def9b75961e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15772 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-21mainboard/google/reef: handle eMMC power signal polarity changeAaron Durbin
The EVT board uses an active high power control signal while the previous board used an active low signal. Update the tables to reflect the differences. BUG=chrome-os-partner:55470 Change-Id: I198c0e4e019fcffe2cf748d382351ac965a81077 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15763 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21mainboard/google/reef: reverse the memory config bitsAaron Durbin
I mistakenly assumed the order of the bits matched how one would assign values as they wrote them msb .. lsb. However, the gpio lib doesn't do that. Correct the order so that values are read out correctly. BUG=chrome-os-partner:54949t Change-Id: I5304dfe2ba6f8eb073acab3377327167573ec2cc Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15753 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-21timestamp: Drop duplicate TS_END_ROMSTAGE entriesKyösti Mälkki
This entry gets added in run_ramstage(). Change-Id: I18cda4ead3614c6d07c3269cbee53e6def6408c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15755 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-20google/reef: Add wake signal for trackpadFurquan Shaikh
EVT has a wake signal for track pad which is routed to GP_15. BUG=chrome-os-partner:54960 Change-Id: I9a73a3dc74e3bbed63509a3c076ec17a6559da55 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15723 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-20amd/db-ft3b-lc: Add board supportKyösti Mälkki
Change-Id: Ibab9039306730bfd3063b34cf085e854e4608902 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14970 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-07-20amd/db-ft3b-lc: Copy of amd/olivehillplusKyösti Mälkki
Change-Id: I70330278bae54392e236d762716ba7c4d39a05a6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14969 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-19intel/amenia: Add DA7219 support in acpiHarsha Priya
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45021 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15625 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-19mainboard/google/reef: explicitly set shipping Chrome OS optionsAaron Durbin
The Chrome OS options that will be shipped on this platform were being set in the chromium repo with an external config file. Set the options in the mainboard Kconfig file so there's no discrepancy as to what will be used. Change-Id: I05f0d1245611c16f54273728519a08e6edff3429 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15733 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-18google/oak & elm: initialize touchscreen reset gpioYH Huang
In order to save power in S3, we remove reset gpio setting in kernel. We still need to initialize touchscreen ic. Do it by pulling low reset gpio for 500us and then pulling high in firmware. BRANCH=none BUG=chrome-os-partner:55170 TEST=build on elm. Change-Id: Idbe0175a1fc1fa0b05e81706194c79d52c6101f6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: f40cc9a22c2551c2c9455cb8b60f36353602bca6 Original-Change-Id: If2ac815c4fd5c5ae15443348a49eb31449b724b1 Original-Signed-off-by: YH Huang <yh.huang@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/360312 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Johnny Chuang <johnny.chuang@emc.com.tw> Reviewed-on: https://review.coreboot.org/15719 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-18gru: implement hw reset functionVadim Bendebury
Asserting this GPIO will send a signal to the EC to trigger a reset for the AP and the CR50. BRANCH=none BUG=chrome-os-partner:55252 TEST=the device now reboots when it needs to switch between different boot modes instead of hanging with "failed to reboot" message. Change-Id: I8d168e313b6983c96c80f7ad6d70bb84c1ec1d9c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 83a4c8ff68ab24a103f2166e948eb23624ea97f7 Original-Change-Id: Idfd20977cf3682bd8933f89e8eec53005e55864e Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/360238 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15718 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-07-17mainboard/amd: add support for F2950 system boardAndrey Korolyov
F2950 SBC, also known as TONK 1201/TONK 1202, was originally produced as a Centerm F2950 using DB800 reference design. Common configuration does include a 600 MHz GeodeLX CPU underclocked to 500 or 400 MHz, 128 or 512 MiB of RAM in the single SODIMM slot and 128 or 512 MB IDE DOM. The board does have three USB 2.0 ports (none of them possessing debug capabilities), PS/2, VGA, Geode audio in/out and the serial port. EEPROM needs to be soldered out and flashed externally at the time of this message because flashrom would neither be able to dump BIOS correctly while running vendor BIOS nor write flash contents. All peripherals were tested against Linux 3.16 and seem to work flawlessly. At the moment of this commit coreboot does not pass PCI_COMMAND_IO from the configuration space to SeaBIOS, thereby preventing VGA OPROM from being executed. This would be fixed in the SeaBIOS itself or in a subsequent commit. As a workaround, user may put VGA OPROM to vgaroms/seavgabios.bin in CBFS. Signed-off-by: Andrey Korolyov <andrey@xdel.ru> Change-Id: I93f13ecb53bd05abc0e07e0bd7ba40e646dcb4c4 Reviewed-on: https://review.coreboot.org/15565 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-15intel/amenia: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Platform wakes up from S3 on lidopen. Change-Id: I48b456baf5f7e1c2f28454fa66bb90ad761bb103 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15618 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15soc/intel/apollolake: Consolidate ISH enablingAndrey Petrov
Since the Integrated Sensor Hub can be disabled through devicetree.cb as a PCI device, there is no need for a separate register variable. Remove handling the register and update mainboards' devicetrees. Also keep ISH disabled on both Reef and Amenia. Change-Id: I90dbf57b353ae1b80295ecf39877b10ed21de146 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15710 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15google/reef: Add wake-up from lid openShaunak Saha
This patch adds support to wake up from S3 on lidopen. mainboard.asl has the _PRW defined for the wakeup support in S3. BUG = chrome-os-partner:53992 TEST = Reef board wakes up from S3 on lidopen. Change-Id: Ic3bae26cea0642f98d938b3523d08f5902a1f4b5 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15643 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-15mainboards/skylake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Ie83e93db514aa0e12e71d371d7afab34a70797fd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15689 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-15mainboards/apollolake: use common Chrome EC SMI helpersAaron Durbin
Reduce duplicate code by using the Chrome EC SMI helper functions. BUG=chrome-os-partner:54977 Change-Id: Iba2ca7185ad7f0566858ce99f5ad8325ecc243cf Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15687 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-07-15mainboards: remove direct acpi_slp_type usageAaron Durbin
Use the acpi_is_wakeup_s3() API instead of comparing a raw value to a global variable. This allows for easier refactoring. Change-Id: I2813b5d275cbe700be713272e3a88fdb5759db99 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15690 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2016-07-15mainboards: align on using ACPI_Sx definitionsAaron Durbin
The mainboard_smi_sleep() function takes ACPI sleep values of the form S3=3, S4=4, S5=5, etc. All the chipsets ensure that whatever hardware PM1 control register values are used the interface to the mainboard is the same. Move all the SMI handlers in the mainboard directory to not open code the literal values 3 and 5 for ACPI_S3 and ACPI_S5. There were a few notable exceptions where the code was attempting to use the hardware values and not the common translated values. The few users of SLEEP_STATE_X were updated to align with ACPI_SX as those defines are already equal. The removal of SLEEP_STATE_X defines is forthcoming in a subsequent patch. BUG=chrome-os-partner:54977 Change-Id: I76592c9107778cce5995e5af764760453f54dc50 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15664 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-15Google Mainboards: Increase RO coreboot size on flashDaisuke Nojiri
Bitmap images will be moved to CBFS from GBB. This patch adjusts the flash map accordingly for rambi, samus, peppy, parrot, falco, panther, auron, and strago. BUG=chromium:622501 BRANCH=tot TEST=emerge-{samus,falco} chromeos-bootimage CQ-DEPEND=CL:354710,CL:355100 Change-Id: I6b59d0fd4cc7929f0de5317650faf17c269c4178 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 201a82311ba539b9b02d546ba331ff5bf73e0edf Original-Change-Id: I0b82285186540aa27757e312e7bd02957f9962ec Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/355040 Reviewed-on: https://review.coreboot.org/15658 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-07-14spike-riscv: Look for the CBFS in RAMJonathan Neuschäfer
Change-Id: I98927a70adc45d9aca916bd985932b94287921de Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15285 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins)
2016-07-14spike-riscv: Register RAM resource at 0x80000000Jonathan Neuschäfer
Without this patch, the CBFS loader won't load segments into the RAM. Change-Id: If05c8edb51f9fe2f7af84178826f93b193cfd8a9 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15511 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-07-14siemens/mc_bdx1: Add usage of external RTC PCF8523Werner Zeh
This mainboard contains an external RTC chip PCF8523. Enable usage of this chip and add some initialization values to device tree. Change-Id: I25c0a017899ee904f3aa02bdc7dcaf61dee67e3a Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-14intel/amenia: Add mainboard SMI handlerShaunak Saha
This patch adds a mainboard SMI handler file which has functions to set proper Wake mask before going to sleep so that system can wake up on lidopen, key press etc. Also SCI mask is set on boot which will enable timely update of battery UI on charger connect/disconnect. BUG = chrome-os-partner:53992 TEST = Amenia platform wakes from S3 on lidopen, key press and also sysfs entry for AC is updated on charger connect/disconnect. Change-Id: If3dc6924c51c228241b7a647566b97398326ec0e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15616 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14google/reef: Add mainboard SMI handlerShaunak Saha
This patch adds a mainboard SMI handler file which has functions to set proper Wake mask before going to sleep so that system can wake up on lidopen, key press etc. Also SCI mask is set on boot which will enable timely update of battery UI on charger connect/disconnect. BUG = chrome-os-partner:53992 TEST = Reef Platform wakes from S3 on lidopen, key press and also sysfs entry for AC is updated on charger connect/disconnect. Change-Id: I8c087994b48223b253dcf1cbb3ed3c3a0f366e36 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15615 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-14intel/amenia: Add Maxim98357a supportHarsha Priya
Adds Maxim98357a support for amenia using the generic driver in drivers/generic/max98357 Change-Id: I333d4e810e42309ac76dd90c19f05cf3e3a518f1 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15624 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>