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2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02lenovo/x60: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/lenovo/x60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16372 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02lenovo/x200,t400: use gpio.h instead of gpio_setupArthur Heymans
Uses gpio.h instead of default_southbridge_gpio_setup to configure southbridge GPIO's. This is more consistent with how GPIO's are configured on newer targets. Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16379 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02Fix newlines at the end of filesMartin Roth
All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-01mainboard/google/reef: drop proto gpio supportAaron Durbin
Many changes make proto boards very hard to work with since proto boards were using A stepping processors. Everyone has moved on. Therefore, drop non-proto support. BUG=chrome-os-partner:56791 Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16377 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-09-01mainboard/google/reef: add pen connectionsAaron Durbin
A pen interface was added. Prepare for possibly testing it by plumbing in the gpio configuration. It's very possible these changes need to be tweaked, but no driver code has been seen yet nor a datasheet detailing how some of these signals actually function. BUG=chrome-os-partner:56739 Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16376 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: fix polarity of FP_INTAaron Durbin
The formerly name FP_INT_L net is actually active high and is push-pull. Therefore adjust for the new net name, FP_INT, and polarity. The pulldowns are there because the device is on another board that isn't always available. BUG=chrome-os-partner:56740 Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16375 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: add new memory SKUsAaron Durbin
Two new SKUs are being utilized for reef DVT. Add the following: Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100 Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101 BUG=chrome-os-partner:56738 Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16374 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: support WLAN_PE_RSTAaron Durbin
The reef DVT build added another way to assert the wifi module's reset line. Ensure it's deasserted by default. For previous boards this GPIO doesn't matter because it wasn't routed anyway. BUG=chrome-os-partner:56737 Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpuEric Gao
Before, we calculate the pwm duties for cpu cores and centerlogic by hand, adding pwm_regulator.c to handle this. The default pwm design min/max voltage may be different between revs. With the pwm regulator, this patch changes the little cpu frequency from 600M to 1512M, and raises CPU voltage to 1.2V correspondingly. This also means we decide to drop the ES1 because it may fail to bootup with 1.5G ~ 1.2v. BRANCH=none BUG=chrome-os-partner:54376,chrome-os-partner:54862 TEST=Bootup on kevin board Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9 Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31rockchip/rk3399: Move romstage.c to mainboard/gruShunqian Zheng
The romstage.c is more board related than soc specific, like setting the pwm regulators, so moving it to mainboard/gru. BRANCH=none BUG=chrome-os-partner:54819 TEST=Bootup on kevin board Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474 Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/375398 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31mainboard/*/Kconfig: Set GBB_HWID where missingPatrick Georgi
Provide GBB's hardware ID (used on Chrome OS devices) because it will be dropped from depthcharge. BRANCH=none BUG=none TEST=none Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00 Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/372579 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16363 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31soc/intel/apollolake: Disable Periodic Retraining per-SKUAndrey Petrov
Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=run RMT test, pass Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-30nyan-blaze: Correct indentation for sdram configsPaul Kocialkowski
This corrects indentation for sdram configs in nyan_blaze. Change-Id: Ia9ad2a37c6e3b79e1260f490db893244c32685b6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16342 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-30mainboard/google/reef: set SLP_S3_L assertion width to 28msAaron Durbin
The reef board needs at least ~28ms for its S0 rails to discharge when S3 is entered. Because of the granularity in the chipset the effective SLP_S3_L assertion width is 50ms. BUG=chrome-os-partner:56581 Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16327 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-27gru: Make SDRAM parameters individual struct files in CBFSJulius Werner
This patch changes Gru SDRAM parameters from structures that just get compiled into the romstage to individual CBFS files. This allows us to only load the parameter set we need for the board we're booting from flash, which reduces our boot time and the SRAM memory footprint required to hold the romstage. TEST=Booted Kevin. Change-Id: Ie88a515cbdb19a794ca0a230a56bcc82bed1e550 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27lenovo/x200,t400: enable C4 cpu low power stateArthur Heymans
This enables the C4 low power state on the lenovo x200 and t400. It's inspired by the thread on the mailinglist: "[coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS". What this does, is to enable a C3 state using MWAIT(C3) request and set the southbridge config c4onc3_enable to automatically upgrade C3 to the lower power C4 state. The latency (0x37) is the same value used by the vendor bios. With C4 enabled the idle power consumption is about ~2-3W lower. TEST= build and install on target. Use powertop top to measure power usage. To manually disable c-state to compare them, do (tested on linux 4.4): echo 1 > /sys/devices/system/cpu/cpu*/cpuidle/stateX/disable Change-Id: I1a1663a7662ebc7157a965667680688ad6a33545 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15251 Tested-by: build bot (Jenkins) Reviewed-by: Swift Geek Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-25vboot: consolidate google_chromeec_early_init() callsAaron Durbin
On x86 platforms, google_chromeec_early_init() is used to put the EC into RO mode when there's a recovery request. This is to avoid training memory multiple times when the recovery request is through an EC host event while the EC is running RW code. Under that condition the EC will be reset (along with the rest of the system) when the kernel verification happens. This leads to an execessively long recovery path because of the double reboot performing full memory training each time. By putting this logic into the verstage program this reduces the bootblock size on the skylake boards. Additionally, this provides the the correct logic for all future boards since it's not tied to FSP nor the mainboard itself. Lastly, this double memory training protection works only for platforms which verify starting from bootblock. The platforms which don't start verifying until after romstage need to have their own calls (such as haswell and baytrail). Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16318 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-24google/reef: Tune eMMC DLL settings for reef evtChiranjeevi Rapolu
Apply eMMC tuned DLL settings for reef evt. Modify comments to avoid replicating info. Add EDS reference. BUG=chrome-os-partner:55648 BRANCH=none TEST=Verify that reef evt boots to OS from eMMC. Change-Id: If3bf51f3b7d38320f504ea6fbecf7c188a94ae5c Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://review.coreboot.org/16296 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
Not all SBI calls are implemented, but it's enough to see a couple dozen lines of Linux boot output. It should also be noted that the SBI is still in flux: https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16119 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23src/mainboard: Remove unnecessary whitespace before "\n"Elyes HAOUAS
Change-Id: I9789b0b3339435fbe30c69221826bf23c9b3c77b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16283 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23emulation/qemu-i440fx: add cmos.default fileAntonello Dettori
Add cmos.default file in order to ease future testing and debugging of cmos related code. Change-Id: I7c6a0aa4e38bb08a520e4838fa216c81b50f2917 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16247 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-22mb/asus/kgpe-d16: Add TPM supportTimothy Pearson
The ASUS KGPE-D16 accepts an optional Infineon LPC TPM module. Expose the TPM LPC device to the host operating system. Change-Id: If500e9162bf1e233ccaa35db79452daa59a34f2f Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16269 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-21mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cbTimothy Pearson
Change-Id: I49925040d951dffb9c11425334674d8d498821f0 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16268 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-20google/reef: Save DIMM info from SMBIOS memory HOBRavi Sarawadi
Add support for SMBIOS memory HOB save. Add DIMM 'part_num' info to be saved as part of SMBIOS memory HOB. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: I53b4a578f31c93b8921dea373842b8d998127508 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-19rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevinLin Huang
We should be running faster. Faster = better. BRANCH=None BUG=chrome-os-partner:54873 TEST=Boot; stressapptest -M 1028 -s 10000 Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362822 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19qemu-riscv: Remove obsolete CSR - send_ipiMartin Roth
This aligns the code in qemu-riscv with the code in spike-riscv. The previous code gives an error in the updated toolchain as the send_ipi CSR is no longer valid. This gave the build error: src/mainboard/emulation/qemu-riscv/qemu_util.c:64: Error: Instruction csrw requires absolute expression Change-Id: Iac0f66e8e9935f45c8094d5e16bedb7ac5225424 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16244 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-08-19google/reef: Configure NFC gpios correctly before entering sleepFurquan Shaikh
Before entering sleep, ensure that the NFC gpios are configured correctly to avoid leakage. BUG=chrome-os-partner:56281 Change-Id: I2bb2e7ba468df445aa5f6c2b22ae0a74fcaa44f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16243 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-18intel/amenia: Update eMMC DLL settingsBora Guvendik
Update eMMC DLL setting for amenia board, after that system can boot up with eMMC successfully. BUG=chrome-os-partner:51844 TEST=Boot up with eMMC Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16237 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-18Kconfig: lay groundwork for not assuming SPI flash boot deviceAaron Durbin
Almost all boards and chipsets within the codebase assume or use SPI flash as the boot device. Therefore, provide an option for the boards/chipsets which don't currently support SPI flash as the boot device. The default is to assume SPI flash is the boot device unless otherwise instructed. This falls in line with the current assumptions, but it also allows one to differentiate a platform desiring SPI flash support while it not being the actual boot device. One thing to note is that while google/daisy does boot with SPI flash part no SPI API interfaces were ever implemented. Therefore, mark that board as not having a SPI boot device. BUG=chrome-os-partner:56151 Change-Id: Id4e0b4ec5e440e41421fbb6d0ca2be4185b62a6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16191 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-16Revert "rockchip: rk3399: enable sdhci clk for emmc"Shunqian Zheng
This reverts commit 462e1413 ("rockchip: rk3399: enable sdhci clk for emmc") Enabling this clock in coreboot is no longer needed as it's handled in the kernel driver now. BUG=chrome-os-partner:52873 TEST=boot from usb/sdcard and check there is /dev/mmcblk0 BRANCH=none Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0 Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/367421 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16152 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-15reef: Increase TSR2 threshold to 100Furquan Shaikh
This is a temporary work-around since the current threshold of 70 on TSR2 results in thermal trip and shutdown while the kernel is booting. Changing this threshold to 100 allows kernel to boot up to userspace. Following values were read: $ cat /sys/class/thermal/thermal_zone4/temp 81800 $ cat /sys/class/thermal/thermal_zone4/type TSR2 BUG=chrome-os-partner:56155 BRANCH=None TEST=Boots to OS. Change-Id: I951553ed4c93b02239a51a0d3036e4a750eea04b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16156 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-08-15mainboard/google: remove unused BOOT_MEDIA_SPI_CHIP_SELECT optionAaron Durbin
The BOOT_MEDIA_SPI_CHIP_SELECT option is not used in any of the code. Remove its usage. BUG=chrome-os-partner:56151 Change-Id: I522b62a2371b8a167ce17c48117669390cda14cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16185 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-15mb/gigabyte/ga-b75m-d3v: Add missing board URLJonathan Neuschäfer
Change-Id: I990038c09f5805c8e670fd316808dde767e8671b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16159 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-13Revert "gru: Show the current time on start-up"Julius Werner
This reverts commit 850e45f19f498eedd80da4a97a5ce641e2cec6d5. google_chromeec_init() is a weird function that can lead to confusing behavior. I'm not sure how it's meant to work on the boards that use it, but it causes problems on Kevin and other non-x86 boards have never used it either. It doesn't really do anything anyway (the EC works fine without an initial HELLO), so at best it's just a waste of time... let's take it back out. There's also no need to display the current time on every boot... other boards don't do that and the eventlog already fills the same purpose. Cut it out to avoid one extra host command overhead. BRANCH=None BUG=chrome-os-partner:55995 TEST=Recovery reasons now get correctly propagated across the EC reboot. Change-Id: Ic3b772780d4d05e362c269969e6e4e7069482bb6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 103d86e68cd164bea39aa1edc8668d80358edbde Original-Change-Id: I58fd5e6094e1c8cb6368e7a4569ab9231375fbc9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/367351 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/16153 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11reef: Update chromeos.fmdFurquan Shaikh
1. Get rid of LBP2 partition 2. Shrink RO size 3. Increase RW-A and RW-B sizes 4. Increase RW_MRC_CACHE size CQ-DEPEND=CL:366793 BUG=chrome-os-partner:52127, chrome-os-partner:55699, chrome-os-partner:55778 BRANCH=None TEST=Compiles successfully. Boots to OS. Change-Id: Iad41d8cc7697e6d73f1aa2c699b0e8559349b77e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11rockchip/rk3399: Add code to neuter Type-C PHY for firmware USBJulius Werner
The Rockchip RK3399 integrates a USB Type-C PHY in charge of things like SuperSpeed line muxing for rotated cable orientations in the SoC. While fancy, this is very complicated and we don't want to implement support for the whole thing in firmware. The USB Type-C standard has intentionally been designed in a way that the USB 2.0 (HighSpeed) lines always "just work" in any orientation (by just shorting different pins in the connector together) so that simple use cases like ours can get basic USB functionality without much hassle. However, a semi-configured Type-C PHY can confuse USB 3.0 capable devices into thinking we're actually supporting SuperSpeed, and fail at that rather than establishing a reliable HighSpeed connection. This patch sets enough bits in the Type-C PHY to electrically isolate the SuperSpeed lines from the connector so that the connected device isn't going to get any fancy ideas and reliably falls back to USB 2.0. Also clean up the rest of the USB code while we're at it: avoid writing a few bits that are already in the right state from their reset values anyway, or reading values whose content we already know for this SoC. Rename the USB controllers to the name actually used in the Rockchip documentation (USB OTGx) rather than the name blindly copied from Exynos code (USB DRDx). BRANCH=None BUG=chrome-os-partner:54621 TEST=Plug a USB 3.0 Patriot Memory stick into both ports in all orientations, observe how it gets reliably detected now (safe for some known hardware issues on my board). Change-Id: Ifce6bcddd69f2e8f2e2a2f48faf65551e084da1e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c526906f998bf66067d3addb8b3d3a126c188b1e Original-Change-Id: Ie80a201a58764c4d851fe4a5098a5acfc4bcebdf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/366160 Original-Reviewed-by: liangfeng wu <wulf@rock-chips.com> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: <515506667@qq.com> Reviewed-on: https://review.coreboot.org/16125 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-11lenovo/x60: add info message if dock is presentAlexander Couzens
Change-Id: I5a6d41f815f65719780499fa18c131311a9dc8f7 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16136 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-11lenovo/x60: add GPIOs initialisation before dock checkAntonello Dettori
Add GPIOs initialisation before dock check. Needed in order to properly detect the presence or absence of the lenovo dock. Previously the check always reported the dock as connected and currently it always reports it as disconnected since the GPIOs are not properly initialised during the check. Tested and confirmed working. Change-Id: I7fbf8c2262a1eb5dee9cbe5e23bf44f7f8181009 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16139 Tested-by: build bot (Jenkins) Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-11intel/amenia: Add MAINBOARD_FAMILY for ameniaBora Guvendik
BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: I66178cc75872f14941434081d9650a569a084d04 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16135 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-11intel/amenia: set default value for BOOT_MEDIA_SPI_BUSBora Guvendik
BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: I60d411482812d98cb8dd11d66b0fc96ea9bae895 Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16134 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-11intel/amenia: Select UART_FOR_CONSOLE for ameniaBora Guvendik
Set default value for UART port BUG=chrome-os-partner:51844 TEST=Boot to chrome and check console Change-Id: I5e76066e0ff531303595dcd5a99f2f8db379e89b Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16133 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11intel/amenia: Update flash size to 16MBBora Guvendik
Update flash image size to 16MB and update image layout in flashmap descriptor file. BUG=chrome-os-partner:51844 TEST=Boot to chrome Change-Id: Ibdfb2949d06aedc38ddcef1078c2d14abcfa2dac Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16083 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-10google/reef: Add mainboard handler function for gpio SMIShaunak Saha
This patch adds mainboard_smi_gpi_handler which handles the SMI event. This can happen in situations like lidclose and system goes to shutdown. BUG=chrome-os-partner:54977 TEST=When system is in firmware mode executing the command lidclose from ec console shuts down the system. Change-Id: I8ff6001e48dcbbd4cee5097e759352d8fea6189b Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15834 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-09google/gru: Fix rk3399-gru write protectDouglas Anderson
The write protect GPIO is active high, not active low. After fixing I can see this after removing the write-protect screw: $ crossystem | grep wpsw_boot wpsw_boot = 0 Putting the screw in shows: $ crossystem | grep wpsw_boot wpsw_boot = 1 Caution: this CL contains explicit material. It explicitly sets the pullup on the WP GPIO even though that's the boot default. BRANCH=None BUG=chrome-os-partner:55933 TEST=See desc. Change-Id: I23e17e3bbbe7dcd83e81814de46117491e61baaa Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e6969f4be42c00c6e88bbb14929cf0454462ad21 Original-Change-Id: Ie65db9cf182b0a0a05ae412f86904df6b239e0f4 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/366131 Original-Tested-by: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-09gigbyte/ga-g41m-es2l: add cmos.layout and cmos.defaultArthur Heymans
This adds a cmos.layout and a cmos.default to ga-g41m-es2l. This allows to set things like baud_rate, debug_level, etc. from cmos. Change-Id: I25df7a1f3a0ce486b96cfe05bda628f604b0baec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15493 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-09mainboard/google/rush_ryu: remove rush_ryu mainboardAaron Durbin
The rush_ryu board was a development platform that never made it into a product. Remove it as it's not available to anyone. BUG=chrome-os-partner:55932 Change-Id: Ia3836ff8cade3009730543177a66736ae197572b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16107 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-09mainboard/google/rush: remove rush mainboardAaron Durbin
The rush board was a development platform that never made it into a product. Remove it as it's not available to anyone. BUG=chrome-os-partner:55932 Change-Id: I0f77bb791491509da7bd9cf25050e01c2f734a2f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16106 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-09google/gru: Update board/RAM ID ADC valuesJulius Werner
Looks like our hardware guys have decided to change some voltage ranges in the Gru/Kevin ADC IDs since we last wrote a table. This patch updates it to the latest values from the Spreadsheet of Truth. Also adds further values up to rev15. BRANCH=none BUG=none TEST=none Change-Id: I1aa093ca3abe952afd658eb7da01b325f798eaa0 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e42b4685c91f01ce1cff61638b17042be9d575fd Original-Change-Id: I646fd03dc385df1a8f0af8cb85ff3128cc31f8d8 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/365111 Original-Tested-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16053 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-08supermicro/h8scm: Remove last unused chip.h fileMartin Roth
Change-Id: I84d61c8ade6e42e314a31e1155b4d5628b16199a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16081 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-08skylake/devicetree: Add PIRQ Routing programmingBarnali Sarkar
Program PIRQ Routing with correct values, as done by FSP, and also in 'soc/intel/skylake/romstage/pch.c' file. If not done, these values get overridden by "0" during PxRC -> PIRQ programming in ramstage, in 'soc/intel/skylake/lpc.c' file pch_pirq_init()function. BUG=none BRANCH=none TEST=Build and boot kunimitsu Change-Id: Ibeb9a64824a71c253e45d6a1c6088abd737cf046 Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Reviewed-on: https://review.coreboot.org/16044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2016-08-08google/reef: Configure SDIO D1 to enable SCS Power GatingJagadish Krishnamoorthy
SDIO D1 pin needs to be configured as Native mode to enable SCS Power Gating. BUG=chrome-os-partner:54251 TEST=Verify SCS Power Gating Change-Id: Ic33b26443203217678e11d195eb965a7e628ad82 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/16062 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-06google/reef: Enable I2C2 for use in bootblockDuncan Laurie
Enable I2C bus 2 for early init so it can be used by vboot for TPM communication for verifying the memory init code. BUG=chrome-os-partner:53336 BRANCH=none TEST=build and boot on reef Change-Id: Id4940ab01d8ccf288ab0a7a9a2f19867ed464e8d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16059 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05google/reef: Correct SD card pins configChiranjeevi Rapolu
SD CLK and CLK_FB needs to be pulled down by 20K. SD CD_N is active LOW, needs to be pulled up by 20K SD WP pin is not connected for uSD cards, enable writes by default by pulling low by 20K. BUG=chrome-os-partner:54866 BRANCH=None TEST=Test with uSD cards. Change-Id: Ia4bbd966ffb21e276dfc31a74f4ea54718900d66 Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://review.coreboot.org/16057 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-05soc/intel/quark: Add FSP 2.0 romstage supportLee Leahy
Add the pieces necessary to successfully build and run romstage using the FSP 2.0 build. Because romstage is using postcar, add the postcar pieces so that romstage can attempt to load postcar. TEST=Build and run on Galileo Gen2 Change-Id: I66b3437e3c7840223535f6ab643599c9e4924968 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15866 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-05soc/intel/quark: Add FSP 2.0 boot block supportLee Leahy
Add the pieces necessary to successfully build and run bootblock using the FSP 2.0 build. TEST=Build and run bootblock on Galileo Gen2 Change-Id: I2377f0b0147196f100396b8cd7eaca8f92d6932f Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15865 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-04chromeec: Chrome EC firmware source selection for EC and PD firmwaresPaul Kocialkowski
In some cases, we don't want the Chrome EC firmwares (both EC and PD) built directly by the coreboot build system or included in images at all. This is already supported with EC_EXTERNAL_FIRMWARE but it does implement a binary (build and include) or (neither build nor include) policy. Some cases require the ability to separately control whether the EC and PD firmwares should be built and included by the coreboot build system, only included from externally-built images or not included at all. This introduces config changes implementing that behaviour, renaming options to make it clear that they are specific to the Chrome EC. Change-Id: I44ccee715419360eb7d83863f4f134fcda14a8e4 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16033 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-04google/reef: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: If5a6a1cb8f065a8c3a6a19d9441a21d60b39e579 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16031 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-03lenovo/x60: Fetch 16 bits when trying to parse bit 13Patrick Georgi
I'm not sure if that's the right fix here, but assuming the bit mask is right, the inb is wrong. Change-Id: I7e33019af088780a09be12513200bec63734bf97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1229556 Reviewed-on: https://review.coreboot.org/16026 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-08-03google/gale: Add more board ID variantsKan Yan
EVT1 has two board IDs. Use binary first mode of base3 encoding for board ID. BUG=chrome-os-partner:55320 TEST=None. BRANCH=None Change-Id: I1cac1f74207f42616111d39db5c0494b7d1a0fb2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 2b16cc74c4c147315b7db345678bbaf536ab4a7b Original-Change-Id: I6e95c7be4a6d28a0aae38b0838bd2ab71d288ba1 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364623 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Suresh Rajashekara <sureshraj@chromium.org> Reviewed-on: https://review.coreboot.org/16030 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add code to support I2C TPM for KevinJulius Werner
Coming Kevin revisions will switch back to an I2C TPM. This patch adds the required configuration options and code to support that. Since the TPM type can currently only be changed at compile time, we can no longer support older Kevins with the same image. In order to build for Kevin revisions < 5, you have to explicitly override the CONFIG_GRU_HAS_TPM2. BRANCH=None BUG=chrome-os-partner:55523 TEST=Compiled both Kevin and Gru, confirmed that bootblock and verstage binary had the appropriate code differences. Change-Id: I1b2abe0f331eb103eb0a84f773ee7521d31ae5d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3245bff937154f0f9f39894de9c98a75631d59d9 Original-Change-Id: I81a15c9fb037a7ca2d69818e46cbb4f9a5ae1989 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364222 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16029 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-08-03google/gru: Add support for Gru rev1Julius Werner
This patch adds support for the Gru rev1 board. This board differs from rev0 by no longer relying on the I2C backlight booster and requiring the same ODT SDRAM settings as newer Kevin boards. BRANCH=None BUG=chrome-os-partner:55087 TEST=None Change-Id: I1428760540a0aaaa0c02c6cb5b0981294ba4df33 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8de7bcc78c6c48c251c85185e238cea7812f7a28 Original-Change-Id: I3cb49bc644190f35300e6c618b2934956fa88e5b Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/364624 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16028 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-03mainboard/intel/galileo: Add FSP 2.0 Kconfig supportLee Leahy
Add and adjust the Kconfig flags to support both FSP 1.1 and FSP 2.0 builds for Quark. TEST=Build and run on Galileo Gen2 Change-Id: I7c5b7efd2635180edcfe4e1a98bb292030117bc8 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15864 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-03mainboard/intel/galileo: Remove use of EDK-II macros & data typesLee Leahy
Add assert.h to use coreboot's ASSERT macro. Replace the use of UINT8 data type with uint8_t. TEST=Build and run on Galileo Gen2. Change-Id: I0756b0f30b3488647530e2dd1a4ab62813815f3e Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15859 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-02arch/riscv: Add include/arch/barrier.hJonathan Neuschäfer
mb() is used in src/arch/riscv/ and src/mainboard/emulation/*-riscv/. It is currently provided by atomic.h, but I think it fits better into barrier.h. The "fence" instruction represents a full memory fence, as opposed to variants such as "fence r, rw" which represent a partial fence. An operating system might want to use precisely the right fence, but coreboot doesn't need this level of performance at the cost of simplicity. Change-Id: I8d33ef32ad31e8fda38f6a5183210e7bd6c65815 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15830 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-02google/lars & intel/kunimitsu: Disable EC buildMartin Roth
The Chrome EC codebase no longer supports the google/lars and intel/kunimitsu boards. Disable the build in those platforms. Change-Id: Ic4f5a1a34bb19ee31632c1ad8430c30f7154f138 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15869 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-02google/reef: Add pull up 20K for LPC SERIRQKane Chen
per hw team's check and info from EDS, this pin needs to be pu 20K. Otherwise SoC may not notice interrupt request from EC over LPC because SERIRQ line is floating. BUG=chrome-os-partner:55586 BRANCH=none TEST=boot ok and Quanta factory verified the keyboard issue is gone Signed-off-by: Kane Chen <kane.chen@intel.com> Change-Id: I5b0213514ce152d4e2cecdda8786925495a0f24a Reviewed-on: https://review.coreboot.org/15951 Tested-by: build bot (Jenkins) Reviewed-by: Freddy Paul <freddy.paul@intel.com> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-08-02intel/amenia: Add GPIO changes to assert SLP_S0/Reset signalShankar, Vaibhav
PMIC/PMU: Set the iosstates for PMIC to assert the reset signal, PMU to assert SLP_S0 signal. Change-Id: Iec2dd659ea21f07d0bfe74194756786375cf775c Signed-off-by: Shankar, Vaibhav <vaibhav.shankar@intel.com> Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/15777 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-01Remove non-ascii & unprintable charactersMartin Roth
These non-ascii & unprintable characters aren't needed. Change-Id: I129f729f66d6a692de729d76971f7deb7a19c254 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15977 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-08-01Add newlines at the end of all coreboot filesMartin Roth
Change-Id: I7930d5cded290f2605d0c92a9c465a3f0c1291a2 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15974 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-08-01siemens/sitemp_g1p1: Fix typoPatrick Georgi
Change-Id: I1c9af223d3598c4822905acce0cf9b1dca6ad1b6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1287066 Reviewed-on: https://review.coreboot.org/15981 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2016-07-31mainboard/bap/ode_e20XX: Enable UART 3/4 in devicetreeFabian Kunkel
This patch adds IO and IRQ information for UART 3/4 to the devicetree. Patch with Change-Id: Ief5d70c8b25a2fb6cd787c45a52410e20b0eaf2e is needed. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: I1d8fa16950079a47775f48166486415bd5d24f42 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15621 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard/bap/ode_e20XX: Add different DDR3 clk settingsFabian Kunkel
This patch adds two SPD files with different DDR3 clk settings. The user can choose which setting to use. Lower clk settings saves power under load. SoC Model GX-411GA supports only up to DDR3-1066 clk mode. Both SPD settings were tested with memtest for several hours. Power saving is around half a watt under heavy memory load. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Ibb81e22e19297fdf64360bc3e213529e9d183586 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15907 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31mainboard/bap/ode_e20XX: Change PCIe linesFabian Kunkel
This patch binds PCIe lanes 2 and 3 to one PCIe device. PCIe device 2.4 becomes x2. Tested with the connected FPGA on PCIe 2.4. FPGA doubles transfer rate from/to the AMD. Payload SeaBIOS 1.9.1 stable, Lubuntu 16.04, Kernel 4.4.0 Change-Id: Icee567272312a7df4c3b5a6db5b420a054ec3230 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15905 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31sunw/ultra40m2: Fix handling non-existence of a devicePatrick Georgi
This probably never happens, but since we already test for the presence of the device, it makes no sense to try to configure it after its absense was determined. Change-Id: I9877dcd15819fb7949fa08a0954b05780df66316 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Found-by: Coverity Scan #1347362 Reviewed-on: https://review.coreboot.org/15982 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-31google/reef: Update chromeos.fmd RO_SECTIONFurquan Shaikh
Update RO_SECTION to match the changes in depthcharge: https://chromium-review.googlesource.com/#/c/364261 BUG=chrome-os-partner:55713 Change-Id: I7238856cf73a62345778ea87e191a11190b7fb38 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15966 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31intel/amenia: Enable DPTF in mainboardShaunak Saha
This patch enables DPTF support for Intel Amenia platform, adds the ASL settings specific to Amenia boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Amenia board. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: I400e2312a20870058f3a386004fad748d3ee4460 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15094 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31google/reef: Enable DPTF in mainboardShaunak Saha
This patch enables DPTF support for Google Reef platform, adds the ASL settings specific to Reef boards. BUG=chrome-os-partner:53096 TEST=Verify that the thermal zones are enumerated under /sys/class/thermal in Reef boards. Navigate to /sys/class/thermal, and verify that a thermal zone of type TCPU exists there. Change-Id: Ib43e4e9dd0d92fffc1b2c8459c552acd04ca0150 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15640 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-31gigabyte/ga_2761gxdk: Remove comment *endif*Paul Menzel
After the indentation is fixed in commit *mainboard: Format irq_tables.c* [1], the comment is redundant. So remove it. [1] Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Change-Id: Iebbcf10ee3cef1b4cf60ea34a6b3ad51e2208671 Reviewed-on: https://review.coreboot.org/15933 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-31mainboard: Format irq_tables.cPaul Menzel
Run the command below to format the files `irq_tables.c` of (mostly AMD) mainboards correctly with GNU indent 2.2.10. ``` $ git grep -l 'if (sum != pirq->checksum) {' | xargs indent -l ``` Fix up the following two checkpatch.pl errors manually. ``` ERROR: that open brace { should be on the previous line #1219: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:129: + uint8_t reg[8] = + { 0x41, 0x42, 0x43, 0x44, 0x60, 0x61, 0x62, 0x63 }; ERROR: that open brace { should be on the previous line #1221: FILE: src/mainboard/gigabyte/ga_2761gxdk/irq_tables.c:131: + uint8_t irq[8] = + { 0x0A, 0X0B, 0X0, 0X0a, 0X0B, 0X05, 0X0, 0X07 }; ``` This is needed, so that follow-up commits, fixing checkpatch.pl errors and warnings, won’t run into conflicts with the git commit hooks, when for example, spaces instead of tabs are used for indentation. Change-Id: If254723f3013377fb3b9b08dd5eca6b76730ec4a Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/15932 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan A. Kollasch <jakllsch@kollasch.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-31google/gale: Change board ID definition.Kan Yan
Change EVT3 board id to 5. BUG=chrome-os-partner:55320 TEST=None. BRANCH=None Change-Id: I020be47e1fdbf886c7c471d7fdcace1537875b6d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 63bd6541055172765c31a9b1220a24d4e3604cdc Original-Change-Id: I21a8764ff95892430944778f4898d2f1d4c97fd7 Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362391 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: https://review.coreboot.org/15949 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31Update degree symbol to utf-8 encoding in commentsMartin Roth
Almost all of the places where we have the degree symbol '°', it's encoded as 0xc2 0xb0 (utf-8 encoding). There are a few places where it is encoded as just a high ascii byte: 0xb0. Editors that support the high ascii 0xb0 seem to support the utf-8 0xc2 0xb0 encoding as well, but the opposite does not seem to be true. Change the high-ascii degree symbols to utf-8 encoding. Change-Id: I3d06289b802f45e938dc72b4c437fca56235b62b Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15978 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31Remove extra newlines from the end of all coreboot files.Martin Roth
This removes the newlines from all files found by the new int-015-final-newlines script. Change-Id: I65b6d5b403fe3fa30b7ac11958cc0f9880704ed7 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/15975 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-31intel/wifi: Include conditionally in the buildKyösti Mälkki
Keep this enabled by default as most x86 platforms could have PCI-e slots equipped with one of these Intel WiFi adapters. The Kconfig entries under google boards had no function previously, the variable was never referenced. Change-Id: I728ce3fd83d51d4e5e32b848a2079c5fcee29349 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15931 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30mainboard/bap/ode_e21XX: Add board supportFabian Kunkel
Add next generation of BAPs (https://www.unibap.com/) SOC module, called ode_e21XX. Hardware is similar to e20XX (AMD G-Series GX-411GA Kabini), but it includes a new AMD G-Series GX-412HC (Steppe Eagle) and an updated Microsemi FPGA. Changes to Olivehillplus: - Add SuperIO Fintek F81866D - Soldered down DDR3 with ECC - User can choose between different DDR3 clk settings (lowest setting can save up to 1.2W) - Soldered down Microsemi M2S060 FPGA on PCIe lanes 2-3 Tested with: - Payload SeaBIOS 1.9.1 - Lubuntu 16.04, Kernel 4.4.0 - Windows 10 (UART functionality) Known problems: - S3 not working - IOMMU not working Change-Id: I41f6a3334ad2128695a3f7c0a6444f1678d2626e Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15918 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-30mainboard/bap/ode_e21XX: Add copy of amd/olivehillplusFabian Kunkel
Initial copy of olivehillplus. Change-Id: Ibe9b450c05bfad15a95852addb1465ac2d3cef61 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15917 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-30chromeos mainboards: remove chromeos.aslAaron Durbin
Use the ACPI generator for creating the Chrome OS gpio package. Each mainboard has its own list of Chrome OS gpios that are fed into a helper to generate the ACPI external OIPG package. Additionally, the common chromeos.asl is now conditionally included based on CONFIG_CHROMEOS. Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15909 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-07-30google/reef: Use GPE0_DW1_15 as wake signal for touchpadFurquan Shaikh
Due to GPE routing, raw GPIO cannot be used for indicating the wake signal for touchpad. Instead we need to reference GPE pins. BUG=chrome-os-partner:55670 Change-Id: Ie5d8473df4301c7beef0cae8fe84e71b2838261b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15947 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-28google/gru & kevin: Update DRAM configurationLin Huang
We need to enable DRAM ODT on kevin/gru board to improve the DRAM signal. Note, if the DRAM ODT is enabled and set to 120ohms, the sdram VREF need to adjust to 840mv. This patch also makes following changes: 1. For compatiblity with the old board, add the "sdram-lpddr3-hynix-4GB-666-no-odt.inc" and "sdram-lpddr3-hynix-4GB-800-no-odt.inc" files which do not enable sdram ODT. 2. Delete the 300MHz dram inc file. The 300MHz sdram config just reduced 666MHz to 300MHz based on the 666MHz config file, and it is not stable, so delete it. 3. Delete the 928MHz dram inc file, 928MHz sdram config still in debuging, delete it for now. BRANCH=none BUG=chrome-os-partner:54871 TEST=run "stressapptest -M 1024 -s 1000" on kevin board and pass Change-Id: If0248e1bc4cef2c298762080f1ca018653af0521 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 78d8a28e2d3489c99c9bba2c1c9aa76812e2e33f Original-Change-Id: I35f0685782d6fb178a95780ec77c45f565dd2194 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/358763 Original-Commit-Ready: Dan Shi <dshi@chromium.org> Original-Tested-by: Caesar Wang <wxt@rock-chips.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15813 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-07-28google/reef: Write protect GPIO relative to bank offsetSusendra Selvaraj
Update the write protect GPIO reported in ACPI to GPIO_75. Also update the controller ID to "INT3452:01" which will point at the goldmont device and includes write protect GPIO. BUG=chrome-os-partner:55604 BRANCH=none TEST=verify crossystem output for wpsw_cur. Change-Id: Ibe6a013aaab18bfa2436698298177218ca934fab Signed-off-by: Susendra Selvaraj <susendra.selvaraj@intel.com> Reviewed-on: https://coreboot.intel.com/7929 Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15691 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28skylake/devicetree: Add LPC EC decode rangeSubrata Banik
Define LPC decode ranges for EC communication. BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu to ensure no EC timeout error Change-Id: Idefdd79e67e89a794195c6821fee16550d1eda53 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15898 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28skylake/mainboard: Define mainboard hook in bootblockSubrata Banik
Move mainboard post console init functionality (google_chrome_ec_init & early_gpio programming) from verstage to bootblock. Add chromeos-ec support in bootblock BUG=chrome-os-partner:55357 BRANCH=none TEST=Built and boot kunimitsu till POST code 0x34 Change-Id: I1b912985a0234d103dcf025b1a88094e639d197d Signed-off-by: Barnali Sarkar <barnali.sarkar@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/15786 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-28chromeos: Clean up elog handlingFurquan Shaikh
1. Currenty, boot reason is being added to elog only for some ARM32/ARM64 platforms. Change this so that boot reason is logged by default in elog for all devices which have CHROMEOS selected. 2. Add a new option to select ELOG_WATCHDOG_RESET for the devices that want to add details about watchdog reset in elog. This requires a special region WATCHDOG to be present in the memlayout. 3. Remove calls to elog add boot reason and watchdog reset from mainboards. BUG=chrome-os-partner:55639 Change-Id: I91ff5b158cfd2a0749e7fefc498d8659f7e6aa91 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15897 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28google/urara: Provide dummy implementations of rec/dev functionsFurquan Shaikh
This is required to enable elog support in ChromeOS by default. BUG=chrome-os-partner:55639 Change-Id: I9c97143d794de4bf220ddf67c0ca2eac2f7a326d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15896 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28qualcomm/gale: Add required files to enable elog in ramstageFurquan Shaikh
BUG=chrome-os-partner:55639 Change-Id: Idbad4f8763be18002907a62be755b2fdf7e479ec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15895 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-07-28qualcomm/storm: Add required files to enable elog in ramstageFurquan Shaikh
BUG=chrome-os-partner:55639 Change-Id: Ie859ec3ff682e91a4d7d38d3c3cd6badf7385431 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15894 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-30 08:39:09 +0000