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2020-07-12haswell boards: Fix writes to 16-bit DxxIR registersAngel Pons
The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide, so do not use 32-bit operations to program them. Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so using 32-bit operations on them is correct. Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Drop `struct romstage_params` typeAngel Pons
It only contains a pointer to another struct. Flatten it. Change-Id: Iab427592c332646e032a768719fc380c5794086b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Make `copy_spd` a weak functionAngel Pons
Instead of using function pointers, we can use weak functions. So, drop the pointer from `romstage_params`, leaving `pei_data` as the only remaining member. This will be cleaned up in a follow-up commit. Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-11mb/asrock/b85m_pro4: Reduce Super I/O ACPI codeAngel Pons
We only need ACPI for the PS/2 devices. Plus, the NCT6776 ACPI code makes Windows BSOD with STOP 0xA5 (ACPI_BIOS_ERROR), which is bad. Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42430 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11nb/intel/haswell: Add `mb_late_romstage_setup` functionAngel Pons
This function is called at the end of `romstage_common`. Only one board makes use of it, the Lenovo ThinkPad T440p. To preserve behavior, call it after `romstage_common` has done nearly everything. Change-Id: I35742879e737be4f383a0e36aecc6682fc9df058 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43094 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-11mb/google/beltino: Move Super I/O init to bootblockAngel Pons
Also remove an unneeded `pch_enable_lpc` function call. Change-Id: I83158a655670d4e6cd91f6bf3332d1b6f9f655d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-07-10mb/hp/abm: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I2a97954a36e5af37dc3c379c39afa24030daceea Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-10mb/google/zork: Rename get_gpe_table to variant_gpe_tableRaul E Rangel
This matches the other methods. BUG=b:154756391 TEST=Build trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I6ba1fc5756c17da4dc1727425af17c4582c01a18 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-10mb/google/volteer: remove ripto variantNick Vaccaro
BUG=b:160711124 TEST="FW_NAME=ripto emerge-volteer coreboot chromeos-bootimage" and verify that the build does not fail. Change-Id: Ic132256a192b8cb77662963bea844f193eb912d9 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43227 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-10mb/google/zork: enable i2c devices in verstageMartin Roth
Zork devices shut down the i2c controllers in S3 to save power. On resume, they need to be enabled in verstage before being accessed or the system hangs. BUG=b:160834101 TEST=Resume works with psp_verstage. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I7b8c7e12847876dab4ca74d67d3c41e63d7727cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/43334 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10AMD mainboards: Drop commented-out includeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I6f71419ea23b973b0bedb426e20cb3dc460ef68d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43271 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-10mb/asrock/imb-a180: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I00b3af64b6f842d298e91c20ab5f54f0ca3197ee Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43238 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-10mb/*/Kconfig: Drop spurious warning about disabled boardsAngel Pons
No boards are disabled anymore. Change-Id: Ic8f7bdcc02faa73ce8e647756d40b20a920fc430 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43290 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-10mb/gizmosphere/gizmo2: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Icc3f9a4f71001547ef3d1efe6fc7551b5c690f92 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-10mb/biostar: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I18ddd8a4821d83c038f0a1d17f50247271566e42 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-10mb/amd/olivehill: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ic09b0ee6437766a3ddf126217540f25854a2a562 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-10mb/bap/ode_e20XX: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I9cc4fe7c643458c9d2fa124539a0fd21013ef451 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43233 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09mb/lippert: Align whitespace and commentsAngel Pons
This reduces the diffstat between the two boards. Change-Id: I6754d22139be52c66a9dda5d8e71f1092ecf0697 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43272 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09ACPI: Drop commented-out DSDT DefinitionBlock instancesAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I9b5589d4596eead83a5897b083ccb85ef05a03d5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43270 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09mb/lippert/toucan-af: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Icb59d04c2a8f6ec3b0d1b8b74336c003f521acfe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09mb/lippert/frontrunner-af: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I8836bf05dc84a25640dc63b41e1232d8fb1f50a9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09mb/emulation/qemu-i440fx: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I8781912fe87ee568b7ea6003414c75f255c8cd07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43244 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09mb/emulation/qemu-q35: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I54f3fe0d3b0c988ab6f9065bea81a385507e9747 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09mb/aopen/dxplplusu: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I3f9b31a2bfb85ceb9ff833c076e062291c944923 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43242 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09mb/intel/glkrvp: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I6948a0b9a6b699cb44e3e02d9e134180bac2fa14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-09mb/asrock/b85m_pro4: Add Super I/O GPIO tableAngel Pons
Information taken from the boardviews. We are not configuring any GPIO in bootblock, but we may want to do so in the future. Change-Id: Iac16f02490adcccd9486718847ca2b1a47f4e6cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42404 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09mb/asrock/b85m_pro4: Properly select muxed functionsAngel Pons
The old values were completely out of whack. Use the same settings as vendor firmware. The SUPERIO_NUVOTON_NCT6776_COM_A option overwrites configured settings, so drop it from Kconfig to prevent conflicts. Change-Id: I9743741518adc153d594ccae65298c7dcc8a88d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-09haswell: Drop GPIO indirection layersAngel Pons
This simplifies things and makes type checking possible. Change-Id: Iefc9baabae286aac2f2c46853adf1f6edf01586f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09mb/google/slippy: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: Iec6dac1a271b22d6c09b4064a9e8a310e57026a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09mb/google/beltino: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: I536225351a0353298381c16cff25f39098c19bba Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09haswell: Turn RCBA configuration into a functionAngel Pons
Instead of passing around a pointer to an array, just write the relevant registers directly. Note that intel/baskingridge used spaces to indent line continuations and had to be replaced with tabs to quell Jenkins. Change-Id: Ifa06a2ab24da9b8c6aac6480542fa32d04f6d6fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43097 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-09mb/siemens/mc_apl1: Use OPCODE menu set up of fast SPI driverWerner Zeh
The common fast SPI driver has a function to set up the SPI OPCODE menu. Use this function here instead of coding it again as it results in the very same register values being written. TEST=Compare register values in both cases and make sure they match. Change-Id: I98457a0b0652f746734ee4204e10acd09b6e5fda Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43166 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: <uwe.poeche@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-09mb/lenovo/t440p/romstage.c: Drop empty functionAngel Pons
There's a weak definition in chipset code that does nothing as well. Change-Id: I2531e8b9d48eb4a1a667f22a81bb082ec98c1199 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43297 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-09soc/intel/baytrail: Rename "pmc.h" to "pm.h"Angel Pons
This reduces the differences between Bay Trail and Braswell. Tested with BUILD_TIMELESS=1, Google Ninja remains identical. Change-Id: I3d4c1285bdc4b061383b7bb6262f69671166b9c4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43185 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-07-09mainboard/intel/tglrvp: Remove unused PrmrrSize chip configSubrata Banik
Refer to commit 7736bfc TEST=Able to build and boot TGLRVP. Change-Id: Ie9a97cee7d7793077167db3a642dcbca45b09427 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43139 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Do not select VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for VilbozFurquan Shaikh
This change drops the selection of VARIANT_SUPPORTS_PRE_V3_SCHEMATICS for Vilboz since it did not have any build with pre-v3 schematics. Change-Id: I3919ad43e1dae95a4fa71073e83865e92f30dfec Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43225 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Add helpers for v3 schematics and wifi power enableFurquan Shaikh
This change adds following two helper functions: 1. variant_uses_v3_schematics() - Check whether the variant is using v3 version of schematics. 2. variant_has_active_low_wifi_power() - Check whether the variant is using active low power enable for WiFi. In addition to this, Kconfig options are reorganized to add two new configs - VARIANT_SUPPORTS_PRE_V3_SCHEMATICS and VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. This allows the helper functions to return `true` early without checking for board version. Eventually, when a variant decides to drop support for pre-v3 schematics, it can be dropped from selecting VARIANT_SUPPORTS_PRE_V3_SCHEMATICS. Similarly, when the variant decides to drop support for active high power enable for WiFi, it can be dropped from selecting VARIANT_SUPPORTS_WIFI_POWER_ACTIVE_HIGH. Change-Id: I62851299e8dd7929a8e1e9a287389abd71c7706c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43224 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Move GPIO_137 configuration to ramstageFurquan Shaikh
This change moves the configuration of GPIO_137 to happen in ramstage since there is nothing in coreboot that requires the state of write protect GPIO for zork. Change-Id: Ibaf8e7d9dd5d13a9b39b10ac0174de345b8380f5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/google/zork: Do not share "write protect" information with depthchargeFurquan Shaikh
This change removes "write protect" entry from the list of GPIOs shared with depthcharge as done for other Chrome OS boards in CB:39318. Change-Id: Ibd39e8d6835e465b2ab5eebcc245e45db5d84deb Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43222 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Disable PS/2 keyboard wakeupAngel Pons
This results in a wake from S5 as well. Since the PS/2 keyboard now works, this behavior is annoying and, therefore, undesired. Change-Id: I180f17c87df23f2a1bbd5c968c64a4b2bc7d9978 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42431 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Correct GP01 output levelAngel Pons
This allows the CPU fan tach signal to reach the Super I/O. Change-Id: Ibf73d7c7c1951b75ee4e0c731caf951f2c6bfcae Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42402 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Add missing HWM IRQ on devicetreeAngel Pons
Otherwise, there are complaints about it from the allocator. Change-Id: Ibf6124c3720959154d0b9649871f9bf68a912f14 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42401 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Correct Super I/O GPIOsAngel Pons
GPIO2 is not used as such, GPIO7 is though. Also relocate GPIO1 settings under the correct PnP device. Confirmed findings against boardviews. Change-Id: I4a88ac82d640ca709e7875b4d34b9babb1f2e0a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42400 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Expand Super I/O commentsAngel Pons
Change-Id: I03ca67d748725283ba8382e476d70eb5554f5fb8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42399 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Correct PS/2 keyboard IRQAngel Pons
No wonder why the PS/2 keyboard was being detected as a mouse! Change-Id: I7080c8210d96b079a5c08d98554ed154141086a6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42398 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asrock/b85m_pro4: Drop spurious LPC decode rangesAngel Pons
Only one generic decode range is needed for the HWM. Change-Id: I964a073efbfaa1d79d3483d59ad04fe674bcb275 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42131 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/asus/p8z77-v_lx2: Correct Super I/O GPIO settingsAngel Pons
Compared against superiotool dumps with vendor firmware. Still boots. Change-Id: I49f36b2805e36695d7a53865e87dfafdb897594e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42482 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/intel/baskingridge: Put GPIOs in a C fileAngel Pons
This will allow dropping the pointer inside romstage_params. Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08sb/intel/lynxpoint: Factor out RCBA Function DisableAngel Pons
Comments stating that this was mainboard-specific were very wrong. Change-Id: I7026ca9c7dabd01b4a0c0549b697e006d5f75eb8 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43096 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-08mb/google/slippy: Factor out common romstage settingsAngel Pons
There's no need to repeat the same values over four variants. Change-Id: Ifc4a9961fe9c87f15a6039e6e478682fab5b0bb7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43039 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-08mb/google/zork: Enable psp_verstageMartin Roth
Finally enable psp_verstage for zork. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If6a12c2074d7c84c0cb766393c66f5eff29a58d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42226 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2020-07-08mb/google/waddledee: Enable AudioMaulik V Vaghela
1. Enable HDA Pci device in devicetree 2. Enable I2C4 in devicetree and fill ACPI information 3. Pass correct IRQ GPIO for headset jack BUG=None BRANCH=None TEST=Audio playback and recording works on Waddledee. Change-Id: I77aaa27bb29460ef834c3dd090ced868f2e99616 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Yong Zhi <yong.zhi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41765 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-08mb/ocp/deltalake: Enable LPC IO 0x600 decode for BICBryant Ou
BIC uses LPCflash utility to flash FW, it uses LPC to send the bridge IC image from host to bridge IC, 0x600 ~ 0x6FF is used to send BIC image for in-band update support. TEST=Use LPCflash utility to flash BIC FW on YV3 successfully. [root@localhost lpcflash_101_bin]# ./lpc_update.sh Y3BRDL_D06.bin Update Bridge IC Firmware from LPC Deltalake linux utility ver:1.01 build time: Feb 11 2020 14:30:55 Processing image file: Y3BRDL_D06.bin .. of size 206968 (0x00032878) bytes .. file will be padded to a 64-byte size .. with DEBUG Enabled Generating CRC-32 for file. Done (0x4e3905a3). iBytesRead (0x00007c00). Discovering LPC boot loader. Discovered @ 0x3f8. Configuring LPC boot loader. Configured @ 0x00000600. Sending header block. Sent. Loading firmware into target. Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 31744 bytes ............................... Sending 16512 bytes ................. Load complete. Update done! Signed-off-by: Bryant Ou <Bryant.Ou.Q@gmail.com> Change-Id: Ia1ea9b35b154225fdfd8955830e6c42b453a81ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/42856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/google/dedede/var/drawcia: add elan touchscreenWisley Chen
BUG=b:155002684 TEST=build drawcia, and check touchscreen can work Change-Id: Ib6a190d2f6fc5132af0e58c6df9919381e88f699 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-08mb/ocp/deltalake: Configure IPMI FRB2 watchdog timer via VPD variables in ↵Johnny Lin
romstage Add VPD variables for enabling/disabling FRB2 watchdog timer and setting the timer countdown value. By default it would start the timer and trigger hard reset when it's expired. The timer is expected to be stopped later by payload or OS. Tested on OCP Delta Lake. Change-Id: I3ce3bdc24a41d27eb1877655b3148ba02f7f5497 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-08mb/ocp/deltalake: Update IIO PCIe bifurcation according to different configsJohnny Lin
In romstage get the config from BMC IPMI and update the IIO accordingly. Tested on OCP Delta Lake with FSP WW24 release, with lspci checking bifurcation register values are expected. Change-Id: I412336c32d093fe2bbdc7175f8e596923c77876f Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41527 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-08mb/google/dedede/var/drawcia: Support Elan touchpadWisley Chen
BUG=b:155002811 TEST=build drawcia, and check touchpad can work. Change-Id: I674236aa6937a0444a85e6b8e2fb9a7925b56f5c Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42922 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07google/trogdor: Add new variant PompomJulius Werner
This patch adds a new variant called Pompom that is identical to Lazor for now. Also reorder variants alphabetically while we're here. Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I5a0f297413765bce8353d5a781f0f67446de4e7c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2020-07-07vendorcode/intel/fsp/fsp2_0/cpx_sp: Update to FSP ww26 release and adapt socJonathan Zhang
CPX-SP FSP ww26 release added UPDs to allow FSP serial redirection. Also update memory map HOB definition file accordingly. The CPX-SP soc code is updated to direct FSP log to SOL. Signed-off-by: Jonathan Zhang <jonzhang@fb.com> Change-Id: Ifd86fb710a0b2bdc8a43225b50b24f585d320caf Reviewed-on: https://review.coreboot.org/c/coreboot/+/42840 Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/lenovo/t60: Fix override devicetreesNico Huber
When converting to override trees in commit c1dc2d5e68 (mb/lenovo/t60: Switch to override tree), some device nodes were missed. These are essential, as `chip` configuration data is always tied to device nodes. The resulting `static.c` contained multiple copies of the `chip` configuration structs, but the wrong ones were hooked up. The therefore missing configuration of the clock gen led to general instability, especially with SMP under Linux (probably due to the attempt to enter lower C states on an idle core). Passing `maxcpus=1` to the Linux kernel served as a workaround. Change-Id: I6c26d633d1860cf9a5415994444e75ae1c2e59ad Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43150 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/vilboz: Drop gpio.c from variants/vilbozPeichao Wang
Update GPIOs since Vilboz hardware design follow schematic V3.2, so gpio.c is unnecessary. BUG=b:157744136 BRANCH=NONE TEST=flash the bios to vilboz DUT and test touchpad function Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I575f8b233b56185f3281ad7127bc274bda5ea801 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42986 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/vilboz: Fix variant ID for v3+ schematics for vilbozPeichao Wang
At this moment, Vilboz board version is 1 and it according to v3+ schematics, however WiFi power enable is active high. This change sets VARIANT_MIN_BOARD_ID_V3_SCHEMATICS for Vilboz as 1 and VARIANT_MIN_BOARD_ID_WIFI_POWER_ACTIVE_LOW as 2. BUG=b:160547115 BRANCH=None TEST=flash the bios to vilboz DUT and test WIFI module Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I9699bb839a801ab7d14c38b971ec28e3a322a997 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-07mb/intel/tglrvp: Add PMC.MUX.CONx devices to devicetree for tglrvp_up3John Zhao
Two usb Type-C ports under the actual mux device. Each port has its own ACPI device entry. These nodes are the ones that the USB Type-C port/connector device will refer to in order to configure the mux. TEST=Verified the scope of PMC.MUX CONx in the SSDT on Tigerlake RVP board. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I7210e00cebe16a5fb8417ac23abad98e574e0982 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42953 Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer: Change ov2740 HID of Chrome driver to match withDaniel Kang
Windows definition There was a review comment for Chromium Linux ov2740 driver that Windows driver already set the HID as INT3474 and suggested to have the same value for Chrome. The upstreamed Linux driver code has INT3474 as HID and this patch is to set the same HID in ACPI configuration. https://patchwork.kernel.org/patch/11540753/ BUG=b:160334865 BRANCH=none TEST=User-facing camera should work with the driver which set the HID as INT3474 Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I10e98d32899f31d91c1cc7ddfa099af73d8aef37 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43006 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer: Fix world-facing camera LED is always on issueDaniel Kang
Volteer world-facing camera has a privacy LED and it is supposed to be turned on only when the camera is being used. But the LED is always on and this is to fix the issue. RCAM_SNR_PWR_EN (RearCAMera_SeNsoR_PoWeR_ENable) GPIO, which controls the world-facing camera LED, was not in the power-up and power-down sequence definitions and this caused the issue. BUG=b:160341981 BRANCH=none TEST=Build and boot volteer proto 2 board. Start a camera app and check the world-facing camera LED is only turned on only when the camera is working. Signed-off-by: Daniel Kang <daniel.h.kang@intel.com> Change-Id: I564690baffddfdd0f998525992643aaf16ba4b02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42985 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Daniel H Kang <daniel.h.kang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/zork: update telemetry settings for dalbozChris Wang
update telemetry value for SDLE test result. BUG=b:152922299,b:152369472 TEST=emerge-zork coreboot Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I14d218243931271ba15ec4113e9bc46c670fb2ca Reviewed-on: https://review.coreboot.org/c/coreboot/+/42999 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer/var/terrador: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of terrador, generate gpio settings and overridetree.cb for terrador. BUG=b:156435028,b:151978872 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Verify that the image-terrador.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I4bf9081b034bc4cd566dde45586be8309cdbb4a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42302 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-07mb/google/volteer/var/terrador: Add memory parts and generate DRAM IDsDavid Wu
This change adds memory parts used by variant terrador to mem_list_variant.txt and generates DRAM IDs allocated to these parts. Added memory 1. MT53E512M64D4NW-046 WT:E 2. MT53E1G64D8NW-046 WT:E BUG=b:159195585,b:152936481,b:156435028 TEST="emerge-volteer coreboot chromeos-bootimage", flash terrador and verify terrador boots to kernel. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia14f76e9cb0df64961d46f4b61b39439e56f6a8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41995 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06trogdor: Add board variant checks in KconfigRavi Kumar Bokka
Diffentiate Lazor and trogdor build configuration Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Change-Id: I3ad413ea6e658e939796bebdff8c1e0dd76417cc Reviewed-on: https://review.coreboot.org/c/coreboot/+/42730 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer: Enable HotPlug on PCIe root port for the SD expressnick_xr_chen
Enable HotPlug for the PCIe root port that the SD express is on so the OS can re-train the link without needing a reboot if it goes down unexpectedly at runtime. BUG=b:156879564 BRANCH=master TEST=enable HotPlug on Volteer Root Port 7 (SD express) and check in linux that it is identified as a HotPlug capable root port Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: Ie9d427dd297567f06123119a670b5ed2e1f73701 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42897 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/amd/mandolin: Drop SPD eeproms in devicetreeKyösti Mälkki
Even with previous platforms, these entries were not utilised for raminit. Change-Id: I9a9a1a292bad8c4c89cbacb826c80f4098cae00f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43046 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-07-06mb/google/volteer: Rename remaining pmc_mux/con to connPatrick Georgi
CB:43090 renamed con to conn to avoid issues when building on Windows. CB:42905 introduced more uses of the old name. Adapt the latter to comply with the former. Change-Id: I723141add5452fc541f67cb8591793f2d64cc231 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43141 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/asus/p8z77-m_pro: Remove PS/2 keyboard & mouse duplicateKeith Hui
PS/2 keyboard and mouse devices are declared twice in the DSDT, once in mainboard and once in southbridge. It would appear in Windows Device Manager as two PS/2 keyboards and two PS/2 mouses, all with resource conflicts. This change drops the declaration from mainboard. The issue was discovered when this setup was copied for p8z77-m and being boot tested. Change-Id: I746a960aaf3992acbcb6a7364641fc4fd12002d2 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41225 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/intel/dg43gt: Don't redefine MMCONF_BASE_ADDRESSArthur Heymans
Change-Id: I4d62a04778c8f634b48eee459808f640451b9b48 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35871 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-07-06mb/google/volteer/var/voxel: Update gpio settings and overridetree.cbDavid Wu
Based on schematic and gpio table of voxel, generate gpio settings and overridetree.cb for voxel. BUG=b:157879197,b:155062762 TEST=FW_NAME=voxel emerge-volteer coreboot chromeos-bootimage Verify that the image-voxel.bin is generated successfully. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I49c1923e63d87f11de362fd893905ac2f1137bba Reviewed-on: https://review.coreboot.org/c/coreboot/+/42731 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-06mb/google/zork: Apply cereme telemetry settings for dalbozChris Wang
Currently, the telemetry settings are not for the pollock platform and might causethe power and performance issue. so applied the Pollock reference board settings to Dalboz to improve the performance, and the values need to be updated after the SDLE test finished. BUG=b:157961590,b:152922299 TEST=Build. Change-Id: I0da5b81afaa5814c13ec0257dc0eb3471be94c29 Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2228257 Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42998 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/zork: Apply USB2 default phy tune parameter for Zork familyChris Wang
Apply the default USB2 phy tuning parameter for Zork family BUG=b:155132211 TEST=Build, verified the default value been applied on trembyle and the USB2 device works well. Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com> Change-Id: I1f00b04173796d70147e232bafa405487b0761e1 Reviewed-on: https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/+/2260216 Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42997 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-06mb/google/volteer: Add support for passive USB-C daughterboardCaveh Jalali
The USB-C SBU and HSL orientation configuration depends on the USB daughterboard used on the system. This patch adds an additional configuration for supporting passive USB daughterboards using "probe" directives to select the appropriate configuration at runtime. BUG=b:158673460 TEST=verified active USB DBs enumerate at USB3 speeds in linux Signed-off-by: Caveh Jalali <caveh@chromium.org> Change-Id: Ia4bd97de8f974531f97469a5e47ecf4d948beca9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-06mb/google/dedede: Create Boten Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of boten will use 16 MiB SPI ROM. So create a legacy Boten variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the boten and boten_legacy variant. Cq-Depend: TBD Change-Id: Idf7732768aa7fbf2281a4cbf47b7b5b4f8ef51da Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-06mb/google/dedede: Create Drawcia Legacy variantKarthikeyan Ramasubramanian
Upcoming builds of drawcia will use 16 MiB SPI ROM. So create a legacy Drawcia variant to support the builds that use 32 MiB SPI ROM. BUG=None TEST=Build the drawcia and drawcia_legacy variant. Cq-Depend: TBD Change-Id: Ifb5a4778abe38a396e35963a3270b0d3cc9809e0 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42960 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-07-05mb/google/zork: Drop check for ENV_RAMSTAGE in mainboard_ec_initFurquan Shaikh
This change drops the check for ENV_RAMSTAGE in mainboard_ec_init() since it is included only in ramstage. Also, the content of ramstage_ec_init() is moved into mainboard_ec_init(). Change-Id: I282fb07a80f4de6064a544f6dd58e8f973a597b9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43118 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop mainboard_ec_init() from romstageFurquan Shaikh
mainboard_ec_init() does nothing in any stage other than ramstage. So, this change drops the call to mainboard_ec_init() from romstage.c. Additionally, it also drops ec.c from romstage and verstage. Change-Id: Iae0be4d678b0780cf532000a6c0fff1bce333c0e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43117 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Drop unused function variant_romstage_entry()Furquan Shaikh
This change drops the function `variant_romstage_entry()` which is unused on zork. Change-Id: I140ab3e837971c4c7dbef5d27616043b5fc6c2c9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43116 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/zork: Use SSDT generator for Chrome EC audio codec deviceFurquan Shaikh
This change drops the inclusion of codec.asl in DSDT for `GOOG0013` device and instead uses the newly added Chrome EC audio codec driver for filling in the device node in SSDT. TEST=Verified that following node gets generated: Scope (\_SB.PCI0.LPCB.EC0.CREC) { Device (ECA0) { Name (_HID, "GOOG0013") // _HID: Hardware ID Name (_UID, One) // _UID: Unique ID Name (_DDN, "Cros EC audio codec") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } } } Change-Id: I3e626ce01a3735ac2c966c0e95310be4c828b241 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43042 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/kahlee: Drop macro H1_PCH_INTFurquan Shaikh
This change drops H1_PCH_INT macro for GPIO_9 since it is the same across all variants. Also, the name differed from the schematics version `H1_PCH_INT_ODL` creating confusion. Change-Id: I7b038426a984d8abc460a0da3ee1dc5559d7ad5f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-07-05mb/supermicro/x9scl: Select IPMI_KCSAngel Pons
Needed for `chip drivers/ipmi` in the devicetree. Change-Id: Ice70aab7cedaeb91a33dd90d763c5a487f190b8f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41687 Reviewed-by: Michael Niewöhner Reviewed-by: Jonathan Kollasch <jakllsch@kollasch.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/lenovo/x230s: Add MAINBOARD_HAS_LPC_TPMKyösti Mälkki
With devicetree listing drivers/pc80/tpm, it is compulsory to have the corresponding driver included in the build. Followup work will drop the associated weak function declaration that util/sconfig currently generates. Change-Id: Ife8deb2c973ab7c7b820244b6f72efd3b56570ae Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43047 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-05mb/google/poppy-nocturne: Add SX9310 driver unconditionallyKyösti Mälkki
Change-Id: I11b02cc5f8b59559443329fe0c49a6fb82b7862a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41726 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04drivers/intel/pmc_mux: Rename con driver to connTim Wawrzynczak
For historical reasons, Windows has issues with certain names being used for files and directories, 'con' or 'CON' being one of them. Therefore, rename the pmc_mux/con driver to pmc_mux/conn in order to work around this issue. TEST=built volteer (only user of this driver as of now) Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ia78dc4efe647c96a7169a3b95fc3b8944d052c83 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-04mb/ocp/deltalake: Add VPD flash regions and select VPD and VPD_SMBIOS_VERSIONJohnny Lin
Tested on OCP Delta Lake. Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Change-Id: I1e6e2bd25cbe3b0c0547dda9e457c4d55df28388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42428 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-04mb/ocp/deltalake: Update SMBIOS type 2 Location In Chassis from BMCJohnny Lin
There are 4 slots in YV3, Location In Chassis should be 1~4. Tested=on OCP Delta Lake, dmidecode -t 2 verified the string is correct. Change-Id: I3b65ecc6f6421d85d1cb890c522be4787362a01b Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-07-04mb/ocp/deltalake: Populate SMBIOS data and set the read PPIN to BMCJohnny Lin
1. Populate SMBIOS data from OCP_DMI driver read from FRU and PPIN MSR for OEM string 1 to 6, add string 8 for PCIE configuration. 2. Set the read PPIN MSR to BMC. Tested on OCP Delta Lake. Change-Id: I9127cf5da1c56d8012694d070615aec24cc22fdf Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41279 Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/volteer: Enable CSE Lite SKU for ES2 platformsJamie Ryu
BUG=b:158140797 TEST=build and boot volteer with CSE Lite SKU Cq-Depend: chrome-internal:3100721 Change-Id: I4f939883617a1271b30c76d41e61113bbdd6ab5b Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42070 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/zork: adjust eSPI virtual irq settingsAaron Durbin
The eSPI polarity macros were reversed. Those are fixed so adjust the corresponding values related to the correct expectations of the IRQ path: eSPI virtual wire IRQs are active level high. The EC sends active level high virtual wire IRQs. The default interrupt encodings in ACPI for P2/S devices are active edge high. Therefore, there is no need to override anything. BUG=b:157984427 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Change-Id: Ia28d82cd9e432df98839f68bac4eae4447455e53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-03mb/intel/cannonlake_rvp: Unconditionally select audio driversKyösti Mälkki
Change-Id: Ic9f2e44692b20c2efabc468b10ec531e8b5a3e59 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41706 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/intel/coffeelake_rvp: Unconditionally select audio driversKyösti Mälkki
Change-Id: I3fad7cb2ac0b88adbe75acfa7a17f5a9b0bde6c2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41705 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/intel/icelake_rvp,jasperlake_rvp: Select DRIVERS_SPI_ACPIKyösti Mälkki
Change-Id: If25ed7b5cc545abcbf16af66173058dde75260f7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41703 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in WyvernEdward O'Callaghan
V.2: Spare USB routed internally to another peripheral and so no plug event hook needed. BUG=b:1603699358,b:157479891 BRANCH=none TEST=none Change-Id: Ideacac417a46b96f3e82b53bbb341ecce79ee420 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42994 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in NoibatEdward O'Callaghan
BUG=b:160296662 BRANCH=none TEST=none Change-Id: I5298e1779461995a98722099b397692351767089 Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42975 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-03mb/google/hatch: Allow USB2/3 wakeups to (un)plug events in FaffyEdward O'Callaghan
BUG=b:160295948 BRANCH=none TEST=none Change-Id: I3600340d3448457942c827a463b458b280fea19a Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sam McNally <sammc@google.com>
generated by cgit v1.2.3 (git 2.39.1) at 2024-07-17 09:09:29 +0000