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Change-Id: I6a9d71e69ed9230b92f0f330875515a5df29fc06
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29312
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Variants of Nami need to accommodate single channel DDR. Will use
GPP_D10 on nami for identification. GPP_D10 will return 1 when device
is using single channel DDR and 0 when using dual channel DDR.
BUG=b:117194353
BRANCH=None
TEST=dmidecode | grep Channel and make sure that the correct number of
channels gets returned.
Change-Id: If86ab2c5404c4e818ce496ea935227ab5e51730a
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/29233
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Looks like we must do it in the same way as in l520, t420, t420s,
t430s, t520, t530, x201, x220, x230 models. No idea why t430 should be
handled differently.
Change-Id: Ic4851022267caca267b667b4e3c327838e0a0b66
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29031
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Apply commit 12d681b2 (intel/i945 gm45: Use acpi_s3_resume_allowed())
also to the Lenovo T400.
See also commit 42ae0bae with Change-Id
I4e1e0ccf2abbe175c0e5ddcbb6ee7bf6afb1ae88 (mb/lenovo/x200: Use
acpi_s3_resume_allowed())
Change-Id: I9d4ac711375977a979a8b3e5606e2197847e88de
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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Move the usage instructions from their ad-hoc place in Kconfig.name to
the Documentation directory, and expand them a bit.
Change-Id: Id6c7bbca40a21ecba00cab736af2f2662a985106
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28874
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Philipp Hug <philipp@hug.cx>
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Linking should allow to link depending on possible future variants.
E.g. in Makefile.inc romstage-$(CONFIG_'VARIANT0') += gpio_variant0.c
etc.
This commit follows up on commit 7dee9745 with Change-Id
I88b5ef8e12ac606751952a493f626e1b146e98f7 ("mb/lenovo/x201: Link gpio
map instead of including a header").
Change-Id: Ibdb96deafbe422bf50fd2e1fc56a57ae53ccd5a0
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29286
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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IGD display handling was rewritten with commit dd2bc3f8 with Change-Id
I556769e5e28b83e7465e3db689e26c8c0ab44757 ("igd.asl rewrite"). These
comments were removed as well (with some accidentally left behind).
Let's remove them and those who were introduced later with new ports.
Change-Id: I8d3e12d0c3b03b0de38e65f36b94ed706fbf893c
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29271
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These ifdefs are the remains from the following commits:
* fa1d688a with Change-Id I9909a5b2bdb4b59219db6304fa4332802fe0301c
("sandy/ivy native: dedup romstage.c main()")
* 7dee9745 with Change-Id I88b5ef8e12ac606751952a493f626e1b146e98f7
("mb/lenovo/x201: Link gpio map instead of including a header")
Change-Id: If83189688151f531a05780a87db3409cbacfbeff
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29283
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Clone entirely from mainboard/intel/cannonlake_rvp
commit id: af89f49b83260a04dece84b34e97560fb85d29ae
List of changes on top off initial cannonlake_rvp clone
1. Rename "Cannonlake" with "Icelake".
2. Replace "cannonlake_rvp" with "icelake_rvp".
3. Rename "cnl" with "icl".
4. Remove unwanted SPD file, will add correct SPD with mainboard
patches.
5. Remove NHLT related implementation.
6. Remove FSP configs, will add once FSP headers are available.
7. Removed smihandler.c, will add later if needed.
Change-Id: I875972d1fb2f630bf5eb29bd955c484e7f9aa415
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Signed-off-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-on: https://review.coreboot.org/29164
Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In function write_pirq_routing_table(), the function name is used in a print
string. Use __func__ instead.
BUG=b:117642170
TEST=Build grunt.
Change-Id: Ibf8673c5b2cda1105aae1edb46f6589d55208c50
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29245
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Add a new variant of fizz for the kalista board.
Key differences from baseboard include:
- GPIO changes
- devicetree.cb changes
BUG=b:117066935
BRANCH=master
TEST=Build (as initial setup)
Change-Id: I808c5e0883049575cbedd181c249a78a833fa96a
Signed-off-by: David Wu <David_Wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29205
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change enables override device tree for Fizz to allow variants to
provide their own overrides and also moves I2C5 realtek node to
fizz/overridetree.cb since it doesn't apply to some variants being
added for Fizz.
Change-Id: Ia1a069fc539b51a22882ef94b55baf5bf7cd302f
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29242
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
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Get recovery mode switch from EC and pass it to payload.
BUG=b:80501386
BRANCH=none
Test: Boots correctly on Kukui.
Change-Id: Ib92afca885e5a97ec4646f55f2279ef56a61af5a
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/29190
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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Liara auto restart issue is caused by memory access error and consequent
kernel panic. To solve this issue, revert the CL:1243666 (Disable
NbP-state on Liara) and use 2T mode instead.
BUG=b:116082728
TEST=verify the 2T mode is enabled/boot into ChromeOS and no auto restart/run
memtester passed 10 cycle.
Change-Id: I3a96276d88ffb70530d72b15c07b59a01cc6209a
Signed-off-by: Chris Wang <chris.wang@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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1. Update PSV values for cpu and sensers.
2. Change PL1 min value from 3w to 4.5w.
3. Change TSR2 TRT source from charger to CPU.
Refer to 112448519#comment31.
BUG=b:112448519
TEST=Build coreboot for Octopus board
Change-Id: I7c7df0f54374fdaa4cf57d5c255d841d7db38cfc
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This change uses CRFP ACPI name for FP device since user space
utilities expect this name for triggering different actions.
BUG=b:112974410
BRANCH=nocturne
Change-Id: I63309227c916b43917e529c223cf738fc3baa209
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29231
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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On rammus, set GPIO GPP_C22 to 1 for touchscreen power on.
And add touchscreen device "PNP0C50" to I2C0.
According to touchscreen spec, device power on initialization takes
105 ms, so set "generic.enable_delay_ms" to 120.
We found there is i2c error log pop up when we set delay
time to be 110ms or 105ms. If we set delay time to be
120ms. System will not pop up i2c error log.
BUG=b:115944726
BRANCH=master
TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage
Flash FW to DUT, and make sure touchscreen works.
Change-Id: Ibce552d04991e85c99ae3a0a92455fc747d9fced
Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This change uses DIMM_INFO_PART_NUMBER_SIZE to decide the size of
part_num_store that holds the number of DRAM part. It ensures that
host advertises the supported size to read part number from the EC.
BUG=b:115697578
Change-Id: I8439a301fc037b0acdc8b1226ad04d2f363838ef
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Jett Rink <jettrink@chromium.org>
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Before entering the OS, the AP relies on the smi handler to shutdown the
system when the lid closes. Without the smi_events setting, the AP will
not receive the smi handler. As a result, the AP won't shutdown and will
always keep in S0.
This problem is caused by the https://review.coreboot.org/c/coreboot/+/28983
and this patch adds the smi_events back to support the smi handler for
the lid close.
BRANCH=master
BUG=b:115572596
TEST=test_that -b ${BOARD} ${IP} firmware_ECLidShutdown
Change-Id: Id82311a8ccd109f9c26516f59a45bdf34da98529
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/29191
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Change-Id: I6c77f4289b46646872731ef9c20dc115f0cf876d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29161
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The file soc/amd/stoneyridge/acpi/smbus.asl has 0 bytes (no content). Remove
the include of this file.
BUG=b:117814641
TEST=Build grunt and gardenia.
Change-Id: I0c48167195a9708afc255490bb1996b6dfc7bdfb
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29178
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This change uses the newly added macros for configuring the same GPI
pad(GPIO_135) for IRQ (normal interrupt operations) and
wake (interrupt for waking from S3/S0ix) for the trackpad device. The
other pad GPIO_142 is now configured as not connected.
BUG=b:117553222
TEST=Verified that yorp and bobba wake from S3 and S0ix using
trackpad.
Change-Id: I2b704f1be493141629c647b79723b0025b0f7dd6
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29189
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change link frequency of IMX319 from 360Mhz to 482.4 Mhz to match the
changes from kernel driver. IMX319 has two PLLs and it can be configured
either single or dual. Previous driver implemente dual PLL mode, however
image sensor vendor prefer single PLL mode and calculate the pixel rate
became easier. So the kernel driver changed to use single pll, coreboot
change will match that.
Bug=b:116082248
Change-Id: Iac9a72253e0529bf2c0785fb701b7bc251bcbab5
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/28736
Reviewed-by: Tomasz Figa <tfiga@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This is a cosmetic one. It just removes some board names from comments
since these functions sometimes are very similar, so no need to add
extra difference between them.
Change-Id: I26b9296b402d98bcf048580da51da7bbb0c237e4
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29180
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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We didn't have a hard_reset() implementation for these boards. So
select the board_reset() stub for them.
Change-Id: I77651e3844632fb1a347008c96e53d23cc5a2646
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29170
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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And here comes the mess...
This just renames do_hard_reset() to do_board_reset() and keeps current
behaviour. As these are never called from chipset or board code but only
from common code, it's likely that their implementations are untested
and not what we actually want. Also note, that sometimes implementations
for rom- and ramstage differ considerably.
Change-Id: Icdf55ed1a0e0294933f61749a37da2ced01da61c
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29058
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SOUTHBRIDGE_INTEL_COMMON_RESET for all Intel platforms that used to
perform a "system reset" in their hard_reset() implementation. Replace
all duplicate CF9 reset implementations for these platforms.
Change-Id: I8e359b0c4d5a1060edd0940d24c2f78dfed8a590
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Id07e1c7fbd35393ffafda53fc7a15ec0e157d075
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29049
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Change-Id: I6182da172ae2f4107a9b5d8190e4b3b10ed2f0b9
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/29048
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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This change udpates FMAP to wrap MRC training data in RW_PRESERVE
section so that we don't lose the data when performing full firmware
updates on octopus.
BUG=b:117882029
TEST=Verified that chromeos-firmwareupdate doing full firmware update
preserves training data on octopus.
Change-Id: I5adb9bfa926327057b003360150685a8b4778c8c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/29183
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Move current NHLT configuration implementation to baseboard so that
variants can leverage it or provide their own configuration.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I30d93babb6fc09e8642b3740f1f7638fa33f0ade
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add support for ChromeOS GPIO ACPI table information by providing weak
implementation from the baseboard.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I2fa52c005cacdbcc322d107a3ac92d22df3f3697
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28964
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Provide API for gpio table functionality. Default weak
implementations are provided from the baseboard.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: Iaafa8d6932bc0a37826175b15816f1b9a4f4c314
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28963
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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In order to be able to share code across different fizz variants,
provide the concept of baseboard and variants. New directory layout:
variants/baseboard - code
variants/baseboard/include/baseboard - headers
variants/fizz - code
variants/fizz/include/variant - headers
New boards would then add themselves under their board name within
"variants" directory.
This is purely an organizational change.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
CQ-DEPEND=CL:1273514
Change-Id: I28cc41681e7af88ddeba2e847dc0a4686606feb2
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28962
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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I didn't change the offsets of all the other regions because I didn't
want to cause all dogfood devices to lose their corp enrollment.
BUG=b:117797131, b:117798830
BRANCH=none
TEST=Ran autotest and made sure the tests were skipped
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache [ PASSED ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal [ PASSED ]
/tmp/test_that_results_2OZ90v/results-1-firmware_CorruptRecoveryCache/firmware_CorruptRecoveryCache.normal TEST_NA: No RECOVERY_MRC_CACHE was found on DUT.
Change-Id: I5cdbf4139dde80fe6e9d0045139a97841b03bc42
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Reviewed-on: https://review.coreboot.org/29171
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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this patch adds following changes
- Select config to initialize codecs in common HDA driver.
- Add audio verb table for coffee lake RVP11 & RVP8.
BUG: None
TEST: boot to yocto linux and windows os on CFL RVP11 & RVP8. verified audio
playback and record functionality over anolog audio jack & HDMI display.
Change-Id: I567e317c0e9ac9f91e159866c7f896e4c101712b
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29067
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Change-Id: Ib359e4039f87bb87faac040f24f70cc0988c0ea8
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibf23f49e7864c611a3cb32a91891b6023a692e1d
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ibc928dc66e00dbb40d25420fd92f6c5f8049dec1
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28703
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds.
Use frequency as a proxy to determine SKU. The E3805, E3815,
E3825, and E3826 are all <= 1460MHz while the E3827 and E3845
are 1750MHz and 1910MHz, respectively. This will allow to boot
quad-core Minnowboard Turbot especially.
Change-Id: I5e57dd419b443dfa742c8812cec87274af557728
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/27989
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use of device_t is deprecated.
Change-Id: I564319506870f75eab58cce535d4e3535a64a993
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/28642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Change-Id: Ib39305effdb00e032ca07e6d0e0d84cdf3dcf916
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29098
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I020431ba8eb61f5ce256088b919c049985331d64
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29069
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Phase 1. Due to the size of the effort, this CL is broken into several
phases.
Change-Id: I0236e0960cd1e79558ea50c814e1de2830aa0550
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/29065
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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Apparently coreboot still uses magic numbers instead of macros in some
Lenovo mainboards. Let's use macros instead. Also removed FDD from l520
romstage (original value, 0x3c0c, means that FDD_LPC_EN was also
enabled).
Change-Id: I6468e3357f8eed434f8527a852e134380f486d9a
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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This file was extracted directly from the vendor's firmware ver. 2.27.
Change-Id: Ic2d2b259f3b535a791c9dcfdf962c03a0bab87a2
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29148
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
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- Add new mainboard variant coffee lake RVP8, which is CRB for
coffee lake-s processor, support U-DIMM DDR4 memory module.
- Modify cfl_h devicetree to enable IO devices, configure PCIE root
port clock source, usb over current pin as per board schematics.
- Select cannonlake PCH-H chipset config for both cfl_h & cfl_s.
- Add GPIO table as per board schematics.
BUG= None
TEST= Build and flash, confirm boot into yocoto & windows OS on both
cfl RVP11 & RVP8 platform. verified PCI, USB, ethernet, SATA,
display, power functionalities.
Change-Id: Iabd32eb43ee8e6b1a3993ba4e083a80c62485b14
Signed-off-by: praveen hodagatta pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-on: https://review.coreboot.org/29066
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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L520 and T420 should also use it - platforms are very similar to t420s
and t530. Z61t is based on T60/X60, X131e is based on X230 so commit
with Change-Id I13c08b8c6b1bf0f3deb25a464b26880d8469c005 should be
applied as well.
All four platforms are using ec/lenovo/h8 embedded controller.
Change-Id: Ib177f024871e82979dd430da86f1551aef14d446
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29064
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set up USB host controller.
BUG=b:80501386
BRANCH=none
TEST=Boots correctly on Kukui
Change-Id: Iec98f3dc1bbf3dda3d28dbefad15339d48608c7e
Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com>
Reviewed-on: https://review.coreboot.org/28788
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Joel Kitching <kitching@google.com>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
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There is no need to indent these lines with two tabs.
Change-Id: I2164f4e3ea48db8dc5242a55b0452782dae19a4b
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28989
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The assignment of header->checksum was in some cases done twice, or
unnecessarily split into two lines.
Change-Id: Ib0c0890d7589e6a24b11e9bda10e6969c7d73c56
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28988
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
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While these pins were set to a pull-down 20KOhm, NPCX EC consumes
~2.1mW higher power. Becasue there was leakage current on both GPIO67
and GPIO70 from NPCX EC. With the external pull-up 10KOhm for
USB_OC0#/USB2_OC1#, this wasn't enough to prevent leakage current.
BUG=b:117139495
TEST=Check nxpc EC power to see power improvement
Change-Id: I685d876461c263f07ca4c8f8046635cb7087279c
Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com>
Reviewed-on: https://review.coreboot.org/29007
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Update CPU passive temperature threshold value from 70C to 80C,
to avoid early throttling for spiky workloads. Also, change CPU
throttling interval from 1 sec to 5 sec for CPU temperature.
BUG=b:116400298
BRANCH=None
TEST=Manual performance testing on nocturne.
Change-Id: Ic5031a4aa16f750237565f4e4928e78834b1d686
Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/29044
Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
Reviewed-by: Todd Broch <tbroch@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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It always included if ACPI is supported since commit 822bc65 with
Change-Id I372dbd03101030c904dab153552a1291f3b63518 ("ACPI: Remove
CONFIG_GENERATE_ACPI_TABLES").
Change-Id: If17a6f43e368ccf850031b349714fa1ec4d02c1d
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/28954
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Since there are two cameras on Nami and only one camera on Syndra.
We need to disable rear camera/DMIC on all Syndra sku.
BUG=b:112876867
Change-Id: I92fb43ec84387c268ffdb6d0d34a5e5b13bcf50a
Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/29022
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Tried to build all affected mainboards - still compiles fine.
Change-Id: I385cac1a75cee13453b831bd75b3ecc7a6d229fa
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29033
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This define is no longer used by anyone. It was removed everywhere else
with commit with Change-Id I556769e5e28b83e7465e3db689e26c8c0ab44757.
It seems that these two files were simply mislooked. So let's remove it.
Change-Id: Ifbb62441e16e97c0cae0713968844e296619a880
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-on: https://review.coreboot.org/29070
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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This mainboard is quite similar to the p5qc. The main differences being a second
PEG slot, the IDE slot and being DDR2 only.
The following was tested:
- both PEG slots populated (coreboot sets legacy VGA decoding on the GPU in the
black slot)
- USB
- Ethernet NIC
- PS2 Keyboard
- COM1
- S3 resume
Change-Id: I49a4bca4256e2a905aff3252eca76387c81152c1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/29102
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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A shortcoming of this driver is that if multiple devices with the same PCI ID
are present and don't have an eeprom, they would all get the same macadress set.
The r8168 driver deals with such cases so it should be easy to implement if
needed.
Change-Id: I5c32df00e25453c350a45e7f1ee6834b89c4289f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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SeaBIOS does not seem to like the Marvel IDE controller, so disabled SeaBIOS
support for ATA. It works fine in Linux afterwards.
Working:
- SATA on southbridge port
- SATA on marvel IDE controller ports (only in Linux)
- USB
- COM1
- PS2 Keyboard
- DDR2 DIMMs
- PCIe x16 PEG port
- PCI port
- NIC (needs a driver to set macaddress)
- S3 resume
Not working:
- SeaBIOS with ATA support (long timeout marvel controller so disabled)
- DDR3 fails because the proper clock signal does not get enabled. Even when
fixing this it fails later or during memtest, so it should be considered
unsupported for now
Untested:
- PCIe x1 ports (expected to work)
- sound (expected to work)
TODO:
add documentation
Change-Id: I4a81940707566776bd048904ca1387fea741fece
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/28264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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More platforms are not able to hibernate under certain circumstances,
such as when AC is plugged. This original path was conservatively put in
to prevent potential damage when cr50-update-caused asynchronous resets
occur. Julius' compelling argument that async resets from recovery mode
requests should have enough coverage of the design over the course of
project development. Remove the hibernate path and assume all is well
going forward.
Change-Id: I37121e75ff4e6abcb41d8534a1eccf0788ce2ea2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/29076
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I4a9a9366c85206fa460519a26f48b3aada5bc7c3
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/29100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Make the field names of the MISCx00 GPPClkCntrl more manageable by
shortening their names. Make the definitions look more like the
rest of the header file.
Change-Id: I515cd664808e38851a7dbdba899df4fb9bbbcde6
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/29014
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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This change implements the callback to provide google_chromeec_event_info
structure in nocturne variant and sets MKBP SCI based on board id.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: Ifcc10aefc8f450214bd64dfffaf8854ada43f323
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This change adds a variant callback to read google_chromeec_event_info
from variant at runtime to allow override of any events based on
factors like board id.
This callback is used in ramstage and smm to get
google_chromeec_event_info structure for performing various actions
like setting masks and logging wake events from EC.
BUG=b:112366846,b:112112483,b:112111610
Change-Id: If89e904c92372530a0f555952f87702f068e0b03
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Enrico Granata <egranata@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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STAPM devicetree registers do not indicate the unit, which causes confusion.
More importantly, the time was assumed to be in seconds when it's actually
milliseconds. This caused early STAPM configurations to fail.
BUG=b:117590953
TEST=Build grunt
Change-Id: I2a7e3d43601992d1f7b02456913c763d940fe9ee
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/29035
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With correct stapm values audio issue is not observed with
PsPPBalanceLow (Gen1 speed).
BUG=b:117569918
TEST=audio playback multiple times
Change-Id: Iaeae52b262b12622a6753432e3fc40bf5f0fd8e0
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/29028
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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stapm_time passed to smu via agesa is in msec. With earlier value
smu was getting stapm_time as 2.5 sec instead of 2500 sec and thus
causing issue in S3, and audio in PsppBalanceLow state.
BUG=b:117569918, b:117252463
TEST=
1.) audio works with PsppBalanceLow
2.) S3 cycles
Change-Id: I673e7e673d042918dff47141f37bbca354f5c45c
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/29027
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Tune I2C params for I2C buses 0, 5, 6, and 7 to ensure that the
frequency does not exceed 400KHz.
BUG=b:117298114
TEST=emerge-octopus coreboot chromeos-bootimage and measured frequency
under 400 KHz
Change-Id: Id608aae7edf54a24f364606dd7952521d1d67c1a
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/29021
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Only two UARTs are connected to the FTDI UART USB chip.
Change-Id: Id5ae7266ce44c9f64c7f7aeaf23c49122041f47a
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/28986
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
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Need to tune I2C bus 0 clock frequency under the 400KHz
since this bus attached the Stylus EMR pen and need meet the spec.
Bug=b:117297214
TEST=flash coreboot to the DUT and measure I2C bus 0 clock
frequency whether under 400KHz
Change-Id: I06d9d25f52d7f641d937de0d6b7df3d7a076fbf9
Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28973
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Now only those UARTs that are enabled in devicetree.cb are initialized.
Tested on Opencellular Elgon.
Change-Id: I145c224148f0cc078bb1c76f588f603e73121a62
Signed-off-by: Jens Drenhaus <jens.drenhaus@9elements.com>
Reviewed-on: https://review.coreboot.org/28975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
|
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Add SPD file for sdp samsung_dimm_K4AAG165WB-MCRC (ram id: 9)
BUG=b:112679174
TEST=emerge-nami coreboot chromeos-bootimage
Change-Id: Iac1e3ca4b009cc9be94608cd342f535fa581a5eb
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28974
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the new I2C slave reset function and reset all slaves connected to all
4 I2C. Do this in all boards.
BUG=b:114479395
TEST=Added debug code. Build and boot grunt. Examined output, confirmed
GPIO pins changing as required. Removed debug code.
Change-Id: Ia78ee5d5319d3c1a7daa9c56c81d435999b3a359
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/28575
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:117173908
TEST=Build delan
Change-Id: If149b8c43ff16637c38d5320eb606bb72d62e953
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28972
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Clean up Kconfig file in order to support variants for fizz. Add
BOARD_GOOGLE_BASEBOARD_FIZZ that can be set by various fizz variants
to use the common baseboard configs.
BUG=b:117066935
BRANCH=Fizz
TEST=emerge-fizz coreboot
Change-Id: I9c89f1dc526a9d623e1ae4d4b52a923489b389d3
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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After adjustment on Liara EVT
H1: 392.03 KHz
TP: 397.87 KHz
TS: 397.71 KHz
BUG=b:116309237
BRANCH=master
TEST=emerge-grunt coreboot chromeos-bootimage
measure by scope
Change-Id: Ib5d7ce09ac58f33ee826d7541e1a0d14a03add9a
Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28960
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Setting default PSPP setting to BalancedLow was causing audio
playback issue in most of the units. With BalancedLow either there
was no sound or noise on playback.
Switching to BalancedHigh as default option.
BUG=b:116553085, b:112020107
TEST=Test playback and hear proper audio.
Change-Id: Ibf64d7b8e58e60ce931ddc85f11b135708cdb1ee
Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com>
Reviewed-on: https://review.coreboot.org/28967
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Its spreading copies got out of sync. And as it is not a standard header
but used in commonlib code, it belongs into commonlib. While we are at
it, always include it via GCC's `-include` switch.
Some Windows and BSD quirk handling went into the util copies. We always
guard from redefinitions now to prevent further issues.
Change-Id: I850414e6db1d799dce71ff2dc044e6a000ad2552
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/28927
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 3 for DVT.
BUG=b:115697578
TEST=verified it in Bobba EVT board which rework ram id.
Change-Id: I0fb457d8772f5038e5d90188d7682956ddfad46b
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28891
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Wifi wake register is incorrectly set in devicetree.
Set wifi wake to its correct wake source, GPE0_DW2_01.
BUG=b:117330593
TEST='emerge-nocturne coreboot chromeos-bootimage', flash nocture,
connect wifi to a hotspot, suspend device, echo freeze >
/sys/power/state, and then shutdown the hotspot and verify device
wakes.
Change-Id: Iafa865ca79d33541d7f47b69d2fb209e7f9c98af
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28938
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The WAKE# signal has moved to LAN_WAKE, so WAKE# is now
floating and must be disabled. This change disables WAKE#.
BUG=b:117284700
TEST=none
Change-Id: I1c25e4ba28cd2b8807cd155d47c29c0d3ee9e8a5
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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RISC-V is not a project of the University of California, Berkeley,
anymore; it stands on its own feet now.
Remove the "UCB" component from the RISC-V mainboards in the "emulation"
directory, and don't set MAINBOARD_VENDOR to UCB, either.
Change-Id: I301d9d0091a714e62375052e5af06a9197876688
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/28951
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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In order to make the macro name consistent for all PAD_CFG1_IOSSTATE_*
macros, this change uses lower case x for *RXD*. It helps avoid
confusion when using the macros.
Change-Id: I6b1ce259ed184bcf8224dff334fcf0a0289f1788
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28924
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All ampton boards should have the DRAM info configured in CBI and so
DRAM_PART_NUM_ALWAYS_IN_CBI is already selected for ampton. This
change gets rid of the redundant minimum board id value for Ampton.
BUG=b:117071184
Change-Id: I59f60b8c5aa34b55b8e473c06cc49ea7ae284d62
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28933
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Jett Rink <jettrink@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fleex does not have any device on I2C0 and hence this change disables
I2C0 device (16.0) in devicetree and gets rid of the I2C tuning
parameters for I2C0.
BUG=b:115600671
Change-Id: Ib799eae05b667cee2272bbd37f0ca44b7cec66cd
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28931
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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I2C3 is connected to the debug header and won't be required unless
connecting the debugger. This change disables I2C3 device (16.3) in
devicetree.
Change-Id: I650fa040075119a21864c83d8470dd2155c9edb9
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28930
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
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This change uses the generic device driver to provide DMIC properties
in ACPI table to the OS driver.
BUG=b:112888584
Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28797
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for
initialization of HDA codecs only. This prevents adding of any static
devices under the HDA device node. However, there can be boards which
want to add devices under HDA node (e.g. nocturne that wants to
provide DMIC properties to OS) without performing any codec
initialization using the HDA. This change:
1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can
be set explicitly by the boards that want to perform codec
initialization.
2. Uses newly added config option is used to guard the initialization
functions for the codec. Rest of the device operations can still be
used by all the other boards without having to use HDA codec
initialization.
3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in
kblrvp which is the only board enabling HDA codec initialization
using common block code.
4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC.
Above changes need to be bundled and pushed in as a single change in
order to avoid breaking existing users.
BUG=b:112888584
Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c
Signed-off-by: Furquan Shaikh <furquan@google.com>
Reviewed-on: https://review.coreboot.org/28806
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Need to tune I2C bus 0/6/7 clock frequency under the 400KHz for
digitizer, touchpad, and touchscreen.
Bug=b:117126484
TEST=flash coreboot to the DUT and measure I2C bus 0/6/7 clock
frequency whether can <400KHz
Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28907
Reviewed-by: Justin TerAvest <teravest@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber
test, but the root cause is unclear.
Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal
reset issue, so we would apply it until find root cause of this issue.
BUG=b:117130599
BRANCH=poppy
TEST=Built and passed on reliability test with modified coreboot
Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com>
Reviewed-on: https://review.coreboot.org/28785
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This adds the ACPI controls for power sequencing the touchscreen.
The initial setting is to keep the touchscreen powered off and in
reset. When linux is ready to talk to the touchscreen, it powers it
on and releases reset via ACPI.
BUG=b:110286344
TEST=verified touchscreen is functional in chromeos
Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/28869
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Setting the stapm parameters is causing S3 resume failures and
performance issues. Removing these settings until more testing is
done and the issues are solved.
BUG=b:117252463, b:116870267
TEST=boot grunt
Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/28925
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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In CBFS layout:
oem.bin size is 10 bytes.
In cbfs_boot_load_file, buffer size will need to be larger
than decompressed_size, otherwise CBFS data can not be
extracted into buffer.
Then we need to check buffer whether it's empty string separately.
BUG=b:79874904
BRANCH=master
TEST=emerge-grunt coreboot
Change-Id: I4f1bbb690ecca515ac920f5058ee19b5bfd8fa5e
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/28889
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
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Move the FSP param initialization function to a separate file,
as being done on the SoC side and remove the empty romstage.c file.
Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-on: https://review.coreboot.org/28662
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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GPP_C19 is not being set as the code is incorrectly setting
GPP_C16 instead, causing SAR sensor not to work, so this change
sets GPP_C19 to NF1.
GPP_E3 is not being initialized in the code. Initialize GPP_E3
to a no connect as documented in the board schematic.
BUG=b:117124878
TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and
verify that i2c transactions work for the left SAR sensor.
Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28867
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Increase the reset delay for the touchscreen to 10 ms.
BUG=b:116857433
TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot
nocturne to kernel, log in and execute the following two commands:
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind
echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind
and verify the bind command does not echo back a
"-bash: echo: write error: No such device" error.
Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/28803
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Caveh Jalali <caveh@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS"
so that the audio topology file can be loaded properly by the
operating system.
BUG=b:112945714
BRANCH=master
TEST=There is no error message like "failed to load topology firmware" in
kernel v4.4 log.
Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f
Signed-off-by: Marx Wang <marx.wang@intel.com>
Reviewed-on: https://review.coreboot.org/28870
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI
and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT.
BUG=b:116721822
TEST=Verified it in Fleex EVT board which rework ram id.
Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310
Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/28782
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value
to the embedded controller to be exported to the OS.
This interface was tested on a reworked Nocturne board with modified
EC and a modified kernel driver to ensure that the interrupt asserts
as expected and can be used by the kernel driver.
Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/28759
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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