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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C3 | | C0
C2 | | C1
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+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I2153f826d7ff05f42935f08d5d1f5127ac944575
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64728
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
C2 C0 A3 A2
+----------------+
| REAR |
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| FRONT |
+----------------+
C1 A1 A0
BUG=b:232298007
TEST=emerge-brya coreboot
BRANCH=firmware-brya-14505.B
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I6a9ead24ef9d73bc0b09301cf641009ced0c6810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64732
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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With Cr50, the GPIO EC_IN_RW_ODL is used to determine whether EC is
trusted. However, with Ti50 where corsola has been switched to, it is
determined by Ti50's boot mode. If the boot mode is TRUSTED_RO, the
VB2_CONTEXT_EC_TRUSTED flag will be set in check_boot_mode(). Therefore
in the Ti50 case get_ec_is_trusted() can just return 0.
The current code of get_ec_is_trusted() only checks the GPIO, which
causes the EC to be always considered "trusted". Therefore, correct the
return value to 0 for TPM_GOOGLE_TI50.
BUG=b:235053870
TEST=emerge-corsola coreboot
TEST=firmware-DevMode passed in kingler (with Ti50)
BRANCH=none
Change-Id: I59b16238bfb487832ef618668c0f9addc1ee7937
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64998
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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add fw_config probe for auido and enable BT offload support.
BUG=b:232419816 b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Id58e48cc2510d0377040d86bb9dbbb45bec7d624
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ib66a97cd76cb169e3f33a4d2d2465db115939d03
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64888
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Based on latest schematic to update the gpio table.
BUG=b:232419765
TEST=FW_NAME=kuldax emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: If30d872af5d729c0ebd468ebfb099192ec682309
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64862
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Remove EEPROM power source interconnect with camera power on/off
and keep it always on.
There appears to be a rare case where the camera EEPROM is not
able to be read from. As a workaround, this patch leaves the
EEPROM power rail on in S0.
BUG=b:229049914
TEST=tested the changes with redrix 5MP(ov5675/hi556) camera.
Change-Id: I9efab9bb65632a73c1c2635729c38a2aa14c69b2
Signed-off-by: Arec Kao <arec.kao@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64415
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Andy Yeh <andy.yeh@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The _DSM subfunction for the Nvidia GN20 supports 1 additional
subfunction, known as GPS, which is required to support GPU Boost. This
implementation is minimal, essentially letting the GPU manage its own
temperature.
BUG=b:214581372
TEST=abuild
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I21331bd811a13212f3825bda44be44d1b5ae7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Now that the power sequencing for the GPU is in a better shape, ensure
that the ACPI code that performs power sequencing matches the C code
that does the same.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I797ee99f22a7a6aaacfe54862595674d4ada06ee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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During the GPU power down sequence, each power rail should reach below
at least 10% before the next rail is sequenced down; based on scope
shots for a board, conservative delays between each rail are added;
they will likely be more fine-tuned later on.
BUG=b:233959099
TEST=sequence verified by EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I28ada3a01b86996e9c7802f8bd18b9acda6bb343
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Currently, the display does not work in steelix. Steelix uses ps8640
eDP bridge IC, which is different from its reference board kingler.
So we should enable ps8640 for steelix.
BUG=b:232195941
TEST=firmware bootsplash is shown on eDP panel of steelix.
Change-Id: I8c6310794c89fc8aa0e69e114c1f7ebd5479c549
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64790
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add OVTI8856 information for craask
BUG=b:232656913
TEST=Build and boot on craask
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ice490f31e9ab8fffff6a7a5d24f769efea91188d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64376
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add the support LP5 RAM parts for vell:
DRAM Part Name ID to assign Vendor
H58G56AK6BX069 2 (0010) Hynix
BUG=b:227595062
BRANCH=firmware-brya-14505.B
TEST=emerge-brya coreboot
Change-Id: Ibe09285c15b28ceeb6ab0d6c94f90e00584ac07d
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64852
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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With a combined bootblock+romstage ENV_ROMSTAGE might no
longer evaluate true.
Change-Id: I733cf4e4ab177e35cd260318556ece1e73d082dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63376
Reviewed-by: Julius Werner <jwerner@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Board id is same so use cpuid to decide to use ADL or RPL VBT.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Change-Id: I954c228f82110c3e7c8474e47cabab8220ff19b9
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64672
Reviewed-by: Anil Kumar K <anil.kumar.k@intel.com>
Reviewed-by: Jeremy Compostella <jeremy.compostella@intel.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Take adlrvp_p as a baseline code and add a new variant of ADL RVP
with Raptor Lake silicon.
BUG=b:229134437
BRANCH=firmware-brya-14505.B
TEST=build adlrvp_rpl_ext_ec
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Change-Id: I880abe0f300118f461523173cc0d50a2fbc99e72
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64619
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB | A1
| |
+----------------+
BUG=b:232298307
TEST=None
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ic9c45aebaf02a16b755f4731e1e3b46cd5dec829
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB |
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+----------------+
BUG=b:232298017
TEST=None
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Idca3dd468f1b9fde37a1bbf20d65768032c7160b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I0d609f0db475877d0ef1f47ab89c34dccb6e16d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64475
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Since many vboot settings are heavily tuned for Chrome OS support,
use these vboot kconfigs for the non Chrome OS use case and tune for EHL
CRB vboot support.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ie1ffd4973fb18bbca5c5b9c888a4dd0e662b1574
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Praveen HP <praveen.hodagatta.pranesh@intel.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add two combination:
1. ALC5682I-VS and ALC1019
2. NAU88L25 and MAX98360
BUG=b:227165780, b:228879074
TEST=emerge-skyrim coreboot chromeos-bootimage
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I36d7b5c4e88825ceaa6922d9e3bed366f55a0d81
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63779
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-hsuan Hsu <yuhsuan@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Remove TODO's for dummy DXIO descriptors, update comment
to reflect what they are. These devices are needed for the
platform to function properly. Also remove the TODO for
DDI descriptors as they are functioning correctly.
BUG=b:232952508
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I1535c08cac3f0bcb30061aba2aa593eb22109387
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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The Nvidia GPU kernel driver supports another _DSM subfunction which
is known as NVPCF (Nvidia Platform and Control Framework). The
subfunction informs the kernel driver about Dynamic Boost parameters,
which is done at init time, but can also be changed dynamically.
BUG=b:214581372
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I7887bfc2e8e1cae606e12502a9eda3a7954c8d7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Set different power limit values using host command to detect charger
type from ec.
Scenario:
1. With 90W customized adapter, set to baseline.
2. With 170W customized adapter, set to performance.
3. With above 90W barrel jack/type-c adapter, set to performance.
4. With below 90W barrel jack/type-c adapter, set to baseline.
BUG=b:231911918
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I9c8a5a7de8249e61468e277ec55348b660253c5d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I7c50f770c3a7ab261d6ea41f945e2239ba53fd09
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ia5b6c5c72a1eafe1118e92e4579decb4f4abc9e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Change-Id: Ib2d0c6a23b66e6e61cc8ea09a443e19a4b37c66d
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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Enable clk 1, LTR & AER for PCIe-to-i225 bridge.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: I9593f5d0b70f3d231fd1a8f4758b924645392d63
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64902
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When device tcss_xhci is disabled, boot hang occurs at FSP-S
TcssInit(): "IomReadyCheck Failed!"
Enabling this device fixes the issue.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Ie001bd56b403d511c397737fbc214ed64956910d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64901
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Christian Walter <christian.walter@9elements.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: Iea5312055305bc3354755607a7bfafa7980c6d21
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Follow GPIO_Table_0527.xlsx to update gpio configuration.
- Set GPP_A15 to NC.
- Set GPP_A20 to TCP_DP1_HPD (native function1).
BUG=b:225384873
TEST=Build and boot to Chrome OS.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I1c7a211c3bef1f1fe4f94345186c33363a90e11f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64786
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
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Follow thermal table from thermal team.
Chang list:
1. Update TEMP_PCT of Active Policy for TSR1.
BUG=b:230829301
TEST=emerge-brya coreboot
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I2a3fbdbe0dbb00597d5785c90c6e4d6ace54f13c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Nereid
BUG=b:233030505
BRANCH=None
TEST=Build FW and test on Nereid board.
Verified thermal throttling successfully when participant reaches temp
threshold as per Passive Policy.
Also, verified system shutdown when Temperature of participants are
reaching threshold as per Critical policy.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: I195f4b507ee57948751f0119735d8350dfce984b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64468
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Jesper Lin <jesper_lin@wistron.corp-partner.google.com>
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This patch configures external V1p05/Vnn/VnnSx rails for Craask
to achieve the better power savings.
* Enable the external V1p05, Vnn, VnnSx rails in S0i1, S0i2, S0i3, S3,
S4, S5 , S0 states.
* Set the supported voltage states.
* Set the voltage for v1p05 and vnn.
* Set the ICC max for v1p05 and vnn.
BUG=b:233717182
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I95d24c0836f3ee02006868341ccc72d762c155d3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64632
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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In order to enable the UFS controller (PCI device 12.7), the PCI
specification says that the device at function 0 in the same slot must
also be enabled, which is the ISH. Therefore, enable ISH when UFS is
present.
For more context on why this is necessary, see CB:62662 which enabled
UFS and ISH for adlrvp_n.
BUG=b:234136500
TEST=Build test. Will test that UFS works once we have hardware.
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Change-Id: Ib60d44322cfbd8f82c33ecac7598881dfb1d0c3c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64845
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Daniil Lunev <dlunev@chromium.org>
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Hide the Linux gpio-led ACPI device from Windows by setting the device
status (_STA) to 0xB (enabled, hidden) so Windows doesn't show an
unknown device/missing drivers in Device Manger. Linux doesn't care
about the _STA value.
Test: build/boot Windows (10/11) and Linux (PureOS 10) on a Librem Mini
v2, verify LED works under Linux, is ignored under Windows
Change-Id: If3ee0db685a2f7dab505602afa98c3c2d5adf5d3
Signed-off-by: Matt DeVillier <matt.devillier@puri.sm>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64710
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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This commit adds the skolas baseboard, which is basically the brya
baseboard, but using an Intel Raptor Lake-P SoC instead of an Alder
Lake SoC.
This commit also adds the skolas baseboard variant skolas4es.
Since this baseboard is identical to the brya baseboard with the
exception of the SoC used, the new baseboard and the new baseboard's
first variant will be a copy of the current brya baseboard and brya0
variant.
For now, the skolas baseboard and skolas4es variant will continue to
use ADL-P. This allows for two benefits:
1. software to be proven out on existing hardware prior to RPL SoC
support landing, and
2. allows us not to have to wait for RPL SoC changes prior to getting
the mainboard changes in place
Once the RPL SoC code has merged, I will update the skolas baseboard and
skolas4es variant to use RPL instead of ADL.
BUG=b:229134437
TEST=util/abuild/abuild -p none -t google/brya -x -a -c max
Change-Id: Iec100306dca2320eaf2432797f3acc31db2543d3
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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All Osiris SKUs use the new RGB gaming keyboard,
so don't need the fw_config to decide keyboard matrix.
BUG=b:220800586
TEST=FW_NAME="osiris" emerge-brya coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19211c345de0b315d65ec64efc70826e81315810
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64813
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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BUG=None
BRANCH=None
TEST=Build FW and test on adln_rvp board
Verified thermal throttling successfully when participant reaches temp threshold as per Passive Policy.
Verified fan control successfully when participant reaches temp threshold as per Active Policy.
Also, verified system shutdown when Temperature of participants are reaching threshold as per Critical policy.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Icafacfca6a026ec3b42906790831f11fd2f1b085
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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This patch adds support for the ADL-N SKUs based on the PCH ID.
Document reference: 645548 (ADL-N EDS Volume 1).
BUG=None
BRANCH=None
TEST=Build FW and test on adln_rvp board
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Ie49398b8a7de8d8cff3536eae6a5e893980f9c26
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Craask uses CNVi WLAN, so disable the PCIe-related GPIOs.
BUG=b:229040345
Test=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7bcf041503dcee448758dac46b1c9711d0b02ba3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64461
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I9cefa29738b42dd08cb00489ad6e8644e3fc405e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63997
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I47fded50377ab624e4bceb320a5e069a7f36c2fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I92c167bf95e605e098324b9e80cfaab8f589dcab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63995
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I284a5e39ca4b0032ed0c8e3a92c095db319d1691
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63994
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: Ide938a40ed1f6869ee248ed46f6bf29f95649490
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63993
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Signed-off-by: Peter Lemenkov <lemenkov@gmail.com>
Change-Id: I9bf95ed74468e283bab79a5f25aee758d37d926a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63992
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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BUG=b:210970640
TEST=emerge-draco coreboot chromeos-bootimage
Change-Id: I90d9f2e298e54832bc077eae1c8be0e39c151d90
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64808
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Starting with id 2, boards switched the memory SMBus slave address, and
use 0x50, 0x52.
BUG=b:233975373
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I5e683ffdbc0727259ee796610cd97a6e378bf335
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64810
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add a new kingler follower 'steelix'.
BUG=b:232195941
TEST=make # select steelix
Change-Id: Idd2ed1404cde72ecdb6cc3a262e793a6272aa871
Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64789
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Tested with SMI_DEBUG: SMM prints things on the console.
Change-Id: I7db55aaabd16a6ef585c4802218790bf04650b13
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/61494
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia288937ef3a4229088b60d87d31ea88057377a71
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
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+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: If2a77c0239646759e0192b72ba1991d334dd15aa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
+----------------+
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| Screen |
| |
+----------------+
C0 | | C1
A0 | MLB DB | A1
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+----------------+
BUG=b:232256907
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I47b069377046652ba4d278733a15bbca98bdb739
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64729
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This CL adds the delay time into the RTD3 sequence, which will turn
off the eMMC controller (a true D3cold state) during the RTD3 sequence.
We checked power on sequence requires enable pin prior to reset pin
delay of 50ms and add delay of 20ms to meet the sequence on various
eMMC SKUs. Based on BH799BB_Preliminary_DS_R079_20201124.pdf in
chapter 7.2.
BUG=b:232327947
TEST=Build and suspend_stress_test -c 2500 pass
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I42cde5336f73a446cf5157e78f955fef8d70ae7e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64686
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name depending on the AUDIO_CODEC_SOURCE field of
fw_config. Define FW_CONFIG bits 41 - 43 (SSFC bits 9 - 11) for codec
selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BRANCH=dedede
BUG=b:226910787,b:232057623
TEST=on beadrix, verified by FW_NAME=beadrix emerge-dedede coreboot.
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: I059b750743ab3b29d17c50d0d4301fbae4873acc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Super Ni <super.ni@intel.corp-partner.google.com>
Reviewed-by: Ivan Chen <yulunchen@google.com>
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As cpucp prepare takes 300 msec moving to before ramstage
BUG=b:218406702
TEST=Validated on qualcomm sc7280 development board observed
total timestamp as 1.73 sec from 1.97 sec
Change-Id: I1a727514810a505cd1005ae7f52e5215e404b3bb
Signed-off-by: Sudheer Kumar Amrabadi <quic_samrabad@quicinc.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63085
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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These are configured by the TXE, so they do not need to be configured.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia1bf4e32aa156a0e1a74df2f62eb31cdadb376a9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64454
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Use shorter macros to configure GPIOs.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I91961658dca0902080576134e63e6d8a7c78d711
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Disconnect GPIOs that are unused or not connected.
Also, update comments that are vague or have errors.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ic83797b8a8e05eed99db0356f360a329f6fbf347
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64452
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Add supported memory parts in mem_parts_used.txt, and generate SPD id
for this part.
K3LKLKL0EM-MGCN
BUG=b:229938024
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Ie022dd95929549ddd403d4c1d1c52174fd3fd721
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64678
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Select vbt bin files based on DB_DISPLAY field of FW_CONFIG.
BUG=b:233690293
TEST=emerge-brask coreboot
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Idb92be66927259732bfd27e4db2c9f242da7d200
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63918
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
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In order to meet the OEM's acoustic specifications, the pre-wake
randomization time (DPA) is set to 100.
BUG=b:228410327
TEST=build FW and checked DPA value by fsp log.
Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: Idaf3f931a2c0f2373445948e5f53a82328ec7ba2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64372
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Future nissa devices will mostly use 16MB SPI flash. Add 16MB layout and
make it default for nissa.
BUG=b:202783191
TEST=build nissa and brya firmware, check they're still 32MB
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: I04ae46d62d3e018610ca2533c186dda980bd67bc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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In preparation to follow-up commits, rename the mainboard folder from
t440p to haswell, which will have more variants later.
Change-Id: I4a9d68d54d5f0821bbf85faaa620855d456c97f3
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63511
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Peter Lemenkov <lemenkov@gmail.com>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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PERST_0 is not used, so set this to GPIO_PRT0_UDEF (undefined) to
ensure that an undefined address is not added to GNVS.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Iac9b116b2fa28824a89db28911188364dc9a1a53
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64446
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Change-Id: I18398efefcb4171496c39462c23514ad61659213
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64775
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ic22fcbb7923ecac4c70147ae642ac28fac3e6e6d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64774
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: I772ef94c860a26214bdae367d9863a56d5df9469
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64757
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Move board-specific selects out of common configuration and add them to
each board where necessary.
Change-Id: I9940ad2e963458e4bc50c2a2957bb72cbd4109be
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: I8ef0e67a8f26b98acea777afb26ed221bfa90153
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64755
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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To support speaker AMP CS35L53-CWZR'S I2C needs to split to two
I2C ports
BUG=b:207333035
BRANCH=none
TEST=built and verified speaker
Signed-off-by: Eddy Lu <eddylu@ami.corp-partner.google.com>
Change-Id: I8095abc4fc3233b21b818a508c84cd59b39fc1d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63756
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
Reviewed-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
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This reverts commit bd9cec8ae5755e898d107fd061fc2e2f983552b9.
Reason for revert: Enable i2c7 for amp changing to 2 channel
because vell setting amp on i2c0 and i2c7 on next phase
BUG=b:229334701
TEST=emerge-brya coreboot chromeos-bootimage && $powerd_dbus_suspend
&& checks EC log and ensures the DUT could enter s0ix.
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Change-Id: I5988cd9926b2c9ced1d111774abaa897bef91537
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64627
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Kinox has four temperature sensors. Modify the target of DPTF active
policy to map correct temperature sensor.
BUG=b:231380286
TEST=Boot to Chrome OS and doesn't see "DPTF: Invalid sensor ID" from ec
comsole.
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Icb5c285a6f483e2a1b6510a962ff7f7f6e9a79e3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64722
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: I4be0a4ad980b4167eaaafc22399b680abf011553
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63971
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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The dGPU used for some Brya projects requests 32 bits of address space
for one of its BARs via the Resizable BAR mechanism. This Kconfig is
currently set at 29 bits for brya, so the allocation currently is
capped at 29 bits. This patch sets the limit to 32 bits for brya
boards, which is enough for the GPU.
BUG=b:214443809
TEST=all of the dGPU PCI BARs on agah can be successfully allocated
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I61dbe47f1f316967d052bae748ff23babde61ef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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While testing the power sequencing code for the GPU, a few mistakes were
found. This patch fixes those errors:
1) FBVDD load-switch enable is active-low
2) NVVDD VR enable is active-high
3) GPU_PERST_L should be driven low during GPIO table programming
4) The BAR saving code missed the top 32 bits of 64-bit BARs
5) sequence_rail() assumed the pwr_en_gpio and pg_gpio were the same
polarity
6) PEG vGPIOs were not programmed to the correct NF
BUG=b:233552225
TEST=dGPU is able to successfully enumerate over PCIe bus
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I85767d382012a0c7dfdb1f849768e0160f06c273
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64727
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Add fw_config support NMAX98360_ALC5682VS_I2S_2WAY and I2S2 vgpio
config and enabling cnvi_bt_audio_offload UPD bit.
BUG=none
TEST=emerge-brya coreboot
Signed-off-by: Mac Chiang <mac.chiang@intel.com>
Change-Id: I64a4e5479905911b2e9d1597b78131720abb689e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64691
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The default for DPTF is off (0), so remove the entry that sets this to
off.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I0397ff6f71766a2f738ab2b71be298ef8f2b1c9d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64381
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Since using FSP 2.2.0.0, the defaults match the required settings so
they no longer need to be specified.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ie0e00cae67cb89b184392e97b8ec196d45ea5d91
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64450
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Correct the USB-C port setting according to schematics.
AP log:
port C0 DISC req: usage 1 usb3 3 usb2 1
port C1 DISC req: usage 1 usb3 1 usb2 3
BUG=b:233554817
BRANCH=brya
TEST=emerge-draco coreboot chromeos-bootimage
Signed-off-by: Ivy Jian <ivy.jian@quanta.corp-partner.google.com>
Change-Id: Iea4aee19dff8e0bc863be46532f89e81f52f281b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64720
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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We need to put USB setting in mux order.
BUG=b:234103724
TEST=Type C mux configuration is correct.
Wrong:
added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
Correct:
added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0
added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: I4f8dbee35159960d17107e23fcde825a38c7de4e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64721
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Tested using MrChromeBox's `uefipayload_202107` branch:
* Windows 10
* Ubuntu 20.04
* MX Linux 19.4
* Manjaro 21
No known issues.
https://starlabs.systems/pages/labtop-mk-iii-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ia52566e06f50c0abcfb657044538db8e92564c36
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58538
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Ben McMillen <ben@starlabs.systems>
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This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
| MLB DB | A0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ibd36fb961de9e9af9da1fd885eeb958c833d38bd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64618
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A | MLB DB | A
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia66c6fafe08110b8d8f9a138a2516ae03f8e1809
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64617
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
A | MLB DB | A
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Icd56c650a03c5db6e1e68e4ca4c9f0c068a7a430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64616
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C2 | | A0
C0 | MLB DB |
A | |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia493fd28c362d2c0c343c2d121f6611cfd8f7f6c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64615
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C0 | | C1
| | A0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I840b0f363a1ff304b310505efdaba2ac1cd10472
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64614
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C2 | | C1
| MLB DB | A0
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ie4f96e3636a8b519923fdba7f9bd07d7a3e1d7ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
A | | A
C0 | MLB DB | C2
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: Ia1e95aba2f7d02131b0b0cdd6c7211a23e355084
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64612
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
|
|
This patch is to denote the correct value of ACPI _PLD for USB ports.
+----------------+
| |
| Screen |
| |
+----------------+
C2 | | A0
C0 | MLB DB | C1
| |
+----------------+
BUG=b:216490477
TEST=emerge-brya coreboot
Signed-off-by: Won Chung <wonchung@google.com>
Change-Id: I68fb940825bfcf7c77ca3015372025e47e7fcc41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Set tcc_offset value to 10 in devicetree for Thermal Control Circuit
(TCC) activation feature as mentioned in doc #572349.
BUG=b:229804441
BRANCH=None
TEST=Build FW and test on Nivviks board
Change-Id: Ie9533936eccbabcc9a873adcb622bb490928c9e3
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64664
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Skyrim uses the Ti50 GSC and the config should be updated to
reflect that.
BUG=b:233750667
TEST=Builds
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Change-Id: I5d4af19ab2dda35ab687a0659898d79b08c4de97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64669
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Enable the USB port that is used by the Bluetooth interface on the CNVI.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I2a330618c5f1c5fd5e3147cb6307c157b28070ac
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64545
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove the Webcam USB port form the devicetree and handle it solely in
devtree, which will enable or disable it based on the CMOS option.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I9c89c7103aca5c3d42215122e9d94c83947b6fee
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@tutanota.com>
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Set tcc_offset value based on the power_profile value, ranging from 5
to 15 degrees.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Id30bec9c095517884a7361226aed703b370f2207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64650
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: Ie8817434ee0bc6c195eabe090f195512c0043ae5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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AGESA has a lot of code in the .data section which is for initialized
data, that in fact should be .rodata. This adds the 'CONST' keyword
everywhere it is needed.
TEST: See in the .elf file (e.g. using readelf) that there is nothing in
.data section.
Change-Id: I9593c24f764319f66a64715d91175f64edf10608
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64386
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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The baseboard uses port USB2 #9, and USB3 #1, but vell does not,
therefore set the port configuration to EMPTY.
Change-Id: I0d03b967fd2a051205ad5807f0bd8916bad7c036
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64628
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The PMC is accessed via sideband registers, so the PCI device is not
needed.
Disabling it solves a bug where the laptop cannot be powered on
without the charger connected.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I78f4aa4567dfc154ef5cb21f8746265259cd53e0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64451
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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