coreboot.git - my copy of coreboot

Age	Commit message (Collapse)	Author
2020-05-14	mb/google/deltaur: Configure GPIO B11 as PMCALERT	Anil Kumar
	GPIO B11 pin should be configured as PMCALERT function. This is required for the intergrated USB-C feature to work in the SOC BUG=b:154778458, b:156288164 TEST= build and boot coreboot image on deltan. Test Type-C port enumeration on Chrome OS Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I8f995901b0a50d2c74f57aba96f86134c9d569e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41378 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-14	mb/google/volteer: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 ports	Furquan Shaikh
	This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. BUG=b:149186922 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I4cb820e83da40434b00198b934453805e35ef1ab Reviewed-on: https://review.coreboot.org/c/coreboot/+/41156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-05-13	mainboard/lenovo/x230: Add ThinkPad x230s as a variant	Bill XIE
	The code is based on autoport and that for X230. Major differences are: - Only one DDR3 slot - HM77 PCH - M.2 socket instead of mini pci-e - no docking - no tpm Tested: - CPU i5-3337U - Slotted DIMM 8GiB - Camera - pci-e and usb2 on M.2 slot with A key for wlan - sata and usb2 (no superspeed components) on M.2 slot with B key for wwan - On board SDHCI connected to pci-e - USB3 ports - libgfxinit-based graphic init - NVRAM options for North and South bridges - Sound - Thinkpad EC - S3 - Linux 4.9 within Debian GNU/Linux stable, loaded from Seabios. Untested: - Touch screen, which is said to work under ubuntu but not debian. Change-Id: Ie537645d5ffaee799e79af2f821f80c3ebd2dfec Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41168 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-13	mb/google/puff: add a region to cache SPD data	Jamie Chen
	This patch adds a SPI rom region RW_SPD_CACHE on Puff and it can be used on spd_cache to reduce reading SPD data from SODIMM by smbus. It's for saving the boot time and it can be used to trigger MRC retraining when memory DIMM is changed. BUG=b:146457985 BRANCH=None TEST=Build puff successfully and verified below two items. 1. To change memory DIMM can trigger retraining. 2. one DIMM save the boot time : 158ms two DIMM save the boot time : 265ms Change-Id: I8d07fddf113a767d62394cb31e33b56f22f74351 Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-13	mb/google/volteer/variants/halvor: add two SPD files	Nick Vaccaro
	Adds SPD_LPDDR4X_556b_1R_32Gb_8GbD_QDP_4267.spd.hex, which will be used initially for the "H9HKNNNCRMBVAR-NEH" SKhynix part as DRAM ID #0. Adds SPD_LPDDR4X_556b_1R_64Gb_16GbD_QDP_4267.spd.hex, which will be used initially for the "MT53E1G64D4SQ-046 WT:A" Micron part as DRAM ID #1. BUG=b:155423877 TEST=none Change-Id: I5580f602cd411e415dafcb36bd1ffa43c4f02f60 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41076 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13	src/mainboard: Remove unused 'include <stdlib.h>'	Elyes HAOUAS
	Found using following commande: diff <(git grep -l '#include <stdlib.h>' -- src/) <(git grep -l ' memalign\\|malloc\\|free' -- src/) \|grep -v vendorcode \|grep '<' Change-Id: Ib2ee840a10de5c10d57aa7a75b805ef69dc8da84 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41241 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13	mb/google/volteer/variants/volteer: Add three generic SPD files	Nick Vaccaro
	- Add SPD_LPDDR4X_200b_1R_16Gb_16Row_DDP_4267.spd.hex, initially used for the SKhynix H9HCNNNBKMMLXR-NEE part with DRAM ID #2 - Add SPD_LPDDR4X_200b_2R_64Gb_ODP_4267.spd.hex, initially used for the SKhynix H9HCNNNFAMMLXR-NEE part with DRAM ID #3 - Add SPD_LPDDR4X_200b_2R_32Gb_QDP_4267.spd.hex, initially used for the Micron MT53E1G32D2NP-046 WT:A part with DRAM ID #4 BUG=b:147857288 TEST=none Change-Id: I60d8bb05a4d6d3608adc7de69efc8623d1ca610d Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41126 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13	src: Remove unused '#include <stddef.h>'	Elyes HAOUAS
	Unused includes found using following commande: diff <(git grep -l '#include <stddef.h>' -- src/) <(git grep -l 'size_t\\|ssize_t\\|wchar_t\\|wint_t\\|NULL\\|DEVTREE_EARLY\\|DEVTREE_CONST\ \|MAYBE_STATIC_NONZERO\\|MAYBE_STATIC_BSS\\|zeroptr' -- src/)\|grep '<' \|grep -v vendor \|grep -vF '.h' Change-Id: Ic54b1db995fe7c61b416fa5e1c4022238e4a6ad5 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41150 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13	src: Remove unused '#include <stdint.h>'	Elyes HAOUAS
	unused includes of <stdin.h> found using following commande: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\\|uint8_t\\|int16_t\\|uint16_t\\|int32_t\\|uint32_t\\|int64_t\\| uint64_t\\|intptr_t\\|uintptr_t\\|intmax_t\\|uintmax_t\\|s8\\|u8\\|s16\\| u16\\|s32\\|u32\\|s64\\|u64\\|INT8_MIN\\|INT8_MAX\\|UINT8_MAX\\|INT16_MIN\ \|INT16_MAX\\|UINT16_MAX\\|INT32_MIN\\|INT32_MAX\\|UINT32_MAX\\|INT64_MIN\ \|INT64_MAX\\|UINT64_MAX\\|INTMAX_MIN\\|INTMAX_MAX\\|UINTMAX_MAX' -- src/) \|grep '<' \|grep -v vendor \|grep -vF '.h' Change-Id: Icb9b54c6abfb18d1e263665981968a4d7cccabeb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41148 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13	ec/lenovo/h8: Reintroduce h8_mb_init() for specific boards	Bill XIE
	Mainboard specific dock-init mechanism introduced https://review.coreboot.org/c/coreboot/+/36093 works on most boards, but https://ticket.coreboot.org/issues/256 shows that some boards (e.g. x201 and t410) need communication with h8 EC to enable or disable dock, (in dock_connect() and dock_disconnect() respectively) so they must be done after the h8 EC is brought up, which is not garanteed in the above mainboard specific dock-init mechanism. This time, a hook function h8_mb_init() will be called at the end of h8_enable(). (in place of the ancient h8_mainboard_init_dock() removed in CB:36093) Its default implementation is a weak empty function, but could be overrided with a strong one for boards needing to perform actions which should be done after h8 EC is brought up. This should fix the regression detected in https://ticket.coreboot.org/issues/256 Change-Id: I3674fbfeab2ea2cd2a4453a8e77521157d553388 Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-05-13	mb/google/volteer: move SPD files to variant directories	Nick Vaccaro
	Memory SPD files for each variant are now stored in the variant's mb/google/volteer/variants/<variant_name>/spd directory instead of storing them in mb/google/volteer/spd. This change moves SPDs to where they are needed and changes the makefile to look for them in their new locations. BUG=b:156126658 TEST="emerge-volteer coreboot chromeos-bootimage", flash and boot a proto2 SKU4 to the kernel. Change-Id: I759c979027477a2a4c5489a6b12278799488d6e7 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41184 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-13	mb/google/volteer: Enable keyboard backlight feature	Angel Pons
	This enables the keyboard backlight feature in ACPI for volteer. BUG=b:156326050 TEST=Verified 'KBLT' shows up in the DSDT ACPI table. Change-Id: Id1b1bb059368b0cc36cb06e6cdb8b989060a1dde Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41281 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-05-13	mb/google/dedede/variants/waddledoo: Modify ELAN touchscreen slave address	Ian Feng
	Modify ELAN EKTH6918 USI touchscreen slave address to 0x10. BUG=b:152936745 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I999967b0f37c82ff7811e3b6117baab795a11195 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-13	mb/google/octopus/variants/foob: Disable xHCI compliance mode	Tommie
	When any USB image disk is connected to the DUT through HUAWEI/APPLE Dongle, press Ctrl + u on the dev screen, it cannot boot from USB. We found the SS hub cannot be enumerated. So disable xHCI compliance mode. BRANCH=octopus BUG=b:155347573 TEST=Confirm successful boot from USB Change-Id: Iea4a3df156da0627336f7d6c1e03837b6cf0e7f2 Signed-off-by: tong.lin <tong.lin@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40905 Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12	mb/intel/jasperlake_rvp: Remove SataEnable deviceetree config	Ronak Kanabar
	SataEnable UPD override will be filled using devicetree pci device status check. Change-Id: I957dfcf139acd4f4dd5723bc1b010ec45ec91651 Signed-off-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41227 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-12	Revert "mb/{lenovo/x201,packardbell/ms2290}/acpi: Use GOS method"	Nico Huber
	This reverts commit b3100775ae29caebd068db8f6209561abda2fb0c. This was part of a series that moved things to common code and causes regressions. Change-Id: I239906e498c8352e6880408744f176a8aeb13dc8 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41191 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-12	trogdor: Add support for rev1	Julius Werner
	This patch implements the pin changes needed for Trogdor rev1. Unfortunately, coreboot has to get the EC and TPM SPI busses compiled into Kconfig, so we cannot really build a single image that runs on both revisions. Introduce a Kconfig to handle this instead. Change-Id: I2e48dc4565682c12089b6cf92c29f4cef4d61bb8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38773 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	trogdor: Latch GPIO interrupt support	rbokka
	Required for TPM IRQ. Change-Id: I8198213cf2808be5291620892185b1e534263e3f Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38714 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	trogdor: mainboard reference all QUPv3 FW drivers	T Michael Turney
	Change-Id: I8ff5dd63fac28ffa558aec71e79a6de87d7885e0 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37306 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	treewide: Convert more license headers to SPDX style	Patrick Georgi
	Change-Id: Ia3de79c7d71049da00ed108829eac6cb49ff3ed6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41205 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	treewide: Replace BSD-3-Clause and ISC headers with SPDX headers	Patrick Georgi
	Commands used: perl -i -p0e 's\|\/\[\s]Permission[\s]to[\s]use,[\s]copy,[\s]modify,[\s]and.or[\s]distribute[\s]this[\s]software[\s]for[\s]any[\s]purpose[\s]with[\s]or[\s]without[\s]fee[\s]is[\s]hereby[\s]granted,[\s]provided[\s]that[\s]the[\s]above[\s]copyright[\s]notice[\s]and[\s]this[\s]permission[\s]notice[\s]appear[\s]in[\s]all[\s]copies.[\s]THE[\s]SOFTWARE[\s]IS[\s]PROVIDED[\s].AS[\s]IS.[\s]AND[\s]THE[\s]AUTHOR[\s]DISCLAIMS[\s]ALL[\s]WARRANTIES[\s]WITH[\s]REGARD[\s]TO[\s]THIS[\s]SOFTWARE[\s]INCLUDING[\s]ALL[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY[\s]AND[\s]FITNESS.[\s]IN[\s]NO[\s]EVENT[\s]SHALL[\s]THE[\s]AUTHOR[\s]BE[\s]LIABLE[\s]FOR[\s]ANY[\s]SPECIAL,[\s]DIRECT,[\s]INDIRECT,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s]OR[\s]ANY[\s]DAMAGES[\s]WHATSOEVER[\s]RESULTING[\s]FROM[\s]LOSS[\s]OF[\s]USE,[\s]DATA[\s]OR[\s]PROFITS,[\s]WHETHER[\s]IN[\s]AN[\s]ACTION[\s]OF[\s]CONTRACT,[\s]NEGLIGENCE[\s]OR[\s]OTHER[\s]TORTIOUS[\s]ACTION,[\s]ARISING[\s]OUT[\s]OF[\s]OR[\s]IN[\s]CONNECTION[\s]WITH[\s]THE[\s]USE[\s]OR[\s]PERFORMANCE[\s]OF[\s]THIS[\s]SOFTWARE.[\s]\\/\|/* SPDX-License-Identifier: ISC /\|s' $(cat filelist) perl -i -p0e 's\|(\#\#)\sPermission[\#\s]to[\#\s]use,[\#\s]copy,[\#\s]modify,[\#\s]and.or[\#\s]distribute[\#\s]this[\#\s]software[\#\s]for[\#\s]any[\#\s]purpose[\#\s]with[\#\s]or[\#\s]without[\#\s]fee[\#\s]is[\#\s]hereby[\#\s]granted,[\#\s]provided[\#\s]that[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice[\#\s]and[\#\s]this[\#\s]permission[\#\s]notice[\#\s]appear[\#\s]in[\#\s]all[\#\s]copies.[\#\s]THE[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED[\#\s].AS[\#\s]IS.[\#\s]AND[\#\s]THE[\#\s]AUTHOR[\#\s]DISCLAIMS[\#\s]ALL[\#\s]WARRANTIES[\#\s]WITH[\#\s]REGARD[\#\s]TO[\#\s]THIS[\#\s]SOFTWARE[\#\s]INCLUDING[\#\s]ALL[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY[\#\s]AND[\#\s]FITNESS.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL[\#\s]THE[\#\s]AUTHOR[\#\s]BE[\#\s]LIABLE[\#\s]FOR[\#\s]ANY[\#\s]SPECIAL,[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s]OR[\#\s]ANY[\#\s]DAMAGES[\#\s]WHATSOEVER[\#\s]RESULTING[\#\s]FROM[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA[\#\s]OR[\#\s]PROFITS,[\#\s]WHETHER[\#\s]IN[\#\s]AN[\#\s]ACTION[\#\s]OF[\#\s]CONTRACT,[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHER[\#\s]TORTIOUS[\#\s]ACTION,[\#\s]ARISING[\#\s]OUT[\#\s]OF[\#\s]OR[\#\s]IN[\#\s]CONNECTION[\#\s]WITH[\#\s]THE[\#\s]USE[\#\s]OR[\#\s]PERFORMANCE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE.\s(\# \n)\|\1 SPDX-License-Identifier: ISC\n\n\|s' $(cat filelist) perl -i -p0e 's\|\/\[\s]Redistribution[\s]and[\s]use[\s]in[\s]source[\s]and[\s]binary[\s]forms,[\s]with[\s]or[\s]without[\s]modification,[\s]are[\s]permitted[\s]provided[\s]that[\s]the[\s]following[\s]conditions[\s]are[\s]met:[\s][1. ]Redistributions[\s]of[\s]source[\s]code[\s]must[\s]retain[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer.[\s][\s][2. ]Redistributions[\s]in[\s]binary[\s]form[\s]must[\s]reproduce[\s]the[\s]above[\s]copyright[\s]notice,[\s]this[\s]list[\s]of[\s]conditions[\s]and[\s]the[\s]following[\s]disclaimer[\s]in[\s]the[\s]documentation[\s]and.or[\s]other[\s]materials[\s]provided[\s]with[\s]the[\s]distribution.[\s][3. ].used[\s]to[\s]endorse[\s]or[\s]promote[\s]products[\s]derived[\s]from[\s]this[\s]software[\s]without[\s]specific[\s]prior[\s]written[\s]permission.[\s]THIS[\s]SOFTWARE[\s]IS[\s]PROVIDED.AS[\s]IS.[\s]AND[\s]ANY[\s]EXPRESS[\s]OR[\s]IMPLIED[\s]WARRANTIES,[\s]INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]THE[\s]IMPLIED[\s]WARRANTIES[\s]OF[\s]MERCHANTABILITY.FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.ARE[\s]DISCLAIMED.[\s]IN[\s]NO[\s]EVENT[\s]SHALL.LIABLE[\s]FOR[\s]ANY[\s]DIRECT,[\s]INDIRECT,[\s]INCIDENTAL,[\s]SPECIAL,[\s]EXEMPLARY,[\s]OR[\s]CONSEQUENTIAL[\s]DAMAGES[\s].INCLUDING,[\s]BUT[\s]NOT[\s]LIMITED[\s]TO,[\s]PROCUREMENT[\s]OF[\s]SUBSTITUTE[\s]GOODS[\s]OR[\s]SERVICES;[\s]LOSS[\s]OF[\s]USE,[\s]DATA,[\s]OR[\s]PROFITS;[\s]OR[\s]BUSINESS[\s]INTERRUPTION.[\s]HOWEVER[\s]CAUSED[\s]AND[\s]ON[\s]ANY[\s]THEORY[\s]OF[\s]LIABILITY,[\s]WHETHER[\s]IN[\s]CONTRACT,[\s]STRICT[\s]LIABILITY,[\s]OR[\s]TORT[\s].INCLUDING[\s]NEGLIGENCE[\s]OR[\s]OTHERWISE.[\s]ARISING[\s]IN[\s]ANY[\s]WAY[\s]OUT[\s]OF[\s]THE[\s]USE[\s]OF[\s]THIS[\s]SOFTWARE,[\s]EVEN[\s]IF[\s]ADVISED[\s]OF[\s]THE[\s]POSSIBILITY[\s]OF[\s]SUCH[\s]DAMAGE.[\s]\\/\|/ SPDX-License-Identifier: BSD-3-Clause /\|s' $(cat filelist) $1 perl -i -p0e 's\|(\#\#) Redistribution[\#\s]and[\#\s]use[\#\s]in[\#\s]source[\#\s]and[\#\s]binary[\#\s]forms,[\#\s]with[\#\s]or[\#\s]without[\#\s]modification,[\#\s]are[\#\s]permitted[\#\s]provided[\#\s]that[\#\s]the[\#\s]following[\#\s]conditions[\#\s]are[\#\s]met:[\#\s][1. ]Redistributions[\#\s]of[\#\s]source[\#\s]code[\#\s]must[\#\s]retain[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer.[\#\s][2. ]Redistributions[\#\s]in[\#\s]binary[\#\s]form[\#\s]must[\#\s]reproduce[\#\s]the[\#\s]above[\#\s]copyright[\#\s]notice,[\#\s]this[\#\s]list[\#\s]of[\#\s]conditions[\#\s]and[\#\s]the[\#\s]following[\#\s]disclaimer[\#\s]in[\#\s]the[\#\s]documentation[\#\s]and.or[\#\s]other[\#\s]materials[\#\s]provided[\#\s]with[\#\s]the[\#\s]distribution.[\#\s][\#\s][3. ].used[\#\s]to[\#\s]endorse[\#\s]or[\#\s]promote[\#\s]products[\#\s]derived[\#\s]from[\#\s]this[\#\s]software[\#\s]without[\#\s]specific[\#\s]prior[\#\s]written[\#\s]permission.[\#\s]THIS[\#\s]SOFTWARE[\#\s]IS[\#\s]PROVIDED.AS[\#\s]IS.[\#\s]AND[\#\s]ANY[\#\s]EXPRESS[\#\s]OR[\#\s]IMPLIED[\#\s]WARRANTIES,[\#\s]INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]THE[\#\s]IMPLIED[\#\s]WARRANTIES[\#\s]OF[\#\s]MERCHANTABILITY.FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.ARE[\#\s]DISCLAIMED.[\#\s]IN[\#\s]NO[\#\s]EVENT[\#\s]SHALL.LIABLE[\#\s]FOR[\#\s]ANY[\#\s]DIRECT,[\#\s]INDIRECT,[\#\s]INCIDENTAL,[\#\s]SPECIAL,[\#\s]EXEMPLARY,[\#\s]OR[\#\s]CONSEQUENTIAL[\#\s]DAMAGES[\#\s].INCLUDING,[\#\s]BUT[\#\s]NOT[\#\s]LIMITED[\#\s]TO,[\#\s]PROCUREMENT[\#\s]OF[\#\s]SUBSTITUTE[\#\s]GOODS[\#\s]OR[\#\s]SERVICES;[\#\s]LOSS[\#\s]OF[\#\s]USE,[\#\s]DATA,[\#\s]OR[\#\s]PROFITS;[\#\s]OR[\#\s]BUSINESS[\#\s]INTERRUPTION.[\#\s]HOWEVER[\#\s]CAUSED[\#\s]AND[\#\s]ON[\#\s]ANY[\#\s]THEORY[\#\s]OF[\#\s]LIABILITY,[\#\s]WHETHER[\#\s]IN[\#\s]CONTRACT,[\#\s]STRICT[\#\s]LIABILITY,[\#\s]OR[\#\s]TORT[\#\s].INCLUDING[\#\s]NEGLIGENCE[\#\s]OR[\#\s]OTHERWISE.[\#\s]ARISING[\#\s]IN[\#\s]ANY[\#\s]WAY[\#\s]OUT[\#\s]OF[\#\s]THE[\#\s]USE[\#\s]OF[\#\s]THIS[\#\s]SOFTWARE,[\#\s]EVEN[\#\s]IF[\#\s]ADVISED[\#\s]OF[\#\s]THE[\#\s]POSSIBILITY[\#\s]OF[\#\s]SUCH[\#\s]DAMAGE.\s(\#* \n)\|\1 SPDX-License-Identifier: BSD-3-Clause\n\n\|s' $(cat filelist) Change-Id: I7ff9c503a2efe1017a4666baf0b1a758a04f5634 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41204 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-11	treewide: Remove "this file is part of" lines	Patrick Georgi
	Stefan thinks they don't add value. Command used: sed -i -e '/file is part of /d' $(git grep "file is part of " \|egrep ":( /\.\/\$\|#\|;#\|-- \| \ )" \| cut -d: -f1 \|grep -v crossgcc \|grep -v gcov \| grep -v /elf.h \|grep -v nvramtool) The exceptions are for: - crossgcc (patch file) - gcov (imported from gcc) - elf.h (imported from GNU's libc) - nvramtool (more complicated header) The removed lines are: - fmt.Fprintln(f, "/* This file is part of the coreboot project. /") -# This file is part of a set of unofficial pre-commit hooks available -/ This file is part of coreboot / -# This file is part of msrtool. -/ This file is part of msrtool. / - This file is part of ncurses, designed to be appended after curses.h.in -/* This file is part of pgtblgen. / - This file is part of the coreboot project. - /* This file is part of the coreboot project. / -# This file is part of the coreboot project. -# This file is part of the coreboot project. -## This file is part of the coreboot project. --- This file is part of the coreboot project. -/ This file is part of the coreboot project / -/ This file is part of the coreboot project. / -;## This file is part of the coreboot project. -# This file is part of the coreboot project. It originated in the - This file is part of the coreinfo project. -## This file is part of the coreinfo project. - * This file is part of the depthcharge project. -/* This file is part of the depthcharge project. / -/ This file is part of the ectool project. / - This file is part of the GNU C Library. - * This file is part of the libpayload project. -## This file is part of the libpayload project. -/* This file is part of the Linux kernel. / -## This file is part of the superiotool project. -/ This file is part of the superiotool project / -/ This file is part of uio_usbdebug */ Change-Id: I82d872b3b337388c93d5f5bf704e9ee9e53ab3a9 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41194 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	mainboard/asus/p3b-f: Reintroduce as variant of p2b	Keith Hui
	Fold this last ASUS 440BX board into the P2B family, while bringing in some changes: - Devicetree becomes overridetree. - Remove non-existent IR device and disable ACPI device on Super I/O to match OEM firmware. - Add SB GPO settings from OEM firmware to devicetree. This disables the SPD enabling magic this board needs. By moving the enabling part to bootblock the hacky enable_spd hook can be eliminated. - Initialize the serial port in bootblock, like the other boards. Boot tested on hardware. Change-Id: I65f2cb9d1bd4c82550de43889e3502526a46bd18 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41047 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	mb/google/cyan/*: fixup GPIOs	Matt DeVillier
	Commit 73b723d [google/cyan: Switch Touchpad and Touchscreen...] in additon to changing the touchpad/touchscreen interrupts from edge to level triggered, also marked them as maskable. This was partially reverted in a86bbea0 [google/cyan: set touchscreen GPIO to non_maskable], but did not resolve all of the issues. Additionally, 73b723d also accidentally changed the pad interrupt select from L3 to L1 for all touchscreen GPIOs. Clean up this mess by setting all touchpad/touchscreen GPIOs back to maskable, and set the pad level to L3 for all touchscreen GPIOs. Tested on several cyan variants Change-Id: I70e8e2d4ff317c3b9b4108ed6c5bc80e9b0bbc75 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41176 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-11	mb/google/octopus/variants/dood: Disable XHCI LFPS power management	Kenneth Chan
	LTE module Fibocom L850-GL is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:155955302 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] are set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I88357f44317a5cff2e04508638eb065e5ada4c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/41143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2020-05-11	mb/intel/jasperlake_rvp: Turn off unused I2C lanes	Pandya, Varshit B
	Change-Id: Id49032c0f9b701fe12873c80e1bc0e4b64ba7106 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40859 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-11	mb/intel/jasperlake_rvp: Add support for SMI handler	Maulik V Vaghela
	SMI handler was not present in jasperlake rvp to handle wake events when platform goes to sleep or shutdown or s0ix. Adding this support for board which supports chromeec. BUG=None BRANCH=None TEST=Check wake event on board and platform wakes up due to events lid wake event or power button press. Change-Id: I8e35955b06d6efaf9275ec03f519c9bcaa9ba345 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-05-11	mb/google/kukui: fix screen scrolling on devices using anx7625	Paul Ma
	anx7625 enables MIPI receiver to check EOTP packet as default. If MIPI_DSI_MODE_EOT_PACKET is not set in flags, soc dsi will not send out EOTP packet and some panel models will display abnormal such as scrolling all the time. BUG=b:144824303 BRANCH=kukui TEST=boot damu board, edp panel with anx7625 as bridge boots up without scrolling. Signed-off-by: Paul Ma <magf@bitland.corp-partner.google.com> Change-Id: Iad651202bde2a40024af8c12153143ada2ce2439 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41161 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	mb/google/kukui: Fix backlight flash white before show logo	Jitao Shi
	Turn backlight off before panel poweron. BUG=b:155107047 TEST=make # board = kukui BRANCH=kukui Signed-off-by: Jitao Shi <jitao.shi@mediatek.com> Change-Id: I0f31923bd7c1dfa26d4b1bbd0a230ae400b08ca3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41146 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-11	mb/google/octopus: Fix default FMD	Matt DeVillier
	On Apollo Lake/Gemini Lake platforms, FSP requires more than a simple RW_MRC_CACHE; without the RECOVERY and VAR cache regions, FSP-m will fail on s3 resume and trigger a full reset instead. This fixes the default.fmd for octopus to match that used for reef. Test: build/boot google/ampton, verify sleep/resume works under Linux with 5.x kernel. Change-Id: I8565aa93256df7d6e0b359d70e9305f34e5ccb60 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-10	mb/google/kahlee: Hold WLAN PCIe reset low at boot for mordin	Kevin Chiu
	gpio70 is assigned to use as WLAN rst in new schematic to fulfill RTK RTL8822CE power sequence: WLAN rst will need to be active at least 50ms after WLAN power on. Also in order to keep the rst low in consistency, override default gpio70 to low. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I98c8afe42b7f92016f83483acbb3b9ae64b159f7 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40805 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-10	mb/google/kahlee: Don't reset the touchpad/screen on boot	Martin Roth
	touchpad & touchscreen power enable gets reset during resume causing unintended wake interrupts, causing dark resume failures. This prevents the board from being shut down after it's been suspended for a long period of time and can end up draining the battery. BUG=b:153173717 TEST=Build only - Needs to be tested by ODMs. Signed-off-by: Martin Roth <martin@coreboot.org> Change-Id: If403da8853e59eaaf589062c9bd6f10deb626998 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
2020-05-10	src/mainboard: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
	Change-Id: I64d9468682a4aae3084b17b8724d035f17d01dff Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-09	src/: Replace GPL boilerplate with SPDX header	Patrick Georgi
	Command used: perl -i -p0e 's\|(\#\#)[\w].is[\#\s]licensed[\#\s]under[\#\s]the[\#\s]terms[\#\s]of[\#\s]the[\#\s]GNU[\#\s]General[\#\s]Public[\#\s]License[\#\s]version[\#\s]2,[\#\s]as[\#\s]published[\#\s]by[\#\s]the[\#\s]Free[\#\s]Software[\#\s]Foundation,[\#\s]and[\#\s]may[\#\s]be[\#\s]copied,[\#\s]distributed,[\#\s]and[\#\s]modified[\#\s]under[\#\s]those[\#\s]terms.[\#\s]This[\#\s]program[\#\s]is[\#\s]distributed[\#\s]in[\#\s]the[\#\s]hope[\#\s]that[\#\s]it[\#\s]will[\#\s]be[\#\s]useful,[\#\s]but[\#\s]WITHOUT[\#\s]ANY[\#\s]WARRANTY;[\#\s]without[\#\s]even[\#\s]the[\#\s]implied[\#\s]warranty[\#\s]of[\#\s]MERCHANTABILITY[\#\s]or[\#\s]FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.[\#\s]See[\#\s]the[\#\s]GNU[\#\s]General[\#\s]Public[\#\s]License[\#\s]for[\#\s]more[\#\s]details.\s(# \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) Change-Id: Ia7ce0a78f96563b8dc0f6eb648c4ba4cefb2b838 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41180 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-09	src/: Replace GPL boilerplate with SPDX headers	Patrick Georgi
	Used commands: perl -i -p0e 's\|\/\[\s].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/ SPDX-License-Identifier: GPL-2.0-only /\|' $(cat filelist) perl -i -p0e 's\|\/\[\s].is[\s]free[\s]software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]either[\s]version[\s]2[\s]of[\s]the[\s]License,[\s]or[\s].at[\s]your[\s]option.[\s]any[\s]later[\s]version.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.[\s]\\/\|/* SPDX-License-Identifier: GPL-2.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|\/\[\s].is[\s#]free[\s#]software[;:,][\s#]you[\s#]can[\s#]redistribute[\s#]it[\s#]and/or[\s#]modify[\s#]it[\s#]under[\s#]the[\s#]terms[\s#]of[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]as[\s#]published[\s#]by[\s#]the[\s#]Free[\s#]Software[\s#]Foundation[;:,][\s#]either[\s#]version[\s#]3[\s#]of[\s#]the[\s#]License[;:,][\s#]or[\s#].at[\s#]your[\s#]option.[\s#]any[\s#]later[\s#]version.[\s#]This[\s#]program[\s#]is[\s#]distributed[\s#]in[\s#]the[\s#]hope[\s#]that[\s#]it[\s#]will[\s#]be[\s#]useful[;:,][\s#]but[\s#]WITHOUT[\s#]ANY[\s#]WARRANTY[;:,][\s#]without[\s#]even[\s#]the[\s#]implied[\s#]warranty[\s#]of[\s#]MERCHANTABILITY[\s#]or[\s#]FITNESS[\s#]FOR[\s#]A[\s#]PARTICULAR[\s#]PURPOSE.[\s#]See[\s#]the[\s#]GNU[\s#]General[\s#]Public[\s#]License[\s#]for[\s#]more[\s#]details.[\s]\\/\|/* SPDX-License-Identifier: GPL-3.0-or-later /\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\#\s]you[\#\s]can[\#\s]redistribute[\#\s]it[\#\s]and\/or[\#\s]modify[\#\s]it[\s\#]under[\s \#]the[\s\#]terms[\s\#]of[\s\#]the[\s\#]GNU[\s\#]General[\s\#]Public[\s\#]License[\s\#]as[\s\#]published[\s\#]by[\s\#]the[\s\#]Free[\s\#]Software[\s\#]Foundation[;,][\s\#]version[\s\#]2[\s\#]of[\s\#]the[\s\#]License.[\s\#]This[\s\#]program[\s\#]is[\s\#]distributed[\s\#]in[\s\#]the[\s\#]hope[\s\#]that[\s\#]it[\s\#]will[\#\s]be[\#\s]useful,[\#\s]but[\#\s]WITHOUT[\#\s]ANY[\#\s]WARRANTY;[\#\s]without[\#\s]even[\#\s]the[\#\s]implied[\#\s]warranty[\#\s]of[\#\s]MERCHANTABILITY[\#\s]or[\#\s]FITNESS[\#\s]FOR[\#\s]A[\#\s]PARTICULAR[\#\s]PURPOSE.[\#\s]See[\#\s]the[\#\s]GNU[\#\s]General[\#\s]Public[\#\s]License[\#\s]for[\#\s]more[\#\s]details.\s(# \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) perl -i -p0e 's\|(\#\#)[\w].is free software[:;][\s]you[\s]can[\s]redistribute[\s]it[\s]and\/or[\s]modify[\s]it[\s]under[\s]the[\s]terms[\s]of[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]as[\s]published[\s]by[\s]the[\s]Free[\s]Software[\s]Foundation[;,][\s]version[\s]2[\s]of[\s]the[\s]License.[\s]This[\s]program[\s]is[\s]distributed[\s]in[\s]the[\s]hope[\s]that[\s]it[\s]will[\s]be[\s]useful,[\s]but[\s]WITHOUT[\s]ANY[\s]WARRANTY;[\s]without[\s]even[\s]the[\s]implied[\s]warranty[\s]of[\s]MERCHANTABILITY[\s]or[\s]FITNESS[\s]FOR[\s]A[\s]PARTICULAR[\s]PURPOSE.[\s]See[\s]the[\s]GNU[\s]General[\s]Public[\s]License[\s]for[\s]more[\s]details.\s(#* \n)\|\1 SPDX-License-Identifier: GPL-2.0-only\n\n\|' $(cat filelist) Change-Id: Ia01908544f4b92a2e06ea621eca548e582728280 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41178 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08	mainboard///*.asl: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
	Change-Id: I5970cd188d06214d410949f4a3f8816c85c39451 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41141 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08	mainboard//.spd.hex: Replace GPLv2 long form headers with SPDX header	Elyes HAOUAS
	Change-Id: I3eb39d985f2712ab0a7a5a76b06ed625eb51c9d0 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41140 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-08	mb/google/reef: add G2 TS support for snappy	Kevin Chiu
	Add G2 GTCH7503 HID TS support spec from G2: G7500 / Ver.1.2 (3, April, 2018) BUG=b:155827595 BRANCH=master TEST=emerge-snappy coreboot Change-Id: I151bf141148f4f00b3dadd9c44ab3a6b7731cde1 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41090 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-07	mb/x9scl/early_init: Remove unused includes	Elyes HAOUAS
	Change-Id: I455a43ab6c4931a4fb1f717a65013b6b7cefb777 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40827 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06	treewide: replace GPLv2 long form headers with SPDX header	Patrick Georgi
	This replaces GPLv2-or-later and GPLv2-only long form text with the short SPDX identifiers. Commands used: perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.as.published.by.the.Free.Software.Foundation[;,].version.2.of.the.License.or.(at.your.option).any.later.version.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/ SPDX-License-Identifier: GPL-2.0-or-later /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.as.published.by.the.Free.Software.Foundation[;,].version.2.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This program is free software[:;].you.can.redistribute.it.and/or.modify.it.under.the.terms.of.the.GNU.General.Public.License.version.2.as.published.by.the.Free.Software.Foundation[.;,].+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only /\|s' $(cat filelist) perl -i -p0e 's\|/\[\n\t ]This software is licensed under.the.terms.of.the.GNU.General.Public.License.version.2.as.published.by.the.Free.Software.Foundation,.+This.program.is.distributed.in.the.hope.that.it.will.be.useful,.but.;.without.even.the.implied.warranty.of.MERCHANTABILITY.or.FITNESS.FOR.A.PARTICULAR.PURPOSE...See.the.GNU.General.Public.License for more details.[\n\t ]\/\|/* SPDX-License-Identifier: GPL-2.0-only */\|s' $(cat filelist) Change-Id: I7a746088a35633c11fc7ebe86006e96458a1abf8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06	treewide: move copyrights and authors to AUTHORS	Patrick Georgi
	Also split "this is part of" line from copyright notices. Change-Id: Ibc2446410bcb3104ead458b40a9ce7819c61a8eb Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-06	treewide: Move "is part of the coreboot project" line in its own comment	Patrick Georgi
	That makes it easier to identify "license only" headers (because they are now license only) Script line used for that: perl -i -p0e 's\|/\.\n.This file is part of the coreboot project.\n.\\|/* This file is part of the coreboot project. /\n/\|' # ...filelist... Change-Id: I2280b19972e37c36d8c67a67e0320296567fa4f6 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-06	soc/intel/tgl: Synchronize GPIO ASL table with Linux kernel	Shaunak Saha
	Kernel pinctrl driver changed for Tiger Lake and went to old scheme. Kernel patch: https://chromium-review.googlesource.com/c/chromiumos/ third_party/kernel/+/2116670 BUG=b:151683980 BRANCH=none TEST=Build and boot tgl board. In /sys/kernel/debug/pinctrl verify INTC34C5:00 listing all the pins. Cq-Depend:chromium:2116670 Change-Id: I9f1d399ff7380125ad5b935f9590a7d9cc442b04 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39801 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06	mb/google/dedede: Enable PMC, P2SB and PCH SPI in the devicetree	Karthikeyan Ramasubramanian
	BUG=None TEST=Build and boot the mainboard. Change-Id: I1aae4adf1c13fd4ff58aa38a877f34e142f320f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41037 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-06	mb/purism/librem_skl: select DRIVERS_GENERIC_CBFS_SERIAL	Matt DeVillier
	This driver was previously added for another out-of-tree Librem device, but forgot to switch over the librem_skl boards to use it. Remove duplicate functionality from mainboard.c and delete the empty file. Test: build/boot Librem 13v2 and verify serial number read from CBFS via dmidecode. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Ide952197335c6bfbad846c6d6f62be5c4c57e2cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41040 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-06	mb/purism/librem_{bdw,skl}: select MAINBOARD_HAS_TPM1	Matt DeVillier
	Current model Librems all have a TPM 1.2 module, so select it at the board level to avoid having to do so in .config. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Iab8b39c39aef2a3fc182f1a50091f84f2151a394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-05	mb/intel/jasperlake_rvp: Configure IP specific GPIOs	Maulik V Vaghela
	This patch configures all IP related GPIOs as per mainboard schematics. Till now, we were relying on FSP to do IP specific GPIO programming but now we'll program all GPIOs from mainboard. This will remove ambiguity of GPIO programming done by FSP and coreboot will do full GPIO programming Programming GPIOs of following IPs - I2C - Emmc - Display - CPU specific gpio (SLP lines) - Cnvi - SD BUG=None BRANCH=None TEST=compile coreboot and checked that all IP functionality working. Change-Id: I98583b768cbd8ab4af536b31d758cb1cee93edfb Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40572 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
2020-05-04	mb/purism/librem_skl: disable serial console output	Matt DeVillier
	Librem SKL/KBL boards do not have an exposed serial port interface. Set board Kconfig so that a default built image with Tianocore payload is bootable and doesn't hang due to trying to send data over a non-existant serial port. Test: build/boot librem 13v4 with board defaults + Tianocore Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I4c3f8a3c1726f804957b06b437b399291854a3f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40873 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-04	mb/purism/librem_skl: Clean up Kconfig	Matt DeVillier
	Reorder Kconfig selects alphabetically, and select the correct SoC for each variant (even though it currently makes no difference). Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I46f651a530ef0ed617dd1f3eee077e84279a40f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40913 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Michael Niewöhner Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04	mb/purism/librem_skl: rename variant directories	Matt DeVillier
	Since the same variant dirs are used by multiple versions of the same board, drop the v2/v3 labels. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: Id913e31ab52043e49769be9d3ebf6e71ecb0c856 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40912 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-05-04	mb/purism/librem_skl: Convert to use override devicetree	Matt DeVillier
	Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I3dac62a649e12ea2498d3ecafe03fd0d62af5f2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/40911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-04	mb/purism/librem_skl: Fix CLKREQ for 15v3 NVMe	Matt DeVillier
	Per the schematics, SRCCLKREQ2# is used for the NVMe and should be enabled. Enable CLKREQ for PCIe RP9, and adjust comments to indicate correct value used per schematic. Test: build/boot Librem 15v3 with NVMe drive, verify drive identified properly and no errors in boot log. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I159cb7ce1f5195d95c0229490c3bbde26edbd375 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-04	mb/purism/librem_skl: drop SataSpeedLimit restriction	Matt DeVillier
	SataSpeedLimit was set to 3Gbps to work around issues which are now known to be the result of incorrect FSP behavior. Since SataPwrOptEnable is now set at the SoC level and ensures the SIR registers are correctly programmed, we can re-enable 6Gbps operation without errors. Test: build/boot Librem 13v2 with both m.2 and 2.5" SATA drives, check dmesg for errors. Change-Id: I3565dc063724ad288ef92361942fcdc14daac17e Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40909 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04	soc/intel/skl: always enable SataPwrOptEnable	Michael Niewöhner
	For unknown reasons FSP skips a whole bunch of SIR (SATA Initialization Registers) when SataPwrOptEnable=0, which currently is the default in coreboot and FSP. Even if FSP's default was 1, coreboot would reset it. This can lead to all sorts of problems and errors, for example: - links get lost - only 1.5 or 3 Gbps instead of 6 Gbps - "unaligned write" errors in Linux - ... At least on two boards (supermicro/x11-lga1151-series/x11ssm-f and purism/librem13v2) SATA is not working correctly and showing such symptoms. To let FSP correctly initialize the SATA controller, enable the option SataPwrOptEnable statically. There is no valid reason to disable it, which might break SATA, anyway. Currently, there are no reported issues on CML and CNL, so a change there could not be tested reliably. SKL/KBL was tested successfully without any noticable downsides. Thus, only SKL gets changed for now. Change-Id: I8531ba9743453a3118b389565517eb769b5e7929 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40877 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04	mb/up/squared: Fix eMMC speed for UP2 with EDK2	Patrik Tesarik
	Since commit 402fe20e (mb/up/squared: Add mainboard) the UP2's eMMC maximum host speed was reduced to DDR50, because HS200 showed I/O errors in the host kernel. We found out that with EDK2 master the correct Host Speed could not be set properly during EDK2 platform init. Therefore eMMC would not show up for boot device selection. This commit sets the eMMC MaxHostSpeed to the designed max value of the used eMMC on the UP2 board and furthermore drops the override from the ramstage.c. It's already set in the devicetree.cb. Though CRC errors are still visible in EDK II debug logs, no other negative effects have been observed. Signed-off-by: Patrik Tesarik <mail@patrik-tesarik.de> Change-Id: I8d53204d8a776efd560fbdea918f83e180813179 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-04	mb/google/dedede: Read DRAM part number from CBI	Marco Chen
	The index of MEM_STRAPS will be migrated from per DRAM part number to per DRAM characteristic therefore one index mapped to a single SPD binary can represent to multiple DRAM part numbers as long as their characteristic is the same for DRAM controller to support. In this case, the real DRAM part number would be provisioned in the CBI instead of SPD in the factory flow. As a result, we need to extract DRAM part number from CBI. BUG=b:152019429 BRANCH=None TEST=1. provision dram_part_num field of CBI 2. check DRAM part number is correct in SMBIOS for memory device Change-Id: I40780a35e04efb279591e9db179cb86b5e907c0d Signed-off-by: Marco Chen <marcochen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40836 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-04	mb/**/dsdt.asl: Drop unused BRIGHTNESS_{UP,DOWN}	Angel Pons
	It is only used with the Lenovo-specific H8 EC code. Change-Id: If3b209a9ab82a07ce7b4450d8a0b62a1ca86a95c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-04	treewide: Drop ACPI_VIDEO_DEVICE macro	Angel Pons
	It was always defined to the same value, and only used twice. Change-Id: I2736eb7ea2cf15475f7bb99d7d12450730eb8be0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40864 Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-04	mb/**/dsdt.asl: Drop unused ACPI_VIDEO_DEVICE	Angel Pons
	It is only used with the Lenovo-specific H8 EC code. Change-Id: I596d4d19277555894ab728e32a44e34a5a21e21d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40863 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-04	asus/p2b: Enable IDE and UDMA for all variants	Keith Hui
	There's no reason not to. Change-Id: I12c9e0f66c437d8add5c4096fd2a5e747d082799 Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40961 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-05-02	mb/asus/p8h61-m_pro: Disable SVID LDN	Angel Pons
	The SVID functionality is not used on this mainboard. Turn it off. Change-Id: Iea891975b32d24f54edec9d8c36391ec60a37d0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40739 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-02	mb/asus/p8h61-m_pro: Disable SB-TSI base address	Angel Pons
	SB-TSI is specific to AMD platforms, but this is an Intel board. Change-Id: I5eb7e3bc920103279dfca3a9ec14a41666404993 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40738 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02	mb/asus/p8h61-m_pro: Fix function of pin 70	Angel Pons
	The board uses the pin for Deep S5, but the code was setting 3VSBSW. Change-Id: I81c865358002e6af500658efea851ab8c8202950 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40737 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-05-02	acpi: Move ACPI table support out of arch/x86 (3/5)	Furquan Shaikh
	This change moves all ACPI table support in coreboot currently living under arch/x86 into common code to make it architecture independent. ACPI table generation is not really tied to any architecture and hence it makes sense to move this to its own directory. In order to make it easier to review, this change is being split into multiple CLs. This is change 3/5 which basically is generated by running the following command: $ git grep -iIl "arch/acpi" \| xargs sed -i 's/arch\/acpi/acpi\/acpi/g' BUG=b:155428745 Change-Id: I16b1c45d954d6440fb9db1d3710063a47b582eae Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-05-02	mb/asus/p2b*: Get rid of power button device	Keith Hui
	These boards have the same issue as [27272]: Currently, two power buttons are exposed in ACPI, and detected by the operating system. > As per the ACPI specification, there are two types of power button > devices: > 1. Fixed hardware power button > 2. Generic hardware power button > > Fixed hardware power button is added by the OSPM if POWER_BUTTON flag > is not set in FADT by the BIOS. This device has its programming model > in PM1x_EVT_BLK. All ACPI compliant OSes are expected to add this > power button device by default if the power button FADT flag is not > set. > > On the other hand, generic hardware power button can be used by > platforms if fixed register space cannot be used for the power button > device. In order to support this, power button device object with HID > PNP0C0C is expected to be added to ACPI tables. Additionally, > POWER_BUTTON flag should be set to indicate the presence of control > method for power button. > > [i440BX] mainboards implemented the generic hardware power button in > a broken manner i.e. power button object with HID PNP0C0C is added to > ACPI however none of the boards set POWER_BUTTON flag in FADT. This > results in Linux kernel adding both fixed hardware power button as > well as generic hardware power button to the list of devices present > on the system. Though this is mostly harmless, it is logically > incorrect and can confuse any userspace utilities scanning the ACPI > devices. Hardware tests on the P2B-LS shows the generic hardware power button is not working anyway - with FADT power button flag set, the board could not power off with the button. This change removes the generic hardware power button from all P2B mainboards and relies completely on the fixed hardware power button. TEST=Booted on P2B-LS, Linux detects only fixed hardware power button, button still powers off. [27272]: https://review.coreboot.org/27272 Change-Id: I0f5b7aaf32366360de3cce58cd742651a2bb46ba Signed-off-by: Keith Hui <buurin@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02	mb/google/reef: Add and use VBT	Matt DeVillier
	Add VBT file, and override use via Kconfig since all Reef variants use the same VBT file. VBT extracted from firmware in ChromeOS recovery image. Test: built/boot google/reef w/FSP display init Change-Id: I31156ec7371c0443719fdd9ddac6ed4960c83767 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02	mb/purism/librem_bdw: Convert to use override devicetree	Matt DeVillier
	Since the variants' devicetrees are almost identical, convert to using an overridetree setup for simplicity. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I07fb5a09e578bf299081b26e010317385a6c5f7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02	mb/purism/librem_bdw: Clean up 15v2 devicetree	Matt DeVillier
	The Librem 15v2 only uses SATA ports 0/1, so the DTLE settings for ports 2/3 have no consequence. Drop them to make overridetree conversion cleaner. Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Change-Id: I4145feecb389be90f317249426e58752c03aef76 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40914 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-02	mainboard/google/kahlee: Add hook for early wlan rst gpio init	Kevin Chiu
	Base on the grunt board schematic, gpio70 is an alternative way for wlan rst. Add hook for variants to override default state. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Change-Id: Ic3f1c016357dd5090e6adedf96e7593abff29a0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-02	payloads/seabios: Add Hardware IRQ Kconfig	Matt DeVillier
	Certain boards require SeaBIOS' HARDWARE_IRQ option to be deselected in order for the platform to boot. Add a Kconfig to allow selection of HARDWARE_IRQ enablement, and write to SeaBIOS' .config file in cases where it needs to be disabled. Deselect the option for google/rambi variants so they boot with boards defaults. Test: build/boot google/clapper, verify board boots vs hanging at boot menu prompt. Change-Id: I23e9b30d2d1042c86bd10f134d6fe361edaf8cb2 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39869 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02	mb/google/reef: add default non-ChromeOS FMAP	Matt DeVillier
	Add a FMAP which supports SMMSTORE and non-ChromeOS payloads, since Apollo Lake-based devices like Reef cannot use an automatically-generated FMAP due to strict layout requirements. Change-Id: If570f92f4f81c0e29777c87756fc5e45af549064 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-02	mb/supermicro/x11: drop DeepSx config from devicetree	Michael Niewöhner
	Drop the DeepSx config as it's unsupported and disabled for the boards. Change-Id: I91cd15b26a41f376561630cf45ffa192745eae84 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40858 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01	mb/intel/cedarisland_crb: Enable P2SB device	Andrey Petrov
	Enable P2SB in static device tree so that hide/unhide trick works. Change-Id: I7dc20b001605b715155d333a07580e21a5f24136 Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01	mb/intel/cedarisland_crb: Populate 2-socket parameters for FSP-M	Andrey Petrov
	These parameters were found to work fine for 2-socket configuration, for FSP based on tag 16.D.21. Signed-off-by: Andrey Petrov <anpetrov@fb.com> Change-Id: I466a7f2951ef307036ddaed0be0aacf98dd2710f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01	md/tiogapass: move all *.h to dir and make them global	Maxim Polyakov
	It is necessary to rename the file gpio.h so that there are no conflict with another file (src/include/gpio.h) Change-Id: I4e3ef5882d6cb0ddbcb8357b54106ff2f47e4c51 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40733 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01	xeon_sp, ocp/tiogapass: remove unused FSP-style GPIO defs	Maxim Polyakov
	Change-Id: I8599dca99c1f34e3937c5b77b3505815ce625b46 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39453 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01	mb/ocp/tiogapass: fix advanced _PAD_CFG_STRUCT macros in config	Maxim Polyakov
	If the current pad configuration can not be defined using standard macros from the gpio_defs.h [1], then the intelp2m utility generates "advanced" _PAD_CFG_STRUCT() macros. However, often this configuration in the vendor’s firmware is erroneous. Change the extended macros to standard ones taking into account the information based on the schematic diagram and the previous GPIO configuration for FSP-M [2]. [1] src/soc/intel/common/block/include/intelblocks/gpio_defs.h [2] src/mainboard/ocp/tiogapass/skxsp_tp_gpio.h Change-Id: I56e45b1df77acbdd67e6325c3745a7ad137f8805 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40732 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01	mb/ocp/tiogapass: rework GPIOs configuration using macros	Maxim Polyakov
	This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file tiogapass/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input (GPI). The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: I21e98721e58b00be9196927837daa2b5d2560822 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40731 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01	mb/tiogapass: use common driver to configure GPIO	Maxim Polyakov
	According to changes in the soc/xeon_sp code [1,2], server motherboards with Lewisburg PCH can use the soc/intel/common/gpio driver to configure GPIO controller. This patch adds pads configuration map, which has the format required by the GPIO driver. The data for this was taken from the inteltool register dump with AMI firmware. The gpio.h file with pad configuration was generated automatically using the util/intelp2m [3]: ./intelp2m -raw -p lbg -file tiogapass/vendorbios/inteltool_gpio.log [1] https: //review.coreboot.org/c/coreboot/+/39425 [2] https: //review.coreboot.org/c/coreboot/+/39428 [3] https: //review.coreboot.org/c/coreboot/+/35643 Change-Id: I818d040fa33f3e7b94b73c9bbbafca5df424616d Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39427 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01	mb/ocp/sonorapass: Populate FSP-M parameters	Andrey Petrov
	Since CPX FSP headers are not released yet, populate certain settings with hard-coded offsets. Provided values are probably not correct and I do not understand what they mean and there is no documentation available yet. However they were found to work to a certain degree. TEST=tested on OCP Sonora Pass EVT Change-Id: I0f78cde69cb8a49a388a412b97bf8713e5b380ea Signed-off-by: Andrey Petrov <anpetrov@fb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40554 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01	mb/ocp/sonorapass: Add Sonora Pass	Ryback Hung
	Just a minimal set of board files needed to get it to boot in 1 CPU mode. Signed-off-by: Ryback Hung <ryback.hung%quantatw.com@gtempaccount.com> Change-Id: Ia7b45c78b38d091bd9535899b681746e13efb4fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/40469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com>
2020-05-01	mb/google/dedede: Fix crossystem wpsw_cur error	Subrata Banik
	Add GPIO_PCH_WP (GPP_C11) to associate GPP_PCH_WP with community zero. TEST=Build coreboot, flash, boot to and log into kernel, execute "wp enable" in console, execute "crossystem" at kernel prompt and verify that "wpsw_cur" shows as being "1", Execute "wp disable" in console, execute "crossystem" at kernel prompt and verify "wpsw_cur" is 0. Change-Id: Ie4ae1365a7611b8be3e795798c171e3f7ea9e417 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40744 Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01	mb/google/deltaur: Add BT reset gpio	Eric Lai
	Harrison Peak (HrP) 9560 module needs a reset pin for BT power sequence. BUG=b:155248677 TEST=Boot into OS and check BT is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I55ed1b095ba53c414c44088f4a6e7720b970e2f2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40831 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-05-01	mb/google/deltaur: Update USB/WWAN config	Ivy Jian
	Update USB3 ports configuration as schematics design. BUG=b:155026295 TEST=Boot into OS and check WWAN device detected by lsusb. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Icb938e5a9c05fcc9772219b081a6f05334261baf Reviewed-on: https://review.coreboot.org/c/coreboot/+/40818 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01	mainboard/google/kahlee: move specific setting to variant	Kevin Chiu
	Separate specific setting to variant from baseboard. baseboard/romstage.c in current release is only utilized by careena, we could remove it from the rest of variant build. BUG=b:154357210,b:154848243 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I658526e44aadc47bdc5538f506a1bfe2e5f20f63 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40796 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-05-01	mb/google/octopus/variants/bobba: Disable XHCI LFPS power management	Sheng-Liang Pan
	LTE module is lost after idle overnight, with this workaround, host will not initiate U3 wakeup at the same time with device, which will avoid the race condition. Disable XHCI LFPS power management. If the option is set in the devicetree, the bits[7:4] in XHCI MMIO BAR + offset 0x80A4 (PMCTRL_REG) will be updated from default 9 to 0. BUG=b:146768983 BRANCH=octopus TEST=build coreboot with DisableXhciLfpsPM being set to 1 and flash the image to the device. Run following command to check if bits[7:4] is set 0: >iotools mmio_read32 "XHCI MMIO BAR + 0x80A4" Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Ib8e5ae79e097debf0c75ead232ddbb2baced2a2a Reviewed-on: https://review.coreboot.org/c/coreboot/+/40303 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2020-05-01	mb/google/volteer/malefor: Enable touch screen	William Wei
	Enable Goodix touch screen and ensure it works properly. BUG=b:154191288 TEST=FW_NAME=malefor emerge-volteer coreboot chromeos-bootimage Boot to kernel and check the Goodix touch screen function. Signed-off-by: William Wei <wenxu.wei@bitland.corp-partner.google.com> Change-Id: I236ac56dd0a1817092151bae93e699115ba88e4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/40598 Reviewed-by: Alex Levin <levinale@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-05-01	mb/purism/librem_skl: Use ACPI backlight controls	Benjamin Doron
	Enables ACPI backlight controls. Change-Id: Iccf50f427b7555ee1a3ef9cc11a89d532789ac54 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40145 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2020-05-01	mb/google/hatch/vr/puff: Add psys_pmax calculation	Tim Chen
	This patch adds psys_pmax calculation. There are two types of power sources. One is barrel jack and the other is USB TYPE-C. The voltage level is fixed for a barrel jack while TYPE-C may vary depending on power ratings. We need to get voltage information from EC and calculate correct psys_pmax value. The psys_pmax needs to be set before FSP-S since FSP-S will handle the setting passing to pcode, so move the routine ahead to variant_ramstage_init. BUG=b:151972149 TEST=emerge-puff coreboot chromeos-bootimage check firmware log and ensure psys_pmax is passed to FSP check the data from dump_intel_rapl_consumption in the OS and ensure the power data is close to an external power meter. Change-Id: Iff767d4b44a01e766258345545438a54a16d1af5 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40828 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-05-01	mb/google/dedede: Enable USB port for camera support	Ian Feng
	Support USB Chicony user facing camera. BUG=b:155109736 BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using user facing camera. Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Change-Id: I7580a58086977e239dca49c1def4f03583831662 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40774 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01	mb/intel/jasperlake_rvp: Select PcieRpClkReqDetect in device tree	Meera Ravindranath
	This CL selects the PcieRpClkReqDetect for the required root ports which is needed to allow proper clksrc gpio configuration. Also, sets the unused PcieClkSrcUsage to 0xFF. BUG=None BRANCH=None TEST=Build and boot jslrvp with NVMe Change-Id: Ie4ae1365a7621b8be3b795798c171e3f7ea9e487 Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40758 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-05-01	src: Remove not used 'include <smbios.h>'	Elyes HAOUAS
	Change-Id: I12345a5b6c9ce94ca9f8b555154b2278a8ff97bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-05-01	mb/google/dedede: Remove pad termination for RAM_STRAP_4	Karthikeyan Ramasubramanian
	The stuffed resistor straps are weaker compared to the internal pull-up. This can cause the GPIO to read '1' always. Remove the internal pull-up. Also read the GPIO only on the boards where the board version is populated. BUG=b:154301008 TEST=Build and boot the mainboard. Change-Id: Ib640211b9f50dfb0174a570eda1625bacbebb855 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40531 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-01	Helios: Update DPTF settings for smooth fan speed control	Sumeet R Pawnikar
	Update DPTF settings for smooth fan speed control. BRANCH=firmware-hatch-12672.B BUG=b:154074920 TEST=Built and test on Helios system Change-Id: I3f4d9fd9e17541dd5fb7982a8b43a039c41cba87 Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40530 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01	mb/google/dedede: Enable camera support for waddledoo	Pandya, Varshit B
	BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: I51dcf96a82535fc1e0b9247fd52af919885575e5 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40476 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01	mb/google/dedede: Add ACPI support for camera	Pandya, Varshit B
	1. Add support as per the schematics 2. Add 2 Ports and 2 Endpoints 3. Add support for OTVI8856 and OTVI5676 4. Add ON and OFF logic as Power Rails are same for both sensor BUG=None BRANCH=None TEST=Build and Boot waddledoo board and able to capture image using world facing camera. Change-Id: Ic8687bce4896d9fc17b2190b8d11618af3515cc1 Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01	mb/google/dedede: add new variant for wheelie	Peichao Wang
	Add initial support for wheelie variant board. BUG=b:154664137 BRANCH=None TEST=build Change-Id: Id638e987f45c247dae824f221a38ccf32626572f Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-05-01	mb/google/nightfury: Tune the usb2_port[0] strength	Seunghwan Kim
	Update usb2 port strength parameter for usb2_port[0] to improve SI. BUG=b:154668734 BRANCH=firmware-hatch-12672.B TEST=Built and checked SI margin of USB2 ports Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I8b4b58a67dc0835a677770a2968e8d8d61e0374f Reviewed-on: https://review.coreboot.org/c/coreboot/+/40622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-05-01	mb/ocp/tiogapass: Update UPD IIO bifurcation at run-time	Johnny Lin
	Update UPD IIO bifurcation at run-time according to different Riser cards. For detail please reference Facebook Server Intel Motherboard v4.0, Sec. 10.1.2 Riser card types. With the engineering build FSP, it can only configure IIO for one socket so my local test needs to remove all socket1 elements from tp_iio_bifur_table. This change relies on [1] and need to add GPP_C15 and GPP_C16 to early_gpio_table for gpio configuration in bootblock. [1] https://review.coreboot.org/c/coreboot/+/39427/ Tested=OCP Tioga Pass can see socket0 IIO being updated with an engineering build FSP. Change-Id: I8e63a233a2235cd45b14b20542e6efab3de17899 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39895 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-04-30	mb/cedarisland_crb: rework GPIOs configuration using macros	Maxim Polyakov
	This format of PCH GPIOs configuration, unlike the raw DW0 and DW1 registers values from the inteltool dump, is more understandable and makes the code much cleaner. The gpio.h file with PAD_CFG macros was automatically generated using the util/intelp2m [1] utility: ./intelp2m -p lbg -file cedarisland/vendorbios/inteltool_gpio.log According to the documentation [2], the Host Software Pad Ownership register only affects the pads that are configured as input. The intelp2m utility takes this into account when converting macros and ignores bits from this register for the corresponding pads. [1] https://review.coreboot.org/c/coreboot/+/35643 [2] Intel Document Number: 549921 Change-Id: Id671a9021a8313d8c3359b89c2934b929bcab1a4 Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40736 Reviewed-by: Andrey Petrov <andrey.petrov@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>