summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2016-07-05siemens/mc_bdx1: Set up MAC address for available i210 MACsWerner Zeh
Enable the usage of DRIVER_INTEL_I210 and provide a function to search for a valid MAC address for all i210 devices using hwilib. Change-Id: Ic0f4f1579364cf5b0111334a05a8a0926785318b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15517 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-05intel/i210: Change API for function mainboard_get_mac_address()Werner Zeh
The function mainboard_get_mac_address() is used to get a MAC address for a given i210 PCI device. Instead of passing pure numbers for PCI bus, device and function pass the device pointer to this function. In this way the function can retrieve the needed values itself as well as have the pointer to the device tree so that PCI path can be evaluated there. Change-Id: I2335d995651baa5e23a0448f5f32310dcd394f9b Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/15516 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-07-02google/reef: Add DA7219 support in acpiSathyanarayana Nujella
Add DA7219 support in acpi. DA7219 has advanced accessory detection functionality. Also add DA7219's AAD as a ACPI data node. Change-Id: I979275cb2ab1e593ff1e5d360bea83b843e45032 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/15436 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-02amd/olivehillplus: Fix PCIe lane number comments.Derek Waldner
Correct the GPP PCIe lane number comments so that they match the code. Change-Id: If27c6a55ebedb0927dd9e8c7c9a833194e129a25 Signed-off-by: Derek Waldner <derek.waldner.os@gmail.com> Reviewed-on: https://review.coreboot.org/15095 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-07-02google/reef: ACPI: Move touchpad to SSDT and remove TPMDuncan Laurie
Instantiate the touchpad using the drivers/i2c/generic device driver to generate the ACPI object in the SSDT. There is not currently a separate wake pin for this device, this will be added in EVT hardware. This was tested on the reef board by ensuring that the touchpad device continues to work in the OS. Also remove the LPC TPM from the DSDT as it is not present. Change-Id: I3151a28f628e66f63033398d6fab9fd8f5dfc37b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15481 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01mainboard/google/reef: Configure DDI0, DDI1 HPD GPIO linesAbhay Kumar
Configure GPIO_199 and GPIO_200 as NF2 to work as HPD. Change-Id: If3aa6b75ed22c221cfbedaecf16035cdd9939387 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Reviewed-on: https://review.coreboot.org/15447 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-07-01mainboard/google/reef: Use common NHLTSaurabh Satija
Add ACPI NHLT table generation that the current hardware supports. Reef supports two audio codecs, Dialog 7219 for headsets and Maxim 98357 for speakers. Change-Id: Ie39947960c86b8f65140834e31f9ed9f1b578485 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15440 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-07-01mainboard/intel/amenia: add NHLT supportSaurabh Satija
Add ACPI NHLT table generation that the current hardware supports as well select the hardware used on the board. Amenia has support for two audio codecs, Dialog for headsets and Maxim for speakers. Change-Id: Iaba9ec81ffb4f128f2e4413dec5174d9ecb856c9 Signed-off-by: Saurabh Satija <saurabh.satija@intel.com> Reviewed-on: https://review.coreboot.org/15024 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29intel romstage: Use run_ramstage()Kyösti Mälkki
Change-Id: I22a33e6027a4e807f7157a0dfafbd6377bc1285d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15461 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-29google/reef: set 20K PULLUP on SDCARD DATA/CLK/CMDFreddy Paul
SD card need 20K PULLUP on D0-D3/CLOCK/COMMAND lines. Without this SDCARD will throw data read/write errors. BUG=chrome-os-partner:54676 TEST=Build and boot to OS. Verify SD card is detected and data read/write works well. Change-Id: I90da5b84dc2e488eb38f805322bd7b4dee394e5b Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/15345 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-28intel/amenia: Configure unused PadsJagadish Krishnamoorthy
Configure unused Pads as NC and sort the pads according to the gpio community. Move the pad configurations from mainboard to gpio.h BUG=none TEST=Boot to OS and check all functionalities. Change-Id: I8e9eeebf5d75c71c521649c72612c06f3fa43701 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15327 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-28google/reef: disable unused devicesJagadish Krishnamoorthy
BRANCH=none BUG=chrome-os-partner:54325, chrome-os-partner:54581 TEST=device off in devicetree should disable the device. Change-Id: I5dada06cba0eea8a30f297e3a6940a36b2ff40ee Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15339 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-27intel/amenia: disable unused devicesJagadish Krishnamoorthy
BRANCH=none BUG=chrome-os-partner:54325 TEST=device off in devicetree should disable the device. Change-Id: I486a4c5e8970047477068e22b799d06caea03330 Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://review.coreboot.org/15338 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-26intel/nehalem: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: Ic82a732ba28ba24e42a635539cca3d76128b40b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15247 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-26intel/gm45: Use common ACPI S3 recoveryKyösti Mälkki
Change-Id: I3148dbbcb06676f48b6bc357124403b70b9bcb6a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15246 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-24rockchip/rk3399: provide multiple SDRAM configurationsLin Huang
We want to be able to easily change SDRAM clock rate for debugging purposes. This patch adds configurations for 4 different clock rates. Same configs are used for all rk3399 boards at 200, 666 and 800 MHz. Kevin board does not run reliably at 666 MHz, an option for it is added to run at 300 MHz, this option is available to Kevin only. There is not much room left in the coreboot romstage section, this is why the config file for 928 MHz is being added with this patch but is not included in the code, one of the lower frequency options will have to be dropped for the higher frequency option to be added. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 3600" and pass on both kevin and gru. Verified that on Kevin the firmware reports starting up SDRAM at 300 MHz and on Gru at 800 MHz. Change-Id: Ie24c1813d5a0e9f0f9bfc781cade9e28fb6eb2f1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ef5e4551b79c3f0531f9af35491f2c593f8482f1 Original-Change-Id: I08bccd40147ad89d851b995a8aab4d2b6da8258a Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353493 Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15309 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add elog supportSimon Glass
Add code to start up elog. This uses the EC RTC to obtain the timestamp. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages Change-Id: I4971d661b267ae8b7e3befeff482ca703b741743 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e4e9823d8cecbf9873e78b048e389c7a737ff512 Original-Change-Id: I0fcf55b3feccf9a0ad915deb6d323b65bf2e9811 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353822 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15306 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Add get_developer_mode_switch()Simon Glass
Add this function and make it return 0, as there is no physical dev switch (at least I think this is what we are supposed to do). This is needed for elog to work, which is needed so we can test RTC properly. BUG=chrome-os-partner:52220 BRANCH=none TEST=boot on gru with CONFIG_ELOG_DEBUG enabled and see elog messages: elog_init() SF: Detected W25Q64 with sector size 0x1000, total 0x800000 elog_find_flash() FMAP: area RW_ELOG found @ 5d8000 (32768 bytes) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) ELOG: flash area invalid elog_flash_erase(address=0x000000000031d668 offset=0x005d8000 size=4096) SF: Successfully erased 4096 bytes @ 0x5d8000 elog_prepare_empty() elog_flash_write(address=0x000000000031d668 offset=0x005d8000 size=8) elog_scan_flash() elog_is_buffer_clear(base=0x000000000031d668 size=4096) elog_is_header_valid() elog_update_event_buffer_state() elog_is_buffer_clear(base=0x000000000031d670 size=4088) elog_is_area_valid() ELOG: FLASH @0x000000000031d668 [SPI 0x005d8000] ELOG: area is 4096 bytes, full threshold 3834, shrink size 1024 elog_add_event_raw(type=16) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d670 offset=0x005d8008 size=11) ELOG: Event(16) added with size 11 elog_add_event_raw(type=17) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d67b offset=0x005d8013 size=13) ELOG: Event(17) added with size 13 elog_add_event_raw(type=A0) out: cmd=0x44: 03 b9 44 00 00 00 00 00 in-header: 03 3f 00 00 04 00 00 00 in-data: 6e 4c 00 00 elog_flash_write(address=0x000000000031d688 offset=0x005d8020 size=9) ELOG: Event(A0) added with size 9 elog_add_boot_reason: Logged dev mode boot I can't actually see the timestamp, but the EC traffic is visible. Change-Id: I82bcf296dce4f4d146edf90b23bfae955fbe9e3a Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ffc7a7e0e7b136144d2a0b2ed21a543eafee49fa Original-Change-Id: I1489c6b874cc49495635aec0bf303f7098455716 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/353821 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@google.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15305 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Show the current time on start-upSimon Glass
Display the current time from the EC. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) boot on gru and see output: Date: 1970-01-17 (Saturday) Time: 1:42:44 Then reboot ~10 seconds later and see output: Date: 1970-01-17 (Saturday) Time: 1:42:53 Change-Id: I4288efc56f00e47f7575d0379a44871351da6200 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: d0361193e0ec135e21f0611d7fa6e5c02f2b2bfc Original-Change-Id: I04a072c788ba3fc915e6d73703f966955bbd3e7e Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351783 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15304 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24gru: Enable EC-based RTCSimon Glass
Obtain the real-time clock value from the EC on start-up and show the current time. BUG=chrome-os-partner:52220 BRANCH=none TEST=(partial) with future commits and EC clock set, boot on gru into Linux shell and check the firmware log: localhost ~ # grep Date: /sys/firmware/log Date: 2016-06-20 (Monday) Time: 18:09:16 Change-Id: Id3ef791f546419c4881a891251cbb62d7596884b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 348e9373b0e95a17f5c39ec28a480712e6e45caf Original-Change-Id: Iff43b16a86d9fee483420ee2eff5ff3d276716a3 Original-Signed-off-by: Simon Glass <sjg@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/351781 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15303 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24region: Add writeat and eraseat supportAntonello Dettori
Implement writeat and eraseat support into the region_device_ops struct. Change-Id: Iac2cf32e523d2f19ee9e5feefe1fba8c68982f3d Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/15318 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-24intel/kunimitsu: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tesed on a Chell mainboard since I lack a kunitmisu device. I used different GPIOs across boots to verify that the different audio codec devices would be "detected" and generated in the SSDT. Change-Id: I9b3b2247a84aeb7c07780958377d5bea14417ce6 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15317 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/lars: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was tested on a Chell mainboard since I lack a lars device. Change-Id: Ifba6fc6589ddd54f4c85e8858f17997fbb4b6176 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15316 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/glados: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified on a glados board by verifying the SSDT contents against what used to be in the DSDT. Change-Id: I710cbb8462d0fe695297102a64bec8e4212acc65 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-24google/chell: Move devices from mainboard.asl to devicetreeDuncan Laurie
Declare the mainboard attached devices in the devicetree and enable the provided device drivers by default to generate the ACPI objects for these devices. Then remove the static ACPI objects from the DSDT in mainboard.asl. This was verified by comparing the generated ACPI code in the SSDT to what was in mainboard.asl and ensuring the contents are functionally equivalent. Change-Id: I4725bbe2d47178568e3024fe3bb48cc80ff861c3 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15314 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-23samsung/lumpy: Fix build with System Agent blobKyösti Mälkki
Broken with commit: 2585209 mb/samsung/lumpy/romstage: read SPD data of removable DIMM The blob can pick SPDs from the addresses defined in pei_data and we do only define read_spd() with USE_NATIVE_RAMINIT. Change-Id: Ibd6d7a4a53fa808b476d3060872cb10d3dfce534 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15329 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-23intel/sandybridge: Fix builds with System Agent blobKyösti Mälkki
Broken with commit: 5c10abe nb/intel/sandybridge: increase MMCONF_BASE_ADDRESS Available sandybridge/systemagent-r6.bin has MMCONF hard-coded at some places and samsung/lumpy fails at boot here: CBFS: Locating 'mrc.bin' CBFS: Found @ offset 9fec0 size 2fc94 System Agent: Starting up... System Agent: Initializing These are the last lines as captured over USB debug. Change-Id: I441847f0e71a5e1be9c8ef6a04a81eb7bdd8a6d9 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15328 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23google/reef: Update chromeos.fmd fileFurquan Shaikh
1. Mark 256KiB at end of BIOS region as unusable BIOS region is memory-mapped just below 4GiB, however last 256KiB is unusable. Mark it accordingly in fmd file. 2. Use up holes in RW region for RW_A and RW_B. 3. Fill up holes in RO with UNUSED regions. BUG=chrome-os-partner:54672 Change-Id: I5facc566bb70d950522e12228b0631ddf00ac63d Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15313 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-23rockchip/rk3399: correct sdram inc file DENALI_CTL_217_DATA valueLin Huang
for per cs training, there should be more cycles to switch delay line. so increase W2W_DIFFCS_DLY_F0 value from 0x1 to 0x5. BRANCH=none BUG=chrome-os-partner:54144 TEST=run "stressapptest -M 1024 -s 1000" and pass Change-Id: I11720b7c6f009789b88ca26fc5da88597ed1622e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9de93beae09174d50a31d2df655529f71628f77c Original-Change-Id: Ide23fff04fd63fb0afc538b610b7685756f79f8d Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/352953 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Derek Basehore <dbasehore@chromium.org> Reviewed-on: https://review.coreboot.org/15307 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-23gru: kevin: initialize cr50 SPI interfaceVadim Bendebury
Set up the pins and initialize the driver. BRANCH=none BUG=chrome-os-partner:50645, chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to communicate with the cr50. Change-Id: I9fc1cb84ccababa6f58b2d5beec4572dc1d79da1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 6100471db2a00fd411afc05d621429b8f8a2f81d Original-Change-Id: I0ccd8777288e35870658268813c9202dd850c70d Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349852 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/15296 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-22mainboard: Remove use of IFD_BIOS_START/IFD_BIOS_ENDFurquan Shaikh
BUG=chrome-os-partner:54563 Change-Id: If07710333cbb84ce70d6d4fa40602a74c898c08a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15293 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-22intel/model_2065x: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I616143b55d7c5726dc2475434e3fcb08b8d69bda Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15230 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21rockchip: kevin/gru: Slow memory down to 300 MHzDouglas Anderson
At the higher speeds stressapptest shows memory errors. We don't want to track down random problems due to simple memory corruption, so slow memory back down to 300 MHz until someone figures out how to make it faster without sacrificing reliability. BRANCH=None BUG=chrome-os-partner:54144 TEST=stressapptest -M 1024 -s 240 Change-Id: I2417f93f65b1491a028a63ce563ed7dd7831becc Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I02182b25e677e27e8541445938f9da9ae9553fa6 Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/350480 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15120 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21rockchip: gru: pass poweroff gpio parameter to BL31Lin Huang
To support gpio power off SOC, we need to pass the power off gpio parameter to BL31. Gru reuse tsadc overtemp pin as power off gpio, so need to iomux to gpio function when use gpio power off function, either in bl31 or depthcharge. BRANCH=None BUG=chrome-os-partner:53448 TEST=Build gru Change-Id: Ibfe64042f39f6df1b87536b50fe432859bf74426 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: Ie7a1bbea4a12753f0abac7a9142f2e032686ce31 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349703 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15119 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-21rockchip: gru: pass reset gpio parameter to BL31Lin Huang
To support gpio reset SOC, we need to pass the reset gpio parameter to BL31. Note: request BL31 have supported this function. BRANCH=None BUG=chrome-os-partner:51924 TEST=Build gru Change-Id: I182cff11ce6f5dc3354db0dc053c128b813acf9f Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: Original-Change-Id: I8283596565d552b1f3db31c28621a1601c226999 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/349702 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15118 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-21google/reef: Keep ISH enabled for nowFurquan Shaikh
Disabling ISH causes resets in FSP which leads to hang. This should be fixed in a later stepping. Until then keep ISH enabled. BUG=chrome-os-partner:54033 Change-Id: Id9cb276eed8d027ab6d2e81a5ec962bc730c1ff5 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15142 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21google/reef: Add ACPI code for trackpadFreddy Paul
This patch enlists ELAN trackpad on I2C4 for reef board. BUG=None TEST=Build and boot to OS. Ensure ELAN trackpad is working with ELAN trackpad driver enabled in kernel. Change-Id: I788600f16dea9fac0e089cb82ccfc38a960157f9 Signed-off-by: Freddy Paul <freddy.paul@intel.com> Reviewed-on: https://review.coreboot.org/15213 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/model_6ex: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I9bfaa53f8d09962d36df1e86a0edcf100bb08403 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15229 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21beaglebone: Update bootblock.c to use new structs/codeGabe Black
New structures and functions have been added to make it easier and clearer to talk to GPIOs, configure the clock module, and toggle the LEDs. Use that code in bootblock.c instead of doing those things manually with hardcoded addresses. Change-Id: If41db0220de4bc95a6c99945ec402e3026cb4eeb Signed-off-by: Gabe Black <gabeblack@chromium.org> Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/3944 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-06-21mb/google: remove superfluous header includes in bdw chromeboxesMatt DeVillier
Change-Id: I71443c7547a113bf9b64d48fe5a85c6e2302c8aa Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/15208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-06-21intel/car/cache_as_ram_ht.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: Idb0f621553e76e771a5d6f2d492675ccd989d947 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15228 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-21intel/car/cache_as_ram.inc: Prepare for dynamic CONFIG_RAMTOPKyösti Mälkki
Change-Id: I02881ce465cb3835a6fa7c06b718aa42d0d327ec Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15227 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-21qemu/x86: car: drop pointless code, move stack out of the wayGerd Hoffmann
RAM doesn't need any initialization on qemu, so we can simply use it right away. No need to try using the cache as ram in the first place. We also can place the stack in normal ram right from start and we don't have to switch it to another place later on. Place the stack in real mode memory which isn't used for something else. Change-Id: Ib7a3f58a846d139f7babea5f43722a30fe0fe962 Signed-off-by: Gerd Hoffmann <kraxel@redhat.com> Reviewed-on: https://review.coreboot.org/15214 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2016-06-21riscv-spike: Move coreboot to 0x80000000 (2GiB)Jonathan Neuschäfer
This is where the RAM is (now), on RISC-V. We need to put coreboot.rom in RAM because Spike (at the moment) only supports loading code into the RAM, not into the boot ROM. Change-Id: I6c9b7cffe5fa414825491ee4ac0d2dad59a2d75c Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-20nb/intel/sandybridge/raminit: Allow 933Mhz on Lenovo devicesPatrick Rudolph
Set max_mem_clock_mhz in devicetree to 933Mhz. Allows to run the memory at up to DDR3-1866. The same frequency was allowed within the first vendor bios, but Lenovo than decided to limit it to DDR3-1333. Tested on Lenovo T520 and DDR3-1600 DIMM (RMT3170eb86e9w16). The RAM is now running at DDR3-1600 instead of DDR3-1333. This gives about 4% performance increase in glmark2 using the Intel GPU. Change-Id: If15be497402d84a2778f0434b6381a64eda832d6 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15158 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-18emulation/qemu-i440fx qemu-q35: Asmlinkage for romstage main()Kyösti Mälkki
Change-Id: I66238525c5c4d97313a589373144741f1be97483 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15226 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
2016-06-18AMD boards: Fix romstage main() declarationKyösti Mälkki
Boards incorrectly used intel include file for AMD board. Change-Id: I6d3172d1aa5c91c989a6ef63066a7cd6f70013f5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15232 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-18dmp/vortex86ex: Drop excessive includeKyösti Mälkki
Change-Id: Ieeae96d53627768de98006074c8c8e826b1741fc Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15233 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-17google/reef: Update EMMC DLL setting in all modeZhao, Lijian
Update tuned DLL setting on all other mode, including SDR12 SDR25 and DDR50. Change-Id: I1eb85ac6080fd78f63816d3fa9ef482484bd9f94 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/15210 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-17Move definitions of HIGH_MEMORY_SAVEKyösti Mälkki
This is more of ACPI S3 resume and x86 definition than CBMEM. Change-Id: Iffbfb2e30ab5ea0b736e5626f51c86c7452f3129 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15190 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17Fix some cbmem.h includesKyösti Mälkki
Change-Id: I36056af9f2313eff835be805c8479e81d0b742bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15196 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-17Define RAMTOP for x86 onlyKyösti Mälkki
This Kconfig is deprecated, new platforms need to locate ramstage stack in CBMEM instead. Change-Id: I20ece297302321337cc2ce17fdef0c55242a4fc3 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15189 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2016-06-16google/reef: Add NVRAM and LEGACY sections to chromeos.fmdFurquan Shaikh
Now that the flash size is increased to 16MiB, add RW_NVRAM and RW_LEGACY sections to chromeos.fmd file. BUG=chrome-os-partner:54390 Change-Id: I6c79d35295c4bc774f05f8045ac920474d7a791f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15192 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16google/reef: Update flash size to 16MiBFurquan Shaikh
Use entire 16MiB flash size on reef. Adjust SIGN_CSE region accordingly. BUG=chrome-os-partner:54390 Change-Id: I94de509bdb2aa94625814123bf4d9758bfa37fc9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15191 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-16mb/google: Remove whitespace from devicetree on bdw boxes.Prabal Saha
Change-Id: I189836282b4ad084fbbb74199b24505f5e141b60 Signed-off-by: Prabal Saha <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/15207 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins)
2016-06-16google/rikku: Upstream Acer Chromebox CXI2Matt DeVillier
Migrate google/rikku (Acer Chromebox CXI2) from Chromium tree to upstream, using google/guado as a baseline. original source: branch firmware-rikku-6301.110.B commit 2e71207 [CHERRY-PICK: broadwell: Update to microcode 0x1F] TEST=built and booted Linux on rikku with full functionality blobs required for working image: VGA BIOS (vgabios.bin) firmware descriptor (ifd.bin) Intel ME firmware (me.bin) MRC (mrc.bin) external reference code (refcode.elf) Change-Id: Iba618a0b2cf2d613f6429b3e7606e0b47fa97a4d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/12802 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-14google/reef: Correct use of globalnvs.aslFurquan Shaikh
Use the correct globalnvs.asl from apollolake. BUG=chrome-os-partner:54342 Change-Id: I1a5b8f61c540bdb2668b532f032350d8e4d48010 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15178 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-14google/reef: Update EMMC DLL settingsZhao, Lijian
Update EMMC DLL setting for reef board, after that system can boot up into EMMC successfully. BUG=chrome-os-partner:54228 TEST=Boot up into EMMC and check with Rootdev Change-Id: I614cd624dce9069c5565599a955f87906bcea53b Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/15156 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12nb/intel/raminit (native): Read PCI mmio size from devicetreePatrick Rudolph
Instead of hardcoding the PCI mmio size read it from devicetree. Set a default value of 2048 MiB and 1024MiB for laptops without discrete graphics. Tested on Sandybridge Lenovo T520. Change-Id: I791ebd6897c5ba4e2e18bd307d320568b1378a13 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/15140 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-12riscv-spike: Replace custom UART with a memory-mapped 8250Jonathan Neuschäfer
Since the HTIF is a non-standard interface, and coreboot already has a 8250 driver, I started implementing an 8250 core for spike[1]. [1]: https://github.com/riscv/riscv-isa-sim/pull/53 Change-Id: I84adc1169474baa8cc5837358a8ad3d184cfa51b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/15150 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-06-12mt8173: dram: Add more sample points to improve dram timing marginPH Hsu
BRANCH=none BUG=chrome-os-partner:52959 TEST=verified on elm-EVT SKU1/SKU2, Oak-rev5 2GB/4GB models. Change-Id: I228c629d9a3d6cd8fc5c4e8ba24cc52d5283b4e6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3c19e7d Original-Change-Id: I22356aa8d196c4c126742cfc7e85cc693acd9b39 Original-Signed-off-by: PH Hsu <ph.hsu@mediatek.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347716 Original-Commit-Ready: Yidi Lin <yidi.lin@mediatek.com> Original-Tested-by: Yidi Lin <yidi.lin@mediatek.com> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15115 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12oak: Select VBOOT_EC_SLOW_UPDATE Kconfig optionJulius Werner
All current Oak boards have PD chips with update speeds that range from slow (Oak) to "OMG it's so awfully slow I could make a cup of coffee and it would still not be done" (Elm). Set the flag that enables the "Your system is applying a critical update. Please don't turn it off." message on EC software sync so that our users don't accidentally carry it back to the store and demand a refund while it's still not done booting. BRANCH=None BUG=chrome-os-partner:51145 TEST=Booted Oak in normal mode with a new EC-RW image. Confirmed that I saw the magic screen. Change-Id: I000eab36d26b61b25d1f0da505f02ced15457255 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 274644b Original-Change-Id: I64ba698985d5fbcf2b94115df72b70a5319106ac Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/348787 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15114 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12Kconfig: Set VBOOT_OPROM_MATTERS for relevant non-x86 devicesJulius Werner
The VBOOT_OPROM_MATTERS configuration option signals to vboot that the board can skip display initialization in the normal boot path. It's name is a left-over from a time when this could only happen by avoiding loading the VGA option ROM on x86 devices. Now we have other boards that can skip their native display initialization paths too, and the effect to vboot is the same. (Really, we should rename oprom_matters and oprom_loaded to display_skippable and display_initialized or something, but I don't think that's worth the amount of repositories this would need to touch.) The only effect this still has in today's vboot is to reboot and explicitly request display initialization for EC software sync on VBOOT_EC_SLOW_UPDATE devices (which we haven't had yet on ARM). Still, the vboot flag just declares the capability (for skipping display init), and it should be set correctly regardless of whether that actually makes a difference on a given platform (right now). This patch updates all boards/SoCs that have a conditional path based on display_init_required() accordingly. BRANCH=None BUG=chrome-os-partner:51145 TEST=Booted Oak, confirmed that there's no notable boot time impact. Change-Id: Ic7c77dbd8356d67af7aee54e7869f9ac35241b99 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c242f7 Original-Change-Id: I75e5cdda2ba2d111ea50ed2c7cdf94322679f1cd Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/348786 Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/15113 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-12rockchip: gru: Add USB DRD DWC3 controller supportLiangfeng Wu
This patch adds code to initialize the two DWC3 USB host controllers, and uses them to initialize USB3.0 on the gru rk3399 board. BRANCH=none BUG=chrome-os-partner:52684 TEST=boot from USB3.0 on gru/kevin rk3399 platform Change-Id: If6a6e56f3a7c7ce8e8b098634cfc2f250a91810d Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0306a9e Original-Change-Id: I796fa1133510876f75873d134ea752e1b52e40a8 Original-Signed-off-by: Liangfeng Wu <wulf@rock-chips.com> Original-Signed-off-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/347524 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15112 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-11mainboard/intel/galileo: Support bootblock in CLee Leahy
Initialize the GPIOs during the boot block to properly route the SOC UART pins. TEST=Build and run on Galileo Gen2 Change-Id: I22c24f8c83f04566a0bbd598a141a5209569a924 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15133 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09mainboard: Support ROM_SIZE > 16 MiBLee Leahy
Support ROM_SIZE greater than 16 MiB. Work around SMBIOS rom size limitation of 16 MiB by specifying 16 MiB as the ROM size. TEST=Build and run on neoncity Change-Id: I3f464599cd8a1b6482db8b9deab03126c8b92128 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Reviewed-on: https://review.coreboot.org/15108 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-09intel/amenia: Program EMMC dll settingZhao, Lijian
EMMC TX DATA Control needs to be programmed to 0x1A1A to make amenia system can run stable on EMMC with HS400 mode. Change-Id: I42c23ff7e6956e75de5e1b1339a570b35d999301 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15092 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-09skylake: Move I2C bus configuration to separate structureDuncan Laurie
Move the existing I2C voltage configuration variable into a new structure that is equivalent, similar to how USB ports are configured. This is to make room for additional I2C configuration options like bus speed and whether to enable the bus in early boot which are coming in a subsequent commit. The affected mainboards are updated in this commit so it will build. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id2dea3df93e49000d60ddc66eb35d06cca6dd47e Reviewed-on: https://review.coreboot.org/15104 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-09skylake: gpio: Add support for setting 1.8V tolerantDuncan Laurie
Add the voltage tolerance GPIO attribute for configuring I2C/I2S buses that are at 1.8V. This is currently done by passing in a value to FSP but it is needed earlier than FSP if the I2C bus is used in verstage. This does not remove the need for the FSP input parameter, that is still required so FSP doesn't disable what has been set in coreboot. The mainboards that are affected are updated in this commit. This was tested by exercising I2C transactions to the 1.8V codec while in verstage on the google/chell mainboard. Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: I93d22c2e3bc0617c87f03c37a8746e22a112cc9c Reviewed-on: https://review.coreboot.org/15103 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-06-08rockchip: rk3399: Add support i2sXing Zheng
This patch enable and configure the clocks and IOMUX for i2s audio path, and the i2s0 clock is from CPLL. Please refer to TRM V0.3 Part 1 Chapter 3 CRU, P126/P128/P144/P154/P155 for the i2s clock div and gate setting. BRANCH=none BUG=chrome-os-partner:52172 TEST=boot kevin rev1, press ctrl+u and hear the beep voice. Change-Id: Id00baac965c8b9213270ba5516e1ca684e4304a6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 9c58fa7 Original-Change-Id: I130a874a0400712317e5e7a8b3b10a6f04586f68 Original-Signed-off-by: Xing Zheng <zhengxing@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/347526 Original-Commit-Ready: Wonjoon Lee <woojoo.lee@samsung.com> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15034 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08gru: kevin: enable EC SPI interfaceVadim Bendebury
This configures and enables SPI interface #5 used for EC communications on Gru/Kevin. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the appropriate depthcharge change it is possible to trigger booting Chrome OS from the SD card by pressing '^U' on Gru keyboard at the right time. Change-Id: I5304bf47e030c0b9b7794752f30ffdca6c03a4f4 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: b5cc177 Original-Change-Id: I99883daa60562ccddfaeb858c1957d497f05a501 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346632 Reviewed-on: https://review.coreboot.org/15032 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08gru: kevin: configure board GPIOsVadim Bendebury
Set board GPIOs as required and add their description into the appropriate section of the coreboot table, to make them available to depthcharge. BRANCH=none BUG=chrome-os-partner:51537 TEST=with the rest of the patches applied it is possible to use keyboard on Gru, which indicates that the EC interrupt GPIO is properly configured. The rest of the pins will be verified later. Change-Id: I5818bfe855f4e7faa2114484a9b7b44c7d469727 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: e02a05f Original-Change-Id: I82be76bbd3211179e696526a34cc842cb1987e69 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346631 Reviewed-on: https://review.coreboot.org/15031 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08veyron: Add exception_init() to romstageJulius Werner
I'm not even sure how this slipped through... looks like it had never been there in the first place. Anyway, on ARM exceptions should always be reinitialized in all stages to make sure the handlers are still around (especially in an OVERLAP_VERSTAGE_ROMSTAGE board like this one). Change-Id: Ic74ea1448d63b363f2ed59d9e2529971b3d32d9a Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/15099 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-08gru: kevin: define GPIOs used on both platformsVadim Bendebury
The same GPIOs are used on both platforms, definitions are added an a new .h to make it easier to re-use them across the code. BRANCH=none BUG=chrome-os-partner:51537 TEST=panel backlight still enabled on Gru as before. The rest of the GPIOs are used in the upcoming patches. Change-Id: If06f4b33720ab4bf098d23fb91322bba23fe6e90 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c587880 Original-Change-Id: I1a6c5b5beb82ffcc5fea397e8e9ec2f183f4a7e0 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/346219 Original-Tested-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/15029 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-08mainboard/intel/amenia: Enable VIRT_DEV_SWITCHRavi Sarawadi
Enable virtual dev switch config. BUG=None TEST= On Dev FW screen, press SPACE key to boot to normal mode Change-Id: I0fba36ed85025e4d17da106978dcc88497afee09 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/15080 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08Intel/amenia: Make the device address more readableZhao, Lijian
Use central header file to include device address and interrupt line to avoid confusion. Change-Id: I9560031d9f6e12c665c8ae12f7028a67b6c8c904 Signed-off-by: Zhao, Lijian <lijian.zhao@intel.com> Signed-off-by: Rohit Ainapure <rohit.m.ainapure@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7248 Tested-by: N, Harshapriya <harshapriya.n@intel.com> Reviewed-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://chromium.devtools.intel.com/7580 Reviewed-by: N, Harshapriya <harshapriya.n@intel.com> Tested-by: Petrov, Andrey <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/15083 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-08adi/rc-dff: Add Initial implementaionChris Ching
* Add ADI vendor Copy Intel Mohon Peak mainboard to ADI vendor. No functional changes, only string and ifdef names changed. Change-Id: I25a6d0ec549c79a8ff149d39f72648f625dc36fe Signed-off-by: Chris Ching <chingcodes@google.com> Reviewed-on: https://review.coreboot.org/14778 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-08mainboard/lenovo/x220: Clean up codeJan Tatje
thermal.h still has references to X230 in include guard since it seems to have been copied from that port. Code formatting changes in romstage.c. Change-Id: Id8bd931bed127036e8bb4ab604d9d6145f767e56 signed-off-by: Jan Tatje <jan@jnt.io> Reviewed-on: https://review.coreboot.org/15071 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-06-08mainboard/google/reef: Configure sd card pinsJagadish Krishnamoorthy
Since the sd card cmd, data, cd lines are configured as native mode, allow the native controller to control the termination. Configure SDCARD_CLK_FB which is used for calibrating the timing of the actual clock buffer. BUG==chrome-os-partner:53747 TEST=verify sd card detection Change-Id: I56611826afb4fb32fefa7f1e4ba19ca4f30ba578 Signed-off-by: Abhay Kumar <abhay.kumar@intel.com> Signed-off-by: Jagadish Krishnamoorthy <jagadish.krishnamoorthy@intel.com> Reviewed-on: https://chromium-review.googlesource.com/348377 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15096 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins)
2016-06-08lenovo/x60: add hda_verb.cArthur Heymans
This creates a config for the x60 audio based on values taken from vendor bios. The pin config is stored in (for linux 4.5 at least): /sys/class/sound/card0/hw*/init_pin_configs In the left column there is the pin number. In the right column there is the default configuration of that pin. (This has to be done while running the proprietary bios) More information on the sound card can be found in: /proc/asound/card0/codec#* This also hold the information of /sys/class/sound/ What is improved: - internal microphone is chosen by default - when jack is inserted it is chosen instead of internal speaker Before this had to be done manually in alsa or pulseaudio. TEST= check if internal microphone is used by default in pavucontrol if you are using pulseaudio. Plug in a jack with headphones and check if there is sound output through these and not the build-in speaker. Change-Id: Id3b700fd84905a72cc1f69e7d8bfa6145f231756 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15063 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-06-07intel/amenia: Add asl code to enable google ChromeECShaunak Saha
This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: Id908f145789402573ea54fc4f15cf7a0e651ebf4 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/14987 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07google/reef: Add asl code to enable google ChromeECShaunak Saha
This patch adds asl code to include support for Google ChromeEC. We need this to show the battery icon and notifications like charger connect/disconnect etc. BUG = 53096 TEST = Plug/Unplug AC Adapter multiple times and make sure the battery connected is charging properly. Change-Id: I06f48eda894418514c8ed0136500fff0efd12a35 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/15069 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-06-07Kevin/Gru : Update Board ID table.jongpil19.jung
Add board id table as kevin/gru configuration. BUG=chrome-os-partner:53519 BRANCH=chromeos-2016.02 TEST=check boot on Kevin board. Change-Id: I30c16916f3cda0ac88d2ce5a922e936a405fcc89 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 16c7b5486befd73c3e31624970ba1c97e526676f Original-Change-Id: Ib69ed9dad8e1a9e08717545c6be19a90e0298c43 Original-Signed-off-by: jongpil19.jung <jongpil19.jung@samsung.com> Original-Reviewed-on: https://chromium-review.googlesource.com/345736 Original-Commit-Ready: Vadim Bendebury <vbendeb@chromium.org> Original-Tested-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-on: https://review.coreboot.org/15028 Tested-by: build bot (Jenkins) Reviewed-by: Vadim Bendebury <vbendeb@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-07rockchip: gru: update the hynix lpddr3 config to run at 928MHzShunqian Zheng
Update the DDR config and DRAM driver to allow running at up to 928MHz. Kevin config/clock rate are not being changed, but Gru now runs at 928 MHz. BRANCH=none BUG=chrome-os-partner:51537 TEST=booted Kevin and Gru to Linux prompt. Ran stressapptest for 10 min on Gru, Change-Id: I66c1a171d5c7d05b2878c7bc5eaa0d436c7a1be2 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 8baf0d82816a7ea1c4428e15caeefa2795d001f9 Original-Change-Id: I5e1d6d1025f10203da8f11afc3bbdf95f133c586 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/343984 Original-Reviewed-by: Stephen Barber <smbarber@chromium.org> Reviewed-on: https://review.coreboot.org/15027 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-05pcengines/apu1: Add SMBIOS SKU fieldKyösti Mälkki
Just the memory size, there is no strap to identify PCB revision. Change-Id: I65b2f5b0ac6930bead60ea0a551f13a6bcab24c7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14997 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2016-06-04AGESA boards: Split dispatcher to romstage and ramstageKyösti Mälkki
The way dispatcher table is set up prevents linker from optimizing unused code away, we currently have raminit in ramstage. Optimize this manually by configuring AGESA_ENTRY booleans for romstage and ramstage separately. This will remove references in FuncParamsInfo and DispatchTable -arrays. All boards now include multi-core dispatcher, it has minimal footprint: AGESA_ENTRY_LATE_RUN_AP_TASK ACPI S3 support depends on HAVE_ACPI_RESUME being enabled: AGESA_ENTRY_INIT_RESUME AGESA_ENTRY_INIT_LATE_RESTORE AGESA_ENTRY_INIT_S3SAVE Disabled for all boards as it was not used: AGESA_ENTRY_INIT_GENERAL_SERVICES Change-Id: I7ec36a5819a8e526cbeb87b04dce4227a1689285 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14417 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-04gm45: enable setting all vram sizes from cmosArthur Heymans
Setting the size of the preallocated memory for the igd is done using a cmos parameter, gfx_uma_size. This was limited to a subset of all available sizes, that were already implemented elsewhere in the northbridge code. What this does is change the cmos parameter to 4 bits instead of 3 bits to accomodate all vram sizes. It also adds a sane default of 32mb that already was in place. The northbridge code that reads this cmos parameter is also changed for this new cmos settings. 352M is disabled since it causes issues on systems with 4GB or more ram. TEST: Build, flash target. Clear cmos by corrupting the checksum (nvramtool -c something). Set a desired value in gfx_uma_size using nvramtool. "dmesg | grep stolen" to see what is actually allocated. Change-Id: Ia6479d03f1abe6d0c94bd7264365505e8f8eaeec Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14900 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2016-06-04AGESA f12 f15: Add OEM customisationKyösti Mälkki
Follow-up on commits a5d72a3 and 53052fe for f12 and f15. OEM Hooks are not BiosCallOuts. Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14888 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03AMD boards: Drop comment on include fileKyösti Mälkki
The included file does not declare pm_ioread(), and the modified file does not call it either. Change-Id: I9723caf1062db23b4a3648e07c2dc4c02f862619 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14968 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03aopen/dxplplusu: Disable HW scrubberKyösti Mälkki
See initialize_ecc() for the awful hack that got us around cache-as-ram being invalidated as we do ECC HW scrubbing. It once worked, but compiler nowadays puts more registers on the stack. Not much interest to try fix ECC for this particular board. Change-Id: Ie6a09e28b0af5bbf2d68af72f5d98c03df33c402 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/15014 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03rockchip: gru: enable eDP displayLin Huang
This patch enables eDP display by: o. setting HPD pinmux, backlight, vdd for eDP o. setting vop mode o. enabling VGA configs for edid BRANCH=none BUG=chrome-os-partner:51537 TEST=The dev screen is shown on kevin board Change-Id: If8b07307454daa88727d317cc208d6c97de07ad7 Signed-off-by: Martin Roth <martinroth@google.com> Original-Commit-Id: b1ad9337510f5437f691153dc68883edf273e4c7 Original-Change-Id: Id7006619b5be638b286a5402d892a5361ac1e430 Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/340026 Original-Reviewed-by: Shunqian Zheng <zhengsq@rock-chips.com> Reviewed-on: https://review.coreboot.org/14858 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-06-03mainboard/intel/galileo: Add CREATE_BOARD_CHECKLISTLee Leahy
Select CREATE_BOARD_CHECKLIST to create the checklist for the Quark SOC and Galileo board. TEST=Build and run on Galileo Gen2. Change-Id: Ieb3e9a5a4c149cf160e11d44a515591b57fe5c83 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15004 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03mainboard/intel/galileo: Set board versionLee Leahy
Return the correct board version in SMBIOS. TEST=Build and run on Galileo Gen2 Change-Id: I97ec7bcd475142eb90930152da0244a3c5d09634 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/15041 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-03AGESA boards: Drop unused includeKyösti Mälkki
These files do not use definitions from OptionsIds.h. Also those definitions are required and already included for Ids.h. Change-Id: I149fcfe2ad72fe3d7390ee2043a86432aeae3f08 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/14980 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-06-02google/reef: Select UART_FOR_CONSOLE for reefFurquan Shaikh
Change-Id: I714af8ab552dc1923a1b64e0c502d6c7b96dd444 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/15044 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-06-02lenovo/t420: correct the eSATA portIru Cai
The eSATA port of Lenovo T420 is port 3. I've checked it on an iGPU model and a dGPU model. Change-Id: I64bcc887140c1634dd1475d29e97780a5128d0be Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/14632 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nicolas Reinecke <nr@das-labor.org>
2016-06-02Gale board: Move TPM setup function to verstage.cKan Yan
TPM should be only be reset once in verstage. BUG=chrome-os-partner:51096 TEST=Depthcharge no longer shows TPM error. BRANCH=None Original-Signed-off-by: Kan Yan <kyan@google.com> Original-Commit-Id: 911bdaa83a05fa5c8ea82656be0ddc74e19064c3 Original-Change-Id: I52ee6f2c2953e95d617d16f75c8831ecf4f014f9 Original-Reviewed-on: https://chromium-review.googlesource.com/343537 Original-Commit-Ready: Kan Yan <kyan@google.com> Original-Tested-by: Kan Yan <kyan@google.com> Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8047b7ba44c604d97a662dbf400efc9eea2c7719 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/14845 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2016-06-01mb/lenovo/T4xx: enable PEG devicePatrick Rudolph
Enable the PEG device in devicetree to expose the device if any. This is already default behaviour for T5xx series. Change-Id: I16bd253ca96c4cdaad8a829f6490cec9e2599b5f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/14448 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01drivers/lenovo: Add hybrid graphics driverPatrick Rudolph
Add a universal hybrid graphics driver compatible with all supported lenovo devices. Hybrid graphics allows to connect the display panel to either of one GPUs. As there are only two GPUs one GPIO needs to be toggled. In case the discrete GPU is activated the panel is routed to it. On deactivation the panel is routed to the integrated GPU. On lenovo laptops the dGPU is always connected to PEG10 and it is save to disable the PEG slot on dGPU deactivation. Use common gpio.c for southbridge I82801IX. Tested on Lenovo T520 using Nvidia NVS 5200m. Removed Lenovo T430s from the list of supported devices, as the T430s only supports "muxless Optimus". Depends on change id: Iccc6d254bafb927b6470704cec7c9dd7528e2c68 Ibb54c03fd83a529d1ceccfb2c33190e7d42224d8 I8bd981c4696c174152cf41caefa6c083650d283a Iaf0c2f941f2625a5547f9cba79da1b173da6f295 I994114734fa931926c34ed04305cddfbeb429b62 Change-Id: I9b80b31a7749bdf893ed3b772a6505c9f29a56d1 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12896 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
2016-06-01Revert "mainboard/lenovo/t400: Add initial hybrid graphics support"Patrick Rudolph
This reverts commit 59597ead1f26d4c18997bda81b2ec33e52973b80. Will be replaced by lenovo common hybrid driver. Change-Id: I994114734fa931926c34ed04305cddfbeb429b62 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/12895 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@googlemail.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 17:32:25 +0000