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2016-09-21Makefiles: update cbfs types from bare numbers to valuesMartin Roth
These values are found in util/cbfstool/cbfs.h. Change-Id: Iea4807b272c0309ac3283e5a3f5e135da6c5eb66 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16646 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/lenovo-winent: Add space around operatorsElyes HAOUAS
Change-Id: Iab2a879ebdea9d93ef5eb7e3abf875036c1e1cb4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16641 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/getac - kontron: Add space around operatorsElyes HAOUAS
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16640 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru/kevin: Decrease voltage for little cpu 1.5G to 1.15vShunqian Zheng
In kernel side we set 1.1v for 1.5G, even for coreboot RO, a higher voltage could be safer, 1.2v now seems too high. BRANCH=none BUG=chrome-os-partner:56948 TEST=bootup Change-Id: I852e0d532369aad51b12770e2efb01aacf6662ce Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 000b5c099373be2a1f83c020ba23a0e79ea78fab Original-Change-Id: Iecc620deee553c61a330353ac160aa3a36f516df Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/380896 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16583 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Veyron: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted Jerry Change-Id: Ia19d585b69e7701040209e8bf0b8a6990a166c95 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e7a42c999673ebd89c5b30845a4a5ec93852166 Original-Change-Id: I126cb7077c834e1a8b0a625a592dce8789b5876c Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376884 Reviewed-on: https://review.coreboot.org/16581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20google/gru: Fix up PWM regulator rangesJulius Werner
We did yet another small adjustment to the PWM regulator ranges for Kevin rev6... this patch reflects that in code. Also rewrite code and descriptions to indicate that these new ranges are not just for Kevin, but also planned to be used on Gru rev2 and any future Gru derivatives (which as I understand it is the plan, right?). BRANCH=None BUG=chrome-os-partner:54888 TEST=Booted my rev5, for whatever that's worth... Change-Id: Id78501453814d0257ee86a05f6dbd6118b719309 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 4e8be3f09ac16c1c9782dee634e5704e0bd6c7f9 Original-Change-Id: I723dc09b9711c7c6d2b3402d012198438309a8ff Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/379921 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16580 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20Gru: Increase bit-per-pixel to 32Daisuke Nojiri
This enhances gradation of some icons on vboot screens. BUG=chrome-os-partner:56056 BRANCH=none TEST=Booted kevin-tpm2 Change-Id: I2fc943f89386ccc6cd9293f5811182a5a51d99b0 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: bb1f0fb00d023c045305edc6c9fc655b764a4e8c Original-Change-Id: Ieb61830b9555da232936087cdcf7c61a1e55bab4 Original-Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/376883 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16579 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20gru: Add watchdog reset supportJulius Werner
This patch adds support to reboot the whole board after a hardware watchdog reset, to avoid the usual TPM issues. Work 100% equivalent to Veyron. From my tests it looks like both SRAM and PMUSRAM get preserved across warm reboots. I'm putting the WATCHDOG_TOMBSTONE into PMUSRAM since that makes it easier to deal with in coreboot (PMUSRAM is currently not mapped as cached, so we don't need to worry about flushing the results back before reboot). BRANCH=None BUG=chrome-os-partner:56600 TEST='stop daisydog; cat > /dev/watchdog', press CTRL+D, wait 30 seconds. Confirm that system reboots correctly without entering recovery and we get a HW watchdog event in the eventlog. Change-Id: I317266df40bbb221910017d1a6bdec6a1660a511 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 3b8f3d064ad56d181191c1e1c98a73196cb8d098 Original-Change-Id: I17c5a801bef200d7592a315a955234bca11cf7a3 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/375562 Original-Commit-Queue: Douglas Anderson <dianders@chromium.org> Reviewed-on: https://review.coreboot.org/16578 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-20src/mainboard/a-trend - emulation: Add space around operatorsElyes HAOUAS
Change-Id: Ib00a9b2feb723d46642d86b2706728bbca7dd68d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16616 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2016-09-19Revert "mainboard/google/reef: Enable cr50 TPM interrupt"Duncan Laurie
This reverts commit 24de342438208d9b843e87627f15b9a272285b0f.
2016-09-19mainboard/google/reef: Enable cr50 TPM interruptDuncan Laurie
Enable the cr50 TPM and interrupt as GPE0_DW1_28 for use during verstage. The interrupt is left in APIC mode as the GPE is still latched when the GPIO is pulled low. BUG=chrome-os-partner:53336 Change-Id: I28ade5ee3bf08fa17d8cabf16287319480f03921 Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-20gru: Add USB 2.0 PHY tuning for KevinJulius Werner
This patch sets some magic number in magic undocumented registers that are rumored to make USB 2.0 signal integrity better on Kevin. I don't see any difference (unfortunately it doesn't solve the problems with long cables on my board), but I guess it doesn't hurt either way. BRANCH=None BUG=chrome-os-partner:56108,chrome-os-partner:54788 TEST=Booted Kevin with USB connected through Servo. Seems to have roughly the same failure rate as before. Change-Id: If31fb49f1ed7218b50f24e251e54c9400db72720 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 0c5c8f0f80ea1ebb042bcb91506a6100833e7e84 Original-Change-Id: Ifbd47bf6adb63a2ca5371c0b05c5ec27a0fe3195 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/370900 Original-Reviewed-by: Guenter Roeck <groeck@chromium.org> Original-Reviewed-by: David Schneider <dnschneid@chromium.org> Reviewed-on: https://review.coreboot.org/16265 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-09-19mainboard/google/reef: Configure WLAN as wake sourceVaibhav Shankar
This implements PRW method for WLAN and configures PCIe wake pin to generate SCI. BUG=chrome-os-partner:56483 TEST=Suspend the system into S3 or S0ix. System should resume through wake event from wifi. Change-Id: I9bd078c2de19ebcc652b5d981997d2a5b5f0b1b7 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16611 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-19kunimitsu: Remove incorrect dereferencing of pointerRizwan Qureshi
In spd_util.c function mainboard_get_spd_data(), spd_file can either be NULL or will point to the first byte of the SPD data, and should not be dereferenced. Change-Id: I08677976792682cc744ec509dd183eadf5e570a5 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16612 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-15mainboard/reef: add variant support to ASL codeAaron Durbin
There are certain board-specific options for reef variants. The big one is the DPTF settings. Rearrange the ASL files such that dsdt.asl is the main landing area. The ACPI options for Chrome EC are contained in the variant/ec.h header so the actual code #includes can just reside in dstd.asl. Since most of the mainboard specific peripherals are auto generated by the acpigen from devicetree there's no real separate need for mainboard.asl. The one thing not addressed in this CL is the notion of a variant having the Chrome EC or not (along with lid, etc). Future indirection can be provided when needed to address that requirement. BUG=chrome-os-partner:56677 Change-Id: I5c888f5fc64913dcff010c28f87e69ac5449e6b6 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16604 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-15mainboard/bap/ode_e20XX: Change SATA from GEN2 to GEN3Fabian Kunkel
This patch disables the SataSetMaxGen2 flag. This flag is a power saving option, which forces the SATA to GEN2. Payload SeaBIOS 1.9.1, Lubuntu 16.04, Kernel 4.4. $ dmesg | grep ahci #before patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 3 Gbps 0x3 impl SATA mode $ dmesg | grep ahci #after patch ahci 0000:00:11.0: AHCI 0001.0300 32 slots 2 ports 6 Gbps 0x3 impl SATA mode Change-Id: I48361190969e6d38ddb5692f5e54b016b359fbb1 Signed-off-by: Fabian Kunkel <fabi@adv.bruhnspace.com> Reviewed-on: https://review.coreboot.org/15906 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15lenovo: add ps2 spinup timeout to all H8S based boardsAlexander Couzens
The h8s needs around 3s to respond to ps2 commands Change-Id: I0cf01969975b8dd3839eadf90cb2dac0f1eaafc4 Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Reviewed-on: https://review.coreboot.org/16505 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15camelbackmountain_fsp: Select SERIRQ_CONTINUOUS_MODEWerner Zeh
In commit 4f2754c 'fsp_broadwell_de: Add Kconfig switch for SERIRQ operation mode' the default operation mode of SERIRQ was changed from continuous to quiet. Set the mode to continuous for this mainboard to keep the behavior unchanged. Change-Id: I7c3675d4ee8cff428621f4e64411738193e654b2 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16576 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-15google/reef: Remove setting of GPIO_TIER1_SCI enable bitShaunak Saha
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I26fd3fd9fcc83c988bcff1bda4da7a2e3da98ce6 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16566 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-15intel/amenia: Remove setting of GPIO_TIER1_SCI enable bitShaunak Saha
This patch removes setting of gpio_tier1_sci_en from mainboard smihandler code. Gpio_tier1_sci enable bit is set from gpio.asl now. BUG=chrome-os-partner:56483 TEST=System resumes from S3 on lidopen, powerbutton and USB wake. Also from S0iX system is resuming for WIFI wake. Change-Id: I066f0907a1c597e6fee09821910c59a8a90cccaa Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/16565 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Andrey Petrov <andrey.petrov@intel.com>
2016-09-15kunimitsu: Add FSP 2.0 support in romstageRizwan Qureshi
Populate mainboard related Memory Init Params i.e, SPD Rcomp values, DQ and DQs values. Change-Id: Id62c43a72a0e34fa2e8d177ce895d395418e2347 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com> Reviewed-on: https://review.coreboot.org/16316 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboard/intel/amenia: Configure PERST_0 pinVaibhav Shankar
Configure PERST_0 and assign the pin in devicetree. BUG=chrome-os-partner:55877 TEST=Suspend and resume using 'echo freeze > /sys/power/state'. System should resume with PCIE and wifi functional. Change-Id: I39b4d8bba92f352ae121c7552f58480295b48aef Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16350 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboards/apollolake: Set RAPL power limit PL1 value to 12W.Sumeet Pawnikar
This patch sets tuned RAPL power limit PL1 value to 12W in acpi/dptf.asl for RAPL MSR register. With PL1 as 12W for WebGL and stream case, we measured SoC power reaching upto 6W. Above 12W PL1 value, we observed that Soc power going above 6W. With PL1 as 12W, system is able to leverage full TDP capacity. BUG=chrome-os-partner:56524 TEST=Built, booted on reef and verifed the package power with heavy workload. Change-Id: I8185ce890f27e29bc138ea568af536bc274fe7b8 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/16596 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-14mainboard/google/reef: Configure PERST_0 pinVaibhav Shankar
This configures PERST_0 in devicetree. For boards without PERST_0, the pin should be disabled. For boards with PERST_0 the correct GPIO needs to be assigned. BUG=chrome-os-partner:55877 Change-Id: I705009b480e02b4c9b2070bb4f82cb4d552e9a46 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/16603 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-13mainboard/google/reef: add MKBP EC event as SCI event.Gwendal Grignou
Add MKBP as a SCI event: the EC is then able to send events coming from the sensors. BUG=b:27849483 TEST=With EC configure to send MKBP events, check sensor information are retrieved by the kernel. Change-Id: Ib06241bfcdc8567769baff4f3371cc0c6eab3944 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/16594 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-13lenovo/t60: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/lenovo/t60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: I4d87498637d74f96ca5809b0e810755a58fc64ab Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16405 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/bcom/winnetp680: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/bcom/winnetp680. Change-Id: I6f57a669f83bed190e90e1b7be01f8c886546e2e Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16465 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/gigabyte/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/gigabyte/*. Change-Id: Ied62d6234a4f6ea5f851e98a098b2c8f4e3db144 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16439 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13mainboard/asus/*: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/asus/*. Change-Id: I5ddfba2102854adcc9bbfd75f7acbe76f0152b72 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13soc/marvell/mvmap2315: Add DDR driverHakim Giydan
This driver is only a prototype driver, real driver will be integrated at a later time. Testing: booted successfully. Change-Id: I372764962e96e5c9c827d524bc369978c5c1fda8 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/16554 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-13google/rotor: Add support for the Rotor mainboardHakim Giydan
Change-Id: I1f97b6f159a0ac36c96636066332ba355c056186 Signed-off-by: Hakim Giydan <hgiydan@marvell.com> Reviewed-on: https://review.coreboot.org/15507 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-12siemens/mc_bdx1: Enable decoding for COM 3 & COM 4 on LPCWerner Zeh
Since this mainboard provides 4 COM ports on LPC, enable decoding of the corresponding addresses using the generic LPC decode registers. Change-Id: I0e93d40dca01d55f3567a18c7ec02269e3bec466 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/16535 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12lenovo/t60: add hda_verb.cArthur Heymans
This creates a config for the Lenovo T60 sound card based on values taken from vendor bios (in /sys/class/sound/hwC0D0/init_pin_configs on linux 3.16). The sound card configuration on the vendor bios is the same as the one on the Lenovo x60. It improves the default behavior of the sound card: - internal microphone is chosen by default - when jack is inserted it is chosen instead of internal speaker Change-Id: I44e3eaac437fe4ad97ff2b0eb32d36b33222c09b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16529 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2016-09-12kunimitsu: Add initial FSP2.0 supportRizwan Qureshi
Add placeholders for functions required when skylake uses FSP2.0 driver, keeping the fsp1.1 flow intact. Change-Id: I5446f8cd093af289e0f6022b53a985fa29e32471 Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/16301 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Enable lpss s0ixVenkateswarlu Vinjamuri
This setting enables lpss to power gate in S0ix. BUG=chrome-os-partner:53876 Change-Id: I0a0fecb0e2b6e5e2f89ac505dd603f4be1bc161e Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16558 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-12mainboard/google/reef: Disable CLKREQ of unused PCIe root portsVenkateswarlu Vinjamuri
1. Removes PCIe blocker for S0ix. 2. Set the correct PCIe root port for wifi/bt on EVT. 3. Turn off CLKREQs of unused PCIe root ports to power gate the IP. Change-Id: Iefd8869688d3a44b435dab9fc792275cd7f7e091 Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16557 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-09mb/gigabyte/ga-g41m-es2l: Remove PCI disable on PEG bridgeDamien Zammit
Although the goal was to hide the ME device by disabling the PCI bridge, the original comment that this bridge was ME related was a mistake, this bridge is for PEG not for ME. We still need this PCI bridge "on" to enable pci express graphics add-on cards. Change-Id: Ibf322136097d77a8e7c05dcb14f72da938187a0a Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16496 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-08mainboard/google/reef: move devicetree to baseboardAaron Durbin
Move the current devicetree.cb to be under variants/baseboard. New variants can provide their own devicetree as needed. BUG=chrome-os-partner:56677 Change-Id: Ib109ca4be883884b318264500d14aa8d40e3072a Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16510 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-07intel/i82801gx 82801ix: Remove OpRegion of SMBus hostKyösti Mälkki
Defining this OpRegion for SMBus controller prevents linux kernel driver i2c-i801 from registering SMBus under sysfs, with following error in dmesg: ACPI Warning: SystemIO range .. conflicts with OpRegion .. (\_SB.PCI0.SBUS.SMBI) Solution taken from intel/bd82x6x. Worth noting we do not define ENABLE_SMBUS_METHODS anywhere currently. Removed remaining reference to HSTS from GETAC P470. Change-Id: I7c13d344b0343387681b46019cc5061b1435b46b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16266 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07mb/intel/d945gclf: Disable combined mode to fix SATAArthur Heymans
Similarly to 2b2f465fcb1afe4960c613b8ca91e868c64592d4 "mb/gigabyte/ga-g41m-es2l: Fix ACPI IRQ settings for SATA" SATA must function in "plain" mode because it does not work in "combined" mode. Tested on d945gclf Change-Id: I2e051a632a1341c4932cf86855006ae517dbf064 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16319 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07mb/gigabyte/ga-g41m-es2l: Add IRQs for PCI express graphics in ACPIDamien Zammit
With this patch and the previous ones in this set, PCI express graphics is now working. 01:00.0 VGA compatible controller [0300]: NVIDIA Corporation GT218 [GeForce 210] [10de:0a65] (rev a2) (prog-if 00 [VGA controller]) Change-Id: Ife691fb381e90e7744fe2ac4e20977be53419a14 Signed-off-by: Damien Zammit <damien@zamaudio.com> Reviewed-on: https://review.coreboot.org/16497 Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-09-07mainboard/google/reef: Enable audio clock and power gateVenkateswarlu Vinjamuri
Removes S0ix blocker. Sets audio clock gate and power gate bits when audio not in use. Reduces power in S0. Change-Id: Id5c0adc2605480583dc90ee62a706dbfa4027c1b Signed-off-by: Venkateswarlu Vinjamuri <venkateswarlu.v.vinjamuri@intel.com> Reviewed-on: https://review.coreboot.org/16424 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06google/reef: Enable I2C TPMDuncan Laurie
Enable the I2C based TPM on the reef board at bus 2 and address 0x50. This makes vboot functional without needing MOCK_TPM and results in the following in the SSDT: Device (TPMI) { Name (_HID, "GOOG0005") // _HID: Hardware ID Name (_UID, Zero) // _UID: Unique ID Name (_DDN, "I2C TPM") // _DDN: DOS Device Name Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x0F) } Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings { I2cSerialBus (0x0050, ControllerInitiated, 0x00061A80, AddressingMode7Bit, "\\_SB.PCI0.I2C2", 0x00, ResourceConsumer) Interrupt (ResourceConsumer, Edge, ActiveLow, Exclusive) { 0x00000039 } }) } Change-Id: Ia9775caabeac3e6a3bd72de38f9611b4cea7cea4 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16398 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-06google/reef: Enable 20K pull ups for LPC CLKRUN and LAD0:3 linesShamile Khan
The pull up for CLKRUN is required to resolve keyboard slowness and malfunctioning observed on some reef systems. The CLKRUN signal was probed and found to be floating when the pull up was not enabled. Also Added pull ups for the LPC Multiplexed command, address and data lines LAD0:3 because the LPC Interface specification requires them. BUG=chrome-os-partner:55586 BRANCH=none TEST=When a key is pressed, the character is immediately visible on the screen. Also the interrupt count for i8042 increments immediately in /proc/interrupts. Change-Id: I16df1a0301a3994c926a609f61291761219f9e01 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/16426 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-09-06mainboard/google/reef: drop remaining proto board referencesAaron Durbin
The last vestige of the proto boards is the memory sku id gpios. The internal pullups are still required because there's only pulldown stuffing options available on the reef boards. BUG=chrome-os-partner:56791 Change-Id: I04d541a897ec9aacbf2011293d18242fa32896d2 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16432 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-06mainboard/google/reef: add baseboard nhlt configurationAaron Durbin
Move the current NHLT configuration implementation to the baseboard area such that other variants can leverage it or provide their own configuration. BUG=chrome-os-partner:56677 Change-Id: If0d48cacdc793492e1618d0eda02a149e33f0650 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16431 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: add baseboard memory configurationAaron Durbin
Move the current memory configuration implementation to the baseboard area such that other variants can leverage it. The swizzle config is exported as a global to allow duplicate swizzles to use the same structure while still allowing different memory SKUs. BUG=chrome-os-partner:56677 Change-Id: I57201118053051c01f0e3f164ab4bbaf650b892b Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16430 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: provide cros_gpio variant APIAaron Durbin
Add support for Chrome OS gpio ACPI table information by providing weak implementation from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I517764b78f47fb7b3637482ff9efc053cdd1ac69 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16422 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: consolidate gpio related defines to one placeAaron Durbin
Since multiple boards will be living within one directory move all the macros for defining anyting related to GPIOs to the gpio.h header file. That way, when other boards land they can override or use them as is. BUG=chrome-os-partner:56677 Change-Id: I36967e57fc61ef354e0b51d1ff1396ce562fa805 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16421 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: declare mainboard_ec_init() in each C fileAaron Durbin
There's no common EC header file in the code base, and I didn't want to use a header file for single declaration. Therefore, just move the declaration to each file that uses that symbol. BUG=chrome-os-partner:56677 Change-Id: Ibaebb0ea6a07029aec02d5185cf05ffb8593b117 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16420 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-06mainboard/google/reef: add variant API for board_id and gpioAaron Durbin
Provide APIs for the board_id() and gpio table functionality. Default and weak implementations are provided from the baseboard. BUG=chrome-os-partner:56677 Change-Id: I02d8deb7f60f8c4842916a9d35f51d8af74b1da4 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16419 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-09-05intel/minnowmax: Clean up whitespaceMarshall Dawson
Align the column of comments. Change-Id: Iec3a173af26710f8ff56519a14784344ea71d489 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/16427 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-04intel/minnowmax: Enable all PCIe portsMarshall Dawson
A recently announced Turbot system populates two Ethernet controllers. Enable the remaining disabled PCIe port. Also add a clarifying comment regarding the port associated with Function 0. Coreboot must not be allowed to disable the function which breaks PCI compatibility. Change-Id: I2815ba7e6d68b9898091fbc21c96eeeb49c8e05a Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/16429 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04intel/minnowmax: Program GPIO for power LEDMarshall Dawson
MinnowBoard Turbot systems have a GPIO-controlled LED that is generally used to indicate the CPU is running. Commit 2ae9cce8 changed the parameter for GPIO_NC, exposing an issue with the assumed behavior of the signal. Use a pull-down to turn on the LED. Change-Id: I153870904c007d89016c0d47bb3db9b824ebbcff Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/16428 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-09-04google/reef: Fix indent in devicetree.cbDuncan Laurie
Indent the I2C device for touchscreen with tabs so it aligns properly. Change-Id: Id9b2d26a4acdd6fe6c69055907258df3cc035b31 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/16399 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-09-04mainboard/google/reef: provide baseboard and variant conceptsAaron Durbin
To further the ability of multiple variant boards to share code provide a place to land the split up changes. This patch provides the tooling using a new Kconfig value, VARIANT_DIR, as well as the Make plumbing. The directory layout with a single variant, reef (which is also the baseboard), looks like this: variants/baseboard - code variants/baseboard/include/baseboard - headers variants/reef - code variants/reef/include/variant - headers New boards would then add themselves under their board name within the 'variants' directory. No split has been done with providing different logic yet. This is purely a organizational change. BUG=chrome-os-partner:56677 Change-Id: Ib73a3c8a3729546257623171ef6d8fa7a9f16514 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16418 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04mainboard/google/reef: prepare sharing directory for variantsAaron Durbin
Instead of completely duplicating the a reference board's directory when doing a variant or follower device start providing a means to share code within a single directory. This change just starts the process from the Kconfig side, but subsequent patches will follow which disentangles the board specific pieces from and common logic. BUG=chrome-os-partner:56677 Change-Id: I96628920d78012e488ec008e35daac9c1be0cf79 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16417 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-04mainboard/google/reef: correct EC ASL includesAaron Durbin
The superio.asl wasn't being included within the right scope. Fix that as well as clean up the per-mainboard header includes to be in one place. BUG=chrome-os-partner:56677 Change-Id: I5e6a82f9f2e3c7455132263d19b32b2f06220376 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16413 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com>
2016-09-04mainboard/google/reef: remove unused gpio.h macrosAaron Durbin
Some of the macros in gpio.h are no longer used because devicetree.cb is being used to autogeneric the ACPI AML. Therefore remove the unused macros. BUG=chrome-os-partner:56677 Change-Id: I433a929229a0318f6c1df652655d046a5152cc63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16412 Tested-by: build bot (Jenkins) Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2016-09-02drivers/intel/fsp2_0: Make FSP Headers Consumable out of BoxBrandon Breitenstein
The following patch is based off of the UEFI 2.6 patch. The FSP header files are temporarily staying in soc/intel/apollolake and FspUpd.h has been relocated since the other headers expect it to be in the root of an includable directory. Any struct defines were removed since they are defined in the headers and no longer need to be explicity declared as struct with the UEFI 2.6 includes. BUG=chrome-os-partner:54100 BRANCH=none TEST=confirmed coreboot builds successfully Change-Id: I10739dca1b6da3f15bd850adf06238f7c51508f7 Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com># Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16308 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02lenovo/x60: transition away from device_tAntonello Dettori
Replace the use of the old device_t definition inside mainboard/lenovo/x60. The patch has been tested both with the arch/io.h definition of device_t enabled and disabled in order to ensure compatibility while the transaction takes place. Change-Id: Icaceeae2fc7276efa82d37582ecac93aaf37c41c Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16372 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02lenovo/x200,t400: use gpio.h instead of gpio_setupArthur Heymans
Uses gpio.h instead of default_southbridge_gpio_setup to configure southbridge GPIO's. This is more consistent with how GPIO's are configured on newer targets. Change-Id: I6ccd0564b929e958864739b7cde04f5592c58479 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/16379 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-09-02Fix newlines at the end of filesMartin Roth
All but ga-g41m-es2l/cmos.default had multiple final newlines. ga-g41m-es2l/cmos.default had no final newline. Change-Id: Id350b513d5833bb14a2564eb789ab23b6278dcb5 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16361 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Antonello Dettori <dev@dettori.io>
2016-09-01mainboard/google/reef: drop proto gpio supportAaron Durbin
Many changes make proto boards very hard to work with since proto boards were using A stepping processors. Everyone has moved on. Therefore, drop non-proto support. BUG=chrome-os-partner:56791 Change-Id: I2985e3965b1b69445e22506bd664b4cbca13c8ab Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16377 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins)
2016-09-01mainboard/google/reef: add pen connectionsAaron Durbin
A pen interface was added. Prepare for possibly testing it by plumbing in the gpio configuration. It's very possible these changes need to be tweaked, but no driver code has been seen yet nor a datasheet detailing how some of these signals actually function. BUG=chrome-os-partner:56739 Change-Id: I208ff3e151ce55d62e5fcc33a1e39cc87e229970 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16376 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: fix polarity of FP_INTAaron Durbin
The formerly name FP_INT_L net is actually active high and is push-pull. Therefore adjust for the new net name, FP_INT, and polarity. The pulldowns are there because the device is on another board that isn't always available. BUG=chrome-os-partner:56740 Change-Id: I6706fd2c2bd164cf3b5f1457aef69f5675f2112d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16375 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: add new memory SKUsAaron Durbin
Two new SKUs are being utilized for reef DVT. Add the following: Hynix 8GiB using H9HCNNNBPUMLHR-NLE -- id: 4'b0100 Hynix 4GIB using H9HCNNN8KUMLHR-NLE -- id: 4'b0101 BUG=chrome-os-partner:56738 Change-Id: I39ed9e827501939b92cbcce6092302b5a23d1d78 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16374 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-09-01mainboard/google/reef: support WLAN_PE_RSTAaron Durbin
The reef DVT build added another way to assert the wifi module's reset line. Ensure it's deasserted by default. For previous boards this GPIO doesn't matter because it wasn't routed anyway. BUG=chrome-os-partner:56737 Change-Id: I63e97b091ca0a278682c883303b1d7e052d8e677 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16373 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31rockchip/rk3399: Add pwm_regulator.c for pwm then ramp boot up cpuEric Gao
Before, we calculate the pwm duties for cpu cores and centerlogic by hand, adding pwm_regulator.c to handle this. The default pwm design min/max voltage may be different between revs. With the pwm regulator, this patch changes the little cpu frequency from 600M to 1512M, and raises CPU voltage to 1.2V correspondingly. This also means we decide to drop the ES1 because it may fail to bootup with 1.5G ~ 1.2v. BRANCH=none BUG=chrome-os-partner:54376,chrome-os-partner:54862 TEST=Bootup on kevin board Change-Id: Id04c176bddfb9cdf3d25b65736e40249a85f6aa1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: ee4365c787ec523b7ee1028ea100dcfbb331b3a9 Original-Change-Id: Ide75bbd92d1cbb14f934baeec0e38862bc08402b Original-Signed-off-by: Eric Gao <eric.gao@rock-chips.com> Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/364410 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16368 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31i945: Enable changing VRAM sizeArthur Heymans
On i945 the vram size is the default 8mb. It is also possible to set it 1mb or 0mb hardcoding the GGC register in early_init.c The intel documentation on i945, "Mobile Intel® 945 Express Chipset Family datasheet june 2008" only documents those three options. They are set using 3 bits. The documententation also makes mention of 4mb, 16mb, 32mb, 48mb, 64mb but not how to set it. The other non documented (straight forward) bit combinations allow to change the VRAM size to those other states. What this patch does is: - add those undocumented registers with their respective vram size to the i945 NB code; - make this a cmos option on targets that have this northbridge. TEST: build, flash to target, set cmos as desired and boot linux. On Debian it can be found using "dmesg | grep stolen". NOTE: dmesg message about reserved vram are quite different depending on linux version Change-Id: Ia71367ae3efb51bd64affd728407b8386e74594f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/14819 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-31rockchip/rk3399: Move romstage.c to mainboard/gruShunqian Zheng
The romstage.c is more board related than soc specific, like setting the pwm regulators, so moving it to mainboard/gru. BRANCH=none BUG=chrome-os-partner:54819 TEST=Bootup on kevin board Change-Id: I83c6cde9f451480e47e2b4b549cedf65b345134c Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 35feeb07131a6a9de4adde035236987391833474 Original-Change-Id: If2bf245302eb4fb20bb089c1b3ffa03909722443 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/375398 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16367 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-31mainboard/*/Kconfig: Set GBB_HWID where missingPatrick Georgi
Provide GBB's hardware ID (used on Chrome OS devices) because it will be dropped from depthcharge. BRANCH=none BUG=none TEST=none Change-Id: I4851c1bdb21863983277d3283105c88b85a6166b Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 705251d2899bc006e21ff3e34a3fc3eba2dd4d00 Original-Change-Id: I7488533b83b8119f8c85cbf2c2eeddabb8e9487d Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/372579 Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org> Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16363 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-31soc/intel/apollolake: Disable Periodic Retraining per-SKUAndrey Petrov
Certain LPDDR4 models have some HW issues that can be worked around by turning off Periodic Retraining feature in the memory controller. Add option to disable PR per SKU. BUG=chrome-os-partner:55466 TEST=run RMT test, pass Change-Id: Ie7aa79586665f6d3a7edd854a9eef07e6a1b2ab8 Signed-off-by: Andrey Petrov <andrey.petrov@intel.com> Reviewed-on: https://review.coreboot.org/16320 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
2016-08-30nyan-blaze: Correct indentation for sdram configsPaul Kocialkowski
This corrects indentation for sdram configs in nyan_blaze. Change-Id: Ia9ad2a37c6e3b79e1260f490db893244c32685b6 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: https://review.coreboot.org/16342 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-30mainboard/google/reef: set SLP_S3_L assertion width to 28msAaron Durbin
The reef board needs at least ~28ms for its S0 rails to discharge when S3 is entered. Because of the granularity in the chipset the effective SLP_S3_L assertion width is 50ms. BUG=chrome-os-partner:56581 Change-Id: I20514eb0825cd4bc2ee9276b648204b7bfd6a7b0 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16327 Tested-by: build bot (Jenkins) Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-27gru: Make SDRAM parameters individual struct files in CBFSJulius Werner
This patch changes Gru SDRAM parameters from structures that just get compiled into the romstage to individual CBFS files. This allows us to only load the parameter set we need for the board we're booting from flash, which reduces our boot time and the SRAM memory footprint required to hold the romstage. TEST=Booted Kevin. Change-Id: Ie88a515cbdb19a794ca0a230a56bcc82bed1e550 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16274 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-27lenovo/x200,t400: enable C4 cpu low power stateArthur Heymans
This enables the C4 low power state on the lenovo x200 and t400. It's inspired by the thread on the mailinglist: "[coreboot] Lenovo X200 running Coreboot drains 3-4W more power than with Vendor BIOS". What this does, is to enable a C3 state using MWAIT(C3) request and set the southbridge config c4onc3_enable to automatically upgrade C3 to the lower power C4 state. The latency (0x37) is the same value used by the vendor bios. With C4 enabled the idle power consumption is about ~2-3W lower. TEST= build and install on target. Use powertop top to measure power usage. To manually disable c-state to compare them, do (tested on linux 4.4): echo 1 > /sys/devices/system/cpu/cpu*/cpuidle/stateX/disable Change-Id: I1a1663a7662ebc7157a965667680688ad6a33545 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/15251 Tested-by: build bot (Jenkins) Reviewed-by: Swift Geek Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de>
2016-08-25vboot: consolidate google_chromeec_early_init() callsAaron Durbin
On x86 platforms, google_chromeec_early_init() is used to put the EC into RO mode when there's a recovery request. This is to avoid training memory multiple times when the recovery request is through an EC host event while the EC is running RW code. Under that condition the EC will be reset (along with the rest of the system) when the kernel verification happens. This leads to an execessively long recovery path because of the double reboot performing full memory training each time. By putting this logic into the verstage program this reduces the bootblock size on the skylake boards. Additionally, this provides the the correct logic for all future boards since it's not tied to FSP nor the mainboard itself. Lastly, this double memory training protection works only for platforms which verify starting from bootblock. The platforms which don't start verifying until after romstage need to have their own calls (such as haswell and baytrail). Change-Id: Ia8385dfc136b09fb20bd3519f3cc621e540b11a5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16318 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-24google/reef: Tune eMMC DLL settings for reef evtChiranjeevi Rapolu
Apply eMMC tuned DLL settings for reef evt. Modify comments to avoid replicating info. Add EDS reference. BUG=chrome-os-partner:55648 BRANCH=none TEST=Verify that reef evt boots to OS from eMMC. Change-Id: If3bf51f3b7d38320f504ea6fbecf7c188a94ae5c Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Reviewed-on: https://review.coreboot.org/16296 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2016-08-23arch/riscv: Implement the SBI againJonathan Neuschäfer
Not all SBI calls are implemented, but it's enough to see a couple dozen lines of Linux boot output. It should also be noted that the SBI is still in flux: https://groups.google.com/a/groups.riscv.org/forum/#!topic/sw-dev/6oNhlW0OFKM Change-Id: I80e4fe508336d6428ca7136bc388fbc3cda4f1e4 Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16119 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-23src/mainboard: Remove unnecessary whitespace before "\n"Elyes HAOUAS
Change-Id: I9789b0b3339435fbe30c69221826bf23c9b3c77b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/16283 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-23emulation/qemu-i440fx: add cmos.default fileAntonello Dettori
Add cmos.default file in order to ease future testing and debugging of cmos related code. Change-Id: I7c6a0aa4e38bb08a520e4838fa216c81b50f2917 Signed-off-by: Antonello Dettori <dev@dettori.io> Reviewed-on: https://review.coreboot.org/16247 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-22mb/asus/kgpe-d16: Add TPM supportTimothy Pearson
The ASUS KGPE-D16 accepts an optional Infineon LPC TPM module. Expose the TPM LPC device to the host operating system. Change-Id: If500e9162bf1e233ccaa35db79452daa59a34f2f Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16269 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-21mb/asus/[kgpe-d16|kcma-d8]: Fix whitespace errors in devicetree.cbTimothy Pearson
Change-Id: I49925040d951dffb9c11425334674d8d498821f0 Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-on: https://review.coreboot.org/16268 Tested-by: build bot (Jenkins) Reviewed-by: Omar Pakker
2016-08-20google/reef: Save DIMM info from SMBIOS memory HOBRavi Sarawadi
Add support for SMBIOS memory HOB save. Add DIMM 'part_num' info to be saved as part of SMBIOS memory HOB. BUG=chrome-os-partner:55505 TEST='dmidecode -t 17' and 'mosys -k memory spd print all' Change-Id: I53b4a578f31c93b8921dea373842b8d998127508 Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/16249 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-19rockchip/rk3399 & gru/kevin: support sdram 933MHz on kevinLin Huang
We should be running faster. Faster = better. BRANCH=None BUG=chrome-os-partner:54873 TEST=Boot; stressapptest -M 1028 -s 10000 Change-Id: I7f855960af3142efb71cf9c15edd1da66084e9d8 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 51bfd2abb1aba839bd0b5b85e9e918f3cc4fd94d Original-Change-Id: Iec9343763c1a5a5344959b6e8c4dee8079cf8a20 Original-Signed-off-by: Lin Huang <hl@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/362822 Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16241 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-19qemu-riscv: Remove obsolete CSR - send_ipiMartin Roth
This aligns the code in qemu-riscv with the code in spike-riscv. The previous code gives an error in the updated toolchain as the send_ipi CSR is no longer valid. This gave the build error: src/mainboard/emulation/qemu-riscv/qemu_util.c:64: Error: Instruction csrw requires absolute expression Change-Id: Iac0f66e8e9935f45c8094d5e16bedb7ac5225424 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/16244 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
2016-08-19google/reef: Configure NFC gpios correctly before entering sleepFurquan Shaikh
Before entering sleep, ensure that the NFC gpios are configured correctly to avoid leakage. BUG=chrome-os-partner:56281 Change-Id: I2bb2e7ba468df445aa5f6c2b22ae0a74fcaa44f6 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16243 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-18Kconfig: rename BOOT_MEDIA_SPI_BUS to BOOT_DEVICE_SPI_FLASH_BUSAaron Durbin
Provide a default value of 0 in drivers/spi as there weren't default values aside from specific mainboards and arch/x86. Remove any default 0 values while noting to keep the option's default to 0. BUG=chrome-os-partner:56151 Change-Id: If9ef585e011a46b5cd152a03e41d545b36355a61 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16192 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-18intel/amenia: Update eMMC DLL settingsBora Guvendik
Update eMMC DLL setting for amenia board, after that system can boot up with eMMC successfully. BUG=chrome-os-partner:51844 TEST=Boot up with eMMC Change-Id: Ia7bd96db69fbe575e57847249c34d91b2a1fdcef Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/16237 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-18Kconfig: lay groundwork for not assuming SPI flash boot deviceAaron Durbin
Almost all boards and chipsets within the codebase assume or use SPI flash as the boot device. Therefore, provide an option for the boards/chipsets which don't currently support SPI flash as the boot device. The default is to assume SPI flash is the boot device unless otherwise instructed. This falls in line with the current assumptions, but it also allows one to differentiate a platform desiring SPI flash support while it not being the actual boot device. One thing to note is that while google/daisy does boot with SPI flash part no SPI API interfaces were ever implemented. Therefore, mark that board as not having a SPI boot device. BUG=chrome-os-partner:56151 Change-Id: Id4e0b4ec5e440e41421fbb6d0ca2be4185b62a6e Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16191 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com>
2016-08-17mainboard: Clean up boot_option/reboot_bits in cmos.layoutNico Huber
Since commit 3bfd7cc (drivers/pc80: Rework normal / fallback selector code) the reboot counter stored in `reboot_bits` isn't reset on a reboot with `boot_option = 1` any more. Hence, with SKIP_MAX_REBOOT_CNT_CLEAR enabled, later stages (e.g. payload, OS) have to clear the counter too, when they want to switch to normal boot. So change the bits to (h)ex instead of (r)eserved. To clarify their meaning, rename `reboot_bits` to `reboot_counter`. Also remove all occurences of the obsolete `last_boot` bit that have sneaked in again since 24391321 (mainboard: Remove last_boot NVRAM option). Change-Id: Ib3fc38115ce951b75374e0d1347798b23db7243c Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/16157 Tested-by: build bot (Jenkins) Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com> Reviewed-by: York Yang <york.yang@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-16Revert "rockchip: rk3399: enable sdhci clk for emmc"Shunqian Zheng
This reverts commit 462e1413 ("rockchip: rk3399: enable sdhci clk for emmc") Enabling this clock in coreboot is no longer needed as it's handled in the kernel driver now. BUG=chrome-os-partner:52873 TEST=boot from usb/sdcard and check there is /dev/mmcblk0 BRANCH=none Change-Id: I92cf51f175fe56a09ab9329b29a27c77ef4328e1 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 5707d1269a253dabf825be120d1f9348ffaab6d0 Original-Change-Id: I8bca870c663d8ce8fac5daaaaf8225489f22ed13 Original-Signed-off-by: Shunqian Zheng <zhengsq@rock-chips.com> Original-Reviewed-on: https://chromium-review.googlesource.com/367421 Original-Commit-Ready: Brian Norris <briannorris@chromium.org> Original-Reviewed-by: Douglas Anderson <dianders@chromium.org> Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/16152 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2016-08-15reef: Increase TSR2 threshold to 100Furquan Shaikh
This is a temporary work-around since the current threshold of 70 on TSR2 results in thermal trip and shutdown while the kernel is booting. Changing this threshold to 100 allows kernel to boot up to userspace. Following values were read: $ cat /sys/class/thermal/thermal_zone4/temp 81800 $ cat /sys/class/thermal/thermal_zone4/type TSR2 BUG=chrome-os-partner:56155 BRANCH=None TEST=Boots to OS. Change-Id: I951553ed4c93b02239a51a0d3036e4a750eea04b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16156 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins)
2016-08-15mainboard/google: remove unused BOOT_MEDIA_SPI_CHIP_SELECT optionAaron Durbin
The BOOT_MEDIA_SPI_CHIP_SELECT option is not used in any of the code. Remove its usage. BUG=chrome-os-partner:56151 Change-Id: I522b62a2371b8a167ce17c48117669390cda14cd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/16185 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-15mb/gigabyte/ga-b75m-d3v: Add missing board URLJonathan Neuschäfer
Change-Id: I990038c09f5805c8e670fd316808dde767e8671b Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/16159 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2016-08-14src/mainboard: Capitalize ROM, RAM, CPU and APICElyes HAOUAS
Change-Id: Ia1f24d328a065a54975adde067df36c5751bff2d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/15987 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
2016-08-13Revert "gru: Show the current time on start-up"Julius Werner
This reverts commit 850e45f19f498eedd80da4a97a5ce641e2cec6d5. google_chromeec_init() is a weird function that can lead to confusing behavior. I'm not sure how it's meant to work on the boards that use it, but it causes problems on Kevin and other non-x86 boards have never used it either. It doesn't really do anything anyway (the EC works fine without an initial HELLO), so at best it's just a waste of time... let's take it back out. There's also no need to display the current time on every boot... other boards don't do that and the eventlog already fills the same purpose. Cut it out to avoid one extra host command overhead. BRANCH=None BUG=chrome-os-partner:55995 TEST=Recovery reasons now get correctly propagated across the EC reboot. Change-Id: Ic3b772780d4d05e362c269969e6e4e7069482bb6 Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: 103d86e68cd164bea39aa1edc8668d80358edbde Original-Change-Id: I58fd5e6094e1c8cb6368e7a4569ab9231375fbc9 Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/367351 Original-Reviewed-by: Simon Glass <sjg@chromium.org> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/16153 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11reef: Update chromeos.fmdFurquan Shaikh
1. Get rid of LBP2 partition 2. Shrink RO size 3. Increase RW-A and RW-B sizes 4. Increase RW_MRC_CACHE size CQ-DEPEND=CL:366793 BUG=chrome-os-partner:52127, chrome-os-partner:55699, chrome-os-partner:55778 BRANCH=None TEST=Compiles successfully. Boots to OS. Change-Id: Iad41d8cc7697e6d73f1aa2c699b0e8559349b77e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/16145 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2016-08-11rockchip/rk3399: Add code to neuter Type-C PHY for firmware USBJulius Werner
The Rockchip RK3399 integrates a USB Type-C PHY in charge of things like SuperSpeed line muxing for rotated cable orientations in the SoC. While fancy, this is very complicated and we don't want to implement support for the whole thing in firmware. The USB Type-C standard has intentionally been designed in a way that the USB 2.0 (HighSpeed) lines always "just work" in any orientation (by just shorting different pins in the connector together) so that simple use cases like ours can get basic USB functionality without much hassle. However, a semi-configured Type-C PHY can confuse USB 3.0 capable devices into thinking we're actually supporting SuperSpeed, and fail at that rather than establishing a reliable HighSpeed connection. This patch sets enough bits in the Type-C PHY to electrically isolate the SuperSpeed lines from the connector so that the connected device isn't going to get any fancy ideas and reliably falls back to USB 2.0. Also clean up the rest of the USB code while we're at it: avoid writing a few bits that are already in the right state from their reset values anyway, or reading values whose content we already know for this SoC. Rename the USB controllers to the name actually used in the Rockchip documentation (USB OTGx) rather than the name blindly copied from Exynos code (USB DRDx). BRANCH=None BUG=chrome-os-partner:54621 TEST=Plug a USB 3.0 Patriot Memory stick into both ports in all orientations, observe how it gets reliably detected now (safe for some known hardware issues on my board). Change-Id: Ifce6bcddd69f2e8f2e2a2f48faf65551e084da1e Signed-off-by: Martin Roth <martinroth@chromium.org> Original-Commit-Id: c526906f998bf66067d3addb8b3d3a126c188b1e Original-Change-Id: Ie80a201a58764c4d851fe4a5098a5acfc4bcebdf Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/366160 Original-Reviewed-by: liangfeng wu <wulf@rock-chips.com> Original-Reviewed-by: Shelley Chen <shchen@chromium.org> Original-Reviewed-by: <515506667@qq.com> Reviewed-on: https://review.coreboot.org/16125 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-25 15:14:35 +0000