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Move selects from Kconfig.name to Kconfig so that the configuration is
at one place and not distributed over two files.
Change-Id: Ifccf2b3521d84f6a678872bbccf9bf390c25ce37
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60060
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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This patch adds the following list of changes:
1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p
devictree.
2. Add support for 2 mainboards as ADL-N board with default EC (Windows
SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from
adlrvp-p.
3. Add mainboard Kconfig to Kconfig.name file
4. Handle mainboard names in Kconfig file for ADLRVP N
5. Add config options to pick the adlrvp_n devicetree
Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad
Signed-off-by: Usha P <usha.p@intel.com>
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause
the TPM kernel driver to send a shutdown command before s0i3 entry. This
change depends on S0i3 verstage running and reinitializing the TPM.
BUG=b:200578885
BRANCH=None
TEST=TPM shutdown sent during s0i3 entry on guybrush
Change-Id: I206022cc2a29690186206966c5d45bd55c303248
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add new memory parts in the mem_list_variant.txt and generate the
SPD ID for the parts. The memory parts being added are:
1. Micron MT53E512M32D1NP-046 WT:B
2. Samsung K4U6E3S4AB-MGCL
3. Hynix H54G46CYRBX267
BUG=b:209889645
BRANCH=dedede
TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59991
Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The code in these files is meaningless, and can be dropped.
Change-Id: I11571885059e8d5f930f741172c74b25faa09a15
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60103
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 8
BUG=b:204844399
TEST=USE="project_primus emerge-brya coreboot" and verified
the setting meets the audible noise specification
Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com>
Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60071
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up Thunderbolt and related settings to CMOS value of `thunderbolt`.
Changes TcssXhciEn, UsbTcPortEn and the relevant PCI devices.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
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add Hynix H54G56CYRBX247 support
BUG=b:210365851
BRANCH=guybrush
TEST=emerge-guybrush coreboot chromeos-bootimage
power on successfully
Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60075
Reviewed-by: Rob Barnes <robbarnes@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add I2C bus for taniks in Kconfig
BUG=b:210390520
TEST=emerge-brya coreboot and can boot to OS.
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I9b1719c3140c13f67e7cb0e6a69257774884bd4d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60077
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Based on the Taniks's schematic, generate memory settings.
Schematic version is G570_MB_CHROME_1207_1630_ADC.
BUG=b:209531192,b:209553289
TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I0c0794fb94d1f6271de604835ae1d2b20696ee70
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59947
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Add initial gpio configuration for taniks according to schematics
G570_MB_CHROME_1207_1630_ADC. The schematics reserved HPS and FP but
taniks doesn't use them, so set FP and HPS related pins to NC.
BUG=b:209492408, b:209553289
TEST=FW_NAME=taniks emerge-brya coreboot
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59938
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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To save the S3 power, USB3_HUB_RST_L is externally pulled up to a weak
resistor, so we have to reset the hub as early as possible.
Otherwise the USB3 hub may be not usable. Therefore, move USB3 HUB
reset function to bootblock.
BUG=b:210065282
TEST=build pass
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I92feb2316302fda32478b24c014bcd380d0ac55d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60088
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I736234b9a960c58193fcf7bc9184c9581c6c953b
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60059
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Set open-drain GPIOs for ChromeOS as input and high-z mode.
After applying this patch, we can measure these pins from 1.0V to
correct voltage (1.8V) to prevent wrong judgement of low/high.
Reference document:
MT8186_SoC_Pinmux_V1_1
BUG=b:209342636
TEST=measure pins voltage 1.8V on kingler board
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60002
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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ALC5682-VD/ALC5682-VS use different kernel driver by different hid name.
Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:206676530
TEST=build
Change-Id: Ie73dc376078c0836edd980e09629399c5cc19594
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add Elan 6918 touchscreen for dewatt. (EKTH6918 Product Spec V0.5)
BUG=b:208373433
TEST=emerge-guybrush coreboot chromeos-bootimage. Teseted with Elan 6918 touchscreen.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59975
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Add Synaptics S9831 touchpad for dewatt.
BUG=b:208182457
TEST=emerge-guybrush coreboot chromeos-bootimage. Tested with Synaptics S9831 touchpad.
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Change-Id: Id3e0636dd0ce5b80c2044c1dfca20ca7eac87fc9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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Add ALC5682I-VS codec support. ALC5682I-VD/ALC5682I-VS load different
hid name depending on SSFC.
BUG=b:198722640
BRANCH=octopus
TEST=Set CBI SSFC BIT9-11 to select codec, and test audio works
Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8
Signed-off-by: Paul Huang <paul2_huang@pegatron.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marco Chen <marcochen@google.com>
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ALC5682-VD/ALC5682I-VS load different kernel driver by different hid
name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE
field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5)
for codec selection.
ALC5682-VD: _HID = "10EC5682"
ALC5682I-VS: _HID = "RTL5682"
BUG=b:198689479
BRANCH=zork
TEST=ALC5682-VD/ALC5682I-VS audio codec can work
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59558
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Tiger Lake mainboards use the default value for the setting
`SataMode`. Thus, drop it from their devicetree.
Change-Id: I291048250bc82552fde7c71a1dcda4894a61d465
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59890
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Coffee Lake mainboards use the default value for the setting
`SataMode`. Thus, drop it from their devicetree.
Change-Id: Ibb329eb8b752c2220bb25f14fb6ae92dd8a308d6
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59889
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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All Skylake mainboards use the default value for the setting `SataMode`.
Thus, drop it from their devicetree.
Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI
table), PLD is added to ACPI table. It causes the DUT to not boot into
the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2
to solve this issue.
Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table")
BUG=b:209723556
BRANCH=none
TEST=build coreboot and boot into OS.
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59973
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enable TPM init in bootblock so that all further stages and other CBFS
files are directly measured into PCRs immediately instead of being
logged into a buffer and replayed to the TPM in ramstage.
Change-Id: Ib3ac29aa72abe8e967660ae7e8416aeb8812de26
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7
SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4
PCH devices are connected on the platform, an external differential
buffer chip needs to be placed at the platform level.
A mainboard designer can choose to add an external clock chip, and
select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER.
CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to
discrete buffer for further distribution to platform.
TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot.
localhost ~ # dmesg | grep mmc
[ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA
[ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa
[ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB
[ 5.494268] mmcblk0: p1
Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb
Signed-off-by: Subrata Banik <subi.banik@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch adds the setting of PsysPmax to 143 W according to
gimble board design.
BUG=b:206990759
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I851e0871461a9a9769c6b84f7d8287d989c23f06
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59950
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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As per the schematics, smart card is expected to operate in normal mode
by default. So configure the SOC_SC_PWRSV gpio accordingly.
BUG=b:202992077
TEST=Build and boot to OS in Nipperkin board version 2.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I8e12600ad45734b144a30c868f0e4f323aa056f6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59984
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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After assessing the signal integrity, 100 MHz SPI fast speed can be
enabled for SPI ROM.
BUG=None
TEST=Build and boot to OS in Nipperkin board version 2. Perform 250
iterations of warm and cold reset each.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: Id973acb939b69e0beda26252e57a278892f2f57d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59983
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
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CB:58374 (for mb/google/brya0) was merged before brya4es is
available (CB:59728). And since brya4es is forked from brya0, brya0's
change need to be brought into brya4es as well.
BUG=b:203014972
TEST=build
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59935
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Hook up `Device4Enable` FSP setting to devicetree state and drop its
redundant devicetree setting `Device4Enable`.
The following mainboards enable the DPTF device in the devicetree
despite `Device4Enable` is not being set.
* google/deltaur
Thus, set it to off to keep the current state unchanged.
Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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`SataEnable` is set by some boards, but it doesn't have any effect since
its related FSP option is hooked up to the devicetree state. Thus, drop
it.
Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59926
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Hook up `SmbusEnable` FSP setting to devicetree state and drop its
redundant devicetree setting `SmbusEnable`.
The following mainboards enable the SMBus device in the devicetree
despite `SmbusEnable` is not being set.
* google/deltaur
* starlabs/laptop
Thus, set it to off to keep the current state unchanged.
Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Copy the default configuration from Puff.
2. Update the 'stop_gpio' to GPP_H22.
BUG=b:193750191
BRANCH=None
TEST=Update kernel for 8125 outbox driver and test with
command suspend_stress_test.
Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58105
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The original change was for mb/google/redrix (commit 0167f5adbb),
"The ChromeOS kernel platform driver is adding support for a ChromeOS
privacy screen device, and in order to locate that device, the driver
uses the GOOG0010 reserved HID for this"
But it was merged before redrix4es is available. As redrix4es is forked
from redrix, relevant change in redrix need to be brought into
redrix4es as well.
BUG=b:206850071
TEST=build
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: I5ac90c249273bf4e75cccb5889844a7f196f56fc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59987
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory.
CPLD returns different values for every board revision. Use this value
to determine the memory type.
BUG = N/A
TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4
Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59754
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Since 4ES variants were forked from their own original variants,
use the same TPM I2C as well.
BRANCH=none
BUG=b:201767461
TEST=emerge-brya coreboot and check the artifacts
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59849
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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All SPI interface setup related functionality that Stoneyridge
implemented in its southbridge code is already present in the common AMD
SoC code, so use that code instead.
The common fch_spi_early_init function requires the SPI controller's
base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right
before it. fch_spi_early_init then calls lpc_enable_spi_rom and
lpc_enable_spi_prefetch which can be removed from the board code now.
Next it calls fch_spi_configure_4dw_burst which does the same as the now
removed sb_disable_4dw_burst function when
SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default.
This option can also only be set to y for SoCs that aren't Stoneyridge.
Finally fch_spi_early_init calls fch_spi_config_modes which configures
the SPI mode and speed settings according to the Kconfig settings and
the settings in the amdfw part. On Kahlee this was done by calls to
sb_read_mode and sb_set_spi100 before. The previous patch added the
remaining Kconfig settings, so the resulting register values don't
change in the non-EM100 case. In the EM100 case the TPM speed is changed
from 64 to 16 MHz.
TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode
with a first-generation EM100 results in Google/Barla reaching the
payload and the show_spi_speeds_and_modes call in bootblock prints the
expected settings:
relevant bootblock console output in non-EM100 case:
SPI normal read speed: 33.33 MHz
SPI fast read speed: 66.66 Mhz
SPI alt read speed: 66.66 Mhz
SPI TPM read speed: 66.66 Mhz
SPI100: Enabled
SPI Read Mode: Dual IO (1-2-2)
relevant bootblock console output in EM100 case:
SPI normal read speed: 16.66 MHz
SPI fast read speed: 16.66 MHz
SPI alt read speed: 16.66 MHz
SPI TPM read speed: 16.66 MHz
SPI100: Enabled
SPI Read Mode: Normal Read (up to 33M)
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Before this patch only the SPI settings that will also end up in the
amdfw part of the firmware were specified in the board's Kconfig. This
patch adds the settings from Kahlee's bootblock.c to the Kconfig file
which will be needed in subsequent patches. Also add a comment about the
EM100 case.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ie42feb9b41f435c329bf1c78471e65ef5a3fb783
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59967
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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To support gpio reset SoC, we need to pass the reset gpio parameter to
BL31.
TEST=build pass
BUG=b:202871018
Cq-Depend: chromium:3188686
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59824
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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The reference design has changed to use GPIO SET1 for NOR flash.
There are no devices already built using SET0 so we can safely
change the implementation without conditional configs.
Reference document:
kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11.
crab_proto 0_2021112.pdf, page 11.
BUG=b:202871018
TEST=flash verify pass on kingler on bootblock stage
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Retrieve the SKU ID for Corsola via CBI interface.
If that failed (or no data found), fallback to ADC channels for SKU ID.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59944
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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amplifier
Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB"
BUG=b:208912135
TEST=ALC5682I-VD and ALC1015Q-VB can work normally
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: Id661280061ede3fbb63c962dee8fb18a2053ad66
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59865
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush
reference memory parts is used as the base, then Nipperkin memory
parts were appended, followed by DeWatt memory parts. Duplicates were
removed.
The memory id mapping was not affected on guybrush reference and
Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will
need to be adjusted.
This works around a limitation in APCB, which currently only supports
one set of memory SPDs.
BUG=b:209486790, b:204151079
BRANCH=None
TEST=Boot guybrush and nipperkin
Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995
Signed-off-by: Rob Barnes <robbarnes@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59923
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue.
BUG=b:209568644
BRANCH=none
TEST=build coreboot and system boot into OS.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59953
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Initialize SPI bus 2 for TPM control.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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Set VB2_CONTEXT_EC_TRUSTED in verstage_main.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59942
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
|
Initialize SPI bus 1 for Chrome EC control.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I7d032d595f7ca1dbed3de4dfe308ff4be64333cd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59941
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
|
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These functions can't be weak, because they actually need to configure
the GPIOs for eSPI and the TPM. With this change zork boots again.
I also noticed that zork doesn't use the early table in bootblock. This
means that zork will only boot if psp_verstage is enabled.
BUG=b:209465425
TEST=boot zork to ramstage
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I384fd578efe7da0a3d74829cccf38c3ed524f130
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
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Add a list of gpios to lock for brya. This currently includes
GPIOs connected to the FPMCU.
BUG=b:201430600
TEST='emerge-brya coreboot chromeos-bootimage', flash and verify that
brya0 boots successfully to kernel.
Change-Id: Idea42a58575c280be0770d38f934acdf5508c45d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58353
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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- Enable Acoustic noise mitigation
- Set slow slew rate VCCIA and VCCGT to 16
BUG=b:206704930
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I2be3d30403284b98276c837adefd91aa62c971e4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59535
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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According to the latest schematic, exchange I2C port for TPM/touchscreen.
TPM: I2C3 -> I2C1
Touchscreen: I2C1 -> I2C3
BUG=b:205648040
TEST=FW_NAME=redrix emerge-brya coreboot
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Change-Id: I3a8339c23522019da884944246427512170510b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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This patch adds the setting of PsysPmax to 143 W according to
gimble board design.
BUG=b:206990759
TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is
passed to FSP by enabling FSP log & Boot into the OS
Change-Id: Id6a203f05ecfcc1020a422850d35fa3fa64e01d0
Signed-off-by: Chia-Ling Hou <chia-ling.hou@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59797
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ryan Lin <ryan.lin@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Eject event is high. Set wake event to active high. The polarity of the SCI and the wakeup_event_action for the pen ejection feature were both
backwards, and was causing the system to fail to enter sleep states
because the event was always asserted.
BUG=b:208937710
TEST=only release switch can wake system.
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: I568e9175c7a66599f7a525c32e4def7a79b55a0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59861
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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The stryke project/mainboard never ended up being built and was
cancelled early on, therefore remove it from the tree.
Change-Id: I4d91fbd4ba0abe0cf599e8e75f04398ef9ff5222
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59875
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
|
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Add WiFi SAR table for felwinter.
BUG=b:206901900
TEST=emerge-brya chromeos-config chromeos-config-bsp-private
coreboot-private-files-baseboard-brya coreboot chromeos-bootimage
and checked SAR table can load by WiFi driver.
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I0de710f4447302ee545a67cbd79373bdd2077637
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59718
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
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Change HID name from INT3499 to PRP0001 along with size and
address width. Size decreased from 10K to 2K, address width
decreased from 14 to 8.
BUG=b:203014972
Test= Boot board and issue commands:
`cat /sys/bus/i2c/devices/i2c-PRP0001:02/eeprom >
./brya_imx208_eeprom.bin`
`hexdump -C brya_imx208_eeprom.bin > brya_imx208_eeprom_dump.log`
You should see the result in brya_imx208_eeprom_dump.log to be
same as module nvm file by vendor provided or meet the Intel nvm
calibration format.
(e.g. first 4 bytes be 0x01, 0x03, 0x01, 0x00)
Signed-off-by: Bernardo Perez Priego <bernardo.perez.priego@intel.com>
Change-Id: Ib2366ba4c8bb70d8cc82e64ca585b118a96260c0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add new memory parts in memory_parts_used.txt and generate SPD id for
these parts:
Samsung K4U6E3S4AA-MGCL
BUG=b:204014463
TEST=run part_id_gen to generate SPD id
Change-Id: Icb0f211508450b16b2e5d214ae6adc9852718a59
Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59642
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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The Hermes mainboard is used in different system configurations. The
current VBT for Poseidon systems is unsuitable for Avalanche systems
because display ports are connected differently.
Add a new field in the BMC config EEPROM layout and use it to choose
the correct VBT for every system configuration.
Change-Id: I2647f2ae3f496b9ad75980ba86beb7800fdb0668
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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The original RCOMP resistor and target values only apply to ULT CPUs and
do not make sense for the CFL-S CPUs Hermes uses. Fix the RCOMP settings
and the associated comments.
Tested, still boots.
Change-Id: I015797c58c914c6581d472e6d70d2dd7bad2b14f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58364
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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Define a new field in the board config EEPROM layout for port B Vref.
Write port B Vref settings to unused non-volatile NID 0x12 instead of
NID 0x18, the actual port B NID. Because per-port Vref settings don't
persist after codec resets, a custom Realtek driver (ab)uses NID 0x12
to restore port B Vref after resetting the codec.
Change-Id: Iaa11ba9c74f643e94046d4983fbce65dbedd1025
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58879
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Update the pin configs for the front panel jacks.
Change-Id: I3760f0a25e964cf0eba99d180fd6f3e8488af868
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Use lowercase for hex numbers, sort includes alphabetically and avoid
relying on indirect inclusion. Include `<intelblocks/gpio.h>` instead
of `<intelblocks/gpio_defs.h>`, as the latter implcitly relies on one
definition from `<soc/gpio.h>`. Also drop useless dsdt.asl and fix up
the indentation of some includes.
Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.
Change-Id: I3aeb9a644cf33cb4b1987174f40ef0fc7daccfa9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59672
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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There's no need to use a variant structure here. Only one variant is
used, and revision-specific differences are handled at run-time, and
it's unlikely that another variant will ever exist.
Reorganize the mainboard code to get rid of the variant structure.
Change-Id: I1543f5b76975b0e7183fbb759e9bae5c34151d06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59671
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
|
Change-Id: I943d0e2a91778df306f323e2b889cd4e928e0c2b
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59837
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
|
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EN_SPKR GPIO is used as a multiplexer select signal between RAM_ID
straps and Developer Mode Beep signals. During boot up it is LOW and
selects RAM_ID straps. When the system enters OS, it is driven HIGH and
selects DEV BEEP signals. Since in some boards, the GPIO chosen is in S5
domain it does not reset until the system enters mechanical off (G3)
state. On scenarios where the power button is pressed when the system is
in S5, incorrect RAM_ID strap is being read because the EN_SPKR is still
selecting DEV BEEP signal. This causes boot up failures. Fix this by
configuring the EN_SPKR GPIO (in S5 domain) explicitly in PSP verstage.
BUG=b:204450368
TEST=Build and boot to OS in Guybrush. Perform suspend-resume cycle
followed by a S5 -> S0 boot cycle for 2 iterations successfully.
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Change-Id: I9a52a167da9c7040731da5d355ec345fd9b13762
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59813
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Turn on the LAN device in devicetree and add Kconfig item
RT8168_GET_MAC_FROM_VPD to support programming MAC address.
BUG=b:193750191
BRANCH=None
TEST=Use 'vpd -s ethernet_mac0=...' to write MAC to VPD.
Use 'ifconfig' to check if the MAC written successfully.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: Ibb95b02fd6d61621ef46db4d63b48456a0a72732
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207625007
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Change-Id: I20cdd1650d1ca774065a6c051006dfd0b7a3fd79
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59726
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Create the beadrix variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:204882915
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_BEADRIX
Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com>
Change-Id: Ie08cbc19967eca8ba31ea3203e71c4e1fef044d6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59302
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
In next build phase, primus will exchange i2c port for touchscreen and cr50.
BUG=b:207834727
TEST=build pass
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: Ief1b156b866a9aaa2919f0e209b6439c7019e939
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59737
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Due to the vGPIO is not reset when we power on through S5, we would
met MCA when PCIE send L1 request without following Ack
BUG=b:207070967
TEST=S0->S3->S5->power key->S3->S0, see if boot up normal
Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com>
Change-Id: Ice522260f288b165ae66dddc3e1979e806b53f9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59749
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
Create the taniks variant of the brya0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0.)
BUG=b:207402720
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_TANIKS
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I797051f93019ccf72f1007d9c0b98cfb071717b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59643
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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1. Set the PL1, PL2 and PL4 according to issue b:193864533 comment#55
and Intel's doc #626774.
2. Set PsysPL2 and PsysPmax according to the conclusion in issue
b:193864533 comment#23 and comment#29.
BUG=b:193864533
BRANCH=none
TEST=Compare the measured power from adapter with the value of 'psys'
from the command 'dump_intel_rapl_consumption'.
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I9261902b8c892d0b866f326b24988039c1d30b56
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59576
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Copy function variant_update_power_limits from brya to set power limits.
Add function variant_update_psys_power_limits and copy the algorithm
from puff. Add structure system_power_limits and psys_config to define
and configure the psys power limits.
BUG=b:193864533
BRANCH=none
TEST=Build pass
Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com>
Change-Id: I183017068e9c78acb9fa7073c53593d304ba9248
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58241
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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DVT schematic will exchange TPM_I2C3 to TPM_I2C1, that may need swap
TPM I2C with touchscreen I2C to avoid TPM I2C fall on muxed ISH I2C,
need change I2C map, sch amd GPIO map. b/196293623
BUG=b:207613972
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I26d059a7ea5a3fdf00de260214c00d3bba9aa7f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59580
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Follow the latest HW schematic change.
BUG=b:208556921
TEST=build pass
Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com>
Change-Id: Ic05843487ea540b8cd9a50d5f73803905fd80d49
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59799
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Keeping the PM timer enabled will disqualify an ADL system from entering
S0i3, and will also cause an increase in power during suspend states.
The PM timer is not required for brya boards, therefore disabling it.
Fixes: 0e905801 (soc/intel: transition full control over PM Timer from
FSP to coreboot)
BUG=b:206922066
TEST=Boot gimble to OS and verify S0i3 counter incrementing after
exiting S0ix suspend states.
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Change-Id: I8005dacd732c033980ccc479375ff5b06df8dac1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59790
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The Alder Lake code currently supports the PCH-M and PCH-P types, which
have some differences (so far, only the amount of PCIe I/O). Mainboards
can use the `SOC_INTEL_ALDERLAKE_PCH_M` Kconfig option to specify which
PCH type they use: select the option to choose PCH-M, do not select the
option to choose PCH-P. While this works, it can be confusing once more
PCH types are added.
Introduce the `SOC_INTEL_ALDERLAKE_PCH_P` Kconfig option so that boards
have to explicitly choose a PCH type. Also, use this option to restrict
the PCH-P defaults for PCH-dependent settings to avoid unintended reuse
of the PCH-P defaults when adding a new PCH type. To make sure only one
PCH type is selected, add some preprocessor in `bootblock.h` to provoke
a build-time error if this requirement is not met. Kconfig doesn't seem
to have a mechanism to describe sets of mutually-exclusive bool options
that allows said options to be selected (a `choice` block doesn't allow
its elements to be selected). Finally, adapt the ADL boards accordingly.
Change-Id: I7deca820e08ce2b5a220f3c97a511a4f3464a976
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59804
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
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This area is used for storing AP RO verification information.
BRANCH=none
BUG=b:141191727
TEST=built a guybrush firmware image and verified that the RO_GSCVD
area was indeed added:
$ dump_fmap /build/guybrush/firmware/image-guybrush.bin | \
grep -B3 RO_GSCVD
area: 25
area_offset: 0x00808000
area_size: 0x00002000 (8192)
area_name: RO_GSCVD
$
- verified that guybrush device boots fine with the new image.
Change-Id: Ifa24d5a6271a8bcbf737d4580ec85b9cfdd9af01
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57864
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The ChromeOS kernel platform driver is adding support for a ChromeOS
privacy screen device, and in order to locate that device, the driver
uses the GOOG0010 reserved HID for this.
Patch for 5.10 kernel can be found at:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3289984
BUG=b:206850071
TEST=dump SSDT, see _HID instead of _ADR
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: If988ca94b6c70d08a7b07cc9f6bbb077fac84e5b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59731
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Some herobrine variants have USB hub powered by discrete LDO that is
controlled by USB_HUB_LDO_EN gpio. Assert the GPIO on boot.
BUG=b:182963902
TEST=Validated on qualcomm sc7280 development board.
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ia94e046f9eb0d3ce593f3445e0203a7391c14de2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55378
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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Initialize by calling `setup_usb_host0()` from SOC code
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: Ic378352a97e4f3ed89089f1f7545f8ebb172b1f2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56093
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shelley Chen <shchen@google.com>
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BlueTooth disappeared after disabled USB2 port 9,
so we need to re-enable it.
BUG=none
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7971509d7428562c80e781339ead059a189cea13
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: YH Lin <yueherngl@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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BUG=b:207307897
BRANCH=dedede
TEST=enable CHROMEOS_WIFI_SAR in config of coreboot,
emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage.
Change-Id: Ib1682cdafe1b6ed7cc0cf23624f83d2e5bbfb92e
Signed-off-by: Wizard Shen <shenhu5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: zanxi chen <chenzanxi@huaqin.corp-partner.google.com>
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Fork multiple "4ES" variants off some brya devices to
properly support ES SoC.
BRANCH=none
BUG=b:201767461
TEST=emerge-brya coreboot and check the artifacts
Signed-off-by: YH Lin <yueherngl@google.com>
Change-Id: Ic9516fec591429238bde1478eca2522d8ed10127
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59728
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add common USB driver for qualcomm soc sc7180 and sc7280.
This includes dwc3 controller, qmp ss phy, qusb hs phy and snsp hs phy.
BUG=b:182963902
TEST=Validated USB enumeration on qcom sc7180 and
sc7280 development board
Signed-off-by: Sandeep Maheswaram <sanm@codeaurora.org>
Change-Id: I1013ded22855286220cfa747cb25418070fe85a7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56091
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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There are no quad-core CPU models with fam14, \_SB.C002 and .C003 get
removed from ASL.
Change-Id: I96df5b3f93c2dd6a05d5693069b991ca01f71d73
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50658
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Change-Id: Ia65b1873f1d184b8b8c64a61a26820ae0900437d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50657
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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There was a duplicate PCI 0:14.4 device in ASL. Only
keep one.
There are no PCI devices 0:2.0 or 0:3.0 on fam14 northbridge
for graphics. There are no PCIe root ports 0:9.0 or 0:a.0.
Change-Id: Ifa8abb851f8ae4863b2c6d52224d287fd272048d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59179
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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The section is the same and at root scope.
Change-Id: I3b3ff2fddc7d4db09903151bcb92e3e1b5dc7d69
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Dumped using inteltool from the Dell BIOS version A30.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ifdc41a1e6627b68813fb264aed7e30df58fc6d54
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59525
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is no support for SD card on Corsola reference board, so
we add a configuration to disable SD card initialization to
prevent setting GPIOs in a mistaken way.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: Ia05fd046335c6ce6f9198ddbb7cbda2afc6ae3cc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59571
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Corsola the RAM code can be
read from ADC channel 2 and 3.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I485c32dec7b425b604b4063d742a0e37d3961513
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59570
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Raise little CPU to 2GHz at romstage.
TEST=check little core cpu frequency is 2GHz
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: If4c983d15beb2b588230f3db7416cb767b29978d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59569
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Add VPROC12/VSRAM_PROC12 to adjust power for raising little
CPU frequency.
TEST=build pass
BUG=b:202871018
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I59b4627220022a51a116716036a8ba0048039508
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59568
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Configure Chromebook specific GPIOs, including EC_AP_INT,
EC_IN_RW, GSC_AP_INT, EN_SPK, GPIO_AP, and GPIO_RESET.
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Change-Id: I76bde75788889111c0a051eed731dadc9898c0e1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59565
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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Kano EVT will exchange i2c port for touchscreen and cr50.
BUG=b:195853169
TEST=build pass
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I500f0721689ca66b65b8fb1deb79bef2bd988465
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59560
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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In different sku, some unused GPIO pins are processed by NC for power
consumption.
BUG=b:196790249
TEST=emerge-brya coreboot chromeos-bootimage and check power
Signed-off-by: Malik_Hsu <malik_hsu@wistron.corp-partner.google.com>
Change-Id: I753e41dec1825299e6cd437b5f67e2d957bc6148
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59563
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Enabling crashlog helps partners to debug hang issues efficiently.
BUG=b:195327879
TEST=Found BERT table is created and the tcss function is ok in
depthcharge. Warm/cold/suspend_stress test pass 50 cycles on gimble
Change-Id: Ib4bbe5d7cece0c6c5fc170460d55ac820054abb9
Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59486
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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At present the default ROM for for QEMU is too small for U-Boot to fit.
Add a condition to catch this and expand it to a 1MB ROM. This allows
booting U-Boot under emulation.
It also matches the size used by other emulation boards.
Signed-off-by: Simon Glass <sjg@chromium.org>
Change-Id: Ia1a8c1109e3ece5fec56255173a2d19d4a130bcb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59604
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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