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2021-12-23mb/google/dedede/var/magolor: Add stylus functionRen Kuo
Add the stylus field in fw_config. Update devicetree and gpio to handle stylus pen detection. BUG=b:167983049 TEST=Build firmware and check behavior as following: 1) Set the fw_config "bit4=1" for pen present: Wake up from suspend when pen is removed from the garage. Present the stylus menu when pen is removed from the garage. 2) Set the fw_config "bit4=0" for pen absent: Wake up and present menu will not work when pen is removed form the garage. Change-Id: I62489bb289b18f9aa0823005224eda3ef5218e03 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60185 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/asrock: Add ASRock H77 Pro4-M mainboardMichael Büchler
This adds a new port for the ASRock H77 Pro4-M motherboard. It is microATX-sized with an LGA1155 socket and four DIMM sockets for DDR3 SDRAM. The port was initially done with autoport. It is quite similar to the ASRock B75 Pro3-M which is already supported by coreboot. Working: - Sandy Bridge and Ivy Bridge CPUs (tested: i5-2500, Pentium G2120) - Native RAM initialization with four DIMMs of two different types - PS/2 combined port (mouse or keyboard) - Integrated GPU by libgfxinit on all monitor ports (DVI-D, HDMI, D-Sub) - PCIe graphics in the PEG slot - All three additional PCIe slots - All rear and internal USB2 ports - All rear and internal USB3 ports with reasonable transfer rates - All six SATA ports from the PCH (two 6 Gb/s, four 3 Gb/s) - All two SATA ports from the ASM1061 PCIe-to-SATA bridge (6 Gb/s) - Rear eSATA connector (multiplexed with one ASM1061 port) - Console output on the serial port of the Super I/O - SeaBIOS 1.15.0 to boot slackware64 - SeaBIOS 1.15.0 to boot Windows 10 (needs VGA BIOS) - Internal flashing with flashrom-1.2 (needs `--ifd -i bios --noverify-all`) - External flashing with flashrom-1.2 and a Raspberry Pi 1 - S3 suspend/resume from either Linux or Windows 10 Not working: - Booting from the two SATA ports provided by the ASM1061 - Automatic fan control with the NCT6776D Super I/O Untested: - VBT (it is included, though) - Infrared header Change-Id: Ic2c51bf7babd9dfcbaf69a5019b2a034762052f2 Signed-off-by: Michael Büchler <michael.buechler@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45317 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-23mb/google/guybrush/var/dewatt: update DRAM ID tableKenneth Chan
1. Samsung LPDDR4X 4266 4G K4UBE3D4AB-MGCL 2. Hynix LPDDR4X 4266 4G H54G56CYRBX247 (already used by other variants) BUG=b:203014978 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie5ece849a86c75be5af9bc0393090b5f1e33bfed Reviewed-on: https://review.coreboot.org/c/coreboot/+/60090 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/guybrush/var/nipperkin: update telemetry settingsKevin Chiu
Update the two load line slope settings for the SVID3 telemetry. AGESA sends these values to the SMU, which accepts them as units of current. Proper calibration is determined by the AMD SDLE tool and the Stardust test. vdd scale: 73457 -> 73331 vdd offset: 291 -> 1893 soc scale: 30761 -> 31955 soc offset: 834 -> 852 BUG=b:207299255 BRANCH=guybrush TEST=1. emerge-guybrush coreboot 2. pass AMD SDLE/Stardust test Change-Id: I9c9dd4883fd21a70a1e7a50f25a4f76df1e56bc6 Signed-off-by: Kevin Chiu <kevin.chiu.17802@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60243 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/intel/adlrvp_n: Add support for ADL-N LP5 RVPKrishna Prasad Bhat
Add support for Alder lake N LP5 RVP with board ID 0x7. Since SPD index 7 is unused earlier, ADL-N will use it. Change-Id: Ib2f53e65f75e23793d8c85ee924827446fd9fea7 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60193 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-12-23mb/google/dedede/var/beadrix: Remove SD controllerTeddy Shih
Remove SD controller configurations based on the beadrix's schematic. BUG=b:204882915 BRANCH=None TEST=Built test coreboot image Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Iba6f5cbbe90d9307e5e8080d7063a1881acd7ed9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60266 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23mb/google/dedede/var/beadrix: Add internal USB camera supportTeddy Shih
This change adds internal USB camera into devicetree for beadrix. BUG=b:204882915, b:210772511 BRANCH=None TEST=Built and checked camera device existence with lsusb Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: Iddc58c0d27d5da0fa4652f503f15ebb308be18c7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/dedede/var/beadrix: Enable audio featureTeddy Shih
This change adds ALC5682I audio codec and MAX98360A amplifier for beadrix. BUG=b:204882915, b:210756131 BRANCH=None TEST=Built and heared speaker sound on OS Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I6f12f71ec66acd420471ab9a7612b1821650ad54 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/dedede/var/beadrix: Enable PIXA touchpadTeddy Shih
This change adds PIXA touchpad into devicetree for beadrix. BUG=b:204882915, b:203113111 TEST=Built and verified touchpad function Signed-off-by: Teddy Shih <teddyshih@ami.corp-partner.google.com> Change-Id: I0b551554c69d52f0559ace4ad9c1335270dacea9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60246 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/starlabs/labtop: Update VBTSean Rhodes
Using Vbt.bin version 244, with the following changes: * Add 200ms delay to sink (T3) to avoid no response to AUX Channel transaction, which manifests as a repeating, colourful flicker. * Increase maximum supported refresh rate to 120Hz Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ifc03b8f5d45cbbf90fb61d8b08148ed402dd85ec Reviewed-on: https://review.coreboot.org/c/coreboot/+/59727 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-23mb/google/dedede/var/cret: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Samsung K4U6E3S4AB-MGCL 2. Hynix H54G46CYRBX267 BUG=b:203837656 BRANCH=dedede TEST=FW_NAME=cret emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I03980858f89e56320ddff3a808110a5f1dd57784 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58412 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-23mb/google/brya/var/anahera: Enable SaGvWisley Chen
Enable SaGv support for anahera/anahera4es. BUG=b:211362081 TEST=FW_NAME=anahera emerge-brya coreboot Change-Id: I68c916dbc570759dba3a4c32fbb8ebfc6e387be4 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60249 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/taeko4es: Fix PLD group order (W/A)Joey Peng
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Iff1302fa758bcde1ce8b03c16f7cc6eac807e5c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60187 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-23drivers/intel/pmc_mux/conn: Change usb{23}_port_number fields to device pointersReka Norman
Currently, the pmc_mux/conn driver uses integer fields to store the USB-2 and USB-3 port numbers from the SoC's point of view. Specifying these as integers in the devicetree is error-prone, and this information can instead be represented using pointers to the USB-2 and USB-3 devices. The port numbers can then be obtained from the paths of the linked devices, i.e. dev->path.usb.port_id. Modify the driver to store device pointers instead of integer port numbers, and update all devicetrees using the driver. These are the mainboards affected (all are Intel TGL or ADL based): google/brya google/volteer intel/adlrvp intel/shadowmountain intel/tglrvp system76/darp7 system76/galp5 system76/lemp10 Command used to update the devicetrees: git grep -l "usb._port_number" src/mainboard/ | \ xargs sed -i \ -e 's/register "usb2_port_number" = "\(.*\)"/use usb2_port\1 as usb2_port/g' \ -e 's/register "usb3_port_number" = "\(.*\)"/use tcss_usb3_port\1 as usb3_port/g' BUG=b:208502191 TEST=Build test all affected boards. On brya0, boot device and check that the ACPI tables generated with and without the change are the same. Change-Id: I5045b8ea57e8ca6f9ebd7d68a19486736b7e2809 Signed-off-by: Reka Norman <rekanorman@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60143 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Crawford <tcrawford@system76.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2021-12-23mb/google/guybrush/var/dewatt: update USB 2.0 Lane Parameter settings for ↵Kenneth Chan
USB ports Tune the USB phy settings to update txpreempamptune to 3 and txvreftune to 6 for passing USB 2.0 SI Eye diagram measurement (port 0/1/4). BUG=b:199468920 TEST= emerge-guybrush coreboot; pass USB 2.0 SI Eye diagram measurement. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie46c9019186f1893d736fc2806ab74a4f1171be7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-23mb/google/brya/var/vell: update overridetree for SSD setting=
Change CLKSRC#3 to CLKSRC#1 in override devicetree based on schematics BUG=b:208756696 TEST=emerge-brya coreboot Change-Id: I4d452eaa690a91814739cc1b80966fc3a9f1be37 Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/google/brya/var/vell: update overridetree for touchpad=
update override devicetree for touchpad based on schematics BUG=b:209554950 TEST=emerge-brya coreboot Change-Id: I835958349537ed490191db7c8e35847630de64ed Signed-off-by: = <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-23mb/intel/{adlrvp,sm}: Remove unused header `helpers.h`Subrata Banik
This patch removes unused header inclusion as <commonlib/helpers.h> from several mainboard gpio definition files. Change-Id: I36758089a4981bba916f4d9cf485f64fca2f81ae Signed-off-by: subratabanik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-22mb/google/brya/var/taeko: Enable Bayhub LV2 driverTim Wawrzynczak
Some SKUs of google/taeko have a Bayhub LV2 card reader chip, therefore enable the corresponding driver for the mainboard. BUG=b:204343849 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I738af7e77a3c076742a3d6c6f48fad29dfc978ac Reviewed-on: https://review.coreboot.org/c/coreboot/+/60017 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-22mb/google/brya/var/gimble: Configure GPIO to release PERST# earlierMark Hsieh
This change in power sequencing appears to fix issues with power consumption of the SD card controller. Possibly this change ensures the device has enough time to properly initialize itself after reset is deasserted but before it is accessed. BUG=b:206014046 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I90e5dd074ceda365283fe7e1f43dfd8c692d7338 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-21mb/google/brya/variant/taniks: Add devicetree settingsJoey Peng
Based on schematic G570_MB_CHROME_1207_1630_ADC and gpio table of taniks, generate overridetree.cb settings for taniks. BUG=b:209926534 TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ib333150117832480f70fbe13bdbdf2982a7f70e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/reef: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: Id71c63556da73a09c5a6d3e844686ddc3e113ea7 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/reef: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: I9578dd7cd4766b4b2ce8fb14992b1ef4701d9878 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I5bda94b20da4c9184cef2a39598e25a214c044b1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60146 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Drop unnecessary Kconfig optionsFelix Singer
These variant-specific options are only selected by their board options and are not used for anything else. Thus, merge their selects into the board options and drop them. Change-Id: I0eb3fdc4fd7306e76d5479494e3ab80bbdb984fe Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I462426f2ef4a0ff62c0a7c1eb2a4946fba68c4a9 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60188 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/poppy: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: If5cb98712767e2acab8955931d4f342c8f3d7824 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60144 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/guybrush: Enable PSP_S0I3_RESUME_VERSTAGERob Barnes
Enable PSP_S0I3_RESUME_VERSTAGE for all guybrush based boards. This will cause verstage to run during s0i3 resume. The TPM will be reinitialized in verstage during s0i3 resume. This is necessary on guybrush boards because the TPM_RST_L pin is asserted by the SOC in S0i3. BUG=b:200578885 BRANCH=None TEST=TPM initialized after s0i3 Change-Id: I9d64fe92ffc67a421be6d5e013e636332ce86dd5 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60139 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-20mb/google/brya/var/brask: Add wake-on-lan functionRory Liu
Add a wake-on-lan GPIO in devicetree for RTL8125. Modify GPIO A7 for wake-on-lan. BUG=b:204289108 TEST=emerge-brask coreboot chromeos-bootimage Signed-off-by: Rory Liu <rory.liu@quanta.corp-partner.google.com> Change-Id: Ic40301888a138df4a67398485f2a484d69b83fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/vell: update memory settingsShon Wang
DQ/DQS info from Intel_Platform_DQ_DQS_RCOMP_Info_Utility GPIO_MEN_CONFIG_0 GPP_E11 to GPP_E3 GPIO_MEN_CONFIG_3 GPP_E12 to GPP_E7 GPIO_MEM_CH_SEL_GPP_E5 GPP_E13 to GPP_E5 BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ic0bbac5eaebc77639be6c1bc399658ac90e72fbb Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59334 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/vell: update gpio overrideKevin Chiu
Configure GPIOs according to schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Icc91866f7555c294af7eed9e5d1550e73d8059d0 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59305 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/var/*: Add disable_gpio_export_in_crs to all devicetreesTim Wawrzynczak
None of the touchscreens used in the brya program (any brya board) should require exporting of GPIOs in the ACPI _CRS method for any i2c device. This can cause i2c devices to malfunction or cause timing sequence violations if: 1) ACPI exports a PowerResource for the device that uses GPIOs that are also exported in _CRS 2) The kernel driver for the device uses the GPIOs exported in _CRS for its own purposes. This means the state of the pin is out of sync between platform firmware and the kernel. The Linux ELAN I2C touchcsreen driver (https://source.chromium.org/chromiumos/chromiumos/codesearch/+/main:src/third_party/kernel/upstream/drivers/input/touchscreen/elants_i2c.c;l=1429) is one example of this. Therefore, add disable_gpio_export_in_crs to all brya variants that use the drivers/i2c/generic or drivers/i2c/hid chip drivers. Change-Id: Ib4475bd0dc885e230911de6298fd95baa868ef29 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60175 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-20mb/google/brya/var/primus: Update thermal table for primusAriel_Fang
- Because primus have five sensors,we need to define 5 sensors. BUG=b:200836803 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Signed-off-by: Ariel_Fang <ariel_fang@wistron.corp-partner.google.com> Change-Id: I02fb8eee644f9999d9c5d48e3a056499d968f85d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60101 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-20mb/google/brya/variants/brask: Disable autonomous GPIO power managementZhuohao Lee
We experienced the `Cr50 i2c TPM IRQ timeout!` error when the device executed the reboot test even though we have updated the Cr50 firmware to the latest version 0.6.70. Besides, we also experienced the device failed with the IRQ timeout when using the 0.3.22 Cr50 firmware in the factory. In order to fix these issues, we disable the gpio power management from the devicetree. BUG=b:210540890 TEST=reboot 100 cycles without the error message. Change-Id: I5f18fea5bc28493107c6d4951805de640a0b8ae5 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-20mb/starlabs/labtop: Add enum for `power_profile`Angel Pons
Introduce and use an enum for the `power_profile` CMOS option. Add a helper function that converts CMOS values into enum values. Using an enum allows GCC to warn about switch statements using enum types for their control expressions not handling all possible enum values, and also improves readability. Change-Id: I47a453ea12d164d26908a9944a89a481757e753c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60212 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-20mb/starlabs/labtop: Rename some filesAngel Pons
Rename `mainboard.c` to `smbios.c` as it only contains SMBIOS functions. Rename `ramstage.c` to `mainboard.c` as it contains the mainboard chip operations struct. Change-Id: I9548ca72a7583de98f5b154e3381825bba00d5cf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60211 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-20mb/google/zork: use full path of SoC's chip.hFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I50d8c45e711dc62afe6f80e0f66422bcc9924dfd Reviewed-on: https://review.coreboot.org/c/coreboot/+/60202 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/bilby,mandolin: use full path of SoC's chip.hFelix Held
This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iba1948ae2332788b7e0ec9b4e3cea35c6608b152 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/gardenia,padmelon;mb/google/kahlee: use full path of SoC's chip.hFelix Held
This is taken from CB:41355 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I10a18efb92ac0c3cad31044156e32aa6afe1d4d1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60198 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-20mb/amd/gardenia,padmelon;mb/google/kahlee: add missing soc/gpio includesFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie716633bd7602d5e4a7e186aa9e444b7f70dab56 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60197 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-19mainboard: Fix comment about early GPIOsAngel Pons
These boards program the early GPIO table in bootblock, not romstage. Change-Id: Iae9353d106483f30cefa2d035d96e63e4c127261 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Sean Rhodes <admin@starlabs.systems> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-18mb/siemens/chili: Reuse options from Kconfig.nameFelix Singer
Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I35f51756180882d019a3ea8c555ccd18cd588f44 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57761 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-18mb/kontron/bsl6: Reuse options from Kconfig.nameFelix Singer
Reuse the options from Kconfig.name for variant-specific selects. Change-Id: I29ce7ef6f5137c1cf43726faed6081a04c83dea6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-18mb/google/guybrush: Disable GPIO export for Goodix TouchscreenRaul E Rangel
We want ACPI to own the GPIOs. This will stop the GPIOs from being exposed to the OS driver. BUG=b:209705576, b:210694108 TEST=Dump ACPI table and verify GPIO are no longer in _CRS. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I8d2af41e1d04b98f0e3e19a95d7b91d08ecdf17b Reviewed-on: https://review.coreboot.org/c/coreboot/+/60173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-17mb/google/guybrush/var/nipperkin: config eSPI as dedicated alertKevin Chiu
Setup eSPI to dedicated alert per the latest schematic changes. DUT won't hang up at power on boot due to eSPI alert is triggerred unexpectedly. BUG=b:199458949,b:203446084 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage test power on/reboot on DUT (6 units) each 10 loops->pass Change-Id: I55cda7a1af22e555a4f55285cb7e337a69e6c234 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-17google/trogdor: Enable Parade ps8640 edp bridge for pazquelYunlong Jia
BRANCH=none BUG=b:201478528 TEST=build and boot Change-Id: I6130ee00a0e6f469142f5416627e38c7b5076071 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-12-16mb/google/brya/var/felwinter: Add stylus probe for garageEric Lai
Felwinter has non-stylus sku. Add a FW_CONFIG field to indicate stylus presence and add a probe statement to the devicetree for the corresponding device. BUG=b:208937710 TEST=non-stylus doesn't register garage driver. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I06a2c125f2b5a73f9f7c27bf1b20ff8712664809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-16mb/google/guybrush/var/dewatt: Add audio codecKenneth Chan
Add ALC5682I-VD and ALC1019 for dewatt. BUG=b:208172493 TEST=emerge-guybrush coreboot chromeos-bootimage; Tested with proto build. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Ie4d21a11377c73b913a8f79a92d5869ea70f4394 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-16mb/google/brya/var/vell: update overridetreeKevin Chiu
Init basic override devicetree based on initial schematics BUG=b:205908918 TEST=emerge-brya coreboot Change-Id: Ibaa910eb1c5584197907963781258035c668298e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59304 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/fizz/Kconfig: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I2b8a9906671b327bec249f3d16cba3ba80a95669 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/fizz: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: I9201b5bcbf53422cefc6027a0d67fcf2201b14a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/fizz: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: Iaaca82aad3c687939291c051f203b58a9c8cdb70 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/glados/Kconfig: Select board-specific options per boardFelix Singer
Move board-specific selects out of common configuration and add them to each board where necessary. Change-Id: I70ab37588a6b08a0cc194469fd2642b3cfefe301 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/glados: Move selects from Kconfig.name to KconfigFelix Singer
Move selects from Kconfig.name to Kconfig so that the configuration is at one place and not distributed over two files. Change-Id: Ifccf2b3521d84f6a678872bbccf9bf390c25ce37 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-12-15mb/intel/adlrvp_n: Add initial code for adl-n variant boardKrishna Prasad Bhat
This patch adds the following list of changes: 1. Create a new devicetree for adlrvp-n and copy contents of adlrvp-p devictree. 2. Add support for 2 mainboards as ADL-N board with default EC (Windows SKU) and Chrome EC (Chrome SKU) and copy overridetree contents from adlrvp-p. 3. Add mainboard Kconfig to Kconfig.name file 4. Handle mainboard names in Kconfig file for ADLRVP N 5. Add config options to pick the adlrvp_n devicetree Change-Id: I4abf3bf62ec0398ae75e21575a2fab0d44b5c7ad Signed-off-by: Usha P <usha.p@intel.com> Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59915 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-15mb/google/guybrush: Set TPM to to be kernel power managed.Rob Barnes
Set TPM power_managed_mode to TPM_KERNEL_POWER_MANAGED. This will cause the TPM kernel driver to send a shutdown command before s0i3 entry. This change depends on S0i3 verstage running and reinitializing the TPM. BUG=b:200578885 BRANCH=None TEST=TPM shutdown sent during s0i3 entry on guybrush Change-Id: I206022cc2a29690186206966c5d45bd55c303248 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60081 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-15mb/google/dedede/var/madoo: Generate new SPD ID for new memory partsDtrain Hsu
Add new memory parts in the mem_list_variant.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Micron MT53E512M32D1NP-046 WT:B 2. Samsung K4U6E3S4AB-MGCL 3. Hynix H54G46CYRBX267 BUG=b:209889645 BRANCH=dedede TEST=FW_NAME=madoo emerge-dedede coreboot chromeos-bootimage Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I0b2f447a610a0a857e819ede257ac89cfd817018 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59991 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15Denverton-NS boards: Drop useless `thermal.asl`Angel Pons
The code in these files is meaningless, and can be dropped. Change-Id: I11571885059e8d5f930f741172c74b25faa09a15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-12-15mb/google/brya/var/primus{4es}: Configure Acoustic noise mitigationCasper Chang
- Enable Acoustic noise mitigation - Set slow slew rate VCCIA and VCCGT to 8 BUG=b:204844399 TEST=USE="project_primus emerge-brya coreboot" and verified the setting meets the audible noise specification Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Change-Id: I0e0baf78a841278efda912cc5e4e9970329aacf6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mainboard/starlabs/labtop: Hook up Thunderbolt to CMOSSean Rhodes
Hook up Thunderbolt and related settings to CMOS value of `thunderbolt`. Changes TcssXhciEn, UsbTcPortEn and the relevant PCI devices. Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: Ibadc7464831242ae51982610b410ccf0a6811edd Reviewed-on: https://review.coreboot.org/c/coreboot/+/59705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Andy Pont <andy.pont@sdcsystems.com>
2021-12-15mb/google/guybrush/var/nipperkin: update LPDDR4X DRAM tableKevin Chiu
add Hynix H54G56CYRBX247 support BUG=b:210365851 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage power on successfully Change-Id: I99bed32025d10f62e63ace8f7f23e7cc3a740e93 Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60075 Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-15mb/google/brya/var/taniks: Configure DRIVER_TPM_I2C_BUSJoey Peng
Add I2C bus for taniks in Kconfig BUG=b:210390520 TEST=emerge-brya coreboot and can boot to OS. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I9b1719c3140c13f67e7cb0e6a69257774884bd4d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/brya/variant/taniks: Add memory settingsJoey Peng
Based on the Taniks's schematic, generate memory settings. Schematic version is G570_MB_CHROME_1207_1630_ADC. BUG=b:209531192,b:209553289 TEST=FW_NAME=taniks emerge-brya coreboot chromeos-bootimage Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0c0794fb94d1f6271de604835ae1d2b20696ee70 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59947 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-15mb/google/brya/variants/taniks: Configure GPIOs according to schematicsJoey Peng
Add initial gpio configuration for taniks according to schematics G570_MB_CHROME_1207_1630_ADC. The schematics reserved HPS and FP but taniks doesn't use them, so set FP and HPS related pins to NC. BUG=b:209492408, b:209553289 TEST=FW_NAME=taniks emerge-brya coreboot Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Ic5c4ead4ad59137e1764e1226415ab6041c68aab Reviewed-on: https://review.coreboot.org/c/coreboot/+/59938 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-15mb/google/corsola: move USB3 HUB reset funtion to bootblockRex-BC Chen
To save the S3 power, USB3_HUB_RST_L is externally pulled up to a weak resistor, so we have to reset the hub as early as possible. Otherwise the USB3 hub may be not usable. Therefore, move USB3 HUB reset function to bootblock. BUG=b:210065282 TEST=build pass Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I92feb2316302fda32478b24c014bcd380d0ac55d Reviewed-on: https://review.coreboot.org/c/coreboot/+/60088 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-14mb/google/glados: Restore alphabetical order on Kconfig selectsFelix Singer
Change-Id: I736234b9a960c58193fcf7bc9184c9581c6c953b Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-14mb/google/corsola: set up open-drain ChromeOS pinsRex-BC Chen
Set open-drain GPIOs for ChromeOS as input and high-z mode. After applying this patch, we can measure these pins from 1.0V to correct voltage (1.8V) to prevent wrong judgement of low/high. Reference document: MT8186_SoC_Pinmux_V1_1 BUG=b:209342636 TEST=measure pins voltage 1.8V on kingler board Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Ib55a773bb63404a1b952f7e7645eb7aba6638b00 Reviewed-on: https://review.coreboot.org/c/coreboot/+/60002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-13mb/google/dedede/var/lantis: Add fw_config probe for ALC5682-VD/ALC5682-VSWisley Chen
ALC5682-VD/ALC5682-VS use different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:206676530 TEST=build Change-Id: Ie73dc376078c0836edd980e09629399c5cc19594 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-13mb/google/guybrush/var/dewatt: Add Elan touchscreenKenneth Chan
Add Elan 6918 touchscreen for dewatt. (EKTH6918 Product Spec V0.5) BUG=b:208373433 TEST=emerge-guybrush coreboot chromeos-bootimage. Teseted with Elan 6918 touchscreen. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: I28a7f5891e09ffa393c93881be68641d955efdf8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-13mb/google/guybrush/var/dewatt: Add Synaptics touchpadKenneth Chan
Add Synaptics S9831 touchpad for dewatt. BUG=b:208182457 TEST=emerge-guybrush coreboot chromeos-bootimage. Tested with Synaptics S9831 touchpad. Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com> Change-Id: Id3e0636dd0ce5b80c2044c1dfca20ca7eac87fc9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59974 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-13mb/google/octopus: add ALC5682I-VS to be supported in the SSFCPaul Huang
Add ALC5682I-VS codec support. ALC5682I-VD/ALC5682I-VS load different hid name depending on SSFC. BUG=b:198722640 BRANCH=octopus TEST=Set CBI SSFC BIT9-11 to select codec, and test audio works Change-Id: I80be12d88e100ce8586371fc49b36447859e24f8 Signed-off-by: Paul Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-12-13mb/google/zork/var/shuboz: Add fw_config probe for ALC5682-VD & VSKane Chen
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name and machine_dev depending on the AUDIO_CODEC_SOURCE field of fw_config. Define FW_CONFIG bits 36 - 37 (SSFC bits 4 - 5) for codec selection. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:198689479 BRANCH=zork TEST=ALC5682-VD/ALC5682I-VS audio codec can work Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0c78aa166010ffa4d0cacc8a11d418d5a6906749 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59558 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-12mainboard: Drop `SataMode` setting from Tiger Lake devicetreesFelix Singer
All Tiger Lake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: I291048250bc82552fde7c71a1dcda4894a61d465 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59890 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-12mainboard: Drop `SataMode` setting from Cannon Lake devicetreesFelix Singer
All Coffee Lake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: Ibb329eb8b752c2220bb25f14fb6ae92dd8a308d6 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59889 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-12mainboard: Drop `SataMode` setting from Skylake devicetreesFelix Singer
All Skylake mainboards use the default value for the setting `SataMode`. Thus, drop it from their devicetree. Change-Id: I9be5eca93cac65afc4cc30ceb64d9a5b7e5cd514 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59888 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-10mb/google/brya/var/taeko: Fix PLD group order (W/A)Kevin Chang
In commit 667471b8d8 (ec/google/chromeec: Add PLD to EC conn in ACPI table), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. Fixes: 667471b8d8 ("ec/google/chromeec: Add PLD to EC conn in ACPI table") BUG=b:209723556 BRANCH=none TEST=build coreboot and boot into OS. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: Ia4cf2d735de524ae721800600536923d1d47f04b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10mb/siemens/mc_ehl: Enable TPM in bootblockWerner Zeh
Enable TPM init in bootblock so that all further stages and other CBFS files are directly measured into PCRs immediately instead of being logged into a buffer and replayed to the TPM in ramstage. Change-Id: Ib3ac29aa72abe8e967660ae7e8416aeb8812de26 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/60008 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-12-10mb/intel/adlrvp: Add support for external clock bufferSubrata Banik
ADL-P silicon can support 7 SRC CLK's and 10 CLKREQ signals. Out of 7 SRCCLK's 3 will be used for CPU, the rest are for PCH. If more than 4 PCH devices are connected on the platform, an external differential buffer chip needs to be placed at the platform level. A mainboard designer can choose to add an external clock chip, and select the SRC CLK using CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER. CONFIG_CLKSRC_FOR_EXTERNAL_BUFFER provides the CLKSRC that feed clock to discrete buffer for further distribution to platform. TEST=Able to detect SD card connected at x4 PCIe Gen 3 Slot. localhost ~ # dmesg | grep mmc [ 4.997840] mmc0: SDHCI controller on PCI [0000:ae:00.0] using ADMA [ 5.460902] mmc0: new ultra high speed DDR50 SDHC card at address aaaa [ 5.473555] mmcblk0: mmc0:aaaa SS08G 7.40 GiB [ 5.494268] mmcblk0: p1 Change-Id: I21f1155374049c90aa45db25d4128b39aa5898bb Signed-off-by: Subrata Banik <subi.banik@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59976 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-10mb/var/gimble4es: Set PsysPmax to 143 WMark Hsieh
This patch adds the setting of PsysPmax to 143 W according to gimble board design. BUG=b:206990759 TEST=emerge-brya coreboot chromeos-bootimage & ensure the value is passed to FSP by enabling FSP log & Boot into the OS Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: I851e0871461a9a9769c6b84f7d8287d989c23f06 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59950 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/guybrush/var/nipperkin: Configure Smart Card in normal modeKarthikeyan Ramasubramanian
As per the schematics, smart card is expected to operate in normal mode by default. So configure the SOC_SC_PWRSV gpio accordingly. BUG=b:202992077 TEST=Build and boot to OS in Nipperkin board version 2. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I8e12600ad45734b144a30c868f0e4f323aa056f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59984 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/guybrush/var/nipperkin: Override SPI fast speedKarthikeyan Ramasubramanian
After assessing the signal integrity, 100 MHz SPI fast speed can be enabled for SPI ROM. BUG=None TEST=Build and boot to OS in Nipperkin board version 2. Perform 250 iterations of warm and cold reset each. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Id973acb939b69e0beda26252e57a278892f2f57d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59983 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-12-09mb/google/brya4es: sync change from brya0 (CB:58374)YH Lin
CB:58374 (for mb/google/brya0) was merged before brya4es is available (CB:59728). And since brya4es is forked from brya0, brya0's change need to be brought into brya4es as well. BUG=b:203014972 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I97489343b8f7a5b9457cd6f4a61cc37cd10ab450 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59935 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Hook up DPTF device to devicetreeFelix Singer
Hook up `Device4Enable` FSP setting to devicetree state and drop its redundant devicetree setting `Device4Enable`. The following mainboards enable the DPTF device in the devicetree despite `Device4Enable` is not being set. * google/deltaur Thus, set it to off to keep the current state unchanged. Change-Id: Ic7636fc4f63d4beab92e742a6882ac55af2565bc Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59886 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/intel/tigerlake: Drop unused SataEnable settingFelix Singer
`SataEnable` is set by some boards, but it doesn't have any effect since its related FSP option is hooked up to the devicetree state. Thus, drop it. Change-Id: Id645bfcade7ca1d495fb8df538113b3d10392a82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-12-09mb/starlabs/labtop: Enable SMBus in Device TreeSean Rhodes
Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I8bc3025331bb25b02712b5d2b654f7997f0aba4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/59926 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2021-12-09soc/intel/tigerlake: Hook up SMBus device to devicetreeFelix Singer
Hook up `SmbusEnable` FSP setting to devicetree state and drop its redundant devicetree setting `SmbusEnable`. The following mainboards enable the SMBus device in the devicetree despite `SmbusEnable` is not being set. * google/deltaur * starlabs/laptop Thus, set it to off to keep the current state unchanged. Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/brask: Configure the ISOLATE pin of LANAlan Huang
1. Copy the default configuration from Puff. 2. Update the 'stop_gpio' to GPP_H22. BUG=b:193750191 BRANCH=None TEST=Update kernel for 8125 outbox driver and test with command suspend_stress_test. Change-Id: I2e82dbc1e6c68cbd84b603adc7fdc3ee1d4d3392 Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/google/brya/var/redrix4es: sync change from redrixYH Lin
The original change was for mb/google/redrix (commit 0167f5adbb), "The ChromeOS kernel platform driver is adding support for a ChromeOS privacy screen device, and in order to locate that device, the driver uses the GOOG0010 reserved HID for this" But it was merged before redrix4es is available. As redrix4es is forked from redrix, relevant change in redrix need to be brought into redrix4es as well. BUG=b:206850071 TEST=build Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I5ac90c249273bf4e75cccb5889844a7f196f56fc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59987 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09mb/facebook/fbg1701: Remove ONBOARD_SAMSUNG_MEMFrans Hendriks
CONFIG_ONBOARD_SAMSUMG_MEM was used to force Samsung memory. CPLD returns different values for every board revision. Use this value to determine the memory type. BUG = N/A TEST = Boot Facebook FBG1701 Rev 1.0 - 1.4 Change-Id: I21b5ddc430410a1e8b3e9012d0c07d278880ff47 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59754 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-12-09mb/google/brya: keep the same TPM I2C for 4ES variantsYH Lin
Since 4ES variants were forked from their own original variants, use the same TPM I2C as well. BRANCH=none BUG=b:201767461 TEST=emerge-brya coreboot and check the artifacts Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: Iddd6d8c22a181aba596b836f20392f76539b8549 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59849 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-12-09soc/amd/stoneyridge: use common fch_spi_early_initFelix Held
All SPI interface setup related functionality that Stoneyridge implemented in its southbridge code is already present in the common AMD SoC code, so use that code instead. The common fch_spi_early_init function requires the SPI controller's base address to be set, so call lpc_set_spibase(SPI_BASE_ADDRESS) right before it. fch_spi_early_init then calls lpc_enable_spi_rom and lpc_enable_spi_prefetch which can be removed from the board code now. Next it calls fch_spi_configure_4dw_burst which does the same as the now removed sb_disable_4dw_burst function when SOC_AMD_COMMON_BLOCK_SPI_4DW_BURST is set to n which is the default. This option can also only be set to y for SoCs that aren't Stoneyridge. Finally fch_spi_early_init calls fch_spi_config_modes which configures the SPI mode and speed settings according to the Kconfig settings and the settings in the amdfw part. On Kahlee this was done by calls to sb_read_mode and sb_set_spi100 before. The previous patch added the remaining Kconfig settings, so the resulting register values don't change in the non-EM100 case. In the EM100 case the TPM speed is changed from 64 to 16 MHz. TEST=Both the non-EM100 mode with a real SPI flash and the EM100 mode with a first-generation EM100 results in Google/Barla reaching the payload and the show_spi_speeds_and_modes call in bootblock prints the expected settings: relevant bootblock console output in non-EM100 case: SPI normal read speed: 33.33 MHz SPI fast read speed: 66.66 Mhz SPI alt read speed: 66.66 Mhz SPI TPM read speed: 66.66 Mhz SPI100: Enabled SPI Read Mode: Dual IO (1-2-2) relevant bootblock console output in EM100 case: SPI normal read speed: 16.66 MHz SPI fast read speed: 16.66 MHz SPI alt read speed: 16.66 MHz SPI TPM read speed: 16.66 MHz SPI100: Enabled SPI Read Mode: Normal Read (up to 33M) Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I8f37a3b040808d6a5a8e07d39b6d4a1e1981355c Reviewed-on: https://review.coreboot.org/c/coreboot/+/59968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09mb/google/kahlee/Kconfig: add remaining SPI speed settingsFelix Held
Before this patch only the SPI settings that will also end up in the amdfw part of the firmware were specified in the board's Kconfig. This patch adds the settings from Kahlee's bootblock.c to the Kconfig file which will be needed in subsequent patches. Also add a comment about the EM100 case. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ie42feb9b41f435c329bf1c78471e65ef5a3fb783 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-12-09mb/google/corsola: Pass reset gpio parameter to BL31Rex-BC Chen
To support gpio reset SoC, we need to pass the reset gpio parameter to BL31. TEST=build pass BUG=b:202871018 Cq-Depend: chromium:3188686 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I48d8d004ea92e950d0040a11133c57c121b86af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59824 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-09mb/google/corsola: correct NOR flash configuration in GPIO setRex-BC Chen
The reference design has changed to use GPIO SET1 for NOR flash. There are no devices already built using SET0 so we can safely change the implementation without conditional configs. Reference document: kingler_mt8186_mt6366_lpddr4x_e.pdf, page 11. crab_proto 0_2021112.pdf, page 11. BUG=b:202871018 TEST=flash verify pass on kingler on bootblock stage Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I031686ccddcf789f3fa966d113ee48949e454b8f Reviewed-on: https://review.coreboot.org/c/coreboot/+/59945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-12-09mb/google/corsola: get SKU IDRex-BC Chen
Retrieve the SKU ID for Corsola via CBI interface. If that failed (or no data found), fallback to ADC channels for SKU ID. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2888190d498df28b5ae13cf92cc41d088e8f8ee7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59944 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/dedede/var/magolor: Add fw_config probe for multi codec andTyler Wang
amplifier Compatible headphone codec "ALC5682I-VS" and speaker amplifier "ALC1015Q-VB" BUG=b:208912135 TEST=ALC5682I-VD and ALC1015Q-VB can work normally Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Id661280061ede3fbb63c962dee8fb18a2053ad66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-08mb/google/guybrush: Combine mem_parts_used.txtRob Barnes
Combine guybrush mem_parts_used.txt across guybrush variants. Guybrush reference memory parts is used as the base, then Nipperkin memory parts were appended, followed by DeWatt memory parts. Duplicates were removed. The memory id mapping was not affected on guybrush reference and Nipperkin. DeWatt memory id mapping was affected, DeWatt boards will need to be adjusted. This works around a limitation in APCB, which currently only supports one set of memory SPDs. BUG=b:209486790, b:204151079 BRANCH=None TEST=Boot guybrush and nipperkin Change-Id: Ie17025e092f2b9397afea33fce285e80ef5dc995 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-12-08mb/google/brya/var/primus: Fix PLD group orderScott Chao
In ec/google/chromeec: Add PLD to EC conn in ACPI table(667471b8d807da5a5a9277db47e069ad3b1351c7), PLD is added to ACPI table. It causes the DUT to not boot into the OS. So fix the USB3/USB2 Type-C Port C2 PLD group order from 3 to 2 to solve this issue. BUG=b:209568644 BRANCH=none TEST=build coreboot and system boot into OS. Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com> Change-Id: If5ce6ca061d9d56ba0bbb1f157b2ba278d3fa9c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59953 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-12-08mb/google/corsola: Configure TPMRex-BC Chen
Initialize SPI bus 2 for TPM control. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I8ede68d6eb594890195e8464151c1c0f88aeee43 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-12-08mb/google/corsola: implement get_ec_is_trustedRex-BC Chen
Set VB2_CONTEXT_EC_TRUSTED in verstage_main. TEST=build pass BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: If2837f5db52f91f5418d222d4dcd1af2aebcc105 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-03 20:08:52 +0000