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2021-11-15soc/mediatek/mt8186: Add support for PMIC MT6366James Lo
Add basic support for VCORE/VDRAM1/VDDQ of MT6366. TEST=build pass BUG=b:202871018 Signed-off-by: James Lo <james.lo@mediatek.corp-partner.google.com> Change-Id: I22e30421560a32f4a9e15899e8150376b1414494 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59245 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-13mb/google/guybrush: Add variant_espi_gpio_tableRob Barnes
Add separate gpio table for early eSPI bus init. Remove espi GPIO from early_gpio_table. This allows for initializing eSPI separately from other GPIOs. Simplify verstage_mainboard_early_init. BUG=b:200578885 BRANCH=None TEST=Build and boot guybrush Change-Id: I0cd439f207df7c27575ae363b207293d40485bf8 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2021-11-13Revert "mb/google/brask: Correct GPIO GPP_R6 and GPP_R7 setting"David Wu
This reverts commit ba6fdc892d62741e456ac5628fcd6f869c4cb9af. Reason for revert: Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1), GPP_R6 ~ GPP_R7 should be NF3 for dmic. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I460fd99b4ad4b9c470f692032ff7ea2b51cad388 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59149 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12google/stout: Remove duplicate recovery mode switch entryKyösti Mälkki
Change-Id: I6e742b9d5256da2b7edcca0efda4faf999207465 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59192 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12google/butterfly: Refactor get_recovery_mode_switch()Kyösti Mälkki
Do not place console output in low-level GPIO functions. The caller of get_recovery_mode_switch() is in vboot_logic.c that is linked in romstage. So presumably recovery mode is broken and is not fixed with this commit either. Change-Id: I2a0fdbb370d54898c72adb29a0e9b990a5fc0ce1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59003 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12mb/google/trogdor: Modify BOE panel_id for mrblandZanxi Chen
Modify BOE panel_id for mrbland due to hardware changes. BUG=b:205166230,b:198548221 BRANCH=trogdor TEST=emerge-strongbad coreboot Change-Id: I65fecd854c4e3443edc07a44a1d43572d5030e4c Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58995 Reviewed-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-12mb/google/brya/var/primus: Disable autonomous GPIO power managementCasper Chang
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201054849 TEST=USE="project_primus emerge-brya coreboot" and verify it builds without error. Change-Id: If5a99a96e5d4b84be3f2c1165283ce249ca75d58 Signed-off-by: Casper Chang <casper_chang@wistron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-12google/deltaur,drallion,sarien: Refactor ChromeOS GPIOsKyösti Mälkki
Low-level GPIOs should not depend on late cros_gpios that should be guarded with CHROMEOS and implemented for the purpose of ACPI \OIPG package generation. Change-Id: Ibe708330504bc819e312eddaf5dfe4016cda21a1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-12mb/google,intel: Add ChromeOS GPIOs to onboard.hKyösti Mälkki
Change-Id: Ia473596e3c9a75587cd1288c8816bfef66bef82e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11mb/google/brya/var/felwinter: Enable SaGvEric Lai
Enable SaGv. BUG=b:198235324 TEST=Boot into without issues. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I3cbff8d28bb5b5bfdad323f348b9f880245d049d Reviewed-on: https://review.coreboot.org/c/coreboot/+/59095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/system76/gaze16: Add System76 Gazelle 16Jeremy Soller
https://tech-docs.system76.com/models/gaze16/README.html The gaze16 comes in 3 variants due to differences in the discrete GPU and network controller used. - NVIDIA RTX 3050, using Realtek Ethernet controller - NVIDIA RTX 3060, using Realtek Ethernet controller - NVIDIA RTX 3060, using onboard Intel I219-V Ethernet controller Tested on the 3050 variant. Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe SSD - M.2 SATA SSD - 2.5" SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - HDMI output - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio* - 3.5mm microphone input* - S3 suspend/resume - Booting to Pop!_OS Linux 21.04 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics - Mini DisplayPort output (requires NVIDIA GPU) - 3.5mm audio input/output detection on Windows Change-Id: Ifb90f9b73a10abf53a21738e2c466d539df9a37c Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56956 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11mb/google/brya/var/kano: Configure USB2 and USB3 portDavid Wu
Disable unused USB2 and USB3 port BUG=b:192370253 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia2fa10fb21e0a42e51728bc3d78163ca213f8d91 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/brya/var/kano: Add gpio-keys ACPI node for PENHDavid Wu
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:192415743 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ia36119678cfd5c65a62685d3312537d9aa21e83b Reviewed-on: https://review.coreboot.org/c/coreboot/+/59035 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11mb/google/guybrush: Define ACPI Power Resources for FPMCUKarthikeyan Ramasubramanian
Currently all the power sequencing for FPMCU is done explicitly in different stages of coreboot. This can all be done by adding ACPI power resources for FPMCU and clean up the unused code. Here is the expected power sequence: PowerUp : Assert EN_PWR_FP -> 3 ms delay -> De-assert FPMCU_RST_ODL Shutdown : De-assert EN_PWR_FP -> Assert FPMCU_RST_ODL Reboot : Shutdown -> 200 ms delay -> PowerUp BUG=None TEST=Build and boot to OS in Guybrush. Ensure that the FP is able to unlock the system after the first login attempt. Ensure that the FP is able to wakeup the system. Observed that the power resource is added correctly in the FPMCU ACPI object Name (_PR0, Package (0x01) // _PR0: Power Resources for D0 { PR01 }) Name (_PR3, Package (0x01) // _PR3: Power Resources for D3hot { PR01 }) PowerResource (PR01, 0x00, 0x0000) { Method (_STA, 0, NotSerialized) // _STA: Status { Return (0x01) } Method (_ON, 0, Serialized) // _ON_: Power On { \_SB.CTXS (0x0B) \_SB.STXS (0x20) \_SB.STXS (0x0B) } Method (_OFF, 0, Serialized) // _OFF: Power Off { \_SB.CTXS (0x0B) \_SB.CTXS (0x20) } } Change-Id: I52322eaecf6961ff9a196ca9ab2d58b7d4599d4f Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58705 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11mb/google/brya/var/taeko: Enable CPU PCIE RP 1Joey Peng
Modify settings to enable CPU PCIE RP 1 according to schematics. BUG=b:205504257 TEST=emerge-brya coreboot and can successfully boot with ssd and emmc. Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: I0f817c860f2b295c6aa84fa1999d374d99f817f6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11mb/google/guybrush/dewatt: update dewatt configChris.Wang
copy config from guybrush reference board. BUG=b:204151079 BRANCH=guybrush TEST=emerge-guybrush coreboot chromeos-bootimage Signed-off-by: Chris.Wang <chris.wang@amd.corp-partner.google.com> Change-Id: Ide9e002390e59725dc0e45f83280db2a78270993 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59092 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-11mb/google/brya/var/gimble: Improve USB2 eye diagram of DB Type-C portMark Hsieh
- Set MAX OC1 to USB2_C1 BUG=b:205676803 TEST=USE="project_gimble emerge-brya coreboot" and verify it builds without error. Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com>
2021-11-11mb/google/brya/var/felwinter: Update typeC EC mux portEric Lai
We need to put USB setting in mux order. BUG=b:204230406 TEST=Type C mux configuration is correct. Wrong: added type-c port0 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 added type-c port1 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 Correct: added type-c port0 info to cbmem: usb2:3 usb3:3 sbu:0 data:0 added type-c port1 info to cbmem: usb2:2 usb3:2 sbu:0 data:0 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I19338e162db6145dbeb5830de1a372cf98f779a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59012 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-11-11mb/google/brya/variants/gimble: Update audio setting for SmartAMPMark Hsieh
Divide dsm_param_file_name into dsm_param_R and dsm_param_L BUG=b:205684021 TEST=build and check SSDT Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com> Change-Id: Ie2db709a63152c1ccee2f7d594284e366ada8a01 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59046 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-11mb/google/dedede/var/galtic: update Wifi SAR for convertiblesFrankChu
Add wifi sar for galtic/galtic360/galith360 Using convertible mode of SKU ID to load wifi table. Each Project and SKU ID correspond as below galtic (sku id:0x120000) galith (sku id:0x130000) gallop (sku id:0x150000) galtic360 (sku id:0x260000) galith360 (sku id:0x270000) BUG=b:203741126 TEST=emerge-dedede coreboot chromeos-bootimage \ coreboot-private-files-baseboard-dedede verify the SAR table is correct in each project Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: If4203d176dd717fa62c88d9b4fab8a53847213fe Reviewed-on: https://review.coreboot.org/c/coreboot/+/58734 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-11samsung/lumpy,stumpy: Add get_power_switch()Kyösti Mälkki
Change-Id: I75c2e86e64943eb241db48482746317ed9ba47af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11samsung/lumpy: Add get_lid_switch()Kyösti Mälkki
Change-Id: Ib360a6fa00d0ebda4635b96f1b671a66c1ca11c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/59001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11google/beltino,jecht: Refactor ChromeOS GPIOsKyösti Mälkki
Change-Id: I4052baca2d8041b2a6d6fd410fcf99248662d7a5 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11samsung/lumpy,stumpy: Refactor ChromeOS GPIOsKyösti Mälkki
Change-Id: Ic8b189dd82c412aa439694e200d530ae7e71d7e2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-11-11arch/x86: Refactor the SMBIOS type 17 write functionSubrata Banik
List of changes: 1. Create Module Type macros as per Memory Type (i.e. DDR2/DDR3/DDR4/DDR5/LPDDR4/LPDDR5) and fix compilation issue due to renaming of existing macros due to scoping the Memory Type. 2. Use dedicated Memory Type and Module type for `Form Factor` and `TypeDetail` conversion using `get_spd_info()` function. 3. Create a new API (convert_form_factor_to_module_type()) for `Form Factor` to 'Module type' conversion as per `Memory Type`. 4. Add new argument as `Memory Type` to smbios_form_factor_to_spd_mod_type() so that it can internally call convert_form_factor_to_module_type() for `Module Type` conversion. 5. Update `test_smbios_form_factor_to_spd_mod_type()` to accommodate different memory types. 6. Skip fixed module type to form factor conversion using DDR2 SPD4 specification (inside dimm_info_fill()). Refer to datasheet SPD4.1.2.M-1 for LPDDRx and SPD4.1.2.L-3 for DDRx. BUG=b:194659789 TEST=Refer to dmidecode -t 17 output as below: Without this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Unknown .... With this code change: Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2048 MB Form Factor: Row Of Chips .... Change-Id: Ia337ac8f50b61ae78d86a07c7a86aa9c248bad50 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/56628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11ChromeOS: Replace with or add <types.h>Kyösti Mälkki
It's commented in <types.h> that it shall provide <commonlib/helpers.h>. Fix for ARRAY_SIZE() in bulk, followup works will reduce the number of other includes these files have. Change-Id: I2572aaa2cf4254f0dea6698cba627de12725200f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-11intel/strago: Fix some CHROMEOS guardsKyösti Mälkki
MAINBOARD_HAS_CHROMEOS always evaluates true for this board. The commentary about get_write_protect_state() was wrong, it's currently only called in ramstage. Change-Id: I0d5f1520a180ae6762c07dca7284894d9cf661b4 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-11mb/google/brya: Enable thermal control functionality for tpchSumeet Pawnikar
Enable DPTF based thermal control functionality for tpch device on brya device. BUG=b:198582766 BRANCH=None TEST=Build FW and test on brya0 board Change-Id: I6a35a101599bb811fcddaabab5296f8c6c12af31 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-10Rename ECAM-specific MMCONF KconfigsShelley Chen
Currently, the MMCONF Kconfigs only support the Enhanced Configuration Access mechanism (ECAM) method for accessing the PCI config address space. Some platforms have a different way of mapping the PCI config space to memory. This patch renames the following configs to make it clear that these configs are ECAM-specific: - NO_MMCONF_SUPPORT --> NO_ECAM_MMCONF_SUPPORT - MMCONF_SUPPORT --> ECAM_MMCONF_SUPPORT - MMCONF_BASE_ADDRESS --> ECAM_MMCONF_BASE_ADDRESS - MMCONF_BUS_NUMBER --> ECAM_MMCONF_BUS_NUMBER - MMCONF_LENGTH --> ECAM_MMCONF_LENGTH Please refer to CB:57861 "Proposed coreboot Changes" for more details. BUG=b:181098581 BRANCH=None TEST=./util/abuild/abuild -p none -t GOOGLE_KOHAKU -x -a -c max Make sure Jenkins verifies that builds on other boards Change-Id: I1e196a1ed52d131a71f00cba1d93a23e54aca3e2 Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09mb/google/brya/var/redrix: Set RFI Spread Spectrum to 6%Wisley Chen
Set RFI Spread Spectrum to 6% for Redrix as RF team request. The default of Spread Spectrum in FSP is 1.5%, and set 1.5% in baseboard as default. BUG=b:200886627 TEST=build Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: Id0b42446e9e46ef629b5ca8d5d29faf2d771348d Reviewed-on: https://review.coreboot.org/c/coreboot/+/58880 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-09mb/intel/adlrvp: Set same size for CSE_RW and ME_RW_A/BReka Norman
During CSE firmware updates, the CSE RW firmware from ME_RW_A/B is copied to CSE_RW, so the sizes of these regions need to match. BUG=b:189177538 TEST=emerge-brya coreboot chromeos-bootimage Signed-off-by: Reka Norman <rekanorman@google.com> Change-Id: I94e0615088349af34020fb8a126fce9e72df9ee2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/59006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2021-11-09google/trogdor: Update the power on sequence of ps8640xuxinxiong
For the Qualcomm PBL configuration of GPIO, we need to initial the GPIOs for VDD33# and RST# at the beginning of coreboot. According to the pa8640 latest spec v1.4, update the sequence of VDD33# and PD#. BUG=b:204637643 BRANCH=trogdor TEST=verified the waveform of ps8640 at coreboot phase. Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Change-Id: Ia378aafa49ec462c990501ce48721e330d9648b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58994 Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-09mb/google/dedede/var/metaknight: Probe and enable amplifier operation modeDavid Wu
Probe the fw_config for RT1015 speaker amplifier operation mode and enable it accordingly in the device tree. BUG=none BRANCH=dedede TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I2de1487b7f4767e9ba6432174c39feeb25f9534c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Adjust I2C speedSeunghwan Kim
This change adjusts all I2C speed to lower then 400KHz. The rise_time_ns and fall_time_ns values for each port are capured by a scope. BUG=None BRANCH=dedede TEST=built and verified adjusted I2C speed < 400KHz Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I9504608dd8d9a5f5a3848ef34691557942c21023 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58965 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/magolor: Enable ELAN touchscreen for magnetoTyler Wang
Add ELAN touchscreen support for magneto. BUG=b:203122673 TEST=Build and verify that touchscreen works. Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Change-Id: Ie86692901113e952c597fcfc6c58e7ee0fc172fa Reviewed-on: https://review.coreboot.org/c/coreboot/+/58967 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Update charger performance control tableSeunghwan Kim
Update charger performance control table of DPTF for bugzzy. Since the EC change chromium:197776876 modified maximum charging current to reduce skin temperature, this change adjusts the charging performance table with the modified value. BUG=b:197776876 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: I33e176fcf5d380b315ff352c6c65af3b8b93c4b9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58840 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09mb/google/dedede/var/bugzzy: Enable Wifi SARSeunghwan Kim
BUG=None BRANCH=dedede TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot chromeos-bootimage Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Change-Id: Ie967ef7fbc19886c631e634a0b0c3f2cf1e490af Reviewed-on: https://review.coreboot.org/c/coreboot/+/58845 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-09emulation/qemu-i440fx,q35: Split chromeos.cKyösti Mälkki
This drops VBOOT_NO_BOARD_SUPPORT. There is little impact of always having recovery_mode_switch() implemented in bootmode.c. A weak write_protect_state() is not necessary as there is no BOOT_DEVICE_SPI_FLASH with the emulation. Call to fill_lb_gpios() is already guarded with CONFIG(CHROMEOS) so the weak implementation would not be referenced. Change-Id: I3c00b30c5233ae3556b7622f97c3166668c8ab12 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58946 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-09pci_mmio_cfg: Always use pci_s_* functionsNico Huber
When MMIO functions are available, the pci_s_* functions do exactly the same thing. Drop the redundant pci_mmio_* versions. Change-Id: I1043cbb9a1823ef94bcbb42169cb7edf282f560b Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58333 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2021-11-09ChromeOS: Fix <vc/google/chromeos/chromeos.h>Kyösti Mälkki
Change-Id: Ibbdd589119bbccd3516737c8ee9f90c4bef17c1e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-09soc/nvidia,qualcomm: Fix indirect includesKyösti Mälkki
Avoid indirect <vc/google/chromeos/chromeos.h> as the files really only need <security/vboot/vboot_common.h>. Change-Id: Ic02bd5dcdde0bb5c8be0e2c52c20048ed0d4ad94 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58949 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-06google/guybrush: Move SPI speed overrideKyösti Mälkki
SPI speed override is not related to ChromeOS, thus the location in chromeos.c was poor choice. Change-Id: Ie3db89f252af1f44e9539497c05bdf965565a191 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58945 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05mb/google,intel: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I9e7200d60db4333551e34a615433fa21c3135db6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/emulation/qemu-i440fx: Refactor `fw_cfg_max_cpus()`Angel Pons
Return 0 instead of -1 in case of error. Both values indicate an error has happened. Adapt `cpu_bus_scan()` accordingly. Change-Id: I0f83fdc41c20ed3aae80829432fc84024f5b9b47 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58918 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-11-05mb/google: Fix indirect include bootmode.hKyösti Mälkki
Change-Id: I882c567e6bca0982a0d3d44c742777c4d7bd5439 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58920 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google/corsola: Add NOR-Flash supportRex-BC Chen
Add NOR-Flash drivers to pass verification of flash at verstage. TEST=boot to romstage BUG=b:202871018 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: Iee3dd336632b0cf998f5f7c1d118e01e8270e815 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58838 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-05mb/google/taeko: Update the FIVR configurationsKevin Chang
This patch sets the enable the external voltage rails since taeko board have V1p05 and Vnn bypass rails. BRANCH=None BUG=b:204832954 TEST=FW_NAME=Check in FSP log and run PLT test Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I20ff310d48d3e7073fe5e94d03d29cc55a46d1f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58943 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-05mb/google/brya/var/felwinter: Correct typeC EC mux portEric Lai
Type C port2 uses EC mux port0 as per schematics. BUG=b:204230406 TEST=No error message in depthahrge. update_port_state: port C2: get_usb_pd_mux_info failed Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I85218c81018b248c41a2cdaf9360a86e2a7d4d7a Reviewed-on: https://review.coreboot.org/c/coreboot/+/58930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04treewide: Replace bad uses of `find_resource`Angel Pons
The `find_resource` function will never return null (will die instead). In cases where the existing code already accounts for null pointers, it is better to use `probe_resource` instead, which returns a null pointer instead of dying. Change-Id: I329efcb42a444b097794fde4f40acf5ececaea8c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58910 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Lance Zhao
2021-11-04mb/google/sarien: Add OEM product namesFelix Singer
Add OEM product names from public sources. Change-Id: Ic051aa9c8afabd47e7e9f6ac878190d9904ef757 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58911 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/siemens/mc_ehl: Disable PMC low power modesWerner Zeh
All the mainboard variants of mc_ehl do not use the external switches for the bypass rails. Disable the matching UPDs and all the low power modes of the PMC. Change-Id: I08f4effe5c4d5845bed01dfe1bd1251c58012b7f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58895 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04mb/siemens/mc_ehl: Disable all P-StatesWerner Zeh
In order to get a reliable real-time performance disable all P-States for all mc_ehl based mainboard. Change-Id: I22857cc0f1476483ca82c1c872e4519e4b350ea9 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-04mb/siemens/mc_ehl: Disable C-States for CPU and packageWerner Zeh
Disable all C-states other than C0/C1 for CPU and package. Change-Id: I2c163f859dab4b0dc02896c70122e993cdd3db72 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58893 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Clean up devicetreeMario Scheithauer
There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: I7486f9ba362c80b43b6c888a3b40a4c947218299 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58887 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-04mb/google/guybrush: Set Gen3 default for all PCIe devicesMatt Papageorge
Currently link_speed_capability is not specified within the DXIO descriptors sent to FSP. This value specifies the maximum speed that a PCIe device should train up to. The only device on Monkey Island that is not currently running at full speed is the NVME but this may not always be the case. BUG=b:204791296 TEST=Boot to OS and check link speed with LSPCI to verify NVME link speed goes from 2.5 GT/s to 5 GT/s Change-Id: Ibeac4b9e6a60567fb513e157d854399f5d12aee9 Signed-off-by: Matt Papageorge <matthewpapa07@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-11-04mb/google/brya/var/kano: Update GPIO table for speak and dmicDavid Wu
Refer to intel doc #627075 (Intel_600_Series Chipset_Family_PCH_GPIO_Impl_Sumry_ Rev1p5p1) Set GPIO GPP_S0 ~ GPP_S3 to NF4 and GPP_R6 ~ GPP_R7 to NF3. BUG=b:204844177 b:202913826 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Iafe52ec3a6deead1d2fc5ada0f2842cf2a9f41a4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58877 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: CT Lin <ctlin0@nuvoton.corp-partner.google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-04mb/google: Add OEM product names for various boardsMartin Roth
All of these names came from public sources. Signed-off-by: Martin Roth <martin@coreboot.org> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Change-Id: I1ed9cc0c1ff63dc415e0cc63fa9d2dcd429a093b Reviewed-on: https://review.coreboot.org/c/coreboot/+/57392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-04mb/siemens/mc_ehl: Enable Row-Hammer preventionMario Scheithauer
As a prevention of Row-Hammer attacks enable the FSP-M parameter 'RhPrevention'. Change-Id: I52f68525e882aee26822d9b3c488639c00f27d17 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58856 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Configure SD card detect pin in devicetreeMario Scheithauer
This configures GPIO GPP_G5 as an input pin for SD card detect. Change-Id: I708eb112fa054f2f88857001c409fb62493b6206 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58855 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Clean up PCIe root port settings in devicetreeMario Scheithauer
PCIe root ports #4 (00:1c.3) and #6 (00:1c.5) are currently not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I47e8528bea993ed527a0aecdbc93b94bbd9a7a49 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2021-11-04mb/siemens/mc_ehl2: Adjust PCIe clock settings in devicetreeMario Scheithauer
On mc_ehl2 there are currently four of the six PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device. Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I81419887b7f463a937917b971465245c1cb46b94 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58852 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Lean Sheng Tan <lean.sheng.tan@intel.com>
2021-11-04mb/google/guybrush/bootblock: add comment on selecting eSPI interfaceFelix Held
Setting the PM_ESPI_CS_USE_DATA2 bit in PM_SPI_PAD_PU_PD results in the eSPI transactions being sent via the SPI2 pins instead of the SPI1 pins. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Iad8e3a48496a52c14c936ab77c75dc1b403f47bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/58876 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04soc/amd/cezanne/include/gpio: fix GPIO 106 native function namesFelix Held
The name looked a bit odd and the Cezanne PPR #56569 Rev 3.03 confirmed that the native function names don't have the EMMC_ prefix. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I917c74afd98f2e2133e160d352f11f08c19a3ec6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-11-04mb/system76/*: Enable HECI deviceTim Crawford
The HECI device needs to be enabled to send the commands to have the CSME change between Soft Temporary Disable mode and Normal mode. Change-Id: I668507e3b522137bcc827aa615dab1fccd1709a0 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58670 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-04mb/purism/librem_skl: Clean up hda_verb.cAngel Pons
Use the `AZALIA_RESET` macro, write hex values in lowercase and remove redundant comments. Also express verb length in decimal. Tested with BUILD_TIMELESS=1, Purism Librem 15 v4 remains identical. Change-Id: Id9f5ff9614a8f8c0b7f3a3c633a1dcdda8c5876c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-04mb/purism/librem_bdw/hda_verb.c: Rewrite using macrosAngel Pons
Rewrite the HDA configuration using macros for clarity. Tested with BUILD_TIMELESS=1, Purism Librem 13 v1 remains identical. Change-Id: I987a41329425a5c8c7169a7fa66a34de5742532e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58902 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-03mb/google/trogdor: Mark kingoftown as supporting Parade PS84640Kevin Chiu
BUG=b:204272905 BRANCH=master TEST=emerge-trogdor coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ie13ddfef6adfd53adb0a0d3a98995fb00b8a45e6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2021-11-03mb/google/corsola: Add MediaTek MT8186 reference boardRex-BC Chen
Add mainboard folder and drivers for new reference board 'Corsola'. TEST=build pass BUG=b:200134633 Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Change-Id: I2d701c03c97d3253effb6e93a2d55dcf6cf02db6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58648 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.corp-partner.google.com> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2021-11-03mb/siemens/mc_ehl1: Adjust PCIe clock settings in devicetreeWerner Zeh
On mc_ehl1 there are three of the 6 PCIe clocks used to drive PCIe devices. None of the used clock output is dedicated to a special device (CLK0 drives several devices on the mainboard, CLK1 and CLK2 are connected to a PCIe switch). Therefore do not use a port mapping of the clocks to avoid a stopping clock once a device is missing and the matching root port is disabled. Instead set the mapping to 'PCIE_CLK_FREE' to have a free running clock. In addition, use the defined constant 'PCIE_CLK_NOTUSED' instead of the value 0xFF to disable the CLKREQ-feature and unused clocks. Change-Id: I2beea76ff8fefd79f476bef343d13495b45cdfcf Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58740 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/oryp8: Add System76 Oryx Pro 8Jeremy Soller
https://tech-docs.system76.com/models/oryp8/README.html Tested with TianoCore (UeifPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone & microphone jack - Combined 3.5mm microphone & S/PDIF jack* - S3 suspend/resume - Booting to Pop!_OS Linux 21.10 and Windows 10 20H2 - Flashing with flashrom Not working: - Discrete/Hybrid graphics Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: Iabc8e273f997d7f5852ddec63e0c1bf0c9434acb Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/bonw14: Add System76 Bonobo Workstation 14Jeremy Soller
Change-Id: I55a827f8d6a5421c36f77049935630f4db4ba04d Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49173 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/kbl-u: Add Galago Pro 2 as a variantJeremy Soller
Change-Id: Ia277b3ad50c9f821ab3e1dcb8327314ba955fa79 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52219 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/kbl-u: Add Galago Pro 3 as a variantJeremy Soller
Change-Id: Ie203883cc9418585da4f9c7acd89e7624234caf1 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52218 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/system76/kbl-u: Add System76 Galago Pro 3 Rev BJeremy Soller
Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/gaze15: Add Gazelle 14 as a variantTim Crawford
Change-Id: Ib455951d1d26ddfa010d4eb579905235bd1385a9 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/gaze15: Convert to variant setupTim Crawford
Change-Id: I6d8a97d71ff3b4408f5e11230ed3ff00357f7123 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58675 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/oryp6: Add Oryx Pro 7 as a variantJeremy Soller
Change-Id: Id00a45a6a6acf0880934c55f1a3f18e63f2aed43 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52296 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02mb/system76/oryp6: Convert to variant setupTim Crawford
The Oryx Pro 6 has the same board layout as the next model in series, Oryx Pro 7. The primary difference between the two is the dGPU (20 series to 30 series). Convert oryp6 to a variant setup in preparation for adding the oryp7. Change-Id: I976750c7724d23b303d0012f2d83c21a459e5eed Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57786 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-11-02Revert "mb/google/brya/var/kano: disabled autonomous GPIO power management"David Wu
This reverts commit 287cc02c007fd47b515d19389ea00ea0461fd5a1. Reason for revert: it will break s0ix. BUG=b:201266532 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I393077b26e2cdeae055d8eea1030754602e94ada Reviewed-on: https://review.coreboot.org/c/coreboot/+/58809 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/google/volteer: allow MKBP devices and disable TBMC deviceFrankChu
Enable MKBP (Matrix Keyboard Protocol) interface for all volteer family to use for buttons and switches. Disable TBMC (Tablet Mode Switch device), as it is not needed anymore. BUG=b:171365305 TEST=manual test on Volteer: Volume Up/Down and Power buttons, Tablet Mode switch Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I2bb2e895af17fa4280113e57e2b0ca780af8840e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Boris Mittelberg <bmbm@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/intel/adlrvp: Configure EC in RW GPIOAnil Kumar
EC_IN_RW signal from EC GPIO is connected to GPIO E7 of SOC. This GPIO can be used to check EC status trusted (LOW: in RO) or untrusted (HIGH: in RW). Branch=none Bug=none Test=Issue manual recovery and confirm DUT is entering recovery mode on ADL-M RVP. Signed-off-by: Anil Kumar <anil.kumar.k@intel.com> Change-Id: I20804db450ab0b3ebe19c51ba2b294a0137d81a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/google/guybrush: Update STT coefficientsJason Glenesk
Update guybrush STT (Skin Temperature Tracking) configuration settings to values provided by power team after tuning. BUG=b:203123658 Change-Id: I14c69dbe044e4f3f2711be96e5ea80db0686b3eb Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58674 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com>
2021-11-02mb/system76/*: CMOS: Drop power_on_after_fail optionTim Crawford
Our boards do not boot if power_on_after_fail=Disable. Drop the option and use the default of powering on. Change-Id: Ia1857e52f838337048f79f8ca5c12d669cae321a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2021-11-02mb/google/brya: Correct AT24 NVM address sizeVarshit B Pandya
Currently, the address size field of AT24 NVM is incorrect, and Linux v5.10 kernel logs the message below: at24 i2c-PRP0001:01: Bad "address-width" property: 14 The valid size of the AT24 NVM is 16 bits so modify the value from 0x0E to 0x10. TEST=Boot brya and check the kernel log and see "Bad address-width" error message is not shown. Signed-off-by: Varshit B Pandya <varshit.b.pandya@intel.com> Change-Id: I6c1ed5334396e0ca09ea0078426a7b5039ae4e8b Reviewed-on: https://review.coreboot.org/c/coreboot/+/58769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2021-11-02mb/google/brask: add the mkbp deviceZhuohao Lee
In order to let the ec passing the key event like recovery and power key to the OS, we need to include EC_ENABLE_MKBP_DEVICE to generate the MKBP device. BUG=b:204519353, b:204512547 BRANCH=None TEST=pressed recovery key and power button in the OS and checked the UI behavior. Change-Id: Ia1d0b9b301994ad9a0f4bf28b75ab0310a1d63a0 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58744 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-02mb/siemens/mc_ehl1: Clean up PCIe root port settings in devicetreeWerner Zeh
PCIe root ports #5 (00:1c.4) and #6 (00:1c.5) are not used on this mainboard and are not routed either, so remove them from the devicetree completely. PCIe root port #7 (00:1c.6) is connected and used. Add the missing settings for L1 substates and latency reporting to disable these features for this port as well. Change-Id: I06f59f0369ffcd958b5fe12bb3c646d37103811f Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58568 Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-02mb/siemens/mc_ehl1: Clean up devicetreeWerner Zeh
There are a bunch of devices in the devicetree that are disabled in FSP-S and not used on this board. Having them around in the devicetree, even if disabled, is not necessary and leads to a message in the log (left over static devices...check your devicetree). This commit cleans up devicetree.cb and removes all unused and disabled devices. Change-Id: Ia5ffb382e3524e61b8583aca801063942fe2f247 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58567 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2021-11-02mb/google/zork/var/vilboz: Generate new SPD ID for new memory partsFrank Wu
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1. Hynix H5ANAG6NCJR-XNC 2. Micron MT40A512M16TB-062E:R 3. ADATA 4JQA-0622AD BUG=b:199469240 BRANCH=firmware-zork-13434.B TEST=FW_NAME=vilboz emerge-zork coreboot chromeos-bootimage Signed-off-by: Frank Wu <frank_wu@compal.corp-partner.google.com> Change-Id: I57cca403800d9731a7b689ac9773a7940e83904e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-11-01soc/intel/braswell: Set GNVS DPTE via devicetreeAngel Pons
Introduce the `dptf_enable` devicetree setting to set the DPTE GNVS field, as newer Intel platforms do. Change-Id: I88b746c64ca57604f946eefb00a70487a2fb27c0 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/57988 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2021-11-01mb/google/dedede/var/storo: Add fw_config probe for multi audio codecZhi Li
Compatible headphone codec "Realtek ALC5682I-VD" and "ALC5682I-VS" BUG=b:202463494 BRANCH=dedede TEST=ALC5682I-VD or VS audio codec can work normally Signed-off-by: Zhi Li <lizhi7@huaqin.corp-partner.google.com> Change-Id: Ib808ddadef1029d3f06eb2d68164243c386d4905 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-11-01mb/google/brya/var/brya0: add HPS as generic I2C peripheralDan Callaghan
Some brya0 units have HPS fitted and connected to PCH I2C2, rather than a user-facing camera. Because HPS uses I2C address 0x51, which may conflict with the user-facing camera EEPROM, introduce a new fw_config bit to indicate whether HPS is present. BUG=b:202784200 TEST=FW_NAME=brya0 emerge-brya coreboot chromeos-bootimage TEST=ectool cbi set 6 0x28191 4 # set bit 17 for HPS TEST=flashrom -p internal -w image-brya0.serial.bin Signed-off-by: Dan Callaghan <dcallagh@google.com> Change-Id: I322548bcfccf16ba571396bc88fd6fc03c036a4e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58646 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-11-01mb/google/brya: Enable DRIVERS_GENESYSLOGIC_GL9755 for braskDavid Wu
Enable DRIVERS_GENESYSLOGIC_GL9755 support for brask. BUG=b:197385770 TEST=build pass Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If421e0df058b6f2b87267d5e3822940b90062f71 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-11-01mb/google/brya/var/taeko: Add probe for MAX98357+ALC5682I_VSJoey Peng
Add probe function for the "VS" version of the audio amplifier so taeko can recgonize MAX98357 with ALC5682I_VS. BUG=b:202913837 TEST=FW_NAME=taeko emerge-brya coreboot and check taeko can recgonize MAX98357 with ALC5682I_VS Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Change-Id: Id4ff2003ee6a6f6f4ad98694996689e1a84092c5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/58645 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: YH Lin <yueherngl@google.com>
2021-11-01mb/google/dedede/var/kracko: Add Wifi SAR for krackoRobertChen
Add wifi sar for kracko BUG=b:194460420 TEST=emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage Change-Id: I83bca544c9f71142f95ea1137f732c182b3f29b7 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58522 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Henry Sun <henrysun@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Kevin Chiu <kevin.chiu.17802@gmail.com>
2021-10-29mb/google/brya/var/brask: Correct the GPIO config of buzzerAlan Huang
GPP_B14 is used by buzzer and should be set to NF1 'SPKR'. BUG=b:198998974 TEST=emerge-brask coreboot depthcharge and verify if the buzzer beeps. Signed-off-by: Alan Huang <alan-huang@quanta.corp-partner.google.com> Change-Id: I84978af152a7117c1f3398a9b7adde161db058dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/58692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/anahera: Disable autonomous GPIO power managementWisley Chen
With cr50 fw 0.3.22 or older version, it needs to disable autonomous GPIO power management and then can update cr50 fw successfully. BUG=b:202246591 TEST=FW_NAME=anahera emerge-brya coreboot chromeos-bootimage. Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Change-Id: I9137b6264ee80bc9e00dfdc3ab3926bccb4bf47c Reviewed-on: https://review.coreboot.org/c/coreboot/+/58695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/google/brya/var/kano: disabled autonomous GPIO power managementDavid Wu
Used H1 firmware where the last version number is 0.0.22, 0.3.22 or less to production that will need to disable autonomous GPIO power management and then can get H1 version by gsctool -a -f -M BUG=b:201266532 TEST=FW_NAME=kano emerge-brya coreboot and verify it builds without error. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: If6783e0df1404c9a353061fb564210aa0d12896e Reviewed-on: https://review.coreboot.org/c/coreboot/+/58682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-10-29mb/prodrive/hermes: Enable LTR for all PCIe portsAngel Pons
Set the `PcieRpLtrEnable` option to enable the LTR capability on all PCH PCIe root ports. TEST=Verify LTR capability enabled in `DevCap2` using `lspci -vv` Change-Id: I07ea37d178ea61d904c4f131fdea31479e899ef3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58326 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-10-29mb/prodrive/hermes: Map PCIe clocks to root portsAngel Pons
Map each PCIe clock source to the corresponding root port. Also, correct the CLKREQ# mapping for clock sources not associated to any CLKREQ# pin. The default `PcieClkSrcClkReq` value of 0 corresponds to CLKREQ# 0. TEST=Check that Linux sees the same PCIe devices with this commit: - All 5 onboard Ethernet NICs - BMC - Two random graphics cards in PEG0 and PEG1 slots - M.2 M NVMe SSD Change-Id: I0515877a36d42fb8858a0f0b3c0af1199a18d9af Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2021-10-29mb/prodrive/hermes: Fix PCIe ClkSrc configurationAngel Pons
Correct the PCIe clock source configuration as per the schematics. Apparently, FSP does not turn off unused PCIe clock sources when using SPS (Server Platform Services) firmware, but it does when using CSME firmware. TEST=BMC and Ethernet NICs get detected when using CSME firmware. Change-Id: Id25a34816f512510640db95251a7a792c1eebe62 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/58065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-16 11:04:09 +0000