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2018-07-20mediatek: Share GPIO code among similar SOCsTristan Shieh
Refactor GPIO code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Icdd1f2a1dd1bd64a7218bf9c63bd4a0af1acbcc0 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27416 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-20mb/google/poppy/variants/nocturne: set nvme to use clk src 3Nick Vaccaro
Latest nocturne architecture uses clk src 3 for nvme. BUG=b:111514174 BRANCH=none TEST="emerge-nocturne coreboot chromeos-bootimage" and verify nvme nocturne devices are able to recognize the nvme controller. Change-Id: I5b2bf012ba88568cb4b0bb3918a3a2c6770ff4c1 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27536 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-20mainboard/google/kahlee: Create Liara variantMartin Roth
This is based on the Grunt variant. BUG=b:111607004 TEST=Build Liara Change-Id: I8f23e972be0d1665c736d61621a0caaa4c4c5551 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-20mainboard/google/kahlee: Create Aleena variantMartin Roth
This is based on the Grunt variant. BUG=b:111606874 TEST=Build Aleena Change-Id: I6fd42db6f9f309c3c375b670cd22f818555e4195 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27538 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-07-19ec/lenovo/h8/acpi: Apply state on wakePatrick Rudolph
Implement ACPI S3 resume control to restore the state before entering sleep. * Store the requested state wake state for bluetooth and WWAN. * Add new methods to init the state and apply the requested state on wake. * Call the new method on all devices. Change-Id: I13c08b8c6b1bf0f3deb25a464b26880d8469c005 Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/22377 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-19mb/lenovo/x201: Allow use of libgfxinitArthur Heymans
Tested on LVDS (internal), VGA and HDMI (on the dock DP++ connector) output with both native resolution and textmode. Change-Id: Ibfcb586d7b4cac7f1d22540bb96c288704a277a0 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27513 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19soc/cavium: Add PCI supportPatrick Rudolph
* Add support for secure/unsecure split * Use MMCONF to access devices in domain0 * Program MSIX vectors to fix a crash in GNU/Linux Tested on Cavium CN81XX_EVB. All PCI devices are visible. Change-Id: I881f38a26a165e6bd965fcd73547473b5e32d4b0 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25750 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-19arch/x86/smbios: Add support for table 38Patrick Rudolph
Add support for SMBIOS table 'IPMI Device Information' and use it on HP Compaq 8200 Elite SFF. Tested on HP Compaq 8200. dmidecode prints the table and sensors-detect scans for IPMI compatible devices. Change-Id: I66b4c4658da9d44941430d8040384d022d76f51e Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/25386 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18mb/google/octopus/variants/baseboard: Udpate CPU critical tempSumeet Pawnikar
Observed thermal shutdown initiated by DPTF due to CPU temperature reaching critical temperature trip value. During stress testing with busty workloads like Octane, Aquarium on open yorp board with heat sink, sometime CPU temperature spikes till 99 degree Celsius and DPTF initiates system shutdown. With reference to previous APL/reef/coral platforms, this updates 105 degree Celsius for the CPU critical temperature trip value to avoid shutdown. This patch also updates power limit1 value to avoid the abrupt thermal shutdown by DPTF. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Icd786d3c9b5f7c733dac3fd3e22579e2434058a6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27294 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-18mainboard/google/Kahlee: Select low-power mode for WiFiSimon Glass
Put the PCIe clock pins in power-saving mode for the WiFi module to save power. Note: This currently does not appear to have any effect on grunt. BUG=b:110041917 BRANCH=none TEST=boot without this patch: $ iotools mem_read32 0xfed80e00 0x0046f3ff With this patch: $ iotools mem_read32 0xfed80e00 0x0046f3f1 Change-Id: I389815bc36b8610a30b0cbb9d73262ad392e0181 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27465 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-18mainboard/google/kahlee: Enable ASPM on PCI expressSimon Glass
We should use active-state power management where possible to reduce power consumption during normal operation. Enable these options. Linux does not seem to enable this for AMD, and the Intel code in coreboot does enable these options. PCIEXP_COMMON_CLOCK is enabled also, to follow how Intel does it. BUG=b:110041917 TEST=boot on grunt, see that WiFi and eMMC still run OK Change-Id: Ia7c711304ffe460a9fb0d4f654a51485958239ea Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27464 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18mb/google/octopus: Create meep variantJustin TerAvest
This creates a meep variant for octopus. The devicetree overrides are copied from yorp, otherwise everything just defaults to baseboard settings. BUG=b:111543000 TEST=None Change-Id: I791f8d1589d7323fbe884dddf0f9d7362a41b9ac Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27516 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-18mb/lenovo/x201: Add data.vbt fileArthur Heymans
Extracted from live running Thinkpad X201 with vendor firmware. Change-Id: Ia33b4c1a2af6f7d460375cc8ea4e404963a72244 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-17Add VBT data for Gigabyte GA-H61-S2PVp4block
Extracted from the stock UEFI using UEFItool & intelvbttool. Without it, the kernel complains about the missing VBT table. Additionally, the invalid oprom signature warning given by i915 is also gone. Change-Id: I1871eca9e9c21531d842289f6624ec44420d9844 Signed-off-by: Pablo Moyano <42.pablo.ms@gmail.com> Reviewed-on: https://review.coreboot.org/27482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-17mb/google/atlas: Add MIPI camera ASL filesChen, Ping-chung
Atlas has one sensor, create a single endpoint to CIO2. Create power resource for enabling/disabling camera. BUG=b:111141128 Branch=None TEST=Testing on Atlas board Change-Id: Ide0e923bbc34f869dd0227c0a29977645bc5d58d Signed-off-by: Ping-Chung Chen <ping-chung.chen@intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/27350 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Andy Yeh <andy.yeh@intel.com> Reviewed-by: Rajmohan Mani <rajmohan.mani@intel.com>
2018-07-17cavium/bdk: Fix coverity and remove hardcoded DRAM speedPatrick Rudolph
* Fix CID1393963 (Uninitialized variables) * Comment in working code * Remove workaround to limit DDR speed Change-Id: I96289da43c1018c2fdf9d013ce7f21d7511ba595 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/27452 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-17mainboard/google/kahlee: Don't default backlight onMarc Jones
Keep the backlight off until it is needed. BUG=b:72694972 TEST=Backlight turns on at ChromeOS splash screen, not prior. Change-Id: Ia1aba787734e2976146ecd305dd821f0b326f0db Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27489 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-17mainboard/google/kahlee: Enable backlight on resumeMarc Jones
BUG=b:72694972 TEST=Backlight turns on ChromeOS resume Change-Id: I452e2ea94b508b137cf52301df5d2d1ad5c9ab70 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27488 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mainboard/google/kahlee: Enable backlight in SMI APMCMarc Jones
Enable the backlight in the OS callback to SMI for APMC. This keeps the backlight off until the OS is ready to display something. BUG=b:72694972 TEST=Backlight turns on at ChromeOS splash screen Change-Id: Idf32b1a3d45971883571a829a5c0c1f8563bb1f7 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27487 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mainboard/google/kahlee: Add mainboard resume functionMarc Jones
Add the mainboard resume function and __weak variant override. Change-Id: I808734208bd1ce81428771ea203709b53db56cd3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/27486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-17mb/facebook/watson: Update IDPROM region in board.fmdDavid Hendricks
This updates the IDPROM region along with the unused regions. Change-Id: If73bb8162d3d0733e3bd8561cd5549f2184db2be Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/27505 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-16mb/lenovo/x201: Fix EC SSDTPatrick Rudolph
Move the EC under the LPC PCI device to make sure that the SSDT path matches the DSDT. Matches the behaviour of all other Lenovo devices. Change-Id: I9ded7f639866d71d39ea0d5d0c36602d386c177f Signed-off-by: Patrick Rudolph <siro@das-labor.org> Reviewed-on: https://review.coreboot.org/27481 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Matthias Gazzari <mail@qtux.eu> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-16google/grunt: fix thermal zone CPU temperature reportKevin Chiu
there are 3 thermal sensors and index is: 0: 1 Charger 1: 1 SOC 2: 0 CPU it needs to adjust sensor to index 2 to have correct CPU temperature. BUG=b:111284412 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I27afb6c5b64b0c39d6db15e6c61ea16a1fda1ca3 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16mainboard/google/kahlee: Add support for Dediprog em100Simon Glass
This device claims to run at 75MHz with dual read, but it is not always reliable. Add an option to change the SPI flash speed to 16MHz, to avoid any problems. BUG=b:111363976 TEST=manually try to get my em100 running (it doesn't yet) Change-Id: I78d3d32c467aac82c72d31c773bfb0f69808aed4 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-16Kconfig: Make the EM100 config option commonSimon Glass
This applied to AMD devices as well as Intel, although the mechanism is different. Move the option to a common place. BUG=b:111363976 TEST=USE=em100-mode emerge-reef coreboot See that a message appears: * Enabling em100 mode (slow SPI flash) Change-Id: Iea437bdf42e7bc49b1d28c812bfc6128e3eb68bd Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/27467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-07-13mb/google/poppy/variants/nami: Use Pantheon VBTIvy Jian
Add new Pantheon sku-id for loading vbt-pantheon.bin BUG=b:78663963 BRANCH=firmware-nami-10775.B TEST=Boots to OS and display comes up. Check the board specific vbt binary loaded. Change-Id: I1ee156372754ac0e77caae5959a9ca9884de95f4 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27432 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-13mainboard/google/kahlee: Add more 3 SPD filesMartin Roth
BUG=b:111195311 TEST=Build grunt, verify SPDs are present Change-Id: Ief5ed5c3ca1d96b36926f1fc84c344a8d66dcda5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12mainboard/google/nocturne: Update GPIO_FCAM_PWR_ENRicky Liang
The FCAM_PWR_EN gpio should be GPP_B4 according to the latest board schematics. Change-Id: Id926bd224b3392d8a61b6d8ae0509053afaa5b9e Signed-off-by: Ricky Liang <jcliang@chromium.org> Reviewed-on: https://review.coreboot.org/27433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tomasz Figa <tfiga@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-07-12soc/intel/braswell/acpi/dptf/thermal.asl: Make Thermal event optionalFrans Hendriks
Currently thermal event support can not be disabled at board level. Define and dependent code are placed in same file. Move define of HAVE_THERM_EVENT_HANDLER to mainboard file. Change-Id: Icb532e5bc7fd171ee2921f9a4b9b2150ba9f05c5 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-on: https://review.coreboot.org/27415 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-12mb/google/octopus/variants/yorp: Enable TBMC deviceFurquan Shaikh
This change enables tablet mode ACPI device for yorp. BUG=b:111264961 CQ-DEPEND=CL:1132686 Change-Id: I81140b84a1adb5b21f1656fd89d953331e538f01 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27431 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12mb/google/octopus: Enable TBMC device only for phaserFurquan Shaikh
Enabling of TBMC device on AP side requires corresponding support on the EC side as well. Since not all octopus variants have tablet mode support enabled, this change enables TBMC device only for phaser. BUG=b:111264961 Change-Id: I1ce181baa8ebaff0a9d767e97ddc256eef9789e8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-12mb/google/octopus/variants/bip: Enable EC SW syncFurquan Shaikh
This change enables EC SW sync for bip by removing GBB flag selection for disabling SW sync. BUG=b:110523189 TEST=Verified that EC SW sync works fine on bip. Change-Id: Iff8ee67fd682530a4fa82643cd1d00a645b347a3 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-07-11skylake: Remove "IshEnable"li feng
Remove "IshEnable" from soc_intel_skylake_config since it's not used anymore. Enable/disable ISH by checking if ISH device is turned on or not. Refer to https://review.coreboot.org/#/c/coreboot/+/26485/. BUG=b:79244403 BRANCH=none TEST=Built. Change-Id: I4d2889af118659852431c87cb516fd19b577efc5 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26521 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11mainboard/google/poppy/variants/atlas: config ISH in mainboard sideli feng
To enable ISH device on atlas board, change "device pci 13.0 off end" to "device pci 13.0 on end" in file mainboard/google/poppy/variants/atlas/devicetree.cb. "IshEnable" is not needed. Config atlas board specific ISH setting in devicetree.cb. Dynamically load gpio setting for ISH enabled/disabled cases. BUG=b:79244403 BRANCH=none TEST=Verified on Atlas board with ISH rework. ISH log showed on console. Change-Id: I8269a85cd2ab7917bfc0e7d63d988e0e678d0bf2 Signed-off-by: li feng <li1.feng@intel.com> Reviewed-on: https://review.coreboot.org/26486 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-11google/kukui: Update MMU table in romstage and ramstageTristan Shieh
In order to get better performance, map dram as cached after dram ready in romstage. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui. Need a futher check after dram calibration code ready. Change-Id: Ie541fe08ee1d5b260abbabc0a5c18fb04e602b9c Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27304 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mediatek: Share MMU operation code among similar SOCsTristan Shieh
Refactor MMU operation code which will be reused among similar SOCs. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Elm Change-Id: Id8173da0a02e57e863263fcd89c91a9c089e8a0f Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/27349 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-07-11mainboard/google/kahlee: Update existing SPD filesMartin Roth
Add an extra space after 8th value on each line to make it easier to count the values. Update the empty spd to remove two random 0x80 values. BUG=None TEST=None Change-Id: If330dbf0c133f65aedddc58ecb351a80b0e45a05 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27423 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-11mainboard/google/kahlee: Add additional SPDs for variantsMartin Roth
BUG=b:111079089, b:80375243 TEST=Build grunt, verify that SPDs are included. Change-Id: Idb03a3fa0842f7f89bb8c66dedbb8a0b293569be Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/27422 Reviewed-by: Daniel Kurtz <djkurtz@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10soc/cavium: Add secondary CPU supportPatrick Rudolph
Change-Id: I07428161615bcd3d03a3eea0df2dd813e08c8f66 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium/cn81xx: Set cntfrq_el0Patrick Rudolph
Set cntfrq_el0 to provide correct timer frequency. Change-Id: I4b6d0b0cf646a066fc5a51552a1891eccbd91e5e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25450 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10mb/cavium/cn8100_sff_evb: Be verbosePatrick Rudolph
Print some useful information about the board. Change-Id: I0acac7a29290bc2eb9f4283317165fa0cf1b24e1 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25449 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-10soc/cavium: Clean uart codePatrick Rudolph
* Only init UART_FOR_CONSOLE * Allow UART init with zero baudrate. * Init UART0..3 on Cavium's cn8100_sff_evb to fix kernel panic. Tested on CN8100_SFF_EVB. Change-Id: I1043b30318ec6210e2dd6b7ac313a41171d37f55 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10soc/cavium: Enable MMUPatrick Rudolph
* Configure and enable MMU. * Cover the whole I/O space. * A minimum of 512KB TTB space is required. * Use secure mem attribute as firmware is running in ARM TZ region. Tested on Cavium SoC. Change-Id: I969446da62b4cc7adf9393fab69ff84ebf49220d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-10cavium: Add CN81xx SoC and eval board supportDavid Hendricks
This adds Cavium CN81xx SoC and SFF EVB files. Code is based off of Cavium's Octeon-TX SDK: https://github.com/Cavium-Open-Source-Distributions/OCTEON-TX-SDK BDK coreboot differences: bootblock: - Get rid of BDK header - Add Kconfig for link address - Move CAR setup code into assembly - Move unaligned memory access enable into assembly - Implement custom bootblock entry function - Add CLIB and CSIB blobs romstage: - Use minimal DRAM init only devicetree: - Convert FTD to static C file containing key value pairs Tested on CN81xx: - Boots to payload - Tested with GNU/Linux 4.16.3 - All hardware is usable (after applying additional commits) Implemented in future commits: - Vboot integration - MMU suuport - L2 Cache handling - ATF from external repo - Devicetree patching - Extended DRAM testing - UART init Not working: - Booting a payload - Booting upstream ATF TODO: - Configuration straps Change-Id: I47b4412d29203b45aee49bfa026c1d86ef7ce688 Signed-off-by: David Hendricks <dhendricks@fb.com> Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/23037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Hendricks <david.hendricks@gmail.com>
2018-07-09src/mb: Use "foo *bar" instead of "foo* bar"Elyes HAOUAS
Change-Id: Iedc2e48349e40e94863c8080d11e11dbe6084c9d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27406 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-07-06src: Add missing license headersMartin Roth
These two files were added before I was able to get the updated linter committed. Updated/Add the headers so the stable header lint check can be updated. Change-Id: I464ddecb5eebe8c5b907f3dcfeab1b06501af6ab Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/27362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-07-06google/grunt: Update Raydium TS device ACPI nodesKevin Chiu
change I2C irq to EDGE trigger BUG=b:110962003 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: Iff3acf4199d23b29dff209ec1c03a731679c6cbe Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/27327 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-06mb/google/octopus: Enable tablet modeJustin TerAvest
This change configures ACPI to properly route notifications from the EC for tablet mode events to userspace. Relevant EC config changes are at: https://chromium-review.googlesource.com/c/chromiumos/platform/ec/+/1125261 BUG=b:111078678 TEST=With EC change, tablet mode detected by evtest and powerd Change-Id: Ifbc318186b195534f647f062544de4968aa87401 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27346 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06mb/google/poppy/variants/nocturne: fix FPMCU IRQ sensitivityVincent Palatin
the FPMCU_INT_L on GPP_C11 is active low but the kernel irq handler is defined as IRQF_TRIGGER_LOW, so do not invert it twice. BRANCH=poppy BUG=b:78613978 TEST=On Nocturne, the 'cros_ec' IRQ count in /proc/interrupts does not increment wildly. Change-Id: I56c13c797b133dd22669a2299bcd16ef14eed335 Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/27221 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-06mb/intel/d945gclf/romstage.c: Remove unneeded includesElyes HAOUAS
Change-Id: I3bdb93e51cabbfc14fe992ccdb6556e344e03c2f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27345 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-06mb/ibase/mb899: Remove unneeded includesElyes HAOUAS
Change-Id: Iee237206f309409be64307d2daee044da52a05e1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27344 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-06google: Use proper ACPI ID for Semtech chips: STHGwendal Grignou
Change-Id: I85cd567a923cccd2504f351aae276b5f0d9db4de Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27347 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt Delco <delco@google.com> Reviewed-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-03mb/pcengines/apu1: use generic SPDMichał Żygowski
Clean up leftovers of old SPD generation and utilize common procedure to produce SPD binary. Change-Id: I4e48817c03b4372887bc0ea14209736ae2b4e48f Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27301 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-03mb/intel/dg43gt: Expose some SIO devices via ACPIArthur Heymans
Change-Id: I0df578b98c5b346caa6f6df5fdabda28788e6b66 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-03mb/intel/dg41wv: Expose some SIO devices via ACPIArthur Heymans
Change-Id: Ia658c117434c3fae45bbbe6c472ca58ba4f1a117 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-07-03mb/intel/glkrvp: Get rid of DRIVERS_PS2_KEYBOARD selectionFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 Change-Id: I9af48e648231c18f98d0cc1ddd178b8d00082b0a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27292 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-07-03mb/google/*: Remove selection of DRIVERS_PS2_KEYBOARDFurquan Shaikh
Until now, chromeec was doing keyboard initialization for the boards that have DRIVERS_PS2_KEYBOARD selected. However, coreboot does not leave the keyboard controller in a default reset state. This could result in payloads or OS failing to probe the controller as there could be stale data buffered in the controller during the handoff. Since the boards using chromeec already perform keyboard initialization in payload, there is no need to initialize the keyboard in coreboot too. This change gets rid of DRIVERS_PS2_KEYBOARD selection from all google mainboards using chromeec. BUG=b:110024487 TEST=Keyboard works fine after booting to OS even if user hits keys during BIOS to OS handoff. Change-Id: I1f49b060eb005c0f2b86f9d68d6758954eeb3cf0 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27291 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02src: Get rid of unneeded whitespaceElyes HAOUAS
Change-Id: I3873cc8ff82cb043e4867a6fe8c1f253ab18714a Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27295 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02src/mb: Fix non-local header treated as localElyes HAOUAS
Also remove some unnedded includes. Change-Id: I036208a111d009620d8354fa9c97688eb4e872ad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27129 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-07-02mb/lenovo/t400: Change CMOS value name to Dual GraphicsNico Rikken
To uniform the naming of the 'Dual Graphics' mode amongst the ThinkPads that support it, the T400 CMOS value needs a change. This was the outcome of a discussion on another patch: https://review.coreboot.org/#/c/coreboot/+/23040/ This might cause breakage for automated NVRAM configuration scripts, and manuals. I only found one manual using the previous 'Switchable' option: https://libreboot.org/docs/install/r400_external.html#a-note-about-gpus Change-Id: I2e4d8bafbae5de97c78dab118f75fdefff1d7c37 Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/27158 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-07-02mainboard/google/nocturne: Enable IPU3Lijian Zhao
Enable Image Processing Unit and CIO2 device that constitute IPU3. BUG=None TEST=Build and boot up into Nocturne platform and check with lspci. Change-Id: Ic2edf5ec7bde5c55ce1b13cf7b680094a9fffc6a Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/27124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02mainboard/google/nocturne: Set camera power sequenceLijian Zhao
To make image sensor working, the intended power sequence need to applied. BUG=NONE TEST=NONE Change-Id: I4833c0e303174b297c1d193495e08e55d294a717 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/27094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02mainboard/google/nocturne: Enable camera sensorsLijian Zhao
Sensors and CSI2 receiver configuration for Nocturne platform. IMX355 module has VCM, NVM and is on the second port of receiver. IMX319 module has NVM and is on the first port of receiver. Change-Id: I37c877df8062d5c79e25ed27775ab58e977555db Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com> Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com> Signed-off-by: Rajmohan Mani <rajmohan.mani@intel.com> Signed-off-by: Tomasz Figa <tfiga@chromium.org> Reviewed-on: https://review.coreboot.org/26283 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02nocturne: Do not set 4 LSB of SX9310 CRTL0Gwendal Grignou
These bits start the acquisition process. They should only be set by the driver. BUG=b:74363445 TEST=compile Change-Id: I9e10f5570ac82124f7f4b5cc7aaad27da0c578be Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-07-02nocturne: Fix casing for register definitionGwendal Grignou
Use lower case for hex values. BUG=b:74363445 TEST=compile Change-Id: I24afea58b1a791fac3c87ad397a696f7f6e0d127 Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/27264 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-07-02mb/google/poppy/variants/nami: Perform PL2 setting for sonaJohn Su
According to sona thermal table, PL2 need to check cpu id. And then set PL2 value. BUG=b:110867809 TEST=The thermal team verify OK Change-Id: I5759fb3c685e3d4eef1be054541f950843d19874 Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27260 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-06-29mb/google/poppy: Fix bytes 145-146 in nayna_dimm_NT6CL256T32CM SPDT.H. Lin
nayna/NT6CL256T32CM-H1 file change byte 145/146 to be"20" for JEDEC spec BUG=b:79443146,b:109708239 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test on R69.10825 with mosys Change-Id: Iadc820111f0aed34e5b46d7e23dff44cb5bb811d Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27275 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-29sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tablesArthur Heymans
Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. TESTED on Intel DG43GT: show correct PIRQ ACPI entries in /sys/firmware/acpi/tables/SSDT. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22981 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-29sb/intel/i82801ix: Use the common ACPI pirq generatorArthur Heymans
For this to work the northbridge and lpc bridge device need acpi_name functions. TESTED on Thinkpad X200, a valid PIRQ routing in SSDT in /sys/firmware/acpi/tables/SSDT Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/22980 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28nocturne: Fix uid and desc for sx9310Enrico Granata
This commit changes the uid and desc fields for the sx9310 entries in the devicetree to be unique, and correctly identify the position of the respective sensors. Change-Id: I501df7d3349fdebc9673c9815f5b1b2458abac6e Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/27248 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org>
2018-06-28mb/*/*/cmos.layout: Fix coding styleElyes HAOUAS
Change-Id: I4f82482595b0e6c6159c6e1c66158bc18b061f04 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27216 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-28mb/google/poppy/variants/nautilus: Use GPP_B20 to determine SKUSeunghwan Kim
We would use GPP_B20 instead of board id to determine nautilus SKU. BUG=b:80052672 BRANCH=poppy TEST=Verified the new coreboot could determine SKU correctly Change-Id: I1978b544eef7a184a3da191306ee32d862fa8c36 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/27220 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28mb/google/octopus: Create bobba variantJustin TerAvest
This creates a bobba variant for octopus. The devicetree overrides are copied from fleex, otherwise everything just defaults to baseboard settings. BUG=b:110781720 TEST=None Change-Id: Ic30c6b0d955ce26f4a9f40cd7fef1c429ab950fc Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/27223 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-28mb/google/poppy/variants/nocturne: Update TSR sensor infoSumeet Pawnikar
This patch updates TSR sensor info with appropriate names. Also, updates Charger effect with correct TSR sensor mapping. BUG=None BRANCH=None TEST=Build coreboot for Nocturne board. Change-Id: Ia3bbc78f8d823e88a91265e0d55c5ac2a4ea31a9 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27210 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2018-06-27mb/google/*: Add a few VBT filesMatt DeVillier
These files are directly extracted from the vendor firmware Change-Id: I1f05c913872c5d2d8c8279d89eac52fd4bf4e35e Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27222 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-06-26cheza: Fix Kconfig TPM itemsT Michael Turney
TPM config items added upstream before ready SPI/TPM is not functional on Cheza yet Change-Id: I302e00014dc31279fe2574765763ecdbf326b449 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/27213 Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26mb/google/octopus: Enable logging of EC wake sources in S0ixFurquan Shaikh
This change adds GSMI callback elog_gsmi_cb_mainboard_log_wake_source to enable logging of EC wake events in S0ix. BUG=b:79449585 TEST=Verified that S0ix entry/exit events are added to eventlog: =========== Lid open ================ 62 | 2018-06-25 14:02:36 | S0ix Enter 63 | 2018-06-25 14:02:56 | S0ix Exit 64 | 2018-06-25 14:03:26 | Wake Source | GPE # | 15 65 | 2018-06-25 14:03:32 | Wake Source | GPE # | 65 66 | 2018-06-25 14:03:37 | EC Event | Lid Open Change-Id: Icc8cd3624966ff66d2cf189871e452cf650cec40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27235 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-26opencellular/rotundu: Add mainboard supportHong Gan
Adds Open Cellular rotundu mainboard supports. Working: - 2x Ethernet support - MSATA support - CPU init - Memory init - USB support - EMMC but disabled Not working: - TPM support Create directory structure and Kconfig files for OpenCellular Rotundu and copy sources from intel/minnowmax. Change-Id: I391d4bdd485f4bf5396c764fe3f11d98369593e4 Signed-off-by: Hong Gan <hgan@fb.com> Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/22894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-26facebook/watson: Initial commitDavid Hendricks
This adds another camelbackmountain_fsp derivative, along with a .fmd file for the board. For now it's been tested to build and boot. Change-Id: I9e8804264967c19f6b51fc44575b0db36f600f88 Signed-off-by: David Hendricks <dhendricks@fb.com> Reviewed-on: https://review.coreboot.org/25884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-25mb/google/kahlee/variants/grunt: Select low-power mode for BayHub720Simon Glass
Put the PCIe clock pins in power-saving mode for the BayHub eMMC bridge to save power. This requires use of an additional register (Misc control register 2) and another bit in the existing 'protect' register. The naming of bit 0 of that register is incorrect, based on the latest datasheet (14 June 2018) so fix that too. BUG=b:73726008 BRANCH=none TEST=boot without this patch: iotools mem_read32 0xfed80e00 0x0046ffff With this patch: $ iotools mem_read32 0xfed80e00 0x00463fff Also see that the PCIe clock stops when eMMC is idle and can be started by starting disk activity. Change-Id: I5ad1467b2e2e151215d2dfd2ce48cd4a451fe480 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/26515 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-06-25mb/google/octopus: Use the newly added override devicetree featureFurquan Shaikh
Now that sconfig is able to support variant-specific override trees, this change updates octopus boards to use this feature. Following devices are moved from baseboard devicetree to variant specific devicetree: 1. Touchscreen 2. Trackpad 3. Digitizer 4. Audio codec BUG=b:80081934 TEST=Verified that the right devices show up in static.c for each variant. Change-Id: I8df0cdf4dbcd7613aa4ef4042c272eca2915da9e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27219 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25mb/google/poppy/variants/nami: Prevent leakage with touchscreen on PantheonCrystal Lin
We found GPP_C3 keeps high when system in S0ix mode. It caused 1.8V leakage. To fix this problem, add GPP_C3 into config for Pantheon Synaptics touchscreen. BUG=b:78436458 BRANCH=None TEST=Let DUT in S0ix mode and check GPP_C3 is normal. Change-Id: Idb2dab93178af1dae54265e49522b473b69a35af Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27177 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25mb/google/octopus/variants/baseboard: Update DPTF parametersSumeet Pawnikar
This patch updates DPTF parameters for Octopus baseboard. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I1456b7b9ee9e02491c66b0709c710e1a7ec08cc5 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/27027 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-25nb/lenovo/t400: Enable libgfxinitArthur Heymans
Change-Id: I243c22c83a5575c2e1500cc869c41691c4fba415 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27014 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-25mb/google/nami: Enable xDCIShelley Chen
This change enables xDCI controller on nami. BUG=b:110443736 BRANCH=None TEST=None Change-Id: Ieb63e0d65ac1a142c151a3f93afe306b80a5d99a Signed-off-by: Shelley Chen <shchen@google.com> Reviewed-on: https://review.coreboot.org/27181 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-25sb/intel/common/firmware: Enable me_cleaner for NehalemNicola Corna
Recent patches in coreboot have fixed the freeze issues related to the use of me_cleaner on Nehalem. However, at least on the Lenovo X201, with me_cleaner some PCIe devices (like the SATA and USB controllers) disappear. In particular, setting the AltMeDisable bit ("-S" or "-s" flag) makes them disappear completely, while unsetting it makes them disappear only during cold boots. This kind of behaviour was already observed by Youness Alaoui on the Purism Librem laptops ([1]), and it seems related to some required board-specific PCIe configuration in the ME's MFS partition. For this reason, on the Lenovo X201, "-w EFFS" has been added to the me_cleaner arguments, which whitelists the MFS-equivalent partition for ME generation 2. This fixes all the issues, and the PCIe devices work as expected. [1] https://puri.sm/posts/deep-dive-into-intel-me-disablement/ Change-Id: Ie77a80d2cb4945cf1c984bdb0fb1cc2f18e82ebc Signed-off-by: Nicola Corna <nicola@corna.info> Reviewed-on: https://review.coreboot.org/27178 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-06-23mb/asus/p8h61-m_pro: Add new mainboardAngel Pons
Tested with GRUB 2.02 as a payload, booting Arch Linux as well as Debian. This code is based on the output of autoport as well as other mainboards supported in coreboot already. Working: - Serial port I/O - S3 suspend/resume. Untested with SeaBIOS since it failed to resume on a similar board. It is likely to be due to low memory corruption, but I have not worked on it. - USB ports and headers - USB3 ports attached to the ASM1042 controller. SeaBIOS can boot from them, and it is likely GRUB can detect devices on those ports as well. The chip has a small SPI flash nearby, which seems to hold an Option ROM. - Gigabit Ethernet - Integrated graphics (libgfxinit) - VGA BIOS for integrated graphics init - PCIe x16 graphics - PCIe x1 - SATA controller - Hardware Monitor - Fan Control (fancontrol on linux works well) - Native raminit - flashrom, using the internal programmer. Tested with coreboot, as well as with the vendor firmware. - NVRAM settings. Only debug_level has been tested. Untested: - DVI port. It can detect a "fake" display, that is, an EEPROM connected to the DVI port. Thus, gma-mainboard.ads has been setup accordingly. - PS/2 port. - Audio: Only rear output (green) has been tested. - EHCI debug. - Parallel port header. - Non-Linux OSes - ACPI thermal zone and fan control (probably not working) Not working: - Booting from devices attached to the ASM1061 controller. Devices on ports work fine once Linux has loaded. - Any SATA devices with Tianocore (payload issue) Change-Id: I7e89ebe43a2e1ff0308f4876e98bbf2f5a0d85f2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/26419 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23mb/google/poppy/variants/atlas: Add two new Samsung memory optionsCaveh Jalali
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table BUG=b:110498646 BRANCH=none TEST=none Change-Id: Iddacdf1e1d0e2bae0c6168c86e54f5f602cd9d19 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27184 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-23mb/google/poppy/variants/atlas: add GPIO for bluetooth enableCaveh Jalali
This configures a GPIO pin for enabling/disabling bluetooth on the next version of the atlas board. The default is for bluetooth to be enabled at this point. BUG=b:110614620,b:110613353 BRANCH=none TEST=none Change-Id: I4ba940e89b1dc03548b7ab44b8f84dc9a3097acb Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27185 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-22mb/google/poppy/variants/nami: Fix non-working thermal sensor QT2 PSVJohn Su
Modify DPTF TRT parameters to solve thermal sensor QT2 PSV problem. BUG=b:109941652 TEST=The thermal team verify OK Change-Id: Id9d39d8282712a0341fea10f74c0e40bb1ac9d7c Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22mb/google/octopus: Update GBB_FLAG_DISABLE_EC_SOFTWARE_SYNCFurquan Shaikh
Move GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC under each variant config and select it for bip and fleex only. Functional change in this CL is that EC SW sync will be enabled for phaser. BUG=b:110523400 Change-Id: If6f37c6b2ee71130b9ed5b10ce92fb23fa1c39fc Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/27179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-06-22mb/google/poppy/variants/nocturne: Hook up the SX9310 proximity sensor.Enrico Granata
Change-Id: I7358ee34df873098a86d692cc8a909b0ec5023a8 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/27172 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-22soc/intel/common/block/cpu: Add option to skip coreboot AP initSubrata Banik
SoC users from IOTG team is looking forward for a solution to skip coreboot AP initialization flow and make use of FSPS-UPD to perform AP reset. TEST=Assign use_fsp_mp_init=1 to ensure coreboot is not bringing APs out of reset. Change-Id: Ibc8cd411e802fb682436a933073922b2693ba994 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21Revert "sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location"Arthur Heymans
In the end it does not look like RCBA register offsets are fully compatible over southbridges. This reverts commit d2d2aef6a3222af909183fb96dc7bc908fac3cd4. Is squashed with revert of "sb/intel/common: Fix conflicting OIC register definition" 8aaa00401b68e5c5b6c07b0984e3e7c3027e3c2f. Change-Id: Icbf4db8590e60573c8c11385835e0231cf8d63e6 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/27038 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-06-21google/lars,lili: Add SPD mapping for Hynix 8GB configren kuo
Upstreaming Chromium commit 0bc6c43: Lili: Update Memory IDs TEST=Build and boot up on lili board Original-Change-Id: I6da1e97820b1bf2e751102384eed07236143fe2b Original-Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/956782 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: Icf6588582da3b4a7861bced539d51a914b011dc4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/27135 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/lenovo/t520: Add Dual Graphics CMOS supportNico Rikken
Adds the CMOS option for Dual Graphics, as is present in more Lenovo models already. Enabling this option ensures that the NVIDIA GPU is powered. More PCI devices can be observed when activating this setting. It was verified on a W520, also by loading a VGA option ROM and achieving a working Dual Graphics system. The CMOS default has been kept to 'Integrated Only', as the usage of Dual Graphics requires an option ROM and drains the battery more quickly. Change-Id: I41ccabd4554ca019684edd6f8b1c23679212c59f Signed-off-by: Nico Rikken <nico@nicorikken.eu> Reviewed-on: https://review.coreboot.org/26114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-06-21mb/google/poppy/variants/nocturne: add two new memory optionsNick Vaccaro
- add K4E6E304EC-EGCF and K4EBE304EC-EGCF to memory strapping table - add SPD files for K4E6E304EC-EGCF and K4EBE304EC-EGCF BUG=b:110277021 BRANCH=none TEST=none Change-Id: If1322311bd91842d6d32725822d91fd6d9e8077c Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27123 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/nocturne: Update Slave Addresses of Max98373 Amp'sSathyanarayana Nujella
When played Left Only Audio and Right Only Audio, we observed that Audio got swapped. Left Data played on Right Speaker and Viceversa. This patch fixes the above issue. BUG=b:73635449 TEST=Play Left only & Right only Audio and cross check Audio. Change-Id: Ie9c417ad0634a76fc8a4126ee75886603f1b3da0 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-on: https://review.coreboot.org/27167 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-06-21mb/google/poppy/variants/nocturne: disable p-statesNick Vaccaro
Set register speed_shift_enable=0 in devicetree to disable p-states in coreboot as a temporary workaround for an SoC hang. BUG=b:79666828 BRANCH=none TEST="emerge-nocturne depthcharge coreboot chromeos-bootimage", flash spi image onto nocturne, boot to kernel and verify device stays alive and responsive for several minutes without locking up. Change-Id: I71ed4c80c109b28ffa85d48338ce3a62396d272e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/27156 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-06-21mb/google/poppy/variants/atlas: enable camera power and release resetCaveh Jalali
This is a temporary hack to test camera presence before we have full camera support implemented. Basically, we can now probe the camera over i2c to verify that it's connected and the camera LED turns on. BUG=b:80106316 BRANCH=none TEST=camera LED comes on and camera can be probed over i2c. Change-Id: Ibaabf6c6f6a1dabaddd2fc47c820e090ca5984a5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/27128 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-17 22:26:40 +0000