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Add VBT from vendor firmware v5.24 and configure display outputs in
devicetree.
TEST=Boot TianoCore UEFIPayload and notice the UEFI Shell on the
connected display via HDMI or DisplayPort on rear panel.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: Ide560ade5e29844c2f4310639fe5b76ba91865be
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63507
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Tested with 4x KINGSTON KF3600C17D4/8GX DIMMs.
TEST=Include the microcode from vendor firmware and FSP blob from
Intel R&DC. Boot the platform and see ramstage is executing.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I98b9c77d791d18640cb05c133cb0bf14ad22dcdb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63503
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Use USB4 fw_config to enable TBT PCIe RP0.
BUG=b:237619214, b:237623610
TEST=emerge-brya coreboot chromeos-bootimage
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ie3e51a0f30e0c9d20127c017436813d4ede95639
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65696
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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On nissa, WLAN should be a wake source, so don't put it into D3cold
during suspend.
BUG=b:233325709
TEST=Wake-on-WLAN works on nereid
Change-Id: Iddd5fa8db05b85d2c799f679d664876109187d0c
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65688
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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This patch enables Cnvi BT Audio Offload feature and also
configures the virtual GPIO for CNVi Bluetooth I2S pads.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Iffbd08351d083d2b550f309994af931bceb257d9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65670
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Configure the unused virtual CNVi BT GPIOs to NC since we
are using BT over USB mode for Nissa.
BUG=b:233834597
TEST=Verified BT offload feature on Nivviks P1.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Id84823b9ad921ebd7ff773d6cce581563613745f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65669
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Disabling the Package C-state demotion feature for nissa baseboard
as a work around to the S0ix issue and also this doesn't have any
impact on the power and performance measured and verified by the
PNP team.
This feature will be enabled after its functionality is verified with no
issues and also based on its impact on PNP.
BUG=b:235005582
TEST=Boot and verify that S0ix issue is resolved.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I4d586b962c27b86ee75651dcd655bc0868504646
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65664
Reviewed-by: Varshit B Pandya <varshit.b.pandya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Based on latest schematic to update the PCIE and USB setting.
BUG=b:237659398
BRANCH=firmware-brya-14505.B
TEST=emerge-ghost coreboot
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I97989b7a8d9104379ffb0b454d7248d49855f680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65584
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
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DPTF Policy and temperature sensor values from thermal team.
BUG=b:237640264
TEST=USE="project_crota emerge-brya coreboot" and verify it builds
without error.
Signed-off-by: Johnny Li <johnny_li@wistron.corp-partner.google.com>
Change-Id: I43340bd1acfe6ec2036ea80339dbf896615a456a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65563
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The LabTop was renamed to StarBook since the release of the Mk V.
This change keeps the directory name more relevant, as there are
more boards using the name StarBook.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I3513fb56c1adf663ed7bcdade2cc52cd8c0d6f4b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65640
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Change-Id: I76e4438dea6a7fcce06211af808eee51465f19c5
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64770
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I4fd7f86a61d1a1a8133a633eb257275222f27af9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64769
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I65f8e6860a7f734a7d2b8c0055cb18d851f38ad0
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64768
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I62d8374eb7c2499d34c3f43c9f7fd01caaa3e2f4
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64767
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: Ia8a78e9947466e88fb9abf1b91ef21ce763240c1
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Change-Id: I25d0f5a97ec5dd023e2acb458de1b20427fe353e
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64761
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Enable SaGv support for Kinox
BUG=b:238153479
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Id4646f1621a414a1ec4e272c826b0baea2bb4e19
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65340
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This contains the following commits:
* d55c315 mb/starlabs: Remove padding from logo
* 6412d38 mb/starlabs/starbook/cml: Update EC from 1.03 to 1.07
* fb72ac5 mb/starlabs/starbook/tgl: Update EC from 1.00 to 1.03
* cda5eaa mb/starlabs: Rename labtop to starbook
* f16020a Revert "soc/mediatek/mt8186: Update SPM firmware to
pcm_suspend_v0215…
This also changes starlabs/labtop Kconfig to use the new paths for
the EC binaries from the above commits.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I83143118af422276ee335ad4ef9eca76f54a9fc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65634
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Modify ddi_ports_config based on schematic.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_3 = HDMI
BUG=b:237419696
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I7c0458f0dbd4637b91af9e01664073e1f8a7a614
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65660
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Currently the EC's MKBP interrupt line is programmed as dual-routed to
both SCI and IOAPIC. The brya EC will pulse the MKBP GPIO and also
send a host event when there is an MKBP event for host to service.
This causes an extra SCI to be generated, and the kernel will respond
to each MKBP event with an extra unnecessary host command. Changing
the pad configuration for the MKBP GPIO to APIC only fixes this issue.
BUG=b:236706977
BRANCH=firmware-brya-14505.B
TEST=excess GET_NEXT_EVENT host commands are gone from EC log
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ic7dd596987f6d34c69d46674bdd07785235e2d4c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65480
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The EEs have observed the ramp down delay on this signal in more detail
and 40 ms can still meet the sequencing requirements.
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I49ef801f7a3fd7945ded63da1399eaf57fd6aef0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65581
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Since the GPU will be left powered on, the kernel has the opportunity to
save context and this method to save the BARs is not required.
BUG=b:233959099, b:236289930
TEST=build
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I19cf12426361a53e3672c1e05aa6d68d5dd6627c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65208
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Initialize NOR-Flash in the bootblock.
TEST=read nor flash data successfully.
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I8ee24b5b24643bce57eb29682d6d0234a6fe8641
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65622
Reviewed-by: Yidi Lin <yidilin@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Configure TDC current for VR domains.
+-----------+-------+-------+---------+-------------+----------+
| Setting | AC LL | DC LL | ICC MAX | TDC Current | TDC Time |
| |(mOhms)|(mOhms)| (A) | (A) | (msec) |
+-----------+-------+-------+---------+-------------+----------+
| IA | 2.8 | 2.8 | 80 | 43 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
| GT | 3.2 | 3.2 | 40 | 23 | 28000 |
+-----------+-------+-------+---------+-------------+----------+
- IA TDC current from 20A to 43A.
- GT TDC current from 20A to 23A.
- Others comes from 'commit c6d716694272 ("soc/intel/alderlake: Configure the SKU specific parameters for VR domains")'
BUG=b:237230877
TEST=Build and boot to Chrome OS
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ie9cf8975309b57b4189e2b50f37bd61ac0105e14
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65659
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable DPTF oem_variables and override based on charger type.
BUG=b:230803675
TEST=1. With 90W adapter, check ACPI object ODVX and oem_variable[0]=1
Name (ODVX, Package (0x06)
{
0x00000001,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
})
2. With 65W adapter, check ACPI object ODVX and oem_variable[0]=0
Name (ODVX, Package (0x06)
{
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000,
0x00000000
})
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: I78929ecbc9db56aa234b3f46c641d1f2f3b7cba8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65251
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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agah proto boards with i7 silicon face boot issues due to high power
consumption during MRC training.
This patch is a temporary WA to run in SAGV disabled mode while the
thermal issue is being investigated.
BUG=b:234402102
BRANCH=firmware-brya-14505.B
TEST=Build CB image and boot on agah board.
Change-Id: I431d233b23fb4f5c68117ea380fdec5646b88346
Signed-off-by: Anil Kumar <anil.kumar.k@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65300
Reviewed-by: Selma Bensaid <selma.bensaid@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Configure some basic FSP parameters in devicetree for
to allow for booting an OS.
Change-Id: Iff227c70d0155ac27d6ffa50a069d154bb7fce3c
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63499
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Based on the output of:
- inteltool from CB:63374
- intelp2m from CB:63403
TEST=Build coreboot binary for msi/ms7d5 and boot the board.
Change-Id: If37eaf875f8fcfc64299227744a8c40d304a0214
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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Initial mainboard code MSI PRO Z690-A DDR4 WIFI. The platform boots up
up to romstage where it returns from FSP memory init with an error.
What works:
- open-source CAR setup
- NCT6687D serial port with TX pin exposed on JBD1 header
- SMBus reading SPD from all 4 DIMMs
This board will serve as a reference board for enabling Alder Lake-S
support in coreboot. More code and functionalities will be added in
subsequent patches as src/soc/alderlake code will be improved for
PCH-S.
TEST=Extract the microcode from vendor firmware and include it in the
build. The platform should print the console on the serial port even
without FSP blob.
Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5df69822dbb3ff79e087408a0693de37df2142e8
Signed-off-by: Igor Bagnucki <igor.bagnucki@3mdeb.com>
Signed-off-by: Michał Kopeć <michal.kopec@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63463
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
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There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ia087b62904fd515bf73960a188b225f1d49197dd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65646
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Alder Lake-N based nissa boards use compressed ME_RW blobs for CSE FW
Update. Choose SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE Kconfig to perform
CSE FW sync in ramstage.
BRANCH=firmware-brya-14505.B
TEST=Perform CSE FW upgrade/downgrade on nivviks.
Change-Id: I00630096c52434f44914f3ae82ff043ecf77b80d
Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65368
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=build passed.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I9f0fcf52b6b7d622e4fd182e007de6401856c7fb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65645
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Set tcc_offset value to 0 in devicetree for Thermal Control Circuit
(TCC) activation feature. This value is suggested by Thermal team.
BUG=b:236294162
TEST=emerge-brask coreboot
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: I8d4c631e07873923226683c8aa0cf36cb872e2d4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65448
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I068c6e46d85d869afc72280509a03d5ff682b917
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65618
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Define the CCD (aka "Webcam") USB port in the devicetree as
it is used in multiple places. It is used in devtree to
disable it based on the CMOS setting "webcam", and in the
devicetree to configure the port tuning.
This also corrects the port that is disabled on CML, from
usb2_port[6] to usb2_port[3].
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I16e368fc7965f978f2302633122ba63038603c1e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64704
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Group the USB ports by hardware ports, rather than separate USB 2.0 and
3.0 interfaces.
This also removes usb3_port[2] as it is not connected and fixes the labelling of usb3_port[0] and usb3_port[1].
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I7923fc00c36687a7f89d863eb0ea4e01a036502d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64703
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Update the Vbt to disable the fixed mode feature, to allow for
bootloader resolutions higher than 1920x1080.
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Ibd9850dcaef97a58c6694ee594014e9f16ae7f96
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65337
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ieed2d40b0222d8c8c193e0590131f83a5d96add9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65598
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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There is a new ground rule, variant should honor baseboard lock gpios.
Thus, lock the gpio which is locked in baseboard.
BUG=b:216671701
TEST=check gpios are locked in pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I61931b0b2f1f936a672e72c98b83d66ba0059bf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65597
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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In reality the expression should not overflow as the value
fits in 32 bits.
Change-Id: I50d83dce25a4d464e1c979502c290d8ecd733018
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65613
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237725329
TEST=Verify the build for crota board
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: I6dde74c098ba57b7cd66ce7b9ee941b8961ad20c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65594
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Cyan Yang <cyan.yang@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Modify GPIOs according to SOC_GPIO_Table_0629.xlsx.
- GPP_A21 from TCP_DP1_CTRLCLK to NC
- GPP_A22 from TCP_DP1_CTRLDATA to NC
- GPP_E20 from NC to TCP_DP1_CTRLCLK (Native Function 1)
- GPP_E21 from NC to TCP_DP1_CTRLDATA (Native Function 1)
BUG=b:237468533
TEST=emerge-brask coreboot
Change-Id: I8e7d343731efbfc04304d52a3493ab30b8a739b0
Signed-off-by: EricKY Cheng <ericky_cheng@compal.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65552
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
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There is a requirement that the TPM RST signal cannot be asserted by
software. On nissa this is PLT_RST_L, so lock this pin to prevent it
being reconfigured as a GPIO.
BUG=b:216671701
TEST=Try to change GPP_B13 from the kernel:
$ echo 677 > /sys/class/gpio/export
$ echo out > /sys/class/gpio/gpio677/direction
$ echo 0 > /sys/class/gpio/gpio677/value
$ echo 1 > /sys/class/gpio/gpio677/value
GSC console doesn't show "PLT_RST_L ASSERTED" / "PLT_RST_L DEASSERTED"
Change-Id: Id5d64b4b028e4f63c4acb05cd8632d0642866688
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65591
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add G2 touchscreen support for craaskvin.
BUG=b:235919755
TEST=emerge-nissa coreboot
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Change-Id: I7ade3ac1d135b8b21b09ef335ab7b30ae7a5e2c8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65195
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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Set the GPIO configuration of joxer
BUG=b:237628218
TEST=USE="project_joxer emerge-nissa coreboot"
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: I1f7529342fc0800878f875d3641a2f93fbe6009a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65553
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This patch uses ACPI _PLD macros to add custom values for USB ports.
C0 A2 A3
+----------------+
| REAR |
| |
| |
| |
| FRONT |
+----------------+
A1 A0
BUG=b:232419500
TEST=emerge-brask coreboot
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I5ada4e9b25102a9cfd3b02a2abcd956f6cbc5619
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65544
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Won Chung <wonchung@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Branding changes to unify and update Chrome OS to ChromeOS (removing the
space).
This CL also includes changing Chromium OS to ChromiumOS as well.
BUG=None
TEST=N/A
Change-Id: I39af9f1069b62747dbfeebdd62d85fabfa655dcd
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65479
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Create PSP NVRAM and RPMC NVRAM region with size 128K & 64K
respectively, which are supported region by the PSP.
moved CBFS up due to build error, CBFS need not to be at the end the flash for amd Zen cpu.
Change-Id: Ide778c61a755697c1bef1eaa87f2976d8ff12eb6
Signed-off-by: Ritul Guru <ritul.bits@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65341
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for kano board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I19430a68e1e847e71382781563200a4c88f37a59
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65107
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
|
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Fill GPIO table for Pujjo.
BUG=b:235774770
TEST=emerge-nissa coreboot
Signed-off-by: leo.chou <leo.chou@lcfc.corp-partner.google.com>
Change-Id: I307b8460632f1feae9591200057c0e6471cbab24
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65104
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This updates the ACPI locations of Type-C ports.
BUG=b:232806406
TEST=none
Change-Id: Ia15e09a58c731a1364a994fadf8df39115fbe7c4
Signed-off-by: Caveh Jalali <caveh@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65497
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Add mainboard folder and drivers for new reference board 'Geralt'.
TEST=saw the coreboot uart log to bootblock
BUG=b:233720142
Signed-off-by: Bo-Chen Chen <rex-bc.chen@mediatek.com>
Change-Id: I5e437d46097369bef535ff64e6a693b7cf67f2f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65586
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@chromium.org>
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This patch ensures AP UART messages are coming over LPSS UART 0 hence,
select required kconfig and program both early and late UART
RX/TX GPIOs accroding to the rex schematics dated 06/27.
BUG=b:224325352
TEST=Able to see AP UART log over LPSS UART0.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I7daa8200d1a7cf825dfdfed538573efd57ab2d97
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65454
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add the support LP5 RAM parts for rex:
DRAM Part Name ID to assign
MT62F512M32D2DR-031 WT:B 0 (0000)
BUG=b:224325352
TEST=emerge-rex coreboot
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ibcd25ae80d625b623b9a78ff2cd4447e85831cc0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65476
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add memory init with placeholder to fill in required memory
configuration parameters. DQ map and Rcomp can be auto probed by
the FSP-M hence, kept it as default.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Able to boot till FSP-M/MRC using MTL simics.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I5baa87411c28a20602eb5a7077f00664ccab3ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64850
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add SMI handler implementation to manage power cycle,
power state transition and Chrome EC events.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I10aab8257fce92aaf913a53c0c9fb6c1a4f5dea6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64623
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable building for Chrome OS and add associated ACPI configuration.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I75cb2d30d699166a056ed9d3c0779816b733b0d2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64621
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Perform EC initialization in bootblock and ramstages. Add associated
ACPI configuration.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I2ea934f32b34bc43650e20dd2736f4e652004dc2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64622
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Enable ACPI configuration and add DSDT ACPI table.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8374a9b528f8dff4e23b6bdb4d1368dfd2c79b8e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64620
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add stubbed out GPIO configuration and perform GPIO initialization
during bootblock, romstage and ramstage.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I51426f9557dafc357fc54a971b6f76fac5323e0a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64593
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add entry point stubs of each stage for Rex. More functionalities will
be added later.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I2310e58ab92bdb0ce86a9f7284cc0b3e04a2889f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64591
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Add 32MB flashmap descriptor as below:
Descriptor Region -> 0 - 0x3fff (~16KB)
CSE Partition -> 0x4000 - 0x8fffff (~9MB)
BIOS Region -> 0x900000 - 0x1ffffff (23MB)
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Ia5ced770bb02c11a9ab39837e66562d2ee22b6e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64590
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
|
This commit is a stub for rex, which is a an Intel Meteor Lake-P
reference platform.
BUG=b:224325352
TEST=util/abuild/abuild -p none -t google/rex -a -c max
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I46bd8d47b370cacbe0a09bbeaccacf7f1d51d8b6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62969
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for primus board. Please refer Intel doc#723158 for
more information.
BUG=b:237421399
TEST=Verify the build for gimble board
Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Ie66c9679c985215ad7f1a5ae76560b839ea95702
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65474
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: Ifb47e0d1d1b9c01c1332af4135f5578160c491a8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55924
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
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Kingler and Krabby's rev 0 boards both have Cr50 instead of Ti50. In
order to support them with the new firmware where TPM_GOOGLE_TI50 is
selected, use the board rev to determine the EC-is-trusted logic.
BUG=b:237355198
TEST=emerge-corsola coreboot
BRANCH=none
Change-Id: I7797eafaa7a35355d241c4ea425a4716a35a7817
Signed-off-by: Yu-Ping Wu <yupingso@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65472
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
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CB:63368 added a workaround of driving EN_PP3300_WLAN_X low in bootblock
to prevent a kernel crash on warm reboot. The crash has been fixed in
the kernel, so remove the workaround.
Kernel fix:
https://chromium-review.googlesource.com/c/chromiumos/third_party/kernel/+/3463465/
BUG=b:225261075
TEST=Wifi works on nereid, warm reboot doesn't crash the kernel
Change-Id: Idb5547e65ea934954326fcc740b14a83c939432e
Signed-off-by: Reka Norman <rekanorman@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65449
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
|
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Fixes a bug in Makefile.inc.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2664df961a1fc0cd904a5e742face20c3fc8c3c9
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65450
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Debug FSP is ~850KiB larger than release FSP and we don't have
sufficient space for nissa flash layout.
Remove RW_LEGACY and split them into RW_SECTION_A/B so we can have a
room for it.
Note: This fmd will only used for internal testing/debugging and not for
the firmware in released devices.
BUG=b:231395098
TEST=build with CONFIG_BUILDING_WITH_DEBUG_FSP
Signed-off-by: Kangheui Won <khwon@chromium.org>
Change-Id: Idb17f003285575e80feb86bb292b95daf0f5b3b3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65467
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
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Disabling the ASPM for I225V will cause I225V suspend fail, so remove ASPM_DISABLE for I225v.
BUG=b:235565637
TEST=emerge-brask coreboot and check LAN_I225V sku can boot into OS.
Signed-off-by: Raihow Shi <raihow_shi@wistron.corp-partner.google.com>
Change-Id: Id4505a713a3d92cb66c189cc2963111b6e90f092
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65382
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add fingerprint device and select UART_ACPI driver.
Disable FPMCU until the proper boot segment initializes it.
BUG=b:228271993
BRANCH=NONE
TEST=Can add fingerprints and unlock the device using them.
Signed-off-by: Moises Garcia <moisesgarcia@google.com>
Change-Id: I71e1c7d654395284cdec43bb6e5f581e546da36a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65299
Reviewed-by: Jon Murphy <jpmurphy@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bhanu Prakash Maiya <bhanumaiya@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
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DDR interfaces emit electromagnetic radiation which can couple to the
antennas of various radios that are integrated in the system, and cause
radio frequency interference (RFI). The DDR Radio Frequency Interference Mitigation (DDR RFIM) feature is primarily aimed at resolving narrowband RFI from DDR4/5 and LPDDR4/5 technologies for the Wi-Fi high and ultra-high bands (~5-7 GHz). This patch sets CnviDdrRfim UPD and enables CNVI DDR RFIM feature for Nivviks variant.
Refer to Intel doc:640438 and doc:690608 for more details.
BUG=b:237238786
BRANCH=None
TEST=Build and boot Nivviks.
- Verified that Wifi DDR RFIM Feature is enabled and DDR RFI table can be modified.
Signed-off-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.com>
Change-Id: Iea5c6e0c404efb8231321701ea9282347e01f75d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65254
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Based on latest schematic:
1. Update devicetree for USB port description
2. Add touchscreen ILITEK, amplifier ALC1019, codec ALC5682
3. Configure GPIO table to reflect that
4. Remove APW8738BQBI IC so set "disable_external_bypass_vr to "1"
BUG=b:235303242, b:236791101
BRANCH=dedede
TEST=build
Change-Id: I38c8c5b913013d818ac6a26284184c9decdd9f4e
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65079
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Kernel driver will en/disable the IRQ when suspend/resume. If lock
the pin, driver can't change the status which causes the unexpected
behavior. Device will wake when insert the pen. This is workaround
until we figure out the correct setting for driver.
BUG=b:233159811
TEST=Pen garage wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: Ifc7b1e52a24c0e7bd54664d59870cb09536ef868
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65380
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:231690996
TEST=gpios are the same in kernel pinctrl dump.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I67a466fac478b2a3a682451174fbdcdd67816769
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64714
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
|
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Based on schematic and gpio table of pujjo, generate overridetree.cb
settings for pujjo.
BUG=b:235182560
TEST=FW_NAME=pujjo emerge-nissa coreboot chromeos-bootimage
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Change-Id: I47b10d03798004d1f3e398070acb2cbad46900b7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65260
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
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This change sets DRIVER_TPM_I2C_BUS to the i2c 1 bus for TPM for the
skolas4es variant.
BUG=b:230773725
TEST=None
Change-Id: I12b05cdacdd26bfffff47b7a3fb127aa7778f15d
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65493
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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`chipset_lockdown` is no longer configured in this devicetree.
Change-Id: Iaaacd471ab873f150d7a74bba612130c33641c64
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Benjamin Doron <benjamin.doron00@gmail.com>
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The temperature values were taken from guybrush as a starting point for
skyrim.
BUG=b:230428864
TEST=Boot skyrim to OS and verify thermal zones are populated and
working in /sys/class/thermal/
Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com>
Change-Id: I6669b32f5e3dd63c6523f74166089eb4eb2d7848
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65457
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
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Follow google stylus spec. The Stylus-Present GPIO MUST be a wake
pin that interrupts the system in active operation when the stylus
is removed. After confirmed with the owner, the expect behavior is
only wake when eject the pen.
BUG=b:233159811
TEST=EC wake event work as expected.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I7a82e5e8935c9ea27e923661f66809e9169bc86a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65379
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Add MIPI WFC based on schematics
BUG=b:236576117, b:235446911
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I85bd2ba187729a55c00369b218ca0414e0162b9e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65334
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Follow latest schematic to modify SPI flash to 16M.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I56be68b962c38d3f885dcf25a0251b8d9ab6ff3f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65446
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: John Su <john_su@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
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Modify ddi_ports_config based on schematic Kinox_SCH_20220602.pdf.
DDI_PORT_A = DP
DDI_PORT_B = HDMI
DDI_PORT_1 = Type-C DP
DDI_PORT_2 = DP or HDMI
BUG=b:233338341
TEST=Boot to Chrome OS and check all display port working
Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com>
Change-Id: Ib2dbb34af1f85585b77638710d3799520c3f016f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65336
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ricky Chang <rickytlchang@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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mc_apl7 does not use security features like VBOOT and TPM.
Test: flash mc_apl4 mainboard and ensure the disabled features via log.
Change-Id: I16683b92deb047208848b69c5aa79dc4212ce930
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65284
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Add a new board 'Tentacruel', and enable SDCARD_INIT for it.
BUG=b:234409654
BRANCH=corsola
TEST=none
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: Ia10efeead575b4e193a73562275a78839415a706
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65192
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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In order to improve gpio merge mechanism. Change iteration override
to padbased table override. And the following patch will change fw
config override with ramstage gpio table override.
BUG=b:231690996
TEST=check gpios in pinctrl are the same.
Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I3d0beabc2c185405cb0af31e5506b6df94e9522c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64713
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Change-Id: Ic31eb81bc98fd94877a51ebf44cfb2c69e4db0ae
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55923
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable caching of memory training data for recovery as well as normal
mode. We had HAS_RECOVERY_MRC_CACHE selected in the sc7280 Kconfig,
but never allocated a RECOVERY_MRC_CACHE in the herobrine fmap so it
never worked. Adding RECOVERY_MRC_CACHE and also removing
RO_DDR_TRAINING, RO_LIMITS_CFG, RW_LIMITS_CFG entries which have been
deprecated.
BUG=b:236995289
BRANCH=None
TEST=run dut-control power_state:rec twice and make sure that
DDR training doesn't run on the second boot.
Change-Id: I39ac7eca4ae94075874324b13c69eef59522e3c5
Signed-off-by: Shelley Chen <shchen@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65370
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
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We have clarified the powerdown sequence with Nvidia, and the EEs have
come up with this modified sequence which still meets the requirements
from the hardware design guide.
BUG=b:233959099
TEST=Verified by ODM and EE
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: I37715165ab488f994c825fb9ff532ebf8d7f4cb0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65182
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Robert Zieba <robertzieba@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for osiris board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for osiris board
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: Ia30a7b915df14c91a2526dca3e374436da286b7a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65324
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Update override devicetree based on schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I2986ae6fd1f51efc6b9bb18ff2b7186357e55fcf
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65332
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Configure GPIOs according to schematics.
BUG=b:236576117
BRANCH=None
TEST=emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I8c4347fcc975ed994261c7738e5ef811a12e4b0d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65288
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
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Base on bernadino 14 adl-p 20220531.pdf, configure GPIOs
according to schematics.
GPP_B2 => BYPASS_DET
GPP_F19 => FP_USER_PRES_FP_L
BUG=b:234384954
TEST= USE="project_crota" emerge-brya coreboot
Signed-off-by: Terry Chen <terry_chen@wistron.corp-partner.google.com>
Change-Id: Ic2e7ecc34912f07463e0025787fdf59c7602e40b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65309
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This patch ensures google/volmar eMMC SKU has advanced PM support
enabled.
BUG=b:235915257
TEST=Able to boot to eMMC SKU to ChromeOS.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I3e2883d894d2ca7f810f4b72af1c12037c8fdabc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65244
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
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Adjust sensor trigger point and fan duty according to thermal team
tuning results.
BRANCH=brya
BUG=b:215033682
TEST=Built and tested on taniks board
Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com>
Change-Id: I8135684d471fdcfdbbe2f1bc5455902d56bb71de
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65287
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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The patch disables PCH USB2 Phy power gating to prevent possible display
flicker issue for kano board. Please refer Intel doc#723158 for
more information.
BUG=None
TEST=Verify the build for volmar board
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Change-Id: I4d12f7214a306ded54b4536a27fe0fb7f3c33b8b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65307
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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This patch adds a new mainboard variant called mc_apl7 which is based
on mc_apl4. So far only the names have been adjusted with no further
changes. Following commits will introduce the needed changes for this
mainboard variant.
Test: build mc_apl7, flash to mc_apl4 and compare log level 8 output
Change-Id: Ie9f2f5c29d071de442f8f3e3eaf4b3c2a6b8920f
Signed-off-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65283
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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There is an existing issue for nissa boards where wake up from
RTC wake is not working during suspend_stress_test.
This issue was root caused to the patch which was setting GPE_EN
bits for the GPIOs before locking.
Reference: https://review.coreboot.org/c/coreboot/+/64089
Later issue was found to be with GPP_F14 configuration for nissa
boards. When coreboot skips setting GPE_EN bit for GPP_F14, RTC
wake works properly. Another way to make it work is to skip locking
GPP_F14 GPIO to allow kernel to configure it properly.
This patch skips the locking for GPP_F14 to allow kernel to
configure it later. This fixes the issue of RTC wake not working.
Note: This patch provides workaround for the existing issue and
BUG will be closed once actual reason is identified and proper
fix is available.
BUG=b:234097956
BRANCH=None
TEST=RTC wake works on Nivviks board with the patch.
Change-Id: Ie8091ab8acf2b3f064cb79bdf4700f6b4c1674a5
Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65086
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
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Add the support RAM parts for Xivu.
Here is the ram part number list:
DRAM Part Name ID to assign
MT62F1G32D4DR-031 WT:B 0 (0000)
MT62F512M32D2DR-031 WT:B 1 (0001)
H9JCNNNBK3MLYR-N6E 1 (0001)
K3LKBKB0BM-MGCP 2 (0010)
BUG=b:236576117
BRANCH=None
TEST=Use part_id_gen to generate related settings and
emerge-nissa coreboot
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I02866f7dcdc70d1051d187fdda30e04bb654ece3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65252
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Frank Wu <frank_wu@compal.corp-partner.google.com>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Create the xivu variant of the nissa reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:235025984
BRANCH=None
TEST=util/abuild/abuild -p none -t google/brya -x -a
make sure the build includes GOOGLE_XIVU
Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
Change-Id: I12341a2414e58ebc1c22429d35a03afef27adace
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65235
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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