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2021-04-28mb/google/dedede/var/metaknight: Define stop_gpio for goodix touch screenDavid Wu
Define TOUCH_RPT_EN pin(GPP_A11) as the stop_gpio for the touch screen and control TOUCH_RPT_EN pin to keep low. BUG=b:176253069 TEST=Build and boot metaknight to OS, confirm GPP_A11 pin keep low. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I816e29eccac0f1935aeaa3b94c907870e2451e3a Reviewed-on: https://review.coreboot.org/c/coreboot/+/52653 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-28mb/google/brya: remove WLAN PCIE settingEric Lai
Brya uses CNVi WiFi module, PCIE setting is not required. TEST=WiFi is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib82c98905ed3b30075e9830c1a2638817f140abe Reviewed-on: https://review.coreboot.org/c/coreboot/+/52623 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-28mb/amd/majolica:Set IRQ for GPIO controllerJason Glenesk
AMD GPIO driver will not load if IRQ is not set. As a consequence, it does not clear the interrupt when waking from S0i3. BUG=178728116 TEST=Perform 2 S0i3 cycles, confirming second cycle does not return instantly due to first interrupt not being cleared. Change-Id: I3072263e8e68f939a47ed4125444c60133087824 Signed-off-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52682 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-28mb/prodrive/hermes: Drop Vref configuration for older boardsPatrick Rudolph
Drop Vref verbs from the baseboard table as it's not required for Rev. 3 and earlier. Change-Id: I41c207f97dad6c9107c1999eb46d2d6304a6c217 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51919 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2021-04-27mb/google/guybrush: Fix EC SCI configurationRaul E Rangel
This change fixes two problems: 1) We had the enum values for .direction and .level swapped. The naming is very confusing... 2) ESPI_SYS is not a good event to use for EC SCI. It is a level/low event that is only cleared by reading the eSPI status register 0x9C. Cezanne has added a new event source that directly exposes the SCI bit. This is the correct event source to use for EC SCI. BUG=b:186045622, b:181139095 TEST=`lpc sci` on EC console and see /proc/interrupts increase by 1 Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I764b9ec202376d5124331a320767cbf79371dc07 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-26mb/google/volteer/variant/lindar: Disable acoustic mitigationKevin Chang
Roll back CPU slow slew rate setting to Intel default "SLEW_FAST_2" Because baseboard modify slow slew rate setting to "SLEW_FASE_8" for all project, but Lindar and Lillipup is using "SLEW_FAST_2", so this setting need to roll back. BUG=b:186140230 TEST=Build FW and boot to OS checking with CPU log. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I7de252b26c75f8dad218f3eb79a0988e60964f4c Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52620 Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/google/guybrush: Add STAPM values to overridetreeMartin Roth
This enables STAPM power management. Values follow the AMD specification. BUG=b:185209734 TEST=Build & Boot guybrush Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ib9f2ec9a8ac118c55ae53b9419ea4ff74ce7b599 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: chris wang <Chris.Wang@amd.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-26mb/system76/oryp6: Add System76 Oryx Pro 6Tim Crawford
https://tech-docs.system76.com/models/oryp6/README.html Tested with TianoCore (UefiPayloadPkg). Working: - PS/2 keyboard, touchpad - Both DIMM slots - M.2 NVMe - M.2 SATA - MicroSD card slot - All USB ports - Integrated graphics using Intel GOP driver - Webcam - Ethernet - Internal microphone - Combined headphone + mic 3.5mm jack - Combined microphone + S/PDIF 3.5mm jack - Booting to Ubuntu Linux 20.10 and Windows 10 - Flashing with flashrom Not working: - S3 suspend/resume: System hangs on wake from S3 - Discrete/Hybrid graphics: Requires a new driver - Internal speakers: Enabled in separate patch Not tested: - Thunderbolt functionality - S/PDIF output Change-Id: If017d65ca6cb36fe1f631d4dadd050a1547c93fa Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47768 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/hp/snb_ivb_laptops: Do not set EC SLPT on S5Iru Cai
Linux kernel now uses S5 for reboot, which makes reboot fail if EC SLPT bit is set. Tested on HP EliteBook 2560p, reboot and S3 resume work after this change. Change-Id: I9b3ea737f85cc4045714263657bcdaac08f3a20d Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-26mb/**/cmos.layout: Drop unreferenced `iommu` optionAngel Pons
No code in coreboot uses this option, so it might as well be dropped. Change-Id: Ie58bab7e87831db08b9f398a777ba350920b707b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52639 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mainboard: Drop unreferenced CMOS optionsAngel Pons
Remove CMOS options that are not read anywhere in the code. They may have been used in the native AMD platform code, or got copied around from board to board and never did anything to begin with. Change-Id: Ib19ace4fa6e610a28e68fe2612b4e623f200f064 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52638 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/google/mancomb: Add mancomb APCBs into buildIvy Jian
This adds the Mancomb APCBs into the AMD firmware binary. BUG=b:182211161 TEST=Build and check log showing APCB sources present. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Ifdf1e813fce6f93378c2495cf76bdace81d87c16 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52600 Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-26mb/google/mancomb: PCIe GPIOs - enable enables, disable resetsIvy Jian
To train PCIe devices, the devices need to be enabled and taken out of reset. This patch does the bare minimum needed to train PCIe. It is not intended to handle timings, which will be addressed later. Copy the enables for WLAN into early GPIO Init so that they're enabled before FSP-M runs and trains the PCIe busses. Again, this patch is the minimum to let the FSP train the PCIe busses. BUG=b:182202136 TEST=Boot guybrush from NVME. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I5e3e9fe21f44b832e26b0942759ae2ec96ec6c82 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-26mb/google/volteer/variant/lindar: Create dynamic fan table mechanismKevin Chang
Add dynamic fan table mechanism for Lindar and Lillipup. Create different fan tables that provided from thermal team. BUG=b:185308432 TEST=Build FW and boot to OS modify CBI test with DPTF tool. Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Change-Id: I1b79dbe1ae6ee7aa41cef832b4ee305cc8f4b753 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2021-04-26mb/google/guybrush: Enable S0i3Karthikeyan Ramasubramanian
BUG=b:185939089 TEST=Build and boot to OS in Guybrush. Enter S0i3 after passing the sleep state configuration from the mainboard. Change-Id: I4b23b014ca45bd09c76b626b73b0332586dec056 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Mathew King <mathewk@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-26mb/google/brya: Enable GL9755 SD card readerEric Lai
Enable GL9755 SD card reader. BUG=b:185397257 TEST=SD card is functional in the OS. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: Ib3be54274ca796bedda76ce807a0bd630d1d8e4f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52622 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-24mb/kontron/mal10/cmos.layout: Drop unused optionsAngel Pons
The `ethernet1` and `ethernet2` options are not used in this board. Change-Id: I24c8f662d094fb77ed1425ec13486ffa9c3dff07 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52631 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-24mb/kontron/mal10/cmos.layout: Align contents with tabsAngel Pons
Replace spaces with tabs for consistency with other mainboards. Change-Id: I47440eeecf5f2cb2dbdd45b63fe753ffc7d27bd2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52632 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2021-04-24mb/clevo/cml-u/cmos.layout: Align contents with tabsAngel Pons
Replace spaces with tabs for consistency with other mainboards. Change-Id: Ia4042ecf7c62490b0a50bc42d5ddddd5872bf036 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52633 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-24mb/asus/p2b/cmos.layout: Align contents with tabsAngel Pons
Replace spaces with tabs for consistency with other mainboards. Change-Id: Ib0d5bf566148cc4890d5ba010314d11b7a4f8c2b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52634 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/google/dedede/var/storo: Modify eeprom setting for MIPI cameraTao Xia
Currently, it fails to dump the nvme data by test command. It reports the following error: cat: '/sys/bus/i2c/devices/i2c-PRP0001:01/eeprom': Connection timed out So increase the value from 0x0400 to 0x2000 and double the address width from 0x08 to 0x10 to solve this problem. BUG=b:177393430 TEST=1. cat /sys/bus/i2c/devices/i2c-PRP0001:01/eeprom > /tmp/ov8856_eeprom.bin 2. hexdump -C /tmp/ov8856_eeprom.bin > ov8856_eeprom_dump.log 3. cat ov8856_eeprom_dump.log Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ia933927981f07e0f7954a4bc6d82f0bdd70181f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52048 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: ShawnX Tu <shawnx.tu@intel.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/google/guybrush: Update memory configurationMartin Roth
The next guybrush build uses 2 new LPDDR4X memory chips: - Micro MT53E1G32D2NP-046 WT:B - Hynix H9HCNNNBKMMLXR-NEE The MT53E2G32D4NQ-046 WT:A chip has been added to the global LPDDR4X list since the last time guybrush was updated, so that's brought into the guybrush SPD directory as lp4x-spd-10.hex, but it's not used. BUG=b:186027256 TEST=Build only Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: Ia5efd548f8b9442fb3703518387175aba8933a33 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52587 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2021-04-23mb/google/octopus/var/fleex: Add ssfc codec cs42l42 supportEric Lai
Add cs42l42 codec support in fleex. BUG=b:184103445 TEST=boot to check cs42l42 is functional. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I1571003f8b272a573e6ab9fb525f17659bae8c4c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52363 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-23mb/system76/oryp5: Leave NC GPIOs unterminatedTim Crawford
Remove the unneeded pull up, as leaving them unterminated disconnects them from internal logic. Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO where no termination is used. Change-Id: Ia85ea39d46d7d9584b94726a7d601ca06826b1d1 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23mb/intel/shadowmountain: Enable HECI1 interfaceSridhar Siricilla
The patch enables HECI1 interface Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ia2638559bcaac78d024e35abd09534b61eacb843 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52411 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: V Sowmya <v.sowmya@intel.com>
2021-04-23mb/intel/shadowmountain: Enable RTD3 for SD cardRizwan Qureshi
Enable the PCIe RTD3 driver for the PCIe attached SD card interface and specify the srcclk pin and reset GPIO. TEST=Tested on shadowmountain platform to ensure the system can enter the S0ix state and suspend/resume is stable Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Change-Id: Ibeb99bea48d72b019cb2adcf38926c3ed39f7b84 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52134 Reviewed-by: V Sowmya <v.sowmya@intel.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-23mb/intel/adlrvp: Enable DPTF functionality for adlrvp boardSumeet R Pawnikar
Enable DPTF functionality for Alder Lake based adlrvp board BRANCH=None BUG=None TEST=Built and tested on adlrvp board Change-Id: I319bb0ddb9cd9bbe48c8ee09c2742a78da230b7b Signed-off-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52020 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-23mb/intel/adlrvp_m: Enable bluetoothBora Guvendik
Enable bluetooth on ADL-M RVPi. Remove 10.2 pci entry since it is not used anymore. BUG=none TEST=Check lsusb to see if BT enumerated. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I39e77dbb619235129ed894d20f24956242de3aa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52516 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23mb/system76/gaze15: Leave NC GPIOs unterminatedTim Crawford
Remove the unneeded pull up, as leaving them unterminated disconnects them from internal logic. Also replace use of PAD_CFG_TERM_GPO with PAD_CFG_GPO, as none configure termination. Change-Id: I28549a89a885598ba2d5111a9974356562a03cde Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52387 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-23src: Replace remaining {get,set}_option() instancesAngel Pons
With this change, the type-unsafe {get,set}_option() API functions are no longer used directly. The old API gets dropped in a follow-up. Change-Id: Id3f3e172c850d50a7d2f348b1c3736969c73837d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52512 Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22mb/google/brya: Enable display and DSP audio UPDSugnan Prabhu S
This patch includes changes to enable display and DSP audio UPD. BUG=b:181219097,b:183482000 TEST=Audio sound card is detected and listed by the linux kernel. Audio playback and capture is working on the Brya. Change-Id: I3dab02bedb6df995b1efd27332d3aa26985e188e Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-22soc/intel/alderlake: Add enum for HDA audio configurationSugnan Prabhu S
This change adds an enum to configure the audio related UPDs used for configuring the audio over HDMI/DP and rename a variable for better readability. TEST=On shadowmountain audio sound cards are detected and listed by the Linux kernel. Audio playback and capture is working fine. Change-Id: I2834d6f4ce1651a609c5563af375f6e365d931fa Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-22soc/intel/alderlake and mb: Drop PchHdaAudioLink*Enable UPDs from chip.hFurquan Shaikh
FSP uses PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs to configure GPIO pads for audio. However, mainboard is expected to perform all GPIO configration in coreboot and hence these UPDs must be set to 0. There is no need to expose these UPDs in chip.h and provide mainboard an option to set these in devicetree. This change drops PchHdaAudioLink{Hda|Dmic|Ssp|Sndw}Enable UPDs from chip.h and the corresponding devicetree in mainboards. Currently, shadowmountain already set these UPDs to 0, whereas adlrvp set these to 1. But all the ADL boards are correctly configuring the GPIO pads for audio, so this change should not impact audio for any of these boards. BUG=b:183482000 TEST=adlrvp and shadowmountain build successfully. Change-Id: I90e4eb5cc242a789800f4c9f8c71e9d8c8a2becf Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52559 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22mb/google/dedede/var/magolor: Select camera module based on SSFC valueSugnan Prabhu S
This patch has changes to support multiple cameras modules, based on the value set in the SSFC_CONFIG. BUG=b:176065425 TEST=Tested the changes with magolor 5MP and 8MP camera. Change-Id: I764abf70bacbe61452e7b0fd59c1b375227b5748 Signed-off-by: Shawn Tu <shawnx.tu@intel.com> Signed-off-by: Sugnan Prabhu S <sugnan.prabhu.s@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-22guybrush: Increase eSPI bus frequency to 33MhzRob Barnes
Change eSPI bus frequency to 33Mhz. BUG=b:184356693, b:185514521 TEST=Boot guybrush, observe no eSPI bus errors Change-Id: Ie2c1b256531f5c7354600e35e9e5191567197feb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52402 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22guybrush: Add Kconfig for PSP eSPI and port80Rob Barnes
Add PSP_DISABLE_POSTCODES and PSP_POSTCODES_ON_ESPI kconfig options for cezanne. Select PSP_DISABLE_DISABLE_POSTCODES and unselect PSP_POSTCODES_ON_ESPI for guybrush. Port80 codes from PSP can cause bus errors on guybrush. BUG=b:185514903, b:184356693 TEST=Boot guybrush, observe no port80 codes from PSP Change-Id: I7241e47ec1b89782e699135370c796eb251afcaa Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52401 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-22arch/x86/smbios: Let SMBIOS type 9 be able to write slot IDJingleHsuWiwynn
The slot ID can be passed in from the function caller but parsing slot ID from devicetree is not yet supported and would still be 0. Add Slot ID in SMBIOS type 9 for Delta Lake. Tested=Execute "dmidecode -t 9" to verify. Signed-off-by: JingleHsuWiwynn <jingle_hsu@wiwynn.com> Change-Id: I9bf2e3b1232637a25ee595d08f8fbbc2283fcd5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/49917 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-22soc/intel/cannonlake: Set DIMM_SPD_SIZE to 512Felix Singer
All related mainboards are setting DIMM_SPD_SIZE to 512. Therefore, default to 512 in the SoC Kconfig and drop it from related mainboard Kconfigs. Change-Id: Idb6a0e42961eeb490afd76b4aa7d940961991733 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52513 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/asus/p8z77-v_lx2: Add CMOS option supportBill XIE
Based on asus/p8z77-m_pro's, with NMI set to disabled by default, and all available gfx_uma_size values. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I9582747b3d4782f4b02ddecaab636bdbb1b6f530 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52344 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/volteer/variants/drobit: Update DPTF parametersWayne3 Wang
Update the DPTF parameters. Modify TDP, Critical Policy and Active Policy setting. BUG=b:177777472 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by thermal team. Change-Id: Ib57de5535f3d37765ac7051c17445c311c098927 Signed-off-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ariel Chang <ariel_chang@pegatron.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Paul Yang <paul.f.yang@intel.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-21soc/intel/alderlake: Drop unused `PrmrrSize` from devicetreeAngel Pons
The `PrmrrSize` FSP-M UPD is set using `get_valid_prmrr_size()`. As the devicetree option's value is not used anywhere, drop it. Change-Id: Ib6fb77b03a4648adbd8b23c160cfba94d142a2d2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-21ChromeOS: Use CHROMEOS_NVS guardKyösti Mälkki
Replace CONFIG(CHROMEOS) with CONFIG(CHROMEOS_NVS) for cases where the conditional and dependency are clearly about the presence of an ACPI NVS table specified by vendorcode. For couple locations also CONFIG(HAVE_ACPI_TABLES) changes to CONFIG(CHROMEOS_NVS). This also helps find some of the CONFIG(CHROMEOS) cases that might be more FMAP and VPD related and not about ChromeOS per-se, as suggested by followup works. Change-Id: Ife888ae43093949bb2d3e397565033037396f434 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50611 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Lance Zhao Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/volteer/variants/copano: Modify touch controller power sequenceHao Chou
Based on the measurement, adjust the delay time between the main power rail and reset signal to 7ms in order to match the spec. of touch controller, eKTH7918U. BUG=b:184126265 BRANCH=firmware-volteer-13672.B TEST=build test firmware and verified by EE team. Change-Id: Iea84046c1b1f3fe6ab8bb89d86d00b1e89325f71 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Wayne3 Wang <wayne3_wang@pegatron.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2021-04-21mb/google/volteer/variants/copano: Fix pen ejection eventHao Chou
Modify PENH device GPIO GPP_E17 for pen ejection event. BUG=b:182867209 BRANCH=firmware-volteer-13672.B TEST=emerge-volteer coreboot, check evtest if SW_PEN_INSERTED event (value:1/0) when insert/eject pen, and eject pen to wake system from s0ix Change-Id: I1b13d09ed6d065779de9441f2137dcf6559b8f27 Signed-off-by: Hao Chou <hao_chou@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52494 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Paul2 Huang <paul2_huang@pegatron.corp-partner.google.com> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/purism/librem_14: Switch from S76 EC to Librem ECNicole Faerber
Change-Id: Ib2625754e7df818e8a6311e649bc357b2093acb4 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52392 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-21mb/google/dedede/var/sasuke: Update DPTF parametersSeunghwan Kim
Add control charging current from TSR0 and correct charger_perf table value. BUG=b:179067801 BRANCH=dedede TEST=emerge-dedede coreboot Change-Id: Ie0d969898defe76952e5c136fa93b7edffe51de3 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52408 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Edward Doan <edoan@google.com>
2021-04-21mb/google/*: allow LAN MAC to be read from VPD w/o ChromeOSMatt DeVillier
Condition use of RO_VPD for LAN MAC address on CONFIG_VPD rather than CONFIG_CHROMEOS. Test: build/boot google/{beltino,jecht} with RO_VPD propagated from stock firmware, verify MAC address set correctly. Change-Id: I1606fe1936ccee6e03dee145901767c8e73bfe2d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52517 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/google/dedede/metaknight: Add device list and probe daughter-boardDavid Wu
Metaknight has two daughter-board (DB_PORTS_1A_HDMI and DB_PORTS_LTE_HDMI), LTE and USB Type A use the same usb port,so needs to probe daughter-board to avoid USB device cannot recognize correctly. BUG=b:184809456 TEST=build and verify USB device can recognize correctly Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: Ie42d12c7ce5c7341751c3cf92b5f37b6cd4d479f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52369 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Kaiyen Chang <kaiyen.chang@intel.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-21mb/intel/shadowmountain: Disable GSPI1 interface connected to FPSSridhar Siricilla
The patch disables GSPI1 interface connected to fingerprint scanner since no plans to enable FPS on Shadowmountain. TEST=Verified on Shadowmountain Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: Ic693a8c9699d7d1cceef9ca26305cc34498022d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-21mb/asus/am1i-a: Use read_int_option()Angel Pons
Drop "error" (BIOS_DEBUG) messages as well. Change-Id: I61954f8f893c144bbeba1530a486b389bd855ec6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52510 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21mainboard: Use read_int_option()Angel Pons
Change-Id: I9273b90b6a21b8f52fa42d9ff03a9b56eec9fcbf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47137 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2021-04-21mainboard: Use get_int_option() for HWM settingsAngel Pons
Change-Id: I97fbbf2af76a6d4c44221000da7b36378e066ff3 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47135 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21mb/**/early_init.c: Use get_int_option()Angel Pons
Change-Id: I460cad0cc671be830d0fa0f68a531acaea7effcc Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47134 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-21mb/asus/p8z77-m_pro: Use get_int_option()Angel Pons
Change-Id: If75f307c862b24e9208568cdba0a0b05ab4009bf Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2021-04-20mainboard: Drop redundant DEVICETREE configurationFelix Singer
`devicetree.cb` is the default value for the Kconfig DEVICETREE setting. Drop redundant configurations. Change-Id: I5eded3d5e38ca80986da2fda95050815c2702f82 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52504 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20mb/asrock/h110m: Choose `CHIPSET_LOCKDOWN_COREBOOT`Angel Pons
The `chipset_lockdown` option defaults to `CHIPSET_LOCKDOWN_FSP` if omitted. As most of the mainboards use `CHIPSET_LOCKDOWN_COREBOOT`, choose it here as well for consistency. Change-Id: I5ef61f3d931abdb740411d8c58048cf21185802c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52094 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2021-04-20mb/prodrive/hermes: Fix HSI versionPatrick Rudolph
Fix board ID (HSI) read from BMC: * R02 and R03 have an HSI of 2. * R04 has an HSI of 3. Change-Id: I987b2dd848c48e3562bcc07270c958cde3c5a962 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51920 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-20soc/intel/skylake: Move `SataTestMode` to KconfigAngel Pons
This option is not mainboard-specific, and should be user-visible. Change-Id: I9ff2ca984cd238a112af4efd7685f142cc6e5459 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19mb/clevo/cml-u/Kconfig: Use BOARD_CLEVO_L140CU_BASEFelix Singer
To make the L140CU able to be selected by other OEMs, use BOARD_CLEVO_L140CU_BASE for OEM independent options. BOARD_CLEVO_L140CU represents the standard Clevo mainboard without any OEM modifications, while BOARD_CLEVO_L140CU_BASE is used for the baseboard. Change-Id: Iee82eadebfc851619dbb64de09283c5ee55a499f Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52241 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19mb/amd/majolica: use GPIO_40 as reset pin for NVME SSDNikolai Vyssotski
Default Majolica configuration uses GPIO_40 for NVME M2_SSD_RST# BUG=b:182100027 TEST=ls /dev/nvme* Change-Id: Idecc0ec7eaf903b29fea109d3688f3c249da62f5 Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2021-04-19mb/clevo/cml-u: Rename `BOARD_CLEVO_L140CU_OPTIONS`Felix Singer
Rename `BOARD_CLEVO_L140CU_OPTIONS` to `BOARD_CLEVO_L140CU_BASE` to make clear that this option represents the baseboard. Change-Id: I76690626fddafc8e3c37ef760aeb4f064fb6b591 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52480 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19mb/clevo/kbl-u: Move memory init config to variant levelFelix Singer
Memory init config is board specific. Thus, move it to variant level and hook up variant romstage.c. Change-Id: Id78788815ad9c4ed64f0172fb746ff6e50d608ef Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49132 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19mb/clevo/kbl-u: Clean up codeFelix Singer
Change-Id: I98d806ebf126522689b2c101b75add733825fcf1 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49133 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19mb/clevo/l140cu: Move FSP-M config hook to mainboard levelFelix Singer
Hook up FSP-M configuration on mainboard level instead of variant level being able to do common configuration there. Also, hook up variant romstage.c on mainboard level for variant specific configurations. Change-Id: Ic161f83cb629b1e70ca670e10975a25bc0949656 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49077 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2021-04-19mainboard/ocp/tiogapass: Remove redundant PARALLEL_MP_AP_WORKMarc Jones
PARALLEL_MP_AP_WORK is set in the xeon_sp Kconfig. No need to set it here. Change-Id: I66d59fd7cbc3617eb739fdf2f3750f20ee701fbd Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52448 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-19Revert "mb/google/mancomb: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 800193414148d5f39be42110fc2c76ad1ceb7d2f. EC software sync needs to be enabled in payload once the EFS2 requirements are met. BUG=b:185277224 TEST=Build. Cq-Depend: chromium:2829948 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: Ib22a89e221e1e057d82ef76b7008e5d3f14df5e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52451 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-19Revert "mb/google/guybrush: Enable early EC Software Sync"Karthikeyan Ramasubramanian
This reverts commit 1e36dc078e4012f884d67a32f1faac5f80406285. With EFS2 already enabled in EC, enabling early EC sync is not required. Also a workaround has been added in payload to address any boot issues. BUG=b:185277224 TEST=Build and boot to OS in Guybrush in both normal and recovery mode. Cq-Depend: chromium:2832032 Change-Id: I921dc5c814e5187dce283eeff43075b59885723a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52418 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/hatch: Guard ChromeOS fmd selection on CHROMEOSMatt DeVillier
Ensure the ChromeOS FMAPs are used only when CONFIG_CHROMEOS is selected, so non-ChromeOS targets use the default x86 FMAP. Change-Id: Id5d3e7a44973f2fadba3ea15e0e544eee7fa53e6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-18mb/google/mancomb: Remove PS/2 mouse configEric Lai
Sync from guybrush. BUG=b:182211161 TEST=builds Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I02b375b6fc134e56b7f55e1421f694daa4aa994d Reviewed-on: https://review.coreboot.org/c/coreboot/+/52407 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add GPIO override tableKarthikeyan Ramasubramanian
EN_SPKR is routed to SD pin in the ALC1019 speaker amplifier. The concerned pin has a voltage rating of 1.8V whereas the EN_SPKR GPIO has a voltage rating of 3.3 V. The schematics has been updated to bridge the gap. So enable the speaker amplifier by default and add a gpio override table to disable the speakers before board version 2. Also update the codec ACPI HID name for the kernel machine driver to probe the codec successfully. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the GPIO output state is high. Change-Id: I32b29bfae9bc94b5119b33a535d8bc825ef89445 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52355 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush: Enable AMD I2S Machine DriverKarthikeyan Ramasubramanian
Enable AMD I2S machine driver and configure the devicetree with HID information so that the machine driver ACPI objects can be passed to the kernel. BUG=b:182960979 TEST=Build and boot to OS in guybrush. Ensure that the ACPI objects for machine driver is populated. Change-Id: I8ed474d25273082d1e0742ba93746d97930deb19 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52394 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18soc/intel/cnl and mainboards: Drop `cnl_configure_pads()`Furquan Shaikh
CB:31250 ("soc/intel/cannonlake: Configure GPIOs again after FSP-S is done") introduced a workaround in coreboot for `soc/intel/cannonlake` platforms to save and restore GPIO configuration performed by mainboard across call to FSP Silicon Init (FSP-S). This workaround was required because FSP-S was configuring GPIOs differently than mainboard resulting in boot and runtime issues because of misconfigured GPIOs. This issue has since been fixed in FSP (verified with FSP v1263 on hatch). However, there were still 4 boards in coreboot using `cnl_configure_pads()`. As part of RFC CB:50829, librem_cnl, clevo/cml-u and system76/lemp9 were tested to ensure that this workaround is no longer required. This change drops the workaround using `cnl_configure_pads()` and updates all mainboards to use `gpio_configure_pads()` instead. Signed-off-by: Furquan Shaikh <furquan@google.com> Tested-by: Angel Pons <th3fanbus@gmail.com> (Tested purism/librem_cnl) Tested-by: Michael Niewöhner <foss@mniewoehner.de> (Tested clevo/cml-u which is similar to system76/lemp9) Change-Id: I7a4facbf23fc81707cb111859600e641fde34fc4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52248 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/purism/librem_14: Update GPIO configMatt DeVillier
Update GPIO config based on review of latest schematics: - LAN/WLAN reset lines are NC - SDIO lines configured via GPP_G0-G7 - DMIC lines are wired directly to codec, not PCH, so GPP_D17-20 are set to NC - Pads GPP_H0-H3 are configured for I2S2 - Pads GPP_H7-H9 are straps for board revision, so treated as GPI - CPU_C10_GATE# is NC - PWRBTN# does not need an internal pull-up - GPP_C20-23 are configured for M.2 UART - SATAXPCIE1/2 and EC SCI/SMI lines do not need internal pull ups - GPP_C6/C7 set to I2C1 for future use - GPP_E15 changed from SCI to SMI, edge triggered Change-Id: If113cfeadf093e10dd84ab827ead594088f02ba1 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52389 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/purism/librem_14: Remove all PU/PD from NC GPIO padsMatt DeVillier
When a pad is configured as NC, it is set as a GPI with both TX and RX disabled, and as the pad is internally disconnected, no pull up or pull down is needed. Change-Id: Id551b8f6f5b8c772e17670b8b728b5e890ef0b21 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52388 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-18mb/google/guybrush/var/guybrush: Add FPMCU configrationIvy Jian
Enable CRFP in devicetree and configure GPIOs. BUG=b:182201937 BRANCH=None TEST=Boot into OS and confirm FPMCU is responding. Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: I7c56b0db193be6804d07c2f333445c2a1dbf9f59 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52181 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2021-04-18mainboard/ocp/deltalake: Add SATA device to device treeMarc Jones
Add the SATA device to the device tree so it may be found when trying to write SATA registers. Otherwise, it fails on "requests hidden 00:17.0 PCI: dev is NULL!" Change-Id: Ia309805ffd6e97d04b5cf4a0344eaac4c4d0adb6 Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52161 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-17mb/prodrive/hermes: Fix SSDT MPTSPatrick Rudolph
MPTS is currently not executed by the AML interpreter. Use Method (\\_SB.MPTS) instead of Scope (\\_SB) Method (MPTS) ScopeEnd Tested on Prodrive Hermes. MPTS is now executed at S5. Change-Id: I9074eb4ba55aab3f9a47ae5e3c3ddd338406a5e4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52382 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: <wouter.eckhardt@prodrive-technologies.com>
2021-04-16mb/google/guybrush: Enable backlight in the OSMartin Roth
Add ACPI code to enable the backlight when we enter the OS. BUG=b:184198808 TEST=Backlight enabled in the OS Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I3e0a6c06120ac5abf0a0d82494e03d9cf80c1f8c Reviewed-on: https://review.coreboot.org/c/coreboot/+/52113 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure HID over I2C related GPIO as level-triggeredVictor Ding
Both touchpads supported by zork use level-triggered wakeup signal. BRANCH=zork BUG=b:172846122,b:182911201 TEST=1. cros build-ap -b zork 2. both Synaptics and ELAN touchpads work fine on Vilboz 3. Wakeup source is correctly reported on Vilboz Signed-off-by: Victor Ding <victording@google.com> Change-Id: Icc2b5ad3bd434c9759a0fdfc121aa3c94f46630e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52367 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/google/zork: Configure IRQs as level triggered for ELAN touchpadVictor Ding
Based on the datasheet provided by ELAN, the /INT pin is "low active" and "indicates touchpad likes to send data to system(host) when low". The signal is level-triggered. BRANCH=zork BUG=b:172846122 TEST=cros build-ap -b zork Signed-off-by: Victor Ding <victording@google.com> Change-Id: I1f2182aaf483932304591ab14592f35214ea6efd Reviewed-on: https://review.coreboot.org/c/coreboot/+/52366 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/system76/lemp9: correct pad GPP_A11 (INTP_OUT)Michael Niewöhner
This pad is connected to INTP_OUT of the Type-C PD controller. Correct the comment. Also remove the unneeded pull-up. Checked with schematics. Change-Id: I16a769ac6a2d54da700ddb45bd9c7c84383a43dd Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52171 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2021-04-16mb/clevo/cml-u/l140cu: correct pad GPP_A11 (INTP_OUT)Michael Niewöhner
This pad is connected to INTP_OUT of the Type-C PD controller. Correct the comment. Also remove the unneeded pull-up. Checked with schematics. Change-Id: I33a5f177affc3f13d091a85073499b7283f54ada Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52169 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2021-04-16mb/google/dedede/var/galith: support Audio AMP I2C/Auto modeFrankChu
support audio AMP selection with fw_config. BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Ieb169c69a6716082dd218d05479bca46bbc09a3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52286 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-16mb/google/dedede: Add AUDIO_AMP FW_CONFIG in devicetreeFrankChu
Add AUDIO_AMP ports bit field in devicetree. UNPROVISIONED 0 MAX98360 1 RT1015_I2C 2 RT1015P_AUTO 3 BUG=b:185082705 BRANCH=dedede TEST=build pass Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I54f1e44036857dc00df074c38fde0fa82e589320 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52317 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16mb/portwell/m107/Kconfig: Reduce CBFS_SIZEFrans Hendriks
CBFS size equals flash size, leaving no space for descriptor and ME. Reduce CBFS_SIZE. BUG = N/A TEST = Build and boot Portwell M107 Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: Ida5a248edf4f602c4a106ae29d706e732ef8454f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52155 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-16mb/facebook/fbg1701/Kconfig: Remove TPM_INIT_RAMSTAGEFrans Hendriks
TPM_INIT_RAMSTAGE needs to be enabled for measured boot only configuration. Remove TPM_INIT_RAMSTAGE disable. BUG = NA TEST = Boot possible combinations of VBOOT, measured boot and vendorcode security. Signed-off-by: Frans Hendriks <fhendriks@eltan.com> Change-Id: I91bde691d445d4210429c928e90e16653092f1cb Reviewed-on: https://review.coreboot.org/c/coreboot/+/52051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Erik van den Bogaert <ebogaert@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2021-04-16mb/google/dedede/var/storo:Add P-sensor for storoZanxi Chen
Modify GPIO_D22/D23/E11 configuration for P-sensor BUG=b:185214363 BRANCH=dedede TEST=built storo firmware and verified P-sensor function Change-Id: Ia2df1a227b04688a6b98384cd3a4e63023c0c1d9 Signed-off-by: Zanxi Chen <chenzanxi@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52315 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2021-04-16mb/system76/whl-u: Add Darter Pro 5 variantTim Crawford
The darp5 has several GPIO differences to the galp3-c, which are already accounted for in gpio.c. Change-Id: I951e86e53e9c47b9f3038927f44e505d37200c26 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/51870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-16soc/amd/cezanne: Add uart controllers to chipset.cbIvy Jian
Add uart controller to chipset.cb and leave it off by default. Turn uart0 on for console for mainboards. BUG=none TEST=builds and boot into OS Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Change-Id: Iaeb7fea4b92bd89331c7ae7c1c000f8d9961fe9e Reviewed-on: https://review.coreboot.org/c/coreboot/+/52287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16mb/google/brya: Configure TCSS OC pins for bryaMaulik V Vaghela
TCSS OC pins has not been correctly configured for brya. This patch fills the value from devicetree to correct the OC pins mapping BUG=b:184653645 BRANCH=None TEST=check if UPD value has been reflected correctly Change-Id: Ia21cdbf5768ad7516ea52bff7e247291a7d2ebd1 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52321 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
2021-04-16mb/intel/adlrvp: Enable ALC711 over SNDW0Sridhar Siricilla
The patch enables ALC711 over SNDW0. Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com> Change-Id: I43891b94728c8f2d644e14da11946fea3e4515aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/50022 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2021-04-16mb/google/octopus: Add log for ssfc update codecEric Lai
Add log to show the codec has been disabled. BUG=b:185193926 TEST=cbmem -c | grep disabled, can find the codec name Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I8ce7e435ce73beb2a5cbf5883905554227b1989b Reviewed-on: https://review.coreboot.org/c/coreboot/+/52314 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com>
2021-04-16mb/google/guybrush: Implement tis_plat_irq_statusRaul E Rangel
BUG=b:185397933 TEST=boot guybrush and no longer see tis_plat_irq_status warnings Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I9b67cb59221d4e355df8e8a2205e03ead7dba51f Reviewed-on: https://review.coreboot.org/c/coreboot/+/52352 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/{guybrush,mancomb}: Add VBOOT_VBNV_OFFSETRaul E Rangel
This is the same as zork. BUG=b:184126844 TEST=Boot guybrush in developer mode and switch to normal mode. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ib11c255ab7e937de334ecd18dc030006f7724275 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52354 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-16mb/google/guybrush: Sort VBOOT_EARLY_EC_SYNCRaul E Rangel
BUG=none TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I658372d082a8276f15c7165fe4104de4613fe7d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2021-04-15mb/google/guybrush,mancomb: include soc/gpio.h in baseboard/gpio.hFelix Held
This include provides the GPIO_x definitions. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I12a0d95f79658f3852132876e92c389b715f3001 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52358 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: move include to the files where it's usedFelix Held
platform_descriptors.h is unrelated to the contents of baseboard/gpio.h where it was included, so move the includes to the files where it is actually needed. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I94e59b5aac2df834d956106ac953eebfc5cf6921 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52357 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/zork: include amdblocks/gpio_defs.h in baseboard/gpio.hFelix Held
amdblocks/gpio_defs.h provides the definitions of GEVENT_x. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I65d398667e6777de6f1fa4e027cf1c75a3e235c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52356 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15mb/google/kahlee: use defines for GEVENT numbersFelix Held
Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: I353f0d241391dd1122c85866a74984b95ed54770 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52305 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2021-04-15herobrine: sc7280: Provide initial mainboard supportT Michael Turney
BUG=b:182963902 TEST=Validated on qualcomm sc7280 developement board Change-Id: I428cf1a461ee63215f5683abbfed90202d1b2a88 Signed-off-by: Ravi Kumar Bokka <rbokka@codeaurora.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/45206 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-14 01:06:12 +0000