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2023-07-31mb/system76/rpl: galp7: Remove PL4 valueTim Crawford
System76 EC since system76/ec@99dfbeaec3b8 sets PL4 values through PECI based on AC state for all boards. Remove the static PL4 value from coreboot since it won't be used. Change-Id: I2bc37f12aab11910b4fe029efcee891a93257529 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76752 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-31mb/system76: Leave TBT LSX0 as FSP configuredTim Crawford
Do not reconfigured LSX0 so that the FSP values are used. Change-Id: I76e2ab01a5e853e3c1ac78b471ea0aa87d703d52 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76751 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/brya/var/vell: Disable PCH USB2 phy power gatingShon Wang
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for vell board. Please refer Intel doc#723158 for more information. BUG=b:293535284 TEST=build and boot vell Change-Id: I8a4d633fbd362188aedef373e515c7bfe5c4327a Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76770 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-31mb/google/link: Enable HP jack output under WindowsMatt DeVillier
The EAPD pin needs to be enabled and set in order for the headphone jack to work properly. It's already done for the speaker in the beep verbs, but needs to be done for the HP jack as well in order for output to work properly under Windows. TEST=build/boot Win11 on LINK, verify headphone output functional when headphones plugged in. Change-Id: I411d7317aefc1154635c4c17ca0dc1e37c9f40f4 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76746 Reviewed-by: Sean Rhodes <sean@starlabs.systems> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/brya: Create pirrha variantRaymond Chung
Create the pirrha variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0). BUG=b:292134655 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_PIRRHA Change-Id: Idc0a4dbb467cbdb91a5ed55c5e0a9e898e775b11 Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76768 Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-31mb/google/nissa/var/gothrax: Adjust touchscreen driverYunlong Jia
Vendor changes touchscreen firmware to use hid method instead of i2c. BUG=b:274707912 BRANCH=None TEST=emerge-nissa coreboot Change-Id: I8e9e0b757e337db6af3fbf3cd4fdbc0079646179 Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76680 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2023-07-31mb/google/{auron,link,slippy}/acpi: Drop EC serial portMatt DeVillier
The EC serial port on these devices is not accessible to the end user and exposing it to the OS via ACPI serves no purpose. Debugging over the EC serial port (via the servo interface) does not require the ACPI exist. Drop it since it's not needed and serves no purpose. TEST=build/boot Win11 on auron/link/slippy, verify Windows Device Manager no longer shows an unusable COM port. Change-Id: If453bfca8e094aa06043293bdf91a40c38cc7866 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76793 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: CoolStar <coolstarorganization@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-28mb/google/nissa/var/gothrax: Tune SX9324 P-sensor configurationYunlong Jia
Update SX9324 register settings based on tuning value from SEMTECH. －　Enable GPP_B5/GPP_B6 －　Enable GPP_H19 open irq －　Adjust register reg_afe_ctrl0/reg_afe_ctrl3/reg_afe_ctrl4 BUG=b:292016304 BRANCH=None TEST=Check register settings and confirm P-sensor function can work. Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I6f15f7a7c428aee45d35830574ef84aefcae6401 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76711 Reviewed-by: Kyle Lin <kylelinck@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-28mb/google/brask/var/constitution: Add wifi sar tableMorris Hsu
Add wifi sar table for constitution BUG=b:291859402 BRANCH=firmware-brya-14505.B TEST=emerge-constitution coreboot chromeos-bootimage Change-Id: I8f99c5cf486cb3e1f2825bbe3a8084f2fe57a41a Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76674 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
2023-07-28mb/starlabs/starbook: Adjust TCC Offset for all boardsSean Rhodes
Lower the TCC Offset by 10 degress. Change-Id: Ib80d3b73c41ec1196d8294c35b43333e0df218d5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76374 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-28mb/google/link: Change HDA verb subsystem IDMatt DeVillier
Change the SSID to allow the correct Creative Labs Windows audio drivers to attach (vs generic HDA audio ones) and provide full functionality. Linux doesn't care about the SSID, so changing it has no effect there. TEST=build/boot Windows, Linux on google/link, verify the correct audio drivers attach under Windows, no regressions under Linux. Change-Id: Ib5e523b07583289b0222ef156245fb0771ad1f1c Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76745 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sean Rhodes <sean@starlabs.systems> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-27mb/google/nissa/var/uldren: Modify GPIOs for non-touchscreenDtrain Hsu
Set GPP_C6(TCHSCR_REPORT_EN) and GPP_C7(TCHSCR_INT_ODL) to NC for non-touchscreen sku. BUG=b:283199751 BRANCH=firmware-nissa-15217.B TEST=build and boot to ChromeOS Change-Id: Ie062eef24f640c3d6c4a0b4c77792e57ac3a722c Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76749 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-27mb/google/nissa/var/uldren: Add FW_CONFIG probe for fivrDtrain Hsu
Uldren will support internal fivr in next phase and using fw_config to decide the board with internal or external fivr. BUG=b:287379760 BRANCH=firmware-nissa-15217.B TEST=boot to ChromeOS, cold reboot/suspend/recovery mode/install OS work normally. Change-Id: I8a1ac60f599f2895654946d9fa1c4e1f2657fd10 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76419 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-07-27mb/google/nissa/var/craaskov: Add memory parts supportRex Chou
Add new memory parts in the mem_parts_used.txt and generate the SPD ID for the parts. The memory parts being added are: 1) LP5 Memory - 2GB Micron MT62F512M32D2DR-031 WT:B 2) LP5 Memory - 2GB Hynix H9JCNNNBK3MLYR-N6E 3) LP5 Memory - 4GB Samsung K3LKBKB0BM-MGCP 4) LP5 Memory - 4GB Hynix H9JCNNNCP3MLYR-N6E DRAM Part Name ID to assign MT62F512M32D2DR-031 WT:B 0 (0000) H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 1 (0001) H9JCNNNCP3MLYR-N6E 2 (0010) BUG=b:292461498 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I02e49d60e43c4fed8356556ec194d726c30cd609 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76673 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-26mb/google/brya/var/anahera: Disable PCH USB2 phy power gatingWisley Chen
The patch disables PCH USB2 Phy power gating to fix display flicker BUG=b:292403156 TEST=Verified on the defeat board Change-Id: If0c0e655c5d32f39b90635bb3c1d13d8b6993b59 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76669 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-26mb/google/trembyle: Update Touchscreen GPIOJon Murphy
Update Touchscreen GPIO to use the correct GPIO 90. GPIO 32 was a copy/paste from dalboz and corresponds to the FP PWR EN on trembyle platforms. BUG=b:292656388 TEST=build/boot morphius Change-Id: Ia6cdbe9195535093e68dbafedaddb70aaf73da88 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76747 Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2023-07-26mb/google/brya: fix MRC cache failure for hynix partsNick Vaccaro
Set the cs_pi_start_high_in_ect if the DUT is using one of the two following Hynix parts: H54G56CYRBX247 and H54G46CYRBX267. Failure to set cs_pi_start_high_in_ect when using these parts will result in an MRC cache failure and DUT will fail to boot. BUG=b:292153199 TEST=`emerge-brya coreboot chromeos-bootimage`, flash and boot brya variant to kernel. Change-Id: I36040139b959c85c3ac220a34574caa12ca6c5fe Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76661 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-26mb/google/myst: Override PSP_SOFTFUSE_BITS to fix non-serial bootKonrad Adamczyk
With currently set default PSP_SOFTFUSE_BITS for phoenix SoC, the non-serial build does not boot on Myst. Override PSP_SOFTFUSE_BITS by disabling SPIConfig to also get the non-serial build booting. The documentation of PSP_SOFTFUSE_BITS is available in #55758 doc (NDA). BUG=b:292489356 TEST=Flash image-myst.bin, verify that it's able to boot on Myst proto0. Change-Id: Id4472fd85fdefcafb8378199dbaa054fab8b3274 Signed-off-by: Konrad Adamczyk <konrada@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76713 Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
2023-07-26mb/samsung/lumpy: override SMBus subsystem IDMatt DeVillier
Necessary to allow coolstar's Windows touchpad driver for this board, since the touchpad is attached to the SMBus. The VID/DID combo used is not registered/doesn't conflict with any currently in use, and would be difficult to change at this point since the Windows drivers have already been signed. TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify touchpad driver works properly. Change-Id: Ica3756e117fc58166958f37e7b007abb79d9d350 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76744 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-26mb/google/parrot: override SMBus subsystem IDMatt DeVillier
Necessary to allow coolstar's Windows touchpad driver for this board, since the touchpad is attached to the SMBus. The VID/DID combo used is not registered/doesn't conflict with any currently in use, and would be difficult to change at this point since the Windows drivers have already been signed. TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify touchpad driver works properly. Change-Id: Ie1d882cac90211541a636d2dab297c343a12d66d Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76743 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-26mb/google/butterfly: override SMBus subsystem IDMatt DeVillier
Necessary to allow coolstar's Windows touchpad driver for this board, since the touchpad is attached to the SMBus. The VID/DID combo used is not registered/doesn't conflict with any currently in use, and would be difficult to change at this point since the Windows drivers have already been signed. TEST=build/boot Win11, Linux on butterfly/lumpy/parrot, verify touchpad driver works properly. Change-Id: I61912fd6db9eb4b8d202ab633b8c7ca5913e759f Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76742 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-26mb/google/brya/var/redrix: Disable PCH USB2 phy power gatingWisley Chen
The patch disables PCH USB2 Phy power gating to prevent possible display flicker issue for redrix board. Please refer Intel doc#723158 for more information. BUG=b:292435264 TEST=build and boot redrix Change-Id: I34d10c763f4710d2c5678704320fd1cc8d8b6287 Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76670 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-26mb/google/nissa/var/yavilla: avoid mipi camera LED blinking during launchRobert Chen
Camera LED will blink several times as sensor is being probed during kernel boot. Configure _DSC to ACPI_DEVICE_SLEEP_D3_COLD so that driver skips initial probe during kernel boot and prevent privacy LED blink. BUG=b:292173903 TEST=Build and boot on Yavilly EVT unit. Verify & observe Camera LED blinking behavior. Change-Id: Ic3e3439dc9313325189761b277e1a3bd1c1d9418 Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76671 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25mb/system76/adl: gaze17,oryp10: Remove RTD3 configsTim Crawford
These boards do not actually support RTD3. The power GPIOs for components are connected to 3.3V and the reset GPIO is connected to `PLT_RST#`. Change-Id: Id5e318c388f669d6b2935dc98ae29485955e6e72 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76590 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-25mb/system76/adl: darp8,lemp11: Disable RTD3 on SATA portTim Crawford
After switching to S3, it was found that drives on the SATA port do not exit D3cold on S3 exit. Disable RTD3 on the port until the issue can be resolved. Avoids the following error in Linux: pcieport 0000:00:1d.0: Unable to change power state from D3cold to D0, device inaccessible Tested on darp8 with a Samsung 970 EVO or Crucial P5 in J_SSD1. Change-Id: Ib26f59db61acfbf9248cea379c197765d3d9c470 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76593 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25mb/system76/rpl: Add Lemur Pro 12 as a variantJeremy Soller
The Lemur Pro 12 (lemp12) is a Raptor Lake-U board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - DIMM slot with 4800 MT/s memory - Both SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio - 3.5mm microphone input - S3 suspend/resume - TPM 2.0 device - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Onboard RAM Change-Id: I0c4941534b719ea8fc93eb3492d5fe16db208647 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25mb/system76/rpl: Add Bonobo WS 15 as a variantJeremy Soller
The Bonobo Workstation 15 (bonw15) is a Raptor Lake-HX board. Tested with a custom edk2 UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - All M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 - TPM 2.0 device Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: I6d4e408604a0c5c5272e841f4093baaf28c790cd Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25mb/ibm/sbp1: Improve SMBIOS type 17 entriesPatrick Rudolph
Add bank locator and slot existance to the mainboard code. TEST: Verified on Linux that all slots show in dmidecode -t 17. Change-Id: I4ced36e26368d3f99a7341cb55a8deb118b2d1a4 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76677 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-25mb/ibm/sbp1: Drop SuperIO codePatrick Rudolph
The SuperIO is not used so don't enable decoding of 0xE2 and drop all code using it. It's not even required for the virtual UART on 0x3f8 to work. Add the virtual UART on 0x3f8 as ACPI device. TEST: Verified on SBP1 that serial still works. Change-Id: I8e431a0c8417435cc6e3ba16f97ff080e1656a7b Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76676 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2023-07-25mb/google/nissa/var/pujjo: Generate SPD ID for new supported memory partLeo Chou
Add pujjo new supported memory parts in mem_parts_used.txt, generate SPD id for this part. 1. Hynix H58G56BK7BX068 2. Samsung K3KL6L60GM-MGCT, K3KL8L80CM-MGCT 3. Micron MT62F1G32D2DS-026 WT:B BUG=b:292452868 TEST=Use part_id_gen to generate related settings Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: Ia123a1cfd93a5e08ab0ba65f1d9be240d60ff356 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76672 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-25mb/google/rex: Create screebo4es variantSubrata Banik
This patch creates a new variant screebo4es. The new variant will support only ESx samples. The existing rex variant will support the QS samples. BUG=b:292280656 TEST=Able to build google/screebo4es board and boot on target hardware. Change-Id: If77b4a773bee3633008d39c1886b61869c9618de Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76668 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-25mb/google/rex: Use specific mainboard part name for each rex variantsSubrata Banik
BUG=b:290894460 TEST=`emerge-rex coreboot chromeos-bootimage` then check variant name with image*.bin. Signed-off-by: YH Lin <yueherngl@google.com> Change-Id: I8f739485dbaab074f57eaa4dacc9f228a3f4aa14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76667 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-24mb/google/myst: Disable APOB NVFred Reitberger
Disable the APOB cache for only Myst, and re-enable APOB for other Phoenix SOC mainboards. BUG=b:290763369 TEST=verify APOB cache is disabled Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: Ie611e0b84611b2f50c989c75612fc2186b2dbfdf Reviewed-on: https://review.coreboot.org/c/coreboot/+/76567 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2023-07-24mb/google/dedede: Add ALC5650 to AUDIO_AMP in devicetreeDaniel_Peng
Mapping to the fw_config of AUDIO_AMP in dedede, and set new AUDIO_AMP configuration of ALC5650 as value 4. BUG=b:284060672 BRANCH=dedede TEST=build pass Change-Id: Ic3dccd09d3ba1619cce2ac0d5f123badbeeaccdc Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-22mb/google/rex/var/screebo: Reduce TCC from 90°C to 80°CSubrata Banik
This patch increases the `tcc_offset` to reduce the TCC (Thermal Control Circuit) activation temperature to avoid running into abrupt power off during power cycle tests. On Intel processors, the core frequency can be by an HW agent when the current temperature reaches the TCC activation temperature. The default TCC activation temperature is specified by MSR_IA32_TEMPERATURE_TARGET (which is 90°C for google/rex variants). However, this patch adjusted the TCC by specifying an offset in degrees C (i.e., using `tcc_offset` from variant override device tree). Note: The bigger the TCC offset is, the lower the effective TCC activation temperature would be, to ensure that processors can be throttled earlier before the system critical overheats. BUG=b:283008762 TEST=Able to perform power cycle on google/screebo w/o any crash/shutdown. Change-Id: Ib19703877dbbfc26b2d9f538dda4f10c27cf872d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76658 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21mb/google/volteer: Add EC_HOST_EVENT_PANIC to SCI maskRob Barnes
Adding EC_HOST_EVENT_PANIC to SCI mask allows the EC to interrupt the Kernel when an EC panic occurs. If system safe mode is also enabled on the EC, the kernel will have a short period to extract and save info about the EC panic. BUG=b:290985698 BRANCH=firmware-volteer-13672.B TEST=Observe kernel ec panic handler run when ec panics Change-Id: I87173f93d0e47baa816d15dad0777007342b4fdb Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76610 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-21mb/google/rex: Use BOARD_GOOGLE_MODEL_REX instead variant nameSubrata Banik
Choose BOARD_GOOGLE_MODEL_REX while setting up the default config value for variants created using google/rex model. TEST=Able to build and boot google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I107f4e375b5c9e9c0fb80c4d396164c10c1fc1e7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-21mb/google/rex: Create rex4es variantDinesh Gehlot
This patch creates a new variant rex4es. The new variant will support ESx samples. The existing rex variant will support the QS samples. BUG=b:290732344 TEST=Able to build google/rex4es board and boot on target hardware. Change-Id: I25dd1f42ee812f47289da0c2ef7aa79d6f340d48 Signed-off-by: Dinesh Gehlot <digehlot@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76605 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-21mb/google/rex: Create a `rex` model for easier variant integrationSubrata Banik
This patch creates  a rex model so that other variants developed using `rex` baseboard are easy to land without duplicating the config selection. So far, `rex0` and `rex_ec_ish` are developed using the `rex` model. The plan is to extend the support for `rex4es` and `rex4es_ec_ish` variants. TEST=Able to build and boot google/rex. Change-Id: Id4e8d1162da93b7266ee1108f870e89b6d884ab9 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76608 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-20mb/google/rex/var/screebo: Change GPIO of WIFI moduleWentao Qin
Follow baseboard Rex to make GPIO changes BUG=b:286187821 TEST=Ability to enable and disable WIFI function in OS. Change-Id: I805ce859c42c7c0a9d117418a80555658f844e09 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76551 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Jakub Czapiga <jacz@semihalf.com>
2023-07-20mb/google/link: rework TP/TS ACPI for new Windows I2C driverCoolStar
This supports a brand new I2C driver that is designed specifically for the Pixel 2013 chromebook (LINK). The GMBus interface on the IGPU is an i2c-compatible interface, but AFAIK only Link has touch devices attached in this way. On Windows, the PCIe device for the IGP is owned by the Intel proprietary driver, hence a separate ACPI device has to be added for the I2C driver arbitrator to attach to. The MMIO method is used instead of _CRS so that Windows does not try to assign ownership of the resource to our device (even though we're using the MMIO registers at the same time as the IGP driver). Even though in theory 2 drivers accessing the same MMIO may cause problems, in testing, there has been no issues with sleep/wake/hibernate, updating/installing/uninstalling the IGP driver, or changing display resolutions with the i2c driver attached. The arbitrator is necessary as well, since even though there are multiple i2c buses, the MMIO registers are shared. Hence a shared lock is required for i2c access across the buses. The original Sleep Button devices are preserved for Linux due to the completely custom and non-standard implementation of the Windows driver in order to work around the non-standard nature of Link's hardware. Change-Id: If7ee05d15bc17d335cf8c1a8e80bea62800de475 Signed-off-by: CoolStar <coolstarorganization@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76159 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2023-07-20mb/inventec: Add Intel SPR server board Inventec TransformersAnnie Chen
CPU: - 2 SPR sockets - 64 total PCIe 5.0 lanes with up to 64 lanes of Flex Bus/CXL per CPU - Up to 32 DDR5 DIMM - 1 Gbase-T NIC port - 1 USB3.0 type A, 1 USB2.0 connector - 1 VGA connector BMC: - ASPEED AST2600 BMC - 1 DDR4 8Gb memory - 1 8GB eMMC Test: The board boots to Linux 4.19.6 with all 192 cores available. Change-Id: Ic9d99c3aadaa9f69e6d14d4b1a6c5157f5590684 Signed-off-by: Annie Chen <Chen.AnnieET@inventec.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75598 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Wei Chen <Chen.HW@inventec.com> Reviewed-by: Annie Chen <chen.annieet@inventec.com> Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2023-07-20mb/google/nissa/var/uldren: Decrease GT7996F stop_delay_ms to 200msDtrain Hsu
In order to reduce S0ix resume time, decrease stop_delay_ms from 300ms to 200ms for Goodix GT7996F. The value source is from https://partnerissuetracker.corp.google.com/issues/285999032#comment16. BUG=b:285999032 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and touchscreen is workable. Change-Id: I2f0adadbd3d0774da03338cc0abd1639104876d9 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76577 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-20drivers/mipi: Modify INX_P110ZZD_DF0 panel initialization codeCong Yang
There is a problem of screen shake on the old panel[1]. So increase the panel GOP component pull-down circuit size in hardware, and update the initialization code at the same time. The new initialization code is mainly adjusted for GOP timing. When Display sleep in, raise all GOP signals to VGHO and then drop to GND. In order to be consistent with the current panel model, let's rename this file. [1]: INX old panel product number is HJ110IZ-01A-B1, and the new panel product number is HJ110IZ-01A-B2. We have recalled the shipment old panel. BUG=b:270276344 BRANCH=trogdor TEST= test firmware display pass Change-Id: I2b2534afee1ed700c39d3c360aafd685b63ccbfb Signed-off-by: Cong Yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/74973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2023-07-19mb/google/rex/var/ovis: Update the Type-C USB2/3 port mappingSubrata Banik
This patch updates the Type-C USB2/3 port mapping to reflect the mux connection change as mentioned in previous patch commit ee3f796200bf3baf8a1906 (mb/google/rex/var/ovis: Fix mux change as per schematics). Here is the correct port mapping after considering the mux swap: +--------------------------------+-------------+---------------+ | TCSS-USB Mapping | Port C0 | Port C1 | Port C2 | +------------------+-------------+-------------+---------------+ | USB2-Port | 2 | 3 | 1 | | USB3-Port | 0 | 2 | 1 | +------------------+-------------+-------------+---------------+ BUG=b:289300284 TEST=Able to build and boot google/ovis to get display over Type-C1 and Type-C2 port. Change-Id: I460004842dd8fcdc03fca6639d03e422259380ca Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76464 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-19mb/google/rex/var/screebo: Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18Kun Liu
Change SD_CLKREQ_ODL from GPP_D19 to GPP_D18 BUG=b:291051683 BRANCH=none TEST=emerge-rex coreboot Change-Id: Ic102e42482328580c5334e6ff036b774f5002e00 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76565 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Simon Zhou <zhouguohui@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18mb/google/brya/var/osiris: Enable CsPiStartHighinEct for Hynix memoryDavid Wu
According to Intel doc#763797 to overcome early command training hang issue, the CsPiStartHighinEct needs to be enabled for hynix memory. BUG=b:284192689 BRANCH=firmware-brya-14505.B TEST=Built and booted into OS. Change-Id: Ic177c5ffcb6a3d3f76292a0d99ab0e806d43fc11 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76549 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2023-07-18mb/google/brya/var/taeko: Enable CsPiStartHighinEctJoey Peng
Enable CsPiStartHighinEct to fix MRC Cache fail issue BUG=b:279835630 BRANCH=none TEST=Pass MRC Cache test with toolkit 1000 times Change-Id: I25cd856785bab9c661e30e2987b43f0dc2ba9564 Signed-off-by: Joey Peng <joey.peng@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76544 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-18mb/google/brya/var/kano: Enable CsPiStartHighinEct for Hynix memoryDavid Wu
According to Intel doc#763797 to overcome early command training hang issue, the CsPiStartHighinEct needs to be enabled for hynix memory. BUG=b:281643325 BRANCH=firmware-brya-14505.B TEST=Built and booted into OS. Change-Id: I95702e675fa3b73c7e8ee0c8625c7828d8129ea8 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76355 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/rpl: Add Galago Pro 7 as a variantTim Crawford
The Galago Pro 7 (galp7) is a Raptor Lake-H board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots (with NMSO480E82-3200EA00) - M.2 NVMe SSD - All USB ports - SD card reader - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Backlight controls on Windows 10 and Linux 6.2 - HDMI output - DisplayPort output over USB-C - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Detection of devices in TBT slot on boot Change-Id: I1ae3b2c647aa75976a1ea97f7681f93eb000ba8a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75277 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/adl: Disable Intel ME by defaultTim Crawford
Disable the CSME by default now that S3 is used instead of S0ix. The CSME will not go into a low power state during S0ix when it is disabled. This prevents the CPU from reaching C10 and so increases the power usage during suspend compared to leaving CSME enabled. (This was measured to be a ~2W different on TGL-U.) In S3, the state of the CSME doesn't matter because the CPU will be off. Change-Id: I88c0aebdcc977f3ba9dd8f46a6abfaa7a4ae8eb6 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73354 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-18{ec,mb}/system76: Replace color keyboard logicTim Crawford
System76 EC since system76/ec@9ac513128ad9 detects if the keyboard is white or RGB backlit via `RGBKB-DET#` at runtime. Remove the Kconfig for the selection and update the ACPI methods for the new functionality. Change-Id: I60d3d165a58e30d2afc8736c0eb64dd90c8227ca Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76152 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/rpl: Add Darter Pro 9 as a variantTim Crawford
The Darter Pro 9 (darp9) is a Raptor Lake-P board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Change-Id: If19caa90e5f90939b2946392da343b7f91f568ca Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75278 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/rpl: Add Serval WS 13 as a variantTim Crawford
The Serval Workstation 13 (serw13) is a Raptor Lake-HX board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 Keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined 3.5mm headphone + mic audio output - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: Id709a7d06854ba9de673d5e3f25c0a1bbcc53d21 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73440 Reviewed-by: Jeremy Soller <jeremy@system76.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/system76/adl: Switch from S0ix to S3Tim Crawford
After fixing TPM logs clobbering other regions in CB:73297, S3 no longer causes cache issues resulting in power off after multiple suspends. This is required for disabling Intel CSME by default. Change-Id: I7eef4c883fd65db93dae81adabd895b2de90496a Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-18mb/google/dedede/var/boxy: Add fw_config probe for ALC5682-VD & VSStanley Wu
ALC5682-VD/ALC5682I-VS load different kernel driver by different hid name. Update hid name depending on the AUDIO_CODEC_SOURCE field of fw_config. ALC5682-VD: _HID = "10EC5682" ALC5682I-VS: _HID = "RTL5682" BUG=b:290876132 TEST=ALC5682-VD/ALC5682I-VS audio codec can work Change-Id: Id5e0ba7a4ca57e311465ba8e74105f5ee7b8ee8a Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76435 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18pujjoteen5: modify fw_config to separate pujjoteen5 wifi sar tableLeo Chou
Use fw_config to separate pujjoteen5 intel wifi sar table. BUG=b:279984381 Test=emerge-nissa coreboot Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I2e744bf0801bd7b18817a00fcbe3d0c62b8fc3d6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76453 Reviewed-by: Shou-Chieh Hsu <shouchieh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-18mb/google/nissa/var/gothrax: Initialise overridetreeYunlong Jia
Add an initial overridetree for gothrax based on the schematic. BUG=b:274707912 BRANCH=None TEST=emerge-nissa coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: Idfd9788a75f9c342f85d6e1a3d54327d64797dd8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76013 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-18mb/google/nissa/var/gothrax: Set up driver as per schematicsYunlong Jia
Drivers for Pen Garage/SDCard Reader/LTE/SAR/WWAN and I2C for TPM. BUG=b:274707912 BRANCH=None Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I1203ca13bd55b8ab96ce5d323a36ffde06860fa9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76104 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyle Lin <kylelinck@google.com>
2023-07-17mb/amd/mayan: Enable the PCIe bridge for DT/M.2 SSD1 slotsAnand Vaikar
Change-Id: I5c5b125ac03e07a22bcc15ad2d34c62edf74ee04 Signed-off-by: Anand Vaikar <a.vaikar2021@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76452 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/google/rex/var/screebo: Update I2C timingZhongtian Wu
Change i2c[0] parameter Thd:dat = 50ns; Change i2c[1] parameter Thd:dat = 100ns; BUG=b:287898252 BRANCH=none TEST=Test success by EE. Change-Id: Ibdbe4e17cf21c914b48fa6dc7d3eecf8218a2d8b Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76430 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/google/rex: Disable early EC syncSubrata Banik
This patch disables early EC sync to avoid an idle delay (~3sec) without a provision to notify the user about some critical task in progress. Doing EC sync at later stage allows us to notify using graphical msg on screen to make user aware of the WIP task. BUG=b:279944831 TEST=Able to perform EC sync from depthcharge on google/rex. Signed-off-by: Subrata Banik <subratabanik@google.com> Change-Id: I03ed40827c50e75ceaaf94e30d675014ebf22dac Reviewed-on: https://review.coreboot.org/c/coreboot/+/74837 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-17mb/msi/ms7d25: Disable DMI ASPMMichał Żygowski
Disable DMI link ASPM which can degrade performance of overall system. Desktop does not need to be concerned that much about idle power consumption. Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I60af9d2ab2913db449059e1e007999fa2f307f5d Reviewed-on: https://review.coreboot.org/c/coreboot/+/69826 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-17mb/google/rex/var/screebo: Update touchscreen GPIOZhongtian Wu
Change touchscreen reset_gpio GPP_C01 -> GPP_D07; Change touchscreen enable_gpio GPP_C00 -> GPP_B17. BUG=b:289425753 BRANCH=none TEST=Test success by EE. Change-Id: I7be6a2b4e87126b281f138c819d2a0a5b1af5821 Signed-off-by: Zhongtian Wu <wuzhongtian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-17mb/google/nissa: Create craaskov variantRex Chou
Create the craaskov variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0.) BUG=b:290248526 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_CRAASKOV Change-Id: I1d12f7c3d0ef7067f4530c1c69c560f9a83561f6 Signed-off-by: Rex Chou <rex_chou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Ian Feng <ian_feng@compal.corp-partner.google.com>
2023-07-17mb/google/rex/var/karis: Generate SPD ID for supported memory partTyler Wang
Add karis supported memory parts in mem_parts_used.txt, generate SPD id. 1. MICRON MT62F1G32D2DS-023 WT:B 2. HYNIX H9JCNNNBK3MLYR-N6E 3. HYNIX H58G56BK8BX068 4. SAMSUNG K3KL8L80CM-MGCT BUG=b:291018417 TEST=Use part_id_gen to generate related settings Change-Id: I87c2c4f59454dec84d29590ee91379c9fa60ddcf Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76443 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15mb/amd/mayan: Remove useless break after returnElyes Haouas
Change-Id: Iad0244e798c03a26f755024453ecdd745e6286f3 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76473 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-15mb/amd/chausie: Remove useless break after returnElyes Haouas
Change-Id: Iafc3735b6d903a4496828189db14b09d3c4d2081 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76432 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14mb/google/myst: Remove PRESERVE FMD flag for RW_MRC_CACHEMartin Roth
The PRESERVE flag in the FMD file tells futility not to erase the fmap partition when updating the firmware. Because of an issue on myst right now, we want the RW_MRC_CACHE partition to be erased when the firmware is updated. BUG=b:290763369 TEST=None Signed-off-by: Martin Roth <gaumless@gmail.com> Change-Id: Id586ae057b2fd6d513ddbba5e1284dea39467d95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76478 Reviewed-by: Jason Glenesk <jason.glenesk@amd.corp-partner.google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Jon Murphy <jpmurphy@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
2023-07-14mb/system76: Drop VGA_BIOS_IDTim Crawford
System76 boards use the VBT data file, not the VGA optionrom. Change-Id: Ie4100e09221ae4f301a621e7aac62e38ac04a444 Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jeremy Soller <jeremy@system76.com>
2023-07-14mb/amd,google/*/port_descriptors: use dxio_link_hotplug_type enum valuesFelix Held
Use the proper dxio_link_hotplug_type enum values for the link_hotplug field in the DXIO descriptors to replace the magic values in the code. Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Change-Id: Ieb1513737e6022a668287dc80a39d96cda2b18d5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76439 Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14mb/system76: Fix CBFS_SIZE valueTim Crawford
Change `CBFS_SIZE` to match the actual BIOS region size, as specified in the FIT XML config. Fixes building with `VALIDATE_INTEL_DESCRIPTOR` selected. Change-Id: I91a46b3ed6cc3161df27eed19d8cdf2820e90d7e Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76326 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-14mb/google: AMD: move tpm_tis to AMD common codeGrzegorz Bernacki
It moves cr50_plat_irq_status() to common code and adds Kconfig option to specify GPIO used for interrupt. BUG=b:277787305 TEST=Build all affected platform and confirm using right GPIO number. Tested on Skyrim. Change-Id: I775c4e24cffee99b6ac3e05b58a75425029a86c8 Signed-off-by: Grzegorz Bernacki <bernacki@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/75621 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Martin L Roth <gaumless@gmail.com>
2023-07-14mb/system76/rpl: Add Adder WS 3 as a variantJeremy Soller
The Adder Workstation 3 (addw3) is a Raptor Lake-HX board. Tested with a custom TianoCore UefiPayloadPkg. Working: - PS/2 keyboard - I2C HID touchpad - Both DIMM slots with 5200 MT/s memory - Both M.2 SSD slots - All USB ports - Webcam - Ethernet - WiFi/Bluetooth - Integrated graphics using Intel GOP driver - Internal microphone - Internal speakers - Combined headphone + mic 3.5mm audio - 3.5mm microphone input - S3 suspend/resume - Booting Pop!_OS Linux 22.04 with kernel 6.2.7 Not working: - Discrete/Hybrid graphics - Thunderbolt Change-Id: I165a434fe18f8c0aac49cb872bb87f98551d8f2c Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73975 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/google/rex/var/screebo: Configure CNVi GPIO IO Standby StateWentao Qin
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=b:286803481 TEST=Make screebo suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: I7fd342e52fa0f9126eab4c857a5adc04c26e49c6 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76406 Reviewed-by: Kapil Porwal <kapilporwal@google.com> Reviewed-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/google/nissa/var/pujjo: Add WWAN EM060 power on sequenceLeo Chou
Pujjo support WWAN EM060 device, use FW_CONFIG to handle the power on sequence. BUG=b:290709711 TEST=Build and check WWAN EM060 power on sequence. Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Change-Id: I66800c75274e8e1e55d4314c82b7fcdf2a4477bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/76403 Reviewed-by: Derek Huang <derekhuang@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/siemens/mc_ehl4: Change GPIO GPP_B5 polarity for DRAM populationMario Scheithauer
With the latest hardware revision, the polarity of GPP_B5 has been changed. For a full-populated DRAM configuration, the input signal is now connected to 3.3 V and for a half-populated configuration it is connected to ground. BUG=none TEST=Use different populated mainboards and check coreboot log GPP_B5 = 0: [INFO ] meminit_channels: DRAM half-populated [DEBUG] 1 DIMMs found GPP_B5 = 1: [DEBUG] 2 DIMMs found Change-Id: Iaa3a63fa52c802d8f5d8c6cc11dd6edfac117e88 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76434 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Jan Samek <jan.samek@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-13mb/google/nissa/var/uldren: Modify reset_delay_ms for EKTH7D18Dtrain Hsu
Modify reset_delay_ms from 300ms to 6ms for ELAN EKTH7D18. BUG=b:285999032 BRANCH=firmware-nissa-15217.B TEST=boot uldren to ChromeOS and touchscreen is workable. Change-Id: Iffcddbe7735b7a837887dec68e1270c2af5f4556 Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76417 Reviewed-by: Derek Huang <derekhuang@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-12mb/ibm/sbp1: Disable SIO UartsNaresh Solanki
Avoid enabling SIO UART to prevent conflicts with BMC console; utilize VUART0 instead. TEST=Build for sbp1 & make sure coreboot logs do not spill into BMC console. Also made sure coreboot logs are accessible via VUART. Change-Id: I2d4bbd74bb7d37b74378650dd569bca7fa13c29b Signed-off-by: Naresh Solanki <Naresh.Solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76396 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2023-07-12mb/ibm/sbp1: Set coreboot ready GPIO in BS_PAYLOAD_BOOTNaresh Solanki
Set coreboot ready gpio. This gpio is used to indicate to BMC of BIOS completion. Change-Id: Iaed8bec12e593cf1687d973765b0117bdc115cb8 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76404 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12mb/{google, intel}: Enable PCH Energy Reporting for MTL platformsSukumar Ghorai
This patch enables PCH to CPU energy report feature which can be used by Intel Telemetry Driver. BUG=b:269563588 TEST=Able to build and boot google/rex and perform below check to ensure the energy reporting is correct w/o this cl: # lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXX0000 w/ this cl: #lspci -s 00:14.2 -vvv | grep "Region 0" Region 0: Memory at 957f8000 (64-bit, non-prefetchable) [size=16K] # iotools mmio_read32 0x957f8068 #i.e., 104th offset 0xXXXXfc004 Change-Id: I9bd4625ea311a05071878aaec68433a1ba018c0d Signed-off-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76353 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
2023-07-12treewide: Drop the suffixes from ADL and RPL CPUID macros and stringsMichał Żygowski
CPUID is the same for Alder Lake and Raptor Lake S and HX variants. To reduce the confusion and concerns how to name the macros, remove the suffixes from macros and platform reporting strings. Thankfully the stepping names are unique across mobile (P suffixed) and desktop (S and HX suffixed) SKUs. Distinguishing the S from HX is possible via host bridge PCI ID. Change-Id: Ib08fb0923481541dd6f358cf60da44d90bd75ae2 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76203 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2023-07-12mb/google/geralt: Initialize I2C bus for TPS65132 in mainboardRuihai Zhou
The CB:76219 removed mtk_i2c_bus_init() from tps65132s_setup(), so we should initialize I2C bus for TPS65132 in mainboard now. BUG=None TEST=./util/abuild/abuild -t google/geralt -a Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Change-Id: Iacf78221d2416f41467c709402b7e02e03dc5fc7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76358 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2023-07-12mb/emulation/*: Use newer function for resource declarationsArthur Heymans
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Change-Id: Idd623e99ee20ad94e493c8560cfdac9f7baaf890 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76281 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-12mb/google/rex: Disable DRIVERS_INTEL_DPTF_SUPPORTS_TPCHKane Chen
There is no PCH FIVR participant on MTL and we should remove it in Rex. TEST=compile ok and make sure there no TPCH device in acpi BUG=b:290322310 Change-Id: Icf4be86da3f3cb9b1f0a3f2586b029a533c3e6a9 Signed-off-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76402 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11mb/google/rex: LZ4 compress ramstage instead of LZMAWonkyu Kim
for saving boot time, change ramstage compression from LZMA to LZ4. Boot time saving is around 35ms (30-37ms) while SPI size impact is 230KB. For detail, refer below. Existing: LZMA(55.6 ms) 8:starting to load ramstage 894,519 (0) 15:starting LZMA decompress (ignore for x86) 903,556 (9,036) 16:finished LZMA decompress (ignore for x86) 949,997 (46,441) 9:finished loading ramstage 950,179 (182) Changed: LZ4(17.8ms) 8:starting to load ramstage 900,876 (0) 17:starting LZ4 decompress (ignore for x86) 917,650 (16,774) 18:finished LZ4 decompress (ignore for x86) 918,690 (1,040) 9:finished loading ramstage 918,849 (158) Size impact (73KB * 3 = 219KB) fallback/ramstage 0x62940 stage 240281 LZ4 (405524 decompressed) fallback/ramstage 0x62940 stage 165452 LZMA (405524 decompressed) BUG=b:286930648 TEST= Boot to OS and check boot time Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: I6610f405d287bff2eb4eee6f09026e3361405ded Reviewed-on: https://review.coreboot.org/c/coreboot/+/75769 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11mb/google/rex/var/ovis: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi to function properly with the connected bluetooth devices and wake up from low power state. BUG=None TEST=None Change-Id: I977493fd95a99381279f5a3f5e679e4893369b8a Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76362 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com>
2023-07-11mb/google/rex/var/rex0: Configure CNVi GPIO IO Standby StateJamie Ryu
This configures GPIO IO Standby State of GPP_F00 - GPP_F05 as masked for CNVi. Meteor Lake rex platform does not wake up from low power state by bluetooth keyboard and mouse properly. It is identified that IO Standby State needs to be configured as masked to function properly for CNVi. BUG=None TEST=Make rex platform suspend to s0ix state and press a key from bluetooth keyboard. Check the platform wakes up properly from s0ix. Change-Id: Ia98abde584699fa01acba47a9df4ef6332ac16fd Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76338 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sukumar Ghorai <sukumar.ghorai@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-11mb/google/rex/var/rex0: Reduce camera NVM size to 8KBJamie Ryu
The actual NVM size of camera module is 64KB; however, only 8KB is in use to store data. This reduces the size of both NVM0 and NVM1 to 8KB to minimize the time taken to read NVM and launch Camera preview. BUG=NONE TEST=Launch Chrome camera application and check the time taken to read eeprom from camera service log and show camera preview. It takes 2 to 3 seconds to show camera preview while it takes 4 to 5 seconds without the changes. Before the changes: 06:21:04.204944Z OpenDevice(): camera_id = 1 06:21:07.297584Z Read camera eeprom from eeprom 06:21:08.763491Z Read camera eeprom from nvmem After the changes: 21:37:23.923676Z OpenDevice(): camera_id = 1 21:37:24.386020Z Read camera eeprom from eeprom 21:37:24.574515Z Read camera eeprom from nvmem Change-Id: I0e2272b3307fea60ea7406fc6899ae2cb0134fa3 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76189 Reviewed-by: Kiran2 Kumar <kiran2.kumar@intel.corp-partner.google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-11mb/google/nissa/var/gothrax: Update eMMC DLL tuning valuesSimon Yang
Update eMMC DLL tuning values for improved initialization reliability BUG=b:289763421 TEST=cold reboot stress test over 5000 cycles on Foresee and Kingston eMMC Change-Id: I63077b8717feecf3d50507abb188b7fadb5d6c79 Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76221 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/rex/var/ovis: Enable both Memory Channels (MC0 and MC1)Subrata Banik
This patch skips reading the MEM_CH_SEL GPIO aka GPP_E13 to determine the memory channel configuration. The signal behavior is not proper, hence limiting the DIMM capacity to half (only MC0 is enabled). This patch always reports the full memory capacity as in dual channel (both MC0 and MC1 enabled). This change is necessary to ensure that the system reports the correct memory capacity, even if the MEM_CH_SEL GPIO is not working properly. BUG=b:290174538 TEST=Able to detect 32GB memory capacity while booting google/ovis. Without this patch: localhost ~ # cat /proc/meminfo MemTotal: 16183080 kB With this patch: localhost ~ # cat /proc/meminfo   MemTotal: 32673664 kB Change-Id: I6c3fa941abb044b79b13785f7b65d09957f0487d Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76359 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/brya/var/redrix: Use just single GFX entryWon Chung
Since multiple GFX entry causes an ACPI error when trying to write _DOD method multiple times, combine the GFX entry into one so that _DOD method is written just once. BUG=b:289854155 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I22ad70d50f1aecf8da70e8dd04a36a0a7c1c7609 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76329 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Tarun Tuli <taruntuli@google.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
2023-07-10mb/google/rex/var/rex0: Change touch over spi interrupt trigger to edgeEran Mitrani
This CL corrects the trigger for HID over SPI from Level to Edge. BUG:None TEST:Tested with I2C and SPI Change-Id: I78937af22df22d80a702477b6790a7aa40d782a4 Signed-off-by: Eran Mitrani <mitrani@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76116 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
2023-07-10mb/google/corsola: Add support for AW37503 Power ICRuihai Zhou
The AW37503 is designed to supply positive/negative supply for driving the MIPI panel. It doesn't integrate non-volatile memory(EEPROM), so we need to program the registers at boot. We program the target positive/negative output voltage via I2C and enable the power rails by pulling up ENP and ENN pins. On Starmie, we need +/-6V power supply for the MIPI panel. We program the AW37503 registers in coreboot so that kernel can control AW37503 via fixed regulators without additional settings(what we did for TPS65132). Since we distinguish AW37503 and TPS65132 by reading the vendor ID, we need to initialize I2C bus as early as possible. Therefore, we move mtk_i2c_bus_init() to mainboard_init(). BUG=b:289482828 TEST=emerge-staryu coreboot chromeos-bootimage TEST=Test the sequence the voltage Change-Id: I9ccd4db19c93a032226f006eab0427f78f7b6dc8 Signed-off-by: Ruihai Zhou <zhouruihai@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76219 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: cong yang <yangcong5@huaqin.corp-partner.google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/corsola: Add new board 'ponyta'cengjianeng
Add a new kingler follower 'ponyta'. BUG=b:290259648 TEST=make # select ponyta Signed-off-by: cengjianeng <cengjianeng@huaqin.corp-partner.google.com> Change-Id: I74759441957e9901bd7e5a709a2ae7d97a7cd040 Reviewed-on: https://review.coreboot.org/c/coreboot/+/76331 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
2023-07-10mb/google/brya/var/brya: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: Ia756f842943b8e1f1877db7433641e6bbd05f45b Reviewed-on: https://review.coreboot.org/c/coreboot/+/74407 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2023-07-10mb/google/brya/var/skolas: Add new GFX devices with custom _PLDWon Chung
Add new GFX devices for DDI and TCP with custom _PLD to describe the corresponding ports. BUG=b:277629750 TEST=emerge-brya coreboot Signed-off-by: Won Chung <wonchung@google.com> Change-Id: I889db739d6e006c1753eb8c0d208cf471d09f18d Reviewed-on: https://review.coreboot.org/c/coreboot/+/74368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2023-07-10mb/google/brya: put Bluetooth VPGIOs overridableMac Chiang
The BT VGPIOs pad config in variant of gpio.c won't be overwritten on board eventually because no matched gpios existed here. Put BT VGPIOs in gpio_table, ensure that these were able to be overwritten. The fix included crota and omnigul BT offload work successfully. BUG=b:264834572 TEST=test Bluetooth offload playback/capture in SCO profile. Change-Id: I62cecf26abd0411f7cbb0a56b8b8f0a25d370c69 Signed-off-by: Mac Chiang <mac.chiang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76247 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2023-07-10mb/google/brya/var/kuldax: Add fw_config and configurate AUX pinDavid Wu
Add fw_config and configurate AUX pin for MB USB Type-C. MB USB3 doesn't have re-timer, thus have to configurate the AUX pin. BUG=b:275335023 TEST=build pass Change-Id: I1334dcbaec6de1707c6892efbebaf8d460ba8648 Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/76348 Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
2023-07-07mb/google/skyrim/var/crystaldrift: Override SPI flash bus speedYunlong Jia
Add configuration to bump up the SPI flash bus speed from 66 MHz to 100 MHz for starting next phase. BUG=b:270500631 BRANCH=None TEST=emerge-skyrim coreboot Signed-off-by: Yunlong Jia <yunlong.jia@ecs.corp-partner.google.com> Change-Id: I0915d9b10dbfae7fff4e8874011951d1690de870 Reviewed-on: https://review.coreboot.org/c/coreboot/+/75884 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Chao Gui <chaogui@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-17 07:27:20 +0000