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2024-10-24mb/google/nissa/var/glassway: Support Samsung K3LKBKB0BM-MGCPDaniel Peng
Add the new memory support: Samsung K3LKBKB0BM-MGCP BUG=b:374880584 BRANCH=firmware-nissa-15217.B TEST=Run command "go run ./util/spd_tools/src/part_id_gen/\ part_id_gen.go ADL lp5 \ src/mainboard/google/brya/variants/glassway/memory/ \ src/mainboard/google/brya/variants/glassway/memory/\ mem_parts_used.txt" Change-Id: I47d9fd64fa841a2cf60930c5e319a9130019b0a5 Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84831 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-23mb/erying: Add Erying Polestar G613 Pro (TGL-H)Alicja Michalska
Erying is a Chinese manufacturer selling desktop motherboards with laptop SoCs and custom shim to mount desktop coolers. Working: - Serial port (IT8613E 0x3f8) - All rear USB ports (3.0, 2.0) - Both HDMI ports - Realtek GbE NIC - Internal audio (ALC897/ TGL-H HDMI) - Environment Controller (SuperIO fan control) - All SATA ports - All PCI-E/M.2 ports - M.2 NGFF WiFi - PCI-E Resizable BAR (ReBAR) - VT-x WIP/Broken: - PCI-E ASPM (also broken on vendor's FW, clocks are messed up) - S3/s0ix (also broken on stock, setting 3VSB register didn't help - system goes to sleep, but RAM loses power) - DisplayPort on I/O panel (seemingly a simple fix) - One of USB2 FP connectors, as well as NGFF USB isn't mapped (yet) - Automatic fan control (IT8613E can't read CPU_TIN at the moment) Can be flashed using `flashrom -p internal -w build/coreboot.rom`, as vendor hasn't enabled any protections on SPI chip. TEST=Flash coreboot build onto the motherboard, install following PCI-E cards: Radeon RX 7800XT, Kingston KC3000, Optane 900P, Audigy X-Fi. Power the system up and boot into Windows 10 to check ACPI sanity, then reboot into Fedora Linux (kernel 6.10.9) and launch 3D application, disk benchmark, compilation at the same time to check system's stability. Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Signed-off-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/80853 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-23device/pciexp: Add hot-plug capable helper functionPatrick Rudolph
Add and use a new helper function to determine if a device is 1) a PCIe device 2) it's mark hot-plug capable Change-Id: I61cc013844024b43808cd2f054310cb6676ba69e Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84792 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com>
2024-10-23mb/ocp/deltalake: Clean codePatrick Rudolph
Use dev_find_all_devices_on_stack() to find the PCI device on a given stack. That way open coded duplicated code can be dropped and there's no need to call socket0_get_ubox_busno(), which allows to drop socket0_get_ubox_busno(). In addition it adds PCI multi segment support. Change-Id: Ib0ed177ae22112a9f2ed32199409d91cb5851ede Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84790 Reviewed-by: Alicja Michalska <ahplka19@gmail.com> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-21mb/google/fatcat: Disable C1 state auto-demotion for ES SoCJamie Ryu
This disables C1 state auto-demotion to run the coreboot with Panther Lake ES SoC without an issue. This configuration will be remove later once the related features are fully verified. BUG=b:373915085 TEST=Build fatcat and check the platform boots without an issue. Change-Id: I384dba2918cfd04deb90284513c204fa8c21094b Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84767 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com>
2024-10-21mb/google/brox/jubilant: Modify WWAN Rolling RW101R-GL power sequenceRen Kuo
There is no ACPI power resource for LTE module Rolling RW101R-GL, therefore implement the power sequence of power-on, power-off, and reset timing from GPIO init, bootstate init callbacks, and smihandler function. BUG=b:368450447 BRANCH=None TEST= Build firmware and verify on jubilant with LTE:RW101R-GL. Measure the power on, power off, and reset timing. Run warm boot, cold boot and suspend/resume to make sure WWAN devcie is workable. Change-Id: I4a205e3db777c7c225d31b6cc802883fd7167089 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84689 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-10-21mb/google/brox/jubilant: Update CPU power limitsRen Kuo
Update jubilant CPU PL4 from 9 watt to 14 watt for critical battery boot. The maximum peak power is set at 14 watt which is 45W multiplied by 32% efficiency. Overriding power limits for AC power without battery: PL1 (15000, 18000) PL2 (41000, 41000) PL4 (14) BUG=b:364441688 BRANCH=None TEST=Able to successfully boot on jubilant SKU1 and SKU2 with AC only. Test on AC 65W and 45W w/o battery, and check PL4 values from log. Change-Id: Id1e58797206a61d241f48b057b304e05c9c323d9 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84784 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-21mb/google/dedede/var/drawcia: Add Realtek WLAN card supportRobert Chen
Add wifi PCIe hosts M.2 E-key WLAN to fulfill drawman_jsl_schematic_20200528. BUG=None BRANCH=firmware-dedede-13606.B TEST=emerge-dedede coreboot chromeos-bootimage Change-Id: If414ff1941d2d70c5f0444ac58b228ed5c95303a Signed-off-by: Robert Chen <robert.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-10-19mb/google/rauru: Add new board variant NaviLeo Chou
Add a new Rauru follower 'Navi'. BUG=b:341210522 TEST=emerge-cherry coreboot Change-Id: Ia2a6c1c09b3cedc0ef7f51ec93fdabf2c07c8885 Signed-off-by: Leo Chou <leo.chou@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84694 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-19mb/google/rauru: Add NAU8318 supportAmanda Huang
NAU8318 supports beep function via GPIO control. Configure the GPIO pins and pass them to the payload. BUG=b:343143718 TEST=Verify beep function through CLI in depthcharge successfully. We can test with: firmware-shell: badusbbeep firmware-shell: devbeep Change-Id: I79277bc1947dab517dea5aba583c5b4e0ac81bc4 Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84693 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Reviewed-by: Yidi Lin <yidilin@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-19mb/google/rauru: Configure the fingerprint pinsYidi Lin
There is no powering-on control in the fingerprint kernel driver. The fingerprint team of ChromeOS suggests powering-on FP MCU in the FW. Follow trogdor to pull down FP_RST_1V8_S3_L, AP_FP_FW_UP_STRAP, EN_PWR_FP and pull up EN_PWR_FP in ramstage for power rail to be stable. BUG=b:340401582 TEST=measure waveform and the fingerprint works on ChromeOS Change-Id: I05600d90fdf922faeb778a36d8a08f68c1bb4125 Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84692 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-19mb/google/rauru: Pass XHCI_INIT_DONE to the payloadYidi Lin
Configure GPIO EINT28 (XHCI_INIT_DONE) as output, so that payloads (for example depthcharge) can assert it to notify EC to enable USB VBUS. BUG=b:317009620 TEST=emerge-rauru coreboot Change-Id: I5950974435b56997626886b16d371cd8e6472e3c Signed-off-by: Yidi Lin <yidilin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84691 Reviewed-by: Yu-Ping Wu <yupingso@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yidi Lin <yidilin@google.com>
2024-10-17mb/google/nissa/var/glassway: Add convertible and clamshell WIFI SAR ↵Daniel Peng
FW_CONFIG ids Based on Gallida360 design, we add two new options for WIFI_SAR_ID: - WIFI_SAR_ID_INTEL_CONVERTIBLE 2 - WIFI_SAR_ID_INTEL_CLAMSHELL 3 BUG=b:372354703 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: I1b58c4f572d4dbcb269d38485664ddc51e378e5e Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84779 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-17mb/google/fatcat: Create francka variantIan Feng
Create the francka variant of the fatcat reference board. BUG=b:370666276 TEST=util/abuild/abuild -p none -t google/fatcat -x -a make sure the build includes GOOGLE_FRANCKA Change-Id: I372f445f7007d0d33020545a8febbce27c260e41 Signed-off-by: Ian Feng <ian_feng@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84769 Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-17mb/google/fatcat: add pre-mem configuration based on fw_configCliff Huang
Add the GPIO pad configuration to be performed before memory is set up along with the relevant devices definition. This patch includes: - FW config for pre-mem GPIO PAD configuration - Add overridetree changes used by pre-mem FW config BUG=b:348678529 TEST=Boot on Google Fatcat board. Note this cannot be tested by itself directly. Test with CL:84408, set the proper CBI fw_config bit(s) and check that the corresponding GPIO PADs are configured as expected value accordingly. Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: Iac1f637c21a9818512b224dc4cbe4a75dbc516ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/84718 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-16mb/google/brya: Create telith variantKun Liu
Create the telith variant of the nissa reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.5.0) BUG=372506691 BRANCH=None TEST=util/abuild/abuild -p none -t google/brya -x -a make sure the build includes GOOGLE_TELITH Change-Id: I4971b9691d3dd293ca640795967c36472afef9c9 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84759 Reviewed-by: Dinesh Gehlot <digehlot@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Eric Lai <ericllai@google.com>
2024-10-16mb/arm/rdn2: Add support for Arm Neoverse N2Naresh Solanki
Add support for Arm Neoverse N2 Reference design. Based on Arm Neoverse N2 reference design Revision: Release D TEST=Build Arm Neoverse N2 & make sure there is no error. Change-Id: I17908d3ce773d4a88924bafb1d0e9e2a043c7fbc Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2024-10-16mb/ibm/sbp1: Add SMBIOS slotsPatrick Rudolph
Add the BMC and all PCIe slots that the board implements. There are 32 RSSDs and 2 M.2 slots. Change-Id: Id7d72990d6997d1e8b9ce75477ce3dc571c99839 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84560 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-10-16mb/google/brya/var/glassway: Add Stylus FunctionDaniel Peng
1. Add STYLUS fw_config setting. 2. Enable stylus device settings. 3. Disable the stylus GPIO pins based on fw_config. BUG=b:364798563 BRANCH=firmware-nissa-15217.B TEST=1. emerge-nissa coreboot 2. Confirm command evtest for stylus PRP0001:00 and workable. Change-Id: Ifa8555eed1c31e9342a50a735fc618106f26d41a Signed-off-by: Daniel Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84713 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Daniel Peng <daniel_peng@pegatron.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-14i945: Use nullptr instead of NULLElyes Haouas
nullptr was introduced in C11 spec and gcc 4.7. https://en.cppreference.com/w/cpp/language/nullptr https://stackoverflow.com/questions/16256586/how-to-enable-c11-on-later-versions-of-gcc coreboot switched to GCC 4.7.2 on October 25, 2021, prior to coreboot v4.1. https://review.coreboot.org/c/coreboot/+/1609 GCC-13 implemented nullptr constant: https://www.open-std.org/jtc1/sc22/wg14/www/docs/n3042.htm So use it insted of NULL macro. Change-Id: I7d47e692a33d739345a81f589d4329a31beeb8c5 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83860 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-14drivers/pc80/tpm: Remove flag TPM_RDRESP_NEED_DELAYBill XIE
After CB:76315, TPM_RDRESP_NEED_DELAY, whose historical mission has ended, could be removed. Signed-off-by: Bill XIE <persmule@hardenedlinux.org> Change-Id: I51e046fb738d2ff7a23225739de62a1a7780bc1c Reviewed-on: https://review.coreboot.org/c/coreboot/+/84717 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Crawford <tcrawford@system76.com>
2024-10-14mb/google/nissa/var/sundance: Change touch panel and wwan gpio settingRoger Wang
In order to fit the specification, change gpio setting for touch panel and wwan. Change items: 1. wwan : Add WWAN_RST_L to 0. And we want WWAN_EN to pull high more early than WWAN_RST_L, so add WWAN_EN to 1 in romstage stage. 2. touch panel : First we add EN_PP3300_TCHSCR and USI_RST_L to 0 to init status. And we want EN_PP3300_TCHSCR to pull high more early than USI_RST_L so delete USI_RST_L pull high in romstage. BUG=b:357764679 Test=emerge-nissa coreboot Change-Id: I0a07ea8e2bf3d165dcebd89c4c564f157d9d4846 Signed-off-by: Roger Wang <roger2.wang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84668 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-13mb/google/brox/var/lotso: Reduce gspi speed from 10 MHz to 9 MHzKun Liu
Reduce gspi speed from 10 MHz to 9 MHz, because Raptor Lake Refresh platform GSPI supports max frequency 9 MHz. BUG=b:342932183 TEST=emerge-brox coreboot Change-Id: If5b7885d95cfe21ec71cc37e6d72419935b0844f Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84708 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-12mb/google/brox/lotso: Enable devices on unprovisioned fw_configWentao Qin
Setting devices to unprovisioned allows us to perform functional testing without having to rewrite the fw config during the SMT phase of factory production. BUG=None TEST=Build lotso firmware and boot to OS when fw_config is unprovisioned and ensure all devices are enable. Change-Id: I3b8285ce335ee0f3595d184eb0921f697bdbd0c2 Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84714 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-10-11mb/starlabs/*: Rework the performance profilesSean Rhodes
Rather than hardcoded values, simply change these to -25% of the defaults for Power Saving, and +25% for Performance. Change-Id: I16aeb4d5dc25a3f240a775509276c9d3189e9699 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84661 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/*: Adjust the scope of PTTSean Rhodes
The Windows driver only checks PCI0, so move the window accordingly so that it can be used. Tested on `starlite_adl` by booting Windows 11 installation medium. Prior to this patch, it would flag that the security requirements were not met - it now happily installs. Change-Id: I5d0d062502af99104690f9a9affec09f42b5bc71 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84663 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-11mb/starlabs/byte_adl: Configure GPP_E14 as EDP_HPDSean Rhodes
This pin is used by the DisplayPort connector for Hot Plug. Change-Id: I3c63e2e3e168a915daee81afd6a9084a3f01b986 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84662 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/*: Set PL4 to 1.0C of the batterySean Rhodes
Override the PL4 to the maximum power the battery can provide without a charger connected to prevent drawing too much power. Change-Id: I2945e1ed0f33ab6692631e327c1457980b353c06 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84660 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/starlite_adl: Correct the SOC definition in devtreeSean Rhodes
The wrong definition was used, so the code had no effect. The ID for the processor used is `b06e0`. Change-Id: I36e13074a77b93871c1d86664e35a33afe39a402 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84659 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-11mb/starlabs/*: Enhance USB configuration and commentsSean Rhodes
Some boards use hubs for devices, so correct the ACPI configuration for these ports. Also, add more information to the comments for the ports. Change-Id: I8472130aba8e777557cf68280fa0058dbeb77df9 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84650 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2024-10-11mb/starlabs/*: Add PLD Groups to USB ACPI configurationSean Rhodes
Change-Id: I6fb228bab06b050ac1a51de46ffe5c0d3d80adfb Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2024-10-11mb/starlabs/starlite_adl: Make I2C speed configurableSean Rhodes
Make the I2C speed user configurable from CMOS. Both the touchscreen and accelerometer support running at 100MHz or 400MHz. They perform better at 400MHz but use more power - this patch lets the user choose. Change-Id: Ia1b08d7ec6212418bb95d0a52077f01c930f8830 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83882 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2024-10-11mb/starlabs/starlite_adl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: Ibe47f242ce12fc4906baeee89393a34a56eaca76 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83881 Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/*: Disable c6dramSean Rhodes
None of these boards support or use S0ix so c6dram isn't needed, so disable it. Change-Id: I8124899a1f7ce20442f28919f7315ee7e52355e5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84632 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/byte_adl/mk_ii: Correct USB Port Names to Type-ASean Rhodes
There is only 1 Type-C port, the rest are Type-A. Tested on Linux by verified the correct names are shown in dmesg. Change-Id: Iaf5a29f3d25f299658116fa61ae488775e2b70a2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84642 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starlite_adl: Adjust the configuration for USB 2 Port 2Sean Rhodes
Port 2 is a hub, used for the internal keyboard and the card reader. Adjust this to a hub. Change-Id: I3a9b9e6803934291b46fb502ff1b3b088c047703 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-10-10mb/starlabs/starlite_adl: Add PLD groups to USB ACPI configurationSean Rhodes
Change-Id: I8ea01c21ec03c11e9599684dbe51d103c07c172a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84640 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starlite_adl: Reconfigure the touchscreenSean Rhodes
The existing GPIO configuration was IRQ heavy; tweak this to reduce the number of interrupts. Change-Id: I6d23bea5ec12e86a3606186edb29636540283fa3 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84639 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starlite_adl: Adjust the PROCHOT GPIOSean Rhodes
A debug configuration was left in the patch when it was uploaded, remove this. Change-Id: I3ab8137d3841dfa200750a97969af5dca477d7e2 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84638 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim <max.senia.poliak@gmail.com>
2024-10-10mb/starlabs/starlite_adl: Configure Wireless GPIOs laterSean Rhodes
The wireless GPIOs don't need to be configured in the bootblock, so set them up in ramstage. Change-Id: Iab399884edde29891e66ffc097cf6f3dff71c351 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84637 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-10mb/starlabs/starbook: Add options to disable USB devicesSean Rhodes
Add options to disable the card reader and fingerprint reader. Change-Id: Iee985aa2db3da5c2d393b8dc2dc722e990c43272 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84631 Reviewed-by: Maxim <max.senia.poliak@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-09mb/google/brya/var/glassway: Add WFC FunctionDaniel_Peng
1.Add WFC fw_config setting. 2.Used USB2 Port7 for WFC. BUG=b:365184481 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: Ie5dcf5ed8f72a4bdf4c2c7fc63bf94dc7b869eef Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84685 Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-09mb/google/rex/var/ovis: Update EC event parameters for OvisSubrata Banik
This change updates the EC event parameters for Ovis, a Chromebox. As a result, several existing parameters like LID, battery, and AC connect/disconnect are no longer applicable to the Chromebox design. TEST=Successfully built and booted google/ovis. Change-Id: I2b9a6970a07624e16b4483907b8d2b77c04d535c Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84671 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-08mb/google/brox/jubilant: Update FP IRQ pin to GPP_D13 in fp_disable_padsRen Kuo
Commit 8cfe1b3302ff (mb/google/brox/jubilant: Modify FP IRQ pin to GPP_D13): CB:84124, changes the fingerprint IRQ pin from GPP_F15 to GPP_D13, but forgot to update the pin in the array fp_disable_pads. Hence update fp_disable_pads configuration to include that GPIO. BUG=None TEST= build firmware $ emerge-brox coreboot Change-Id: Iee4c3d3f000f884ca8a77ae8c72ccbeebfeb865f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84545 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-10-07mb/starlabs/starbook/rpl: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them. Change-Id: I0e8ef5e3c992f8ff51e4755b80379acfe0361e99 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84630 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07mb/*: Explicitly include static.h for config_of_socNicholas Chin
As per commit 865173153760 ("sconfig: Move config_of_soc from device.h to static.h"), sources that require access to the devicetree should directly include static.h so that it can be removed from device.h, eliminating unnecessary dependencies on static.h for files that only need the types and function declarations in device.h. Change-Id: Ia793666fda47678764fd33891fddb4aecf207bd4 Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84588 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Jayvik Desai <jayvik@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-10-07mb/google/fatcat: Add fatcatnuvo and fatcatite variantsPranava Y N
This patch adds "fatcatnuvo" and "fatcatite" boards to the fatcat Kconfig. BUG=b:369728249 TEST=Able to build fatcat/fatcatnuvo/fatcatite and verify the correct configs selected in coreboot.config Change-Id: Ice3f1d711426cb356c399de6390fef6f0e6bc748 Signed-off-by: Pranava Y N <pranavayn@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84648 Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-07mb/google/brya/var/glassway: Add audio codec ALC5650Daniel_Peng
1.Add AUDIO fw_config setting. 2.Add audio codec ALC5650 related settings for Gallida360 project. BUG=b:364798053 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I3761ca6d4cad18c74f5e1a056f0cb465dc4ac3ea Signed-off-by: Daniel_Peng <Daniel_Peng@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-05mb/google/fatcat/var/fatcat: Rename audio codec optionsSubrata Banik
The new names include the `AUDIO_` prefix to clearly indicate that they are audio-related options. TEST=Able to build google/fatcat w/o any functional impact. Change-Id: Ia651c19f02423ee214a31168e2bd809e097ce8c2 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84657 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-04mb/google/fatcat: change touchscreen fw_config name for THC I2CCliff Huang
use TOUCHSCREEN_THC_I2C instead of TOUCHSCREEN_THC0_I2C BUG=b:348678529 TEST=Able to build google/fatcat Signed-off-by: Cliff Huang <cliff.huang@intel.com> Change-Id: I689dd72a925c76ca6c2c9a941f4857daae20c943 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84652 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-04mb/google/fatcat: Add GPIO settingsJeremy Compostella
BUG=b:348678529 TEST=Boot google fatcat board till FSP memory training Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d52 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84405 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-10-04mb/google/fatcat/var/fatcat: Add FW_CONFIG for UFC and WFCSubrata Banik
BUG=b:348678529 TEST=Able to build google/fatcat. Change-Id: I4061b9b4c1e515e8c078c67f30f29eee87b84a66 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84645 Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-10-03mb/google/hatch/var/dratini: Add FP enableJon Murphy
Add FP enable/disable based on SKU ID for Dratini. This is meant to resolve a UMA issue with Dratini devices that had the FPMCU populated on non-fp devices. Since the FPMCU is present, and the firmware enables the power GPIO's based on variant, not SKU, the devices were reporting data on fingerprint errantly. BUG=b:354769653 BUG=b:200825114 TEST=Flash to Dratini, test FP. Disable test SKU, flash on Dratini, test FP. To test, run `ectool --name=cros_fp version` in the shell When enabled, the fpmcu fw version should be displayed. When disabled, an error should be displayed because the fpmcu is inaccessible. Change-Id: Ifc450f51b00b9c3b62268ce94884f5749a3e18c0 Signed-off-by: Jon Murphy <jpmurphy@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83745 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin L Roth <gaumless@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-03mb/starlabs/{lite_adl,byte_adl}: Don't select MAINBOARD_HAS_TPM2Sean Rhodes
This isn't required by these boards as they both use PTT. Change-Id: I66b3f614914e51116f3cabe457205fb6b3528387 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84629 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/*: Don't disable Turbo Boost in Power Saver profileSean Rhodes
Tested on 24.04, disabling Turbo Boost increases power consumption which doesn't align with the aim of the Power Saver profile. Change-Id: I19e8189ee6c44d19bf222c921429284ed1e1aa2a Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84628 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/starbook/kbl: Disable DPTFSean Rhodes
Change-Id: I68b285ff098127b7becf4aa8736e66fd6b2c4a32 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84276 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/kbl: Remove PMC GPIO routingSean Rhodes
Change-Id: Ibb92d76f15be71ecb1e2187c7e235235585f8793 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84275 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/kbl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I5beda22208fe17338d4136f9d38fd50e55054b01 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/cml: Add USB ACPI to devicetreeSean Rhodes
Change-Id: I140d597750001ad22e2bb1b6971011d2b3bb2bbc Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84272 Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/tgl: Add USB ACPI to devicetreeSean Rhodes
Tested on Ubuntu 24.04 by verifying dmesg output and that USB 2.0 and 3.0 devices are registered correctly. Change-Id: I803a23007f49ea45abc68421e867535081e31b3f Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84271 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/starbook/tgl: Disable DPTFSean Rhodes
DPTF is not used on this platform so disable the PCI device. Change-Id: I763ab948a79e3a020c1b89c69c714dd0d8f54812 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84270 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-10-03mb/starlabs/starbook/tgl: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them. Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/tgl: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook: Move MAINBOARD_HAS_TPM2 selectionSean Rhodes
MAINBOARD_HAS_TPM2 should only be selected for the boards that have memory mapped TPMs. The ones that use Intel PTT don't need it. Change-Id: I02b5b0912afbd7c4634c208bb17db16d0ac7ba99 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84267 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/starlabs/starbook/cml: Disable DPTFSean Rhodes
DPTF is not used on this platform so disable the PCI device. Change-Id: I7fa01936568108dd7707a3c2ea7041a1198533b5 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84266 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-03mb/starlabs/starbook/cml: Remove PMC GPIO routingSean Rhodes
These aren't used so remove them. Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84265 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
2024-10-03mb/starlabs/starfighter: Add Raptor Lake StarFighter Mk I variantSean Rhodes
Tested using `edk2` from `github.com/starlabsltd/edk2/tree/uefipayload_vs`: * Windows 11 * Ubuntu 24.04 No known issues. https://starlabs.systems/pages/starfighter-specification Signed-off-by: Sean Rhodes <sean@starlabs.systems> Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737 Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
2024-10-03mb/google/fatcat: Add Panther Lake SOC supportSaurabh Mishra
- This patch update the original google/fatcat support added with Meteor Lake support as a workaround. - Add initial support to build google/fatcat for Panther Lake SOC - Add soc acpi file entry in mainboard dsdt.asl BUG=b:348678529 TEST=Build google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-02mb/starlabs/starbook/cml: Alphabetize and group FSP UPDsSean Rhodes
Change-Id: I063062d875be61875da136228db06a39bc434833 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-10-02mb/google/brox/jubilant: Modify GPIO for WWANRen Kuo
The LTE module RW101R-GL provide a hardware pin to enable/disable WWAN RF function.The function is disabled in default and is controlled by the AT command.Therefore,set the WWAN_RF_DISABLE Pin to NC, and it has been pull-high by hardware desgin. BUG=b:368450447 BRANCH=None TEST= Build firmware and verify the WWAN on/off function in OS. Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84611 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
2024-10-01mb/starlabs/starbook/adl: Disconnect SCI/SMI GPIOsSean Rhodes
The platform uses eSPI so these are not needed. Change-Id: I507aa59fcf2540ae6170896a51aa952f5e73eee8 Signed-off-by: Sean Rhodes <sean@starlabs.systems> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83691 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-10-01mb/ibm/sbp1: Add SMMSTOREPatrick Rudolph
Add SMMSTORE to the default FMAP to allow using UefiPayload on this board that requires a non-volatile variable store. TEST: Booted an UEFI compatible OS using EDK2 as payload. Change-Id: I32fb0a882c62e42da9f3caec54f8d33333fc8598 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84559 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30soc/amd/glinda: Update gpp bridge naming schemeMaximilian Brune
This patch updates the naming scheme used for the GPP bridges. The naming scheme now matches what we also have on phoenix. Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
2024-09-30mainboard/intel/beechnutcity_crb: Update full IIO configurationJincheng Li
Change-Id: I7f4f5406df8ff82b8d3052ff0f370c280967affd Signed-off-by: Jincheng Li <jincheng.li@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84319 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/google/brya/var/bujia: Add Wifi SAR for bujiaShon
Add wifi sar for bujia. BUG=b:345364452 BRANCH=firmware-brya-14505.B TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot chromeos-bootimage Change-Id: I5a67f3723a9dc33793a5cd95f9a3a2596c3c1fc6 Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84501 Reviewed-by: Jayvik Desai <jayvik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Derek Huang <derekhuang@google.com>
2024-09-30mb/google/kahlee/var/careena: Make sure bid isn't used uninitializedArthur Heymans
GCC with LTO cought this. Warning: src/mainboard/google/kahlee/variants/careena/variant.c:44:12: error: 'bid' may be used uninitialized [-Werror=maybe-uninitialized] 44 | if (bid == 7) | ^ src/mainboard/google/kahlee/variants/careena/variant.c: In function 'car_stage_entry': src/mainboard/google/kahlee/variants/careena/variant.c:24:18: note: 'bid' was declared here 24 | uint32_t bid; Change-Id: Ie732b5be5cd9dc0abaf1a5efe023bcb0738dba1d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84206 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: coreboot org <coreboot.org@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30drivers/i2c/at24rf08c: Disable DRIVER_LENOVO_SERIALS by defaultNicholas Sudsgaard
This should be the sane default, as having this option enabled when the AT24RF08C (Asset Identification EEPROM) is not present on the mainboard can cause SMBIOS table entries to become "*INVALID*". This can, for example, result in strange hostnames when an OS installer uses SMBIOS information to automatically generate one. On the other hand, the coreboot generated SMBIOS tables will at least always contain basic information. Therefore, this driver should be treated as an enhancement rather than a default. Currently, the following mainboards have this option disabled: - ThinkCentre M710s - ThinkCentre M700 / M900 Tiny - Haswell ThinkPads - ThinkPad T440p - ThinkPad W541 Therefore, we can remove this option entirely on these mainboards. Note that there may be other mainboards which do not have this chip present but still have the option enabled. However, this requires a more detailed investigation which would be out of scope of this change. TESTS=Timeless builds on lenovo mainboards produce the same binary. config INCLUDE_CONFIG_FILE default n Was temporarily added to `mb/lenovo/Kconfig` during these tests, as while the configuration does not change, the order of entries do. Therefore, technically producing a different binary when included. Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544 Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2024-09-30mb/google/nissa/var/riven: Add 2 memory parts and generate DRAM IDsDavid Wu
Add two new memory parts 1. K3KL8L80CM-MGCT (Samsung) 2. H58G56BK8BX068 (Hynix) BUG=None TEST=Run part_id_gen tool and check the generated files. Change-Id: I557b359d9e639f6c3fac4239eb28aa7e0bed4c0e Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84529 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-30mb/starlabs/byte_adl/mk_ii: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84502 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sean Rhodes <sean@starlabs.systems>
2024-09-30mb/google: Correct number of jacks in hda_verb.cNicholas Sudsgaard
This corrects the mismatch found in the verb tables of Monroe Chromebase and Link Chromebook. The verb data was not aligned to a multiple of 4, therefore an entry was repeated as padding. This was found due to the `_Static_assert()` from CB:84360 failing. TEST=Tested on LINK under Linux and Win11, audio working properly under both. Change-Id: Id377281af310642a6ba77e5a0002ca1dfca38827 Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84414 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/samsung/lumpy: Correct number of jacks in hda_verb.cNicholas Sudsgaard
The verb data was not aligned to a multiple of 4, therefore an entry was repeated as padding. This has not been tested. This was found due to the `_Static_assert()` from CB:84360 failing. Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84395 Reviewed-by: Paul Menzel <paulepanter@mailbox.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/google/brox/var/lotso: Fix goodix touchscreen power off sequenceKun Liu
Poweroff does not seem to use the ACPI _OFF function, but rather the smihandler. Creating variant_smi_sleep function for nami to handle the power off sequence during reboot/poweroff. BUG=b:364193909 TEST=emerge-brox coreboot Change-Id: I0108be4e5e7c0265aae0f16fd4e2b7cbe5936112 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84412 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/google/brox/var/lotso: Update DTT settings for thermal controlKun Liu
Update DTT settings according to b:348285763#comment20 in order to increase the limit of the charging current to 3A. BUG=b:348285763 TEST=emerge-brox coreboot, and thermal engineer verifies OK. Change-Id: I24978afd819666f635c85f2be9b71d39e0a39f27 Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84527 Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-30mb/google/brox/jubilant: Modify start-up timing for WWAN RW101R-GLRen Kuo
Modify start-up timing for WWAN RW101R-GL to follow spec: PWR_EN H H H FCPO# Tpr H H RESET# L Ton H Tpr: delay for Power stable (>0ms) Ton: delay for reset time (>20ms) BUG=b:349698817 BRANCH=None TEST= Build firmware and verify on jubilant with RW101R-GL Measure the start-up timing sequence to meet spec Boot up in OS, and confirm WWAN can connect to cell site Change-Id: I7aa3e7a172143ff1cebea7f48bda45d4fb2c77f7 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2024-09-27mb/google/fatcat/var/fatcat: add support for wifi sar tableYH Lin
Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG is used to select different sar table (index 0 to 3). BUG=b:348678529 TEST=emerge-fatcat coreboot chromeos-bootimage Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d Signed-off-by: YH Lin <yueherngl@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Pranava Y N <pranavayn@google.com>
2024-09-27mb/hardkernel/odroid-h4: Add support for ODROID-H4 seriesDavid Milosevic
Add support for the ODROID-H4 family of boards. Tested on an ODROID-H4+ board, but all of them use the same PCB (with different components). The four SATA ports on the mainboard are provided by an onboard ASMedia ASM1064B PCIe-to-SATA bridge. Unlike other mainboards in the tree using an ASMedia ASM1061 or ASM1062 PCIe-to-SATA bridge, the ODROID-H4+ comes with a SPI flash chip for the ASM1064B and does not seem to have issues regarding PCIe power management (e.g. ASPM) or unusable SATA AHCI mode. The ODROID-H4 comes with a single 16 MiB SPI flash chip. The ODROID-H4+ and the ODROID-H4 Ultra feature Dual BIOS, consisting of another 16 MiB SPI flash chip and a 3-pin header to select between them. The board can be flashed internally or using a SOIC-8 clip, but the M.2 slot may need to be empty for the clip to fit. Working: - DDR5 SO-DIMM slot - All SATA ports on ASMedia ASM1064B PCIe-to-SATA controller - UART to emit spam - All video outputs (FSP GOP only lights up one output at a time) - All USB ports (on the Ethernet connectors and on EXT_HDR1) - M.2 M connector (PCIe only) - PCIe power management - Ethernet NICs - eMMC - HD audio codec and display audio - S3 suspend/resume - SeaBIOS <current version> - MrChromebox edk2 <current version> - Super I/O HWM on Linux (using out-of-tree it87 kernel module) - Booting Arch Linux from NVMe and SATA - Booting Windows 10 from NVMe Not working: - PECI: undocumented protocol and undocumented Super I/O - Resuming on Windows 10 BSODs with `VIDEO_TDR_FAILURE` Untested: - Fan curves: may need to lower the temperature limits a bit Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb Signed-off-by: David Milosevic <David.Milosevic@9elements.com> Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83979 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2024-09-27mb/google/brya: enable config DRIVER_INTEL_ISH_HAS_MAIN_FW for truloJayvik Desai
Trulo ISH uses the MAIN FW loaded by the kernel driver. This commit enables DRIVER_INTEL_ISH_HAS_MAIN_FW for trulo, which skips printing the ISH BUP version. BUG=b:360144613 TEST=Local build successful and tested on trulo by toggling the config. enabling this config skips printing the ISH version in cbmem. 1. CONFIG enabled ``` trulo-rev1 ~ # cbmem -c | grep ISH [INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin ``` 2. CONFIG disabled ``` trulo-rev1 ~ # cbmem -c | grep ISH [DEBUG] ISH version: 5.4.2.36864 [INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin ``` Change-Id: Ifebd563ec8ddb0378e1215a90396687857f3f71d Signed-off-by: Jayvik Desai <jayvik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84494 Reviewed-by: Eric Lai <ericllai@google.com> Reviewed-by: Dinesh Gehlot <digehlot@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-27mb/google/fatcat/var/fatcat: Add initial FW_CONFIGSubrata Banik
BUG=b:348678529 TEST=Able to build google/fatcat. Change-Id: I5c90aac4873dcc57e65e641656dca3a96f84d6b8 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84543 Reviewed-by: Pranava Y N <pranavayn@google.com> Reviewed-by: YH Lin <yueherngl@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-26mb/amd/birman*/devicetree_glinda.cb: Add usb3_port1Maximilian Brune
Change-Id: Ida2499d9894aa99f341c7a6ef2cd93b3f8ea61fe Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84437 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2024-09-26soc/amd/glinda/chipset.cb: Update for glindaSatya SreenivasL
This also updates the mainboards depending on it. Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57 Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84376 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-26mb/google/{nissa,trulo}: Add Vccin Aux Imon Iccmax default valueSimon Yang
Add default value in nissa and trulo devicetree.cb, ODM have to review the board design to follow RDC#646929 Power Map requirement. NOTE: The VccInAuxImonIccImax remains unchanged w/ and w/o this CL. BUG=b:330117043 BRANCH=firmware-nissa-15217.B TEST='emerge-nissa coreboot chromeos-bootimage' Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c Signed-off-by: Simon Yang <simon1.yang@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/83725 Reviewed-by: Subrata Banik <subratabanik@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-26mb/intel/archercity_crb: Enable native graphics initPatrick Rudolph
Enable the AST 2600 native graphics init driver to have a working UEFI firmware menu displayed over KVM. Change-Id: I2961576077ed3286df080cd09ffe68d835d8c3e7 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shuo Liu <shuo.liu@intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
2024-09-26mb/ibm/sbp1: Update PCIe SBDF in commentNaresh Solanki
Update PCIe Segment, Bus, Device & Function for various IIO bridge devices. Change-Id: I01d164cf0717b3e817348e64e32478c2bb11a8b8 Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/82900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
2024-09-25mb/google/brox/var/lotso: Add RTS522A vdd ctrl by GPP_A17Jian Tong
For next DVT build, hw adds this power ctrl. BUG=b:359409425 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84254 Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/brox/var/lotso: Update cpu power limitsJian Tong
When battery not present, increase PL4 limit from 9 to 40. Get PL setting from internal thermal and power team. AC+DC/DC: PL1=15W PL2=25W PL4=114W AC ONLY: PL1=15W PL2=25W PL4=40W BUG=b:355094551 TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage Confirm on lotso EVT board, as expected. Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928 Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84202 Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/brox/var/lotso: Generate RAM ID for H58G56BK7BX068Jian Tong
BUG=b:342929824 BRANCH=None TEST=boot to kernel success Change-Id: Ibc13137488948ec6cea1904b3964ffed4ff7ea7d Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84499 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/fatcat: Add HDA verb tablesJeremy Compostella
We use ALC256 as HDA codec on fatcat hence, added the verb table. BUG=b:348678529 TEST=Tested audio playback using HDA ALC256 codec on PTL reference board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mb/google/fatcat: Add memory settingsJeremy Compostella
BUG=b:348678529 TEST=Memory training is successful on google fatcat board Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d51 Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84406 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subratabanik@google.com>
2024-09-25mainboard/google/fatcat: Update SoC to Panther LakeSubrata Banik
This commit updates the fatcat mainboard to use the Panther Lake SoC instead of Meteor Lake. The changes include: - Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option. - Updating the `mainboard_update_soc_chip_config()` function to use the `soc_intel_pantherlake_config` struct. - Updating the devicetree to use the `soc/intel/pantherlake` chip. - Updating variant header files to reflect the SoC change. This update enables support for the Panther Lake SoC and its features on the fatcat mainboard. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2024-09-25mainboard/google/fatcat: Remove unused virtual GPIOsSubrata Banik
This commit removes the virtual GPIOs for recovery and write protection from the fatcat variant. These GPIOs are not utilized on the fatcat platform, and their removal simplifies the GPIO configuration and improves code readability. The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther Lake SoCs. Future changes will introduce a suitable GPIO device name that meets the requirements of Panther Lake. BUG=b:347669091 TEST=Able to build google/fatcat. Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536 Reviewed-by: Pranava Y N <pranavayn@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-20 23:54:08 +0000