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2015-10-29mainboard/asus/kgpe-d16: Properly configure SR5690 southbridge PIKE slotTimothy Pearson
Change-Id: I2f1373905ffd6460ac3c7c21738e2e2a9aa2e463 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11992 Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Tested-by: build bot (Jenkins)
2015-10-29pcengines/apu1: adapt comments in devicetree to boardFelix Held
Change-Id: I09d2449af9c1562f4f3d5af1e8764b82b6550007 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12223 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2015-10-29mainboard: Convert #ifdef to IS_ENABLED in get_bus_conf.cTimothy Pearson
Change-Id: I254e9e9e65519edcf4d3f1ecc385af16d18c2367 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12208 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-28google/glados: Set the type-c flex port to max USB2 settingsDuncan Laurie
Change the tuning setting for the type-c port that is over the flex cable to use the max possible drive strength. Also fix up the comments to indicate what Type-c port goes where instead of just referring to them by number. BUG=chrome-os-partner:45367 BRANCH=none TEST=build and boot on glados Change-Id: Iebcffc9ab95d56289258017248c273090c88bb06 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 824ca87c4bf556d493dc8cdec561f37ab135cd2d Original-Change-Id: I081623bbb1b0f39f1569b9f5cf7933abefe202b3 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/309010 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12204 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/chell: Set DPTF critical temperature to 99CDuncan Laurie
If we boot without a heatsink then DPTF may power off the system when it starts if the CPU temp is >90C. Since TJmax is 100C set the critical threshold to just below that value. Also remove the active thresholds as chell does not have a fan. This will have DPTF use the default values but without the DPTF active policy it shouldn't get used. BUG=chrome-os-partner:46694 BRANCH=none TEST=build and boot on chell w/o a heatsink Change-Id: Id9e8f2c547468db8ad0edaf6c362a9a9bb5b95a2 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 23d9117d5d7a4b44fc2298352eba133747f8e246 Original-Change-Id: Ib8e074098e3956efeed0f9b7f8b16652658db374 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/308728 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12202 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/lars: Add new mainboarddavid
This is based on kunimitsu with minor changes: - update GPIOs based on schematic - update SPD data for memory config - disable ALS BUG=None TEST=emerge-lars coreboot Change-Id: Id1c9edfe3cc665e90683344f1662de2e65caf766 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 3201aa573a77fcad3b6b1335d23eb4c2a09c1708 Original-Change-Id: Ifae446e4668569b6100b29bc1f52b0fea1df2952 Original-Signed-off-by: David Wu <David_Wu@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/308283 Original-Commit-Ready: David Wu <david_wu@quantatw.com> Original-Tested-by: David Wu <david_wu@quantatw.com> Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> Original-Reviewed-by: Shawn N <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/12201 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28google/lars: Copy from intel/kunimitsudavid
Change-Id: I95129e6f519735e236c9c13b16e21df25b9ea607 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12200 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-28mainboard/asus/kgpe-d16: Add initial support for the KGPE-D16Timothy Pearson
As of this commit S3 suspend does not work on any K10 boards, including this board. Change-Id: Idd3971422fb2473bff7c60fe8d8161d6e20808ed Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/11946 Tested-by: build bot (Jenkins) Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-27intel/skylake: Clean up USB configuration in devicetreeDuncan Laurie
Instead of having many different arrays for USB configuration, with each array containing one bit of information, have one array containing all the information for each port. This way we can put the basic tuning parameters into a structure and then define structures for the basic supported configurations. The existing port definitions are taken from the Skylake HSIO tuning guide. BUG=chrome-os-partner:40635 BRANCH=none TEST=build and boot on glados, verify USB functionality in all ports. Change-Id: I5873dee011ae9e250b6654c73a7bd5c17681095b Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 864040412b2d2923d3acbfca8055724887c58506 Original-Change-Id: Id518b1086abbe4a8c25d77fd4efc2d0de856bd5f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/306734 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12163 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27intel/kunimitsu: Add device properties for Nuvoton codeYong Zhi
Add default properties for NAU8825 codec Change jack detecion irq to level to match the codec driver BUG=chrome-os-partner:44481 BRANCH=None TEST=Build and Boot Kunimitsu board with this patch Verify Audio jack detection IRQ working Change-Id: Iaab7a7bfbab30fa0914e56477f7c6a93717b4518 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 58c45538ea6a85724f9ab1837e5cf0971611a1f8 Original-Change-Id: I11466b8fd64b768e1e826639ba37bd6e00810370 Original-Signed-off-by: Yong Zhi <yong.zhi@intel.com> Original-Signed-off-by: Fang, Yang A <yang.a.fang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/303760 Original-Commit-Ready: Yang Fang <yang.a.fang@intel.com> Original-Tested-by: Yang Fang <yang.a.fang@intel.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12162 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27intel/kunimitsu: csme: program sml gpios for csme power gatingArchana Patni
For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive. The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables. SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are now configured as GPIOs - input and deep. With this change, the SMT blocks are properly power gating. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for Kunimitsu, boot on FAB3. Change-Id: I16b31a8d5c3c9df0f37df15c751c5a0978ac0feb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d2913a75969008583f454a4bfc9da2156266548b Original-Change-Id: I00dca84a3f6ba7bda4ca1c206b49ff81482279a5 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306391 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12161 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/glados: csme: program sml gpios for csme power gatingArchana Patni
For SMT controllers to power gate, all SMT/SMS clock, data and alert signals should be inactive. The SML0 blocks are not used for any functional purposes and are not configured in the GPIO tables. SMT hardware will not allow the blocks to be power gated in this scenario. The SML* pins are now configured as GPIOs - input and deep. With this change, the SMT blocks are properly power gating. BRANCH=none BUG=chrome-os-partner:45618 TEST=build for Glados. Change-Id: Ie5406f2a1e0c485ac1290e2154755085fa3bb7b9 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 5b3fe3c2ddea4c5daedb04078b24cff14efa49d5 Original-Change-Id: I8dcc0bfc121e612a174e6fe3152650d0fcd68f39 Original-Signed-off-by: Archana Patni <archana.patni@intel.com> Original-Signed-off-by: Subramony Sesha <subramony.sesha@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306481 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12160 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/chell: fix hynix spd dataAaron Durbin
Spreadsheet as built indicates: Samsung 4*8Gb - K4E8E304EE-EGCF - 0b0000 Samsung 4*16Gb - K4E6E304EE-EGCF - 0b0001 Hynix 4*8Gb H9CCNNN8GTMLAR-NUD - 0b0010 Hynix 4*16Gb H9CCNNNBJTMLAR-NUD - 0b0011 Adjust the Hynix spds to match accordingly. BUG=chrome-os-partner:46573 TEST=None BRANCH=None Change-Id: I2ae0335af3557c787cced899bfb80db045f99cd0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 35ed2b0a5af53203480c726b875875d7c2cfd855 Original-Change-Id: I3cb38b28c454fbd60b776954c377b4559c6efebd Original-Signed-off-by: Aaron Durbin <adurbin@chromium.orG> Original-Reviewed-on: https://chromium-review.googlesource.com/306580 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/12159 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/chell: Add new mainboard for chellDuncan Laurie
This is based on glados with minor changes: - updated GPIOs based on schematic - add _PRW for trackpad wake now that it is on a new GPIO - add SPD for new memory config - disable ALS BUG=chrome-os-partner:46289 BRANCH=none TEST=emerge-chell coreboot Change-Id: Id5746bf2b5b26000fcc3f029b901bfe29b788dac Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 9c5ebe98cf599ba80aac5e9ef238b7996789a819 Original-Change-Id: I75efda64a50b0e6e4a5c9008ce05d76c1e605b0c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304927 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12151 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/chell: copy glados to chellDuncan Laurie
Only change is renaming all occurrences of glados to chell, keeping capitalization. Change-Id: I8b1a3efd03d415f27c8872827f8687babbc539f7 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12150 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/glados: Add USB phy settings and update enabled optionsDuncan Laurie
- Add placeholder USB phy settings, needs tuning still - Change UART2 to be skipped during FSP init - Update headphone codec irq to be level triggered as that is how the kernel is configuring it BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I9a15a27dab49d4e19f8ef0574ee2e61ae90c99fc Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 6e7a0032ba23d6762342639c2c7cb877c1f90452 Original-Change-Id: Ie1439f21116022b0644d06853df9490e4651a9ae Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304926 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12149 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27google/glados: Enable TPM PIRQDuncan Laurie
Enable the config option for TPM to use PIRQ instead of SERIRQ and enable the MAINBOARD_HAS_LPC_TPM option. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I990901117a2c478045c403f1039d6eedfc278255 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 44ecaaae1eb482ef5d4cf1e051de4571cc4441be Original-Change-Id: I115d468c72c3fd015abdddffdd1626368bfedb6e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/304925 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12148 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-10-27intel/kunimitsu: USB Phy settings and Skip UART2 init in FSPRizwan Qureshi
FSP 1.7.0 provides UPD to configure USB phy settings update the same for kunimitsu. FSP 1.7.0 also provides UPD to indicate FSP not to reinitialise UART2 controller during MemoryInit. BRANCH=none BUG=chrome-os-partner:45684,chrome-os-partner:41374,chrome-os-partner:42284 TEST=build for Kunimitsu, boot on FAB3, Also checked for Boot from USB, Boot from eMMC, USB Audio, Onboard Audio, Touch, Wifi, S3 entry/resume CQ-DEPEND=CL:303661 Change-Id: Ie0a545c954f472cc822b63786d40399ec93d5166 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 90296e04942c70d972c225fc75dfab6de44d10ed Original-Change-Id: If79e81ef3323e782e96db307d89a01c14174b435 Original-Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Original-Signed-off-by: Rishavnath Satapathy <rishavnath.satapathy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304032 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12145 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27intel/kunimitsu Fab3: Strengthening Rcomp target CTRL valuepchandri
This patch strengthens the Rcomp Target CTRL by 10% for 8GB memory part K4E6E304EE-EGCF as with the current values the MRC training is failing due to more load on CS# BRANCH=None BUG=chrome-os-partner:44647 TEST=BUilds and boots on Kunimitsu. Change-Id: I478002bbebabaac418356d4b5b4755bb56009268 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: b208659e690d8cb5b8dcaf30eed53c01b9f77f6d Original-Change-Id: Ia0a0c1358649af77a3a0d301cb791f26f1e039bf Original-Signed-off-by: pchandri <preetham.chandrian@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/304103 Original-Commit-Ready: Preetham Chandrian <preetham.chandrian@intel.com> Original-Tested-by: Preetham Chandrian <preetham.chandrian@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Preetham Chandrian <preetham.chandrian@intel.com> Reviewed-on: http://review.coreboot.org/12143 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-27asus/f2a85-m: Activate IOMMU supportRudolf Marek
Activate the IOMMU support for the Asus F2A85-M. Add the device to `devicetree.cb`. $ lspci -s 0.2 […] 00:00.2 IOMMU: Advanced Micro Devices [AMD] Family 15h (Models 10h-1fh) I/O Memory Management Unit $ dmesg […] [ 0.000000] ACPI: IVRS 00000000bf144e10 00070 (v02 AMD AMDIOMMU 00000001 AMD 00000000) [ 0.000000] ACPI: SSDT 00000000bf144e80 0051F (v02 AMD ALIB 00000001 MSFT 04000000) [ 0.000000] ACPI: SSDT 00000000bf1453a0 006B2 (v01 AMD POWERNOW 00000001 AMD 00000001) [ 0.000000] ACPI: SSDT 00000000bf145a52 00045 (v02 CORE COREBOOT 0000002A CORE 0000002A) […] Linux 3.10 reported several IO page faults, which could never be explained and which the vendor firmware did not. These errors couldn’t be reproduced with Linux 3.18 by Damien Zammit. Change-Id: I0aa530be17d31656e65db6113343f2ea7008b843 Signed-off-by: Rudolf Marek <r.marek@assembler.cz> Reviewed-on: http://review.coreboot.org/3517 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-25intel/kunimitsu: Add chromeos to verstageLee Leahy
In order to build stand alone verstage the chromeos.c file needs to be part of the verstage target. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Change-Id: I9c547ae177dc95030c8c545a302a2349bf1c9cf8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 07b6465f0b3e18d30647959b8e1db44d8647cf90 Original-Change-Id: I49bf7f1bd2edb32ffe9cc22f6fce1348434fd234 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/301243 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12152 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
2015-10-25google/veyron_rialto: Throttle to 1416MHz @ 1200mV in bootblockDavid Hendricks
The 1392MHz value used to throttle the RK3288 earlier was somewhat arbitrary. This patch brings the throttling in sync with the operating points specified in the Linux device tree for RK3288. BUG=chrome-os-partner:42054 BRANCH=none TEST=Saw print statement in image.serial.bin indicating that APLL was set to the desired frequency. Change-Id: Ibe570267bbfe23f010ad5e1ea651356291b9c63c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a146f23b13cb0f6da93ada65648cf33ecfaaa7d6 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I6bcdb5fd6ffa3f9a22e79c519bdb7980492e2318 Original-Reviewed-on: https://chromium-review.googlesource.com/302633 Reviewed-on: http://review.coreboot.org/12137 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-25google/veyron_rialto: Reduce voltage and frequency in recovery modeDavid Hendricks
This applies CL:300617 to Rialto to down throttle further in recovery mode. BUG=chrome-os-partner:42054 BRANCH=none TEST=Saw print statment in recovery mode with image.serial.bin, device only got mildly warm after several minutes (not hot). Change-Id: I08b6024d31c83c6bbd8c8d9d9a07adc9835e81fd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 74eb9143fbe13df5f386185eab9e5ba9df27cadf Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Change-Id: I9e57d826750cb523c115332fa13a6143bcff7449 Original-Reviewed-on: https://chromium-review.googlesource.com/302631 Reviewed-on: http://review.coreboot.org/12135 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2015-10-24mainboard/asrock/e350m1: Update CMOS layout to match SIO changesTimothy Pearson
Change-Id: I3f1f33b50f788b6d57f1a7986c4bdb912426e4f0 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12125 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24mainboard: Update mainboards using the w83795 sensor deviceTimothy Pearson
Update mainboards using the w83795 sensor device with sane default values. Note that in some cases the defaults may vary from the defaults provided by the old driver, for example the default fan speeds and control modes have changed as I do not have any information on the correct sensor to fan mappings for these boards. Change-Id: Id2ad6222d7a0f29483b022fa097d7d098c6b4122 Signed-off-by: Timothy Pearson <tpearson@raptorengineeringinc.com> Reviewed-on: http://review.coreboot.org/12124 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) Reviewed-by: Peter Stuge <peter@stuge.se>
2015-10-24amd/acpi: Clean up SMBus references.Tobias Diedrich
Replace the AMD SMBus section with the equivalent SB800 smbus.asl include or remove already commented-out sections. Verified by running the cpp preprocessor over the DSDTs and diffing the results against this patch. The only change is in src/mainboard/siemens/sitemp_g1p1/dsdt.asl, where someone added RADD and SADD to the OpRegion, but those are unused, so removing them is fine. Change-Id: I074c8a1ed1c9a944d4988752bd0fc42c199c766c Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10618 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-23google/auron: Remove additional SPD file entriesMarc Jones
Auron only has three GPIOs for RAMID, so there is no need for sixteen SPD file entries. Only include 8 SPD entries. Change-Id: Icf83719a2a5b9271b29f48cde5c66c4c8ccd07f4 Signed-off-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/12073 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23roda/rk9: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: Ifb434db1b8eb01acf48f26366c5237ae49a8730a Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11884 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23lenovo/t400: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: Ide50b34184b80c86b996f86dd589c3cf3bf75587 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11883 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23lenovo/x200: Consolidate `acpi/platform.asl`Paul Menzel
The ASL code is already present in `southbridge/intel/common/acpi/platform.asl` and `cpu/intel/common/acpi/cpu.asl`. So include these files instead of duplicating the code. Something similar was don in commit commit 24813c14 (i945: Consolidate acpi/platform.asl). Change-Id: I1e69cf0fd73e70ed6656b9ed6f55aba4c56a6edd Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11882 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23southbridge/intel: Move `i82801gx/acpi/platform.asl` to `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/southbridge/intel/i82801gx/acpi`. Devices with the southbridge `intel/i82801ix`, like the laptop Lenovo X200, use the exact same ASL code though. So share this in the directory `src/southbridge/intel/common/acpi`. Change-Id: I33b7993bcdbef7233ed85a683b2858ac72c1d642 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11881 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23cpu/intel: Move Power notification ASL code into `common/acpi`Paul Menzel
Commit 24813c14 (i945: Consolidate acpi/platform.asl) creates the file in the directory `src/cpu/intel/model_6dx/acpi`, although the devices can also use different Intel CPU models like, for example, `intel/model_6ex` on the Lenovo T60. Therefore move the file to the directory `src/cpu/intel/common/acpi` so that other devices, like Intel GM45 based devices, can also include it. Change-Id: I90126b66a4d70468923622a8e3aebadeafcbf96f Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/11880 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-23asrock/e350m1: disable unconnected GPP PCIe clocksFelix Held
connections checked by desoldering the FCH and looking at the PCB this lowers the power consumption by about 150-200mW measured on primary side based on change #5397 Change-Id: I986c4cc73a247994f2a47fdfd03f585069ca9385 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/11866 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2015-10-23SB800-mainboards: use write8 to disable unused GPP CLKFelix Held
don't use non-volatile pointers for MMIO access Change-Id: I9f38012a806e43f2535265f1d25537c59b53904e Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: http://review.coreboot.org/12081 Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-23intel/cougar_canyon2: fix buildPatrick Georgi
The reintroduction of cougar_canyon2 crossed beams with the moving the GMA display brightness data in ACPI into individual mainboards. Make things build again by having the board use the same default values that it used to use automatically. They may be wrong, but no worse than what was there before. Change-Id: Id788034c38b42e1c35d9cd17e9bbb2ce49e3e91c Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Reviewed-on: http://review.coreboot.org/12132 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Nico Huber <nico.h@gmx.de>
2015-10-22gma ACPI: Make brightness levels a per board settingNico Huber
Those are actually board specific. Keep the old value as defaults, though. The defaults are included by all affected boards. Change-Id: Ib865c7b4274f2ea3181a89fc52701b740f9bab7d Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11705 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2015-10-22Revert "Remove sandybridge and ivybridge FSP code path"Martin Roth
Please don't remove chipsets and mainboards without discussion and input from the owners. Someone was asking about cougar canyon 2 just a couple of weeks ago - there's obviously still interest. This reverts commit fb50124d22014742b6990a95df87a7a828e891b6. Change-Id: Icd7dcea21fa4a7808b25bb8727020701aeebffc9 Signed-off-by: Martin Roth <martinroth@google.com> Signed-off-by: Ronald G. Minnich <rminnich@gmail.com> Reviewed-on: http://review.coreboot.org/12128 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-17kontron/ktqm77: Tag all four USB3 ports switchable and SS capableNico Huber
With the introduction of these options in commit b26156e (bd82x6x/xhci: Set mask of ports switchable between USB2 and USB3.) the default regressed to disable these capabilities. Maybe other boards regressed too. I didn't check. Change-Id: I220896e656d00145618e61d55b74904517c7d855 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: http://review.coreboot.org/11287 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-16auron: Remove duplicate pei_data assignmentShawn Nematbakhsh
Merge artifact -- don't check spd_index twice. BUG=None TEST=Build only BRANCH=Auron Original-Change-Id: I0cc372fec415646854aa931949ed0f57b473cb01 Original-Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/234421 Original-Reviewed-by: Bernie Thompson <bhthompson@chromium.org> (cherry picked from commit 850125141b52886c845161434a1320676e59534d) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I0070e3f26ebddba716905ebb934bcec4715c4b05 Reviewed-on: http://review.coreboot.org/11912 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins)
2015-10-16auron: fix can not recognize 4G memoryTim Chen
Part of the following patch was lost in the merge from chromium. This patch fixes up the spd_index for the copy from the SPD file. In spd.c "spd_index *= SPD_LEN" will change the original spd_index from gpio and let the following if(spd_index>3) to misjudge and disable channel 1 incorrectly. So we calculate the index for spd file memcpy when calling memcpy(). BUG=chrome-os-partner:32879 TEST=Can get total memory 4G on yuna 4G SKU BRANCH=Auron Original-Change-Id: Iebc49e20e4ca15ef6db8c4defe43cc22382a28bf Original-Signed-off-by: Tim Chen <Tim-Chen@quantatw.com> Original-Reviewed-on: https://chromium-review.googlesource.com/234420 Original-Reviewed-by: Shawn N <shawnn@chromium.org> Original-Commit-Queue: Shawn N <shawnn@chromium.org> Original-Tested-by: Shawn N <shawnn@chromium.org> (cherry picked from commit 3b1fce58b7b4b15e947b40fd011174d4e8e294bc) Signed-off-by: Marc Jones <marc.jones@se-eng.com> Change-Id: I03f9d63623e083c99d349d938fd802d828858f70 Reviewed-on: http://review.coreboot.org/11911 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Georg Wicherski <gw@oxff.net> Tested-by: build bot (Jenkins)
2015-10-15pcengines/apu1: Fill serial number in SMBIOSKyösti Mälkki
Serial number is derived from the MAC address of first NIC. Change-Id: I91e5555b462cca87d48fb56c83aedd1eb02eba62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11901 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins)
2015-10-15pcengines/apu1: Fix CRCs in SPD fileKyösti Mälkki
Do this to wipe error message and hexdump of SPD from console log. Change-Id: I45ffcb1c80aecf43b79d93faedcd62c8f0023cb7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11900 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-15pcengines/apu1: Fix SPD for 4GB modelKyösti Mälkki
Value of tRFCmin was incorrectly using 2 Gigabit chip data. There was no observed instability or bug reports because of this. Change-Id: Ifa03b883afa5a304dd20caf3d4d0383c6cfebdb8 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/11899 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-14Revert "Remove FSP Rangeley SOC and mohonpeak board support"Martin Roth
This chip is still being used and should not have been deleted. It's a current intel chip, and doesn't even require an ME binary. This reverts commit 959478a763c16688d43752adbae2c76e7764da45. Change-Id: I78594871f87af6e882a245077b59727e15f8021a Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: http://review.coreboot.org/11860 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2015-10-14sandy/ivy: Fix PIRQs on ChromebooksKyösti Mälkki
This partially reverts commit 33b535f1. After this commit, samsung/lumpy had its internal USB EHCI controller broken, with no assigned IRQ. PIRQA-PIRQH may be wired as edge-triggered interrupts, making them exclusive for the GPIO to use. They cannot be used for PCI devices at the same time. Change-Id: Ic90343401ac20ca8673baf927cd7703c3481aeab Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/9993 Reviewed-by: Nicolas Reinecke <nr@das-labor.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2015-10-11glados: add chromeos.c to verstageAaron Durbin
In order to build stand alone verstage the chromeos.c file needs to be part of the verstage target. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Change-Id: Id2b05548e4e10cd12002286913f2228b84802e63 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11828 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2015-10-11intel fsp1_1: prepare for romstage vboot verification splitAaron Durbin
In order to introduce a verstage which performs vboot verification the cache-as-ram environment needs to be generalized and split into pieces that can be utilized in romstage and/or verstage. Therefore, the romstage pieces were removed from the cache-as-ram specific pieces that are generic: - Add fsp/car.h to house the declarations for functions in the cache-as-ram environment - Only have cache_as_ram_params which are isolated form the cache-as-ram environment aside from FSP_INFO_HEADER. - Hardware requirements for console initialization is done in the cache-as-ram specific files. - Provide after_raminit.S which can be included from a romstage separated from cache-as-ram as well as one that is tightly coupled to the cache-as-ram environment. - Update the fallout from the API changes in soc/intel/{braswell,common,skylake}. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. Original-Change-Id: I2fb93dfebd7d9213365a8b0e811854fde80c973a Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302481 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Change-Id: Id93089b7c699dd6d83fed8831a7e275410f05afe Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11816 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11intel SOC common: Remove unused parametersLee Leahy
Eliminate unused parameters from the console initialization. BRANCH=none BUG=chrome-os-partner:44827 TEST=Build and run on kunimitsu Original-Change-Id: Iacacea292d43615e9d2f8e5d3ec67e77f3f08906 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/301204 Original-Commit-Ready: Aaron Durbin <adurbin@chromium.org> Original-Tested-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Original-Reviewed-by: Patrick Georgi <pgeorgi@chromium.org> Change-Id: I3a0ea948ce106b07cb6aa872375ce588317dc437 Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11814 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-10-11Kconfig: Hide BOARD_ID_MANUAL.Vladimir Serbinenko
board_id() returns an integer which is platform-specific. 0 for one port is different from 0 for another port. So there is no default board_id() and hence enabling it on boards other than urara would cause build failure. Not enabling it on urara or just setting id to "(none)" as is default results in board_id() = 0 which means urara and an error message on console. Change-Id: I94618f36a75e7505984bbec345a31fe0fa9cc867 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/10379 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-10-11mba4,2: Remove USBDEBUG_HCD_INDEX.Vladimir Serbinenko
MBa doesn't have a usable usbdebug port. Change-Id: Ia8459daa5c9b9405c289954b28ecf1423b1f076c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11849 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2015-10-11lenovo/t60: Enable native intel gfx init.Vladimir Serbinenko
Tested on T60 with intel graphics. Change-Id: Id74d0a1315749052e7313135242e6b64862aa5e1 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/5345 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11Kill lvds_num_lanesVladimir Serbinenko
Only one value would work with corresponding gma code currently (which one depends on board). Going forward, it's possible to compute which number can be used, so there is no need to keep this info around. Change-Id: Iadc77ef94b02f892860e3ae8d70a0a792758565d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11862 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11Derive lvds_dual_channel from EDID timings.Vladimir Serbinenko
Based on the info by Felix Held. Change-Id: Iab84dd8a0e3c942da20a6e21db5510e4ad16cadd Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11857 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11macbookair4_2: fix FIXME's left by autoport.Vladimir Serbinenko
Change-Id: Iff1864982f2f3337c33e56976a0d4eb36f171e66 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11854 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11mba4,2: Fix requested vgabios output.Vladimir Serbinenko
Change-Id: I036c2c300b2aac38b2c30ab86623c9c46b3c5c98 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11850 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11macbookair: Disable native VGA initVladimir Serbinenko
MBA has eDP and not LVDS, so it's not supported by our native init. Change-Id: I489b7a98163b648f0e8000202117593c6b1aaf31 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11842 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11Change macbook air to use a pre-dumped SPD.Vladimir Serbinenko
MBA has a soldered RAM without SPD, so you need to use stored SPD. Change-Id: I0205e6c65ccbfe7764c12c815e60801a3c3623a5 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11841 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-11Autogenerate MacBookAir4,2Vladimir Serbinenko
Just ran autoport on the data from MacBookAir4,2 Change-Id: Iba2a56a6846d81d29e6b090a9a31253ce240914d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/11840 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2015-10-06fsp/cache_as_ram.inc and boards: Fix incorrect usage of POST_IOAlexandru Gagniuc
POST_IO is a user-visible config bool. fsp_1_0/cache_as_ram.inc made a mess of it, by forcing a build-time error when CONFIG_POST_IO was not being set. fsp 1.0 boards ended 'select'ing this in their Kconfig. Refactor fsp/cache_as_ram.inc handling of POST codes, and remove the "select POST_IO" from boards that have it. Instead of implementing an ad-hoc changing post code display and a delay based on port 0xed, just encode the FSP failure code in the POST code. Since FSP failure codes are > 16, we can encode the failure code in the lower nibble, and theirfailing function in the upper nibble. Change-Id: Iaa3e6533e8406b16ec0689abd704984d79293952 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/8485 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2015-10-03Remove FSP Rangeley SOC and mohonpeak board supportAlexandru Gagniuc
mohonpeak is the reference board for Rangeley. I doubt anyone uses it or cares about it. We jokingly refer to it as "Moron Peak". It's code with no known users, so we shouldn't be hauling it around for the eventuality that someone might use it in the future. Change-Id: Id3c9fc39e1b98707d96a95f2a914de6bbb31c615 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11790 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03Remove sandybridge and ivybridge FSP code pathAlexandru Gagniuc
We already have two other code paths for this silicon. Maintaining the FSP path as well doesn't make much sense. There was only one board to use this code, and it's a reference board that I doubt anyone still owns or uses. Change-Id: I4fcfa6c56448416624fd26418df19b354eb72f39 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11789 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-03sandybridge ivybridge: Treat native init as first class citizenAlexandru Gagniuc
This is a sad story. We have three different code paths for sandybridge and ivybridge: proper native path, google MRC path, and, everyone's favorite: Intel FSP path. For the purpose of this patch, the FSP path lives in its own little world, and doesn't concern us. Since MRC was first, when native files and variables were added, they were suffixed with "_native" to separate them from the existing code. This can cause confusion, as the suffix might make the native files seem parasitical. This has been bothering me for many months. MRC should be the parasitical path, especially since we fully support native init, and it works more reliably, on a wider range of hardware. There have been a few board ports that never made it to coreboot.org because MRC would hang. gigabyte/ga-b75m-d3h is a prime example: it did not work with MRC, so the effort was abandoned at first. Once the native path became available, the effort was restarted and the board is now supported. In honor of the hackers and pioneers who made the native code possible, rename things so that their effort is the first class citizen. Change-Id: Ic86cee5e00bf7f598716d3d15d1ea81ca673932f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/11788 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese <zaolin@das-labor.org>
2015-10-02mc_tcu3: Remove dummy blocks from hwinfo.hexWerner Zeh
Remove dummy data from hwinfo.hex as it is not needed anymore in the system. Change-Id: I4f328a4ef61741039eb2c030e23fea33f539c2bb Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11763 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-10-02mc_tcu3: Enable the usage of blobs.Werner Zeh
Since microcode was moved to 3rdparty/blobs, we need to select USE_BLOBS in Kconfig to get the submodule 3rdparty/blobs automaticaly. Change-Id: I25e574fd90b830448cacccd16d01a5a2dbc8517d Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: http://review.coreboot.org/11764 Tested-by: build bot (Jenkins) Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2015-09-30pcengines/apu1: Add CMOS/NVRAM supportMaxime de Roucy
Inspired by the Sage source code (itself from coreboot). Change-Id: I4864923166efb200882d895c572d1ee060c71951 Signed-off-by: Maxime de Roucy <maxime.deroucy@gmail.com> Reviewed-on: http://review.coreboot.org/11730 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-30amd/family14: Add k10temp thermal zone.Tobias Diedrich
The thermal sensor interface exposed in function 3 of the northbridge is a more convenient and faster way to access the processor-internal thermal sensor than using the SMBus/SB-TSI interface from the FCH, see the Family14 BKDG: "Tctl is a processor temperature control value used for processor thermal management. Tctl is accessible through SB-TSI and D18F3xA4[CurTmp]. Tctl is a temperature on its own scale aligned to the processors cooling requirements" Also on at least some of these boards the existing thermal zone is broken and always returns 40C (the default value if the SMBus read failed) because the SMBus muxing register (SmBus0Sel) is not set up correctly. Case in point: The fallback "smbus read failed" temperature is 40 C and the the logs taken from the board status repository for the Asrock E350M1 board all show: "ACPI: Thermal Zone [TZ00] (40 C)" e.g. http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-5054-gf584218/2013-12-20T20:56:20Z/kernel_log.txt#l390 and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-7030-g6d7de4f/2014-10-16T15:34:19Z/kernel_console.txt#l404 and http://review.coreboot.org/gitweb?p=board-status.git;a=blob;f=asrock/e350m1/4.0-9989-gf2dfef0/2015-06-13T00:22:49Z/kernel_log.txt#l425 Example lm-sensors output with this patch on the pcengines APU1, on Linux 4.1.0-rc8+ (wiht both CONFIG_ACPI_THERMAL and CONFIG_SENSORS_K10TEMP enabled): acpitz-virtual-0 Adapter: Virtual device temp1: +54.0 C (crit = +100.0 C) k10temp-pci-00c3 Adapter: PCI adapter temp1: +54.0 C (high = +70.0 C) (crit = +100.0 C, hyst = +97.0 C) Change-Id: Id9c5b783ba424246816677099ec6651814e59f21 Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de> Reviewed-on: http://review.coreboot.org/10940 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30AMD Bettong: Fix usb device in devicetree for Carrizozbao
Add some missing devices to device tree and header. Remove the obsolete devices. Change-Id: Ieeca06c68fe8c8eef6be4fab43193b898aebf013 Signed-off-by: Zheng Bao <zheng.bao@amd.com> Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: http://review.coreboot.org/11378 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-30vboot: provide a unified flow for separate verstageAaron Durbin
The vboot verification in a stage proper is unified replacing duplicate code in the tegra SoC code. The original verstage.c file is renamed to reflect its real purpose. The support for a single verstage flow is added to the vboot2 directory proper. BUG=chrome-os-partner:44827 BRANCH=None TEST=Built glados. Change-Id: I14593e1fc69a1654fa27b512eb4b612395b94ce5 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11744 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-28glados: Provide nau8825 platform data via _DSDBen Zhang
BUG=chrome-os-partner:41280 BRANCH=none TEST=Audio jack insert/eject detection and headset buttons work on glados with the nau8825 driver in chromeos-3.18 and the staging kernel skl2. Change-Id: I813a985b4a39249a2cdbe45117acbdb7710bfa29 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7a5b3dafd407fea2376dff5c3dcde50dff4704fb Original-Change-Id: Ic24a0c444761d0f3a35c268078e70d9aacca4c80 Original-Signed-off-by: Ben Zhang <benzh@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/293610 Original-Reviewed-by: Anatol Pomazau <anatol@google.com> Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11720 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28kunimitsu: Fix typo for WLAN ACPI device nameDuncan Laurie
Fix the typo of _DDR to be _DDN. BUG=chrome-os-partner:40635 BRANCH=none TEST=build kunimitsu with iasl-20150717 Change-Id: I1e7c20d450ea897bfd24506d10a5f466b03610e4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: f136581b653bfb63aac24065c8837307e3fc5432 Original-Change-Id: I3358e6d3d05bcfc291199e8ef12ff92c66f5b74f Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302165 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11718 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-28glados: Fix typo for WLAN ACPI device nameDuncan Laurie
Fix the typo of _DDR to be _DDN. BUG=chrome-os-partner:40635 BRANCH=none TEST=build glados with iasl-20150717 Change-Id: I8d61a6653c3109890d04e54f0d694703b9c9f2bf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d4a2b2583bdbf9afd7b306359338d4c49bbb44ad Original-Change-Id: I7b7905a217d34a8a78b8280c898f1074ecbe3cf6 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/302164 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11717 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
2015-09-24coreboot: move TS_END_ROMSTAGE to one spotAaron Durbin
While the romstage code flow is not consistent across all mainboards/chipsets there is only one way of running ramstage from romstage -- run_ramstage(). Move the timestamp_add_now(TS_END_ROMSTAGE) to be within run_ramstage(). BUG=chrome-os-partner:44827 BRANCH=None TEST=Built and booted glados. TS_END_ROMSTAGE still present in timestamp table. Change-Id: I4b584e274ce2107e83ca6425491fdc71a138e82c Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11700 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-23google: veyron: CBFS_SIZE to match the available size for Coreboot in ChromeOSPaul Kocialkowski
When building for ChromeOS, it is expected that Coreboot will only occupy the first MiB of the SPI flash, according to the veyron fmap description. Otherwise, it makes sense to use the full ROM size. Change-Id: I168386a5011222866654a496d8d054faff7a9406 Signed-off-by: Paul Kocialkowski <contact@paulk.fr> Reviewed-on: http://review.coreboot.org/11117 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-22coreboot: introduce commonlibAaron Durbin
Instead of reaching into src/include and re-writing code allow for cleaner code sharing within coreboot and its utilities. The additional thing needed at this point is for the utilities to provide a printk() declaration within a <console/console.h> file. That way code which uses printk() can than be mapped properly to verbosity of utility parameters. Change-Id: I9e46a279569733336bc0a018aed96bc924c07cdd Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11592 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2015-09-17glados/kunimitsu: remove the implementation of mainboard_add_dimm_inforobbie zhang
This is a follow-up patch to https://chromium-review.googlesource.com/#/c/286877, after fsp support is landed in v1.5. BUG=chrome-os-partner:42975 BRANCH=none TEST=execute "mosys memory spd print all" on glados and kunimitsu Change-Id: I949e287372b190affac36a0efde8a30402eecdc8 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 71a2e1838ff8bbaa358c167dad905b63d23c43fa Original-Change-Id: I64103af4f8456a053a955845a067062122f47af3 Original-Signed-off-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/298967 Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/11657 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I1fe15a5a9b3d868a0e4f1bfb102b69f024c3aa48 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: de9dfee840246866a8dcca2e1c42c0292e820529 Original-Change-Id: I926d74b6bcf6d64c3db61ed23d7c17b51a98b052 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298232 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11651 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Enable wake-on-wifiDuncan Laurie
- Assign GPE DW0 to GPP_B block - Enable GPP_B16 as ACPI_SCI for wake - Define PCIe WLAN device in ACPI with GPE0_DW0_16 for _PRW Note that current designs cannot wake from Deep S3 via wifi. BUG=chrome-os-partner:40635 BRANCH=none TEST=tested on glados: 1-disable deep s3 in devicetree.cb 2-enable magic packet with "iw phy phy0 wowlan enable magic-packet" 3-powerd_dbus_suspend to go to S3 4-wake system with magic packet Change-Id: I989768615e9da8ecf6354852d2db7aae8069aa82 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 894354c5bfd499b911b7f89310c48b503dbaadc2 Original-Change-Id: I9a7a317fc2eccc70fdb4862843de1a654fbc2eee Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298231 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11650 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17kunimitsu: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I547d92b4e852664567792060bf1f7b60976bb9a6 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 4a929eb9ec422e145006505ea4d5fbd1ef3950be Original-Change-Id: I01e80de65e6e1cdcabb24edb43bc671f5a8aa437 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298234 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-17glados: Remove code to set USB charge behavior on sleepDuncan Laurie
The EC doesn't support these commands so sending them is not working. We have had a default policy of wake on USB for a long time now and this runtime config isn't really needed any longer. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Ib789ae3a7ba56a11dfb5918cb40bfa2f044d1dc3 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 0ed7391942afed94bfc7ad04880d4c2b865e5655 Original-Change-Id: I6fe10952f32673a447001b832ac6c6b04b22aef0 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298233 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16riscv-memlayout: fix existing memlayout issues, add sbi interfaceThaminda Edirisooriya
Existing memlayout code placed sections in overlapping areas, and would overwrite the payload if it was large enough. Update memlayout.ld in src/mainboard/emulation/spike-riscv to represent the spike emulator, and add sbi interface which now has room into src/arch/riscv/bootblock.S. Add utility code to qemu-riscv, but emulator itself has yet to be updated to new ISA and as such should not be used. Update Makefile to include all the files necessary for sbi interface. Clean up unused include in src/arch/riscv/include/atomic.h and whitespace in src/mainboard/emulation/spike-riscv/memlayout.ld Fixed whitespace issues in spike_util.c Change-Id: Id97fe75e45ac1361005bec6d421756ee3f98a508 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11370 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-16kunimitsu: Enable ALS connected to ECDuncan Laurie
Kunimitsu has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I7998c19e5514eda781cc20888cdb0732f81389ae Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: a67e5ddfccea0776841fabe04be55c1854bf31f2 Original-Change-Id: I381dc9c5777370df2ea4c41c9e153b3277082718 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298252 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11645 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16glados: Enable ALS connected to ECDuncan Laurie
Glados has an ambient light sensor connected to the EC which is presented to the OS as a standard ACPI0008 device. BUG=chrome-os-partner:43493 BRANCH=none TEST=test ALS functionality on glados P2 board Change-Id: I4a4913a1b407720d85f6e630b674e550bf5e36df Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: aee2b2446ca45039f1b4866feb83754861dba054 Original-Change-Id: I61f3f31ba077f63b36aa0cd9707e128e65c9ea7d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/298251 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11644 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-16kunimitsu: Disable Deep S3 on kunimitsu platformSubrata Banik
This patch will reset Deep S3 flag, hence S3 will work. BUG=chrome-os-partner:40635 BRANCH=None TEST=Build and Boot Kunimitsu and verify S3 is working. Change-Id: Iad87b7a8f7bf560861a270a8c19153cfc3850bc4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: fbfaa29041be49e4c39d19cb94f01ad10d12c7d5 Original-Change-Id: I5ae1738c5de1bee1ad9a45ebde074a6a378492af Original-Signed-off-by: Subrata Banik <subrata.banik@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/297903 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11643 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2015-09-10riscv-trap-handling: Add implementation for trap calls in riscvThaminda Edirisooriya
RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2015-09-10kunimitsu: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: Ia9657f4a39c30ed7a0fd7ca4815bb2614f049911 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 93ae87f2429af5cb9d497f8b5ef8b8dffe370df4 Original-Change-Id: Ifc2f64dc1693e7bd3f5a43144d84ff033b2cfe8b Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297759 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11580 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove functions from acpi_tables.cDuncan Laurie
Remove the acpi_tables.c functions so these functions can move to SOC init code. The file itself is included by x86/arch code and must exist for the build to succeed. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I18e6a0be5eac053598b613b30b622c4963417919 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: af04eb112adf58578c8d2c9d3d182d4c2024abb2 Original-Change-Id: Ibe026d493c25d771357ea39e4b956629fbb799ac Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297758 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11579 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10sklrvp: Remove thermal.h and functions from acpi_tables.cDuncan Laurie
Remove thermal.h as it is not used by this board. Remove functions from acpi_tables.c so they can move to SOC. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-sklrvp coreboot (does not compile due to GPIO changes) Change-Id: I934fcc451a722f853034c0970074ee3259cc704f Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7e3b5c0ed8295091d3d5761b8456f3c13c6bd8bc Original-Change-Id: If855f598e895e38c58657af17130158b2f73de81 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297757 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11578 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Clean up mainboard code to match gladosDuncan Laurie
Clean up the intel/kunimitsu mainboard code to match the code and cleanups in glados. Many of these are trivial changes that do not impact things in a meaningful way but will make it easier to diff the code and keep the mainboards in sync. - use relative path for mainboard includes to make porting easier - fix trivial style issues to match glados so diffs are clean - pull GPIO configuration into gpio.h and use from there - remove thermal.h as it is not used on this board - make info message BIOS_INFO instead of BIOS_ERR - add support for SPD manufacturer and part number in SMBIOS BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I64a053bcec0e0ff25a57f65659f391ab64d9a11a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e47f0fd3e00a665f07098c7ea0018d51b105d1be Original-Change-Id: Ib787f3ccc63115de48c4d608ca2bd81b58d24b6c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297752 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11576 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Select EC PD and software sync and do early initDuncan Laurie
Select the EC PD and software sync kconfig options so they are supported by the mainboard and call the EC early init function to reboot into RO in recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I48316df99b796c568c2481c72588b41f7147bec0 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: c7507470f82848062bc98da809d3c5fe1ca31998 Original-Change-Id: I822aac9c24718f226819e5d3fcc82a4024b7c5a7 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297751 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11575 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10kunimitsu: Select BOARD_ID_AUTO and clean up boardid codeDuncan Laurie
Select the BOARD_ID_AUTO kconfig option to have the coreboot tables populated with the board ID and print it early in romstage as well. Also clean up the code for it. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-kunimitsu coreboot Change-Id: I90bd85ef14543717287cbeaaab77e6c54b94df97 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 1fed7de4a0650a497a240b091fd2eb99d59e1433 Original-Change-Id: I82e9d17ab618b1aae1fd874d9247b7d52b42334d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297750 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11574 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Add Board ID supportDuncan Laurie
Add support for reading board id and populating it in the coreboot tables so it is exposed to payloads. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados and look for reported board ID Change-Id: Iba93a913b67e3b3230aded289c2e25585dec1195 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 472cb7bc84136a1a8b284d661868e64eca4ec004 Original-Change-Id: I478dc0b2f96310b7adbd84701e70598a57306628 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297746 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11570 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Enable DPTFDuncan Laurie
- Add ACPI code for DPTF support with placeholder thresholds - Do not have custom PDL for mainboard - Do not have enable charger control for DPTF as there is already a complicated charge profile in the EC. We may still want to enable this but it would need to be tuned to work well with the EC profile. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I8cd2e0ea9c322ea92c101995e8e706f063428a45 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 55d3614441d6701a6d6f0f9d1ade94364ef2594a Original-Change-Id: Ie4587572742d3bcdba7c008fc195213ac50c9d9e Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297745 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11569 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Misc code cleanupsDuncan Laurie
- romstage.c is using gpio_configure_pads so it should really include soc/gpio.h instead of relying on it to come from "gpio.h" - consistent formatting of array initializers in pei_data.c - remove pei_data->ec_present flag as this is unused in skylake - fix printk level in spd/spd.c to be BIOS_INFO instead of BIOS_ERR - clean up acpi_slp_type usage in ec.c, remove unnecessary post codes, and cleaner console output message. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I0f76a560dc2c4197e66999752c52573ff0278430 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 67c29f900b7709b73bd0d1e0da26f96cca32828b Original-Change-Id: Ia2a320acf879fa85e9f6b06265cfe38e50e51e46 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297744 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11568 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Remove thermal.hDuncan Laurie
The constants defined in thermal.h are never used since there is no defined thermal zone. Remove it to result in less code to worry about in board ports. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: Idb716b47875b20e2110741ae9c154cc52307fbcf Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 01be180b14b5381a8d339dab6c28428c7ac40c10 Original-Change-Id: Ibb710abc301b18d5632f4e01765ea0374b2fe787 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297743 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-10glados: Change include headers to relative pathDuncan Laurie
To make it easier to port glados to a new board name change the include headers to use relative path name instead of including the mainboard name. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-glados coreboot Change-Id: I6d184adab5b6b2df970ddd3998d3413f1330c12e Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 11dd6b73f298cf4867f4a089478132d5e543ea90 Original-Change-Id: Ia8de127fb176784acbbee975e8b950f8c9824c5c Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297742 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09glados: Select EC PD and call early EC initDuncan Laurie
Select the EC PD support in kconfig and call the EC early init code that will reboot into RO for recovery mode. BUG=chrome-os-partner:40635 BRANCH=none TEST=boot on glados in recovery mode Change-Id: Ifa1e2afd91a247c3830d8e705d9d34fb02239fe4 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 135ef6e0e2c4864be1c25a9761e04cfe17aec51e Original-Change-Id: Iac8c092453bfbd94210462be0b377fb77410941d Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297749 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11573 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-09samus: Use EC PD kconfig instead of manual PD rebootDuncan Laurie
Use the new kconfig entry to select the EC PD chip and have it be rebooted before the EC automatically insetad of being done manually by the board. BUG=chrome-os-partner:40635 BRANCH=none TEST=emerge-samus coreboot Change-Id: I9e7baffec500a83af1fcf9b1e43d418489172918 Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 53b086725d9d595e8eff7e1e35b9ba8db17ca199 Original-Change-Id: I9c9a7dd2ba2b78d681b448839f2c5d15ba9dfe60 Original-Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297748 Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11572 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08rk3288: Allow board-specific APLL (CPU clock) settingsDavid Hendricks
This changes the API to rkclk_configure_cpu() such that we can pass in the desired APLL frequency in each veyron board's bootblock.c. Devices with a constrainted form facter (rialto and possibly mickey) will use this to run firmware at a slower speed to mitigate risk of thermal issues (due to the RK808, not the RK3288). BUG=chrome-os-partner:42054 BRANCH=none TEST=amstan says rialto is noticably cooler (and slower) Change-Id: I28b332e1d484bd009599944cd9f5cf633ea468dd Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: d10af5e18b4131a00f202272e405bd22eab4caeb Original-Change-Id: I960cb6ff512c058e72032aa2cbadedde97510631 Original-Signed-off-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/297190 Original-Reviewed-by: Julius Werner <jwerner@chromium.org> Reviewed-on: http://review.coreboot.org/11582 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08veyron: Unify identical mainboardsJulius Werner
This patch removes a lot of code duplication between the virtually identical Veyron Chromebook variants by merging the code into a single directory and handling the different names solely within Kconfig. This also allows us to easily add all the other Chromebook variants that have only been kept in Google's firmware branch to avoid cluttering coreboot too much, making it possible to build these boards with upstream coreboot out of the box. The only effective change this will have on the affected boards is removing quirks for early board revisions (since revision numbers differ between variants). Since all those quirks concerned early pre-MP revisions, I doubt this will bother anyone (and the old code is still available through the Google firmware branch if anyone needs it). It will also expand a recent fix in Jerry that increased an LCD power-on delay to make it compatible with another kind of panel to all boards, which is probably not a bad idea anyway. Leaving all non-Chromebook boards as they are for now since they often contain more extensive differences. BRANCH=None BUG=None TEST=Booted Jerry. Change-Id: I4bd590429b9539a91f837459a804888904cd6f2d Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 10049a59a34ef45ca1458c1549f708b5f83e2ef9 Original-Change-Id: I6a8c813e58fe60d83a0b783141ffed520e197b3c Original-Signed-off-by: Julius Werner <jwerner@chromium.org> Original-Reviewed-on: https://chromium-review.googlesource.com/296053 Original-Reviewed-by: David Hendricks <dhendrix@chromium.org> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11555 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2015-09-08kunimitsu: Modify DQ/DQS mappingMike M Hsieh
Modify DQ Byte Map and DQS Byte Swizzling to match up with design BUG=chrome-os-partner:44647 BRANCH=none TEST=System boot up and pass memory initialization Signed-off-by: Mike Hsieh <mike.m.hsieh@intel.com> Change-Id: I2018b9e6f8b557689d15acfe1f9404a9de5ae3bb Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: 7d0a30d4b12bf4dc588d525399a8d223ff35e3de Original-Change-Id: I6001c853e4c5540717acf813e039c5c5dbe14c78 Original-Reviewed-on: https://chromium-review.googlesource.com/295518 Original-Commit-Ready: Wenkai Du <wenkai.du@intel.com> Original-Tested-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Robbie Zhang <robbie.zhang@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11551 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-14 19:29:29 +0000