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Change-Id: I5beda22208fe17338d4136f9d38fd50e55054b01
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84274
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I140d597750001ad22e2bb1b6971011d2b3bb2bbc
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84272
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Tested on Ubuntu 24.04 by verifying dmesg output and that USB
2.0 and 3.0 devices are registered correctly.
Change-Id: I803a23007f49ea45abc68421e867535081e31b3f
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84271
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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DPTF is not used on this platform so disable the
PCI device.
Change-Id: I763ab948a79e3a020c1b89c69c714dd0d8f54812
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84270
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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These aren't used so remove them.
Change-Id: I6fd33c5242adb93b1251af9c5b11be3734a7aceb
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84269
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Change-Id: I6bab0a316ea7d0f7dfbf599e5c08517cee559635
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84268
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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MAINBOARD_HAS_TPM2 should only be selected for the boards
that have memory mapped TPMs. The ones that use Intel PTT
don't need it.
Change-Id: I02b5b0912afbd7c4634c208bb17db16d0ac7ba99
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84267
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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DPTF is not used on this platform so disable the
PCI device.
Change-Id: I7fa01936568108dd7707a3c2ea7041a1198533b5
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84266
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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These aren't used so remove them.
Change-Id: I6b9cf29843047bff9a37f82b899ff1d10b206888
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84265
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 24.04
No known issues.
https://starlabs.systems/pages/starfighter-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I046e70845a5201d6f6ab062aee91fa8be9728737
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74445
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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- This patch update the original google/fatcat support added
with Meteor Lake support as a workaround.
- Add initial support to build google/fatcat for Panther Lake SOC
- Add soc acpi file entry in mainboard dsdt.asl
BUG=b:348678529
TEST=Build google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d5e
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83419
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: I063062d875be61875da136228db06a39bc434833
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84264
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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The LTE module RW101R-GL provide a hardware pin to enable/disable
WWAN RF function.The function is disabled in default and is
controlled by the AT command.Therefore,set the WWAN_RF_DISABLE
Pin to NC, and it has been pull-high by hardware desgin.
BUG=b:368450447
BRANCH=None
TEST= Build firmware and verify the WWAN on/off function in OS.
Change-Id: I47a28342f67f99c5787077c48a01ddbaa77b5967
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84611
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
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The platform uses eSPI so these are not needed.
Change-Id: I507aa59fcf2540ae6170896a51aa952f5e73eee8
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83691
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add SMMSTORE to the default FMAP to allow using UefiPayload on
this board that requires a non-volatile variable store.
TEST: Booted an UEFI compatible OS using EDK2 as payload.
Change-Id: I32fb0a882c62e42da9f3caec54f8d33333fc8598
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84559
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch updates the naming scheme used for the GPP bridges.
The naming scheme now matches what we also have on phoenix.
Change-Id: I9f740d75a3561dba2ed65acb16bb4259f632307d
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84378
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Change-Id: I7f4f5406df8ff82b8d3052ff0f370c280967affd
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84319
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add wifi sar for bujia.
BUG=b:345364452
BRANCH=firmware-brya-14505.B
TEST=emerge-brask coreboot-private-files-baseboard-brya coreboot
chromeos-bootimage
Change-Id: I5a67f3723a9dc33793a5cd95f9a3a2596c3c1fc6
Signed-off-by: Shon Wang <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84501
Reviewed-by: Jayvik Desai <jayvik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
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GCC with LTO cought this.
Warning:
src/mainboard/google/kahlee/variants/careena/variant.c:44:12: error: 'bid' may be used uninitialized [-Werror=maybe-uninitialized]
44 | if (bid == 7)
| ^
src/mainboard/google/kahlee/variants/careena/variant.c: In function 'car_stage_entry':
src/mainboard/google/kahlee/variants/careena/variant.c:24:18: note: 'bid' was declared here
24 | uint32_t bid;
Change-Id: Ie732b5be5cd9dc0abaf1a5efe023bcb0738dba1d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84206
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: coreboot org <coreboot.org@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This should be the sane default, as having this option enabled when the
AT24RF08C (Asset Identification EEPROM) is not present on the mainboard
can cause SMBIOS table entries to become "*INVALID*". This can,
for example, result in strange hostnames when an OS installer uses
SMBIOS information to automatically generate one. On the other hand,
the coreboot generated SMBIOS tables will at least always contain basic
information. Therefore, this driver should be treated as an enhancement
rather than a default.
Currently, the following mainboards have this option disabled:
- ThinkCentre M710s
- ThinkCentre M700 / M900 Tiny
- Haswell ThinkPads
- ThinkPad T440p
- ThinkPad W541
Therefore, we can remove this option entirely on these mainboards. Note
that there may be other mainboards which do not have this chip present
but still have the option enabled. However, this requires a more
detailed investigation which would be out of scope of this change.
TESTS=Timeless builds on lenovo mainboards produce the same binary.
config INCLUDE_CONFIG_FILE
default n
Was temporarily added to `mb/lenovo/Kconfig` during these tests, as
while the configuration does not change, the order of entries do.
Therefore, technically producing a different binary when included.
Change-Id: I5bb101bd6696c39718ee779426d0ec3e721e1b51
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84544
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Add two new memory parts
1. K3KL8L80CM-MGCT (Samsung)
2. H58G56BK8BX068 (Hynix)
BUG=None
TEST=Run part_id_gen tool and check the generated files.
Change-Id: I557b359d9e639f6c3fac4239eb28aa7e0bed4c0e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84529
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: Ibb167b8dc379ca331812255c3e7e049556f2b57b
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84502
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sean Rhodes <sean@starlabs.systems>
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This corrects the mismatch found in the verb tables of Monroe Chromebase
and Link Chromebook.
The verb data was not aligned to a multiple of 4, therefore an entry was
repeated as padding.
This was found due to the `_Static_assert()` from CB:84360 failing.
TEST=Tested on LINK under Linux and Win11, audio working properly under both.
Change-Id: Id377281af310642a6ba77e5a0002ca1dfca38827
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84414
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The verb data was not aligned to a multiple of 4, therefore an entry was
repeated as padding. This has not been tested.
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I3a40e6229419ee7d1a238916ee6d49cf9314f6ab
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84395
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Poweroff does not seem to use the ACPI _OFF function, but rather the
smihandler. Creating variant_smi_sleep function for nami to handle
the power off sequence during reboot/poweroff.
BUG=b:364193909
TEST=emerge-brox coreboot
Change-Id: I0108be4e5e7c0265aae0f16fd4e2b7cbe5936112
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84412
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Update DTT settings according to b:348285763#comment20 in
order to increase the limit of the charging current to 3A.
BUG=b:348285763
TEST=emerge-brox coreboot, and thermal engineer verifies OK.
Change-Id: I24978afd819666f635c85f2be9b71d39e0a39f27
Signed-off-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84527
Reviewed-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Modify start-up timing for WWAN RW101R-GL to follow spec:
PWR_EN H H H
FCPO# Tpr H H
RESET# L Ton H
Tpr: delay for Power stable (>0ms)
Ton: delay for reset time (>20ms)
BUG=b:349698817
BRANCH=None
TEST= Build firmware and verify on jubilant with RW101R-GL
Measure the start-up timing sequence to meet spec
Boot up in OS, and confirm WWAN can connect to cell site
Change-Id: I7aa3e7a172143ff1cebea7f48bda45d4fb2c77f7
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84413
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Add wifi sar table support for fatcat. Bit 4-5 in CBI/FW_CONFIG
is used to select different sar table (index 0 to 3).
BUG=b:348678529
TEST=emerge-fatcat coreboot chromeos-bootimage
Change-Id: I2d82f76d7c11378ee5c221a6b9621b4cba83720d
Signed-off-by: YH Lin <yueherngl@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pranava Y N <pranavayn@google.com>
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Add support for the ODROID-H4 family of boards. Tested on an ODROID-H4+
board, but all of them use the same PCB (with different components).
The four SATA ports on the mainboard are provided by an onboard ASMedia
ASM1064B PCIe-to-SATA bridge. Unlike other mainboards in the tree using
an ASMedia ASM1061 or ASM1062 PCIe-to-SATA bridge, the ODROID-H4+ comes
with a SPI flash chip for the ASM1064B and does not seem to have issues
regarding PCIe power management (e.g. ASPM) or unusable SATA AHCI mode.
The ODROID-H4 comes with a single 16 MiB SPI flash chip. The ODROID-H4+
and the ODROID-H4 Ultra feature Dual BIOS, consisting of another 16 MiB
SPI flash chip and a 3-pin header to select between them. The board can
be flashed internally or using a SOIC-8 clip, but the M.2 slot may need
to be empty for the clip to fit.
Working:
- DDR5 SO-DIMM slot
- All SATA ports on ASMedia ASM1064B PCIe-to-SATA controller
- UART to emit spam
- All video outputs (FSP GOP only lights up one output at a time)
- All USB ports (on the Ethernet connectors and on EXT_HDR1)
- M.2 M connector (PCIe only)
- PCIe power management
- Ethernet NICs
- eMMC
- HD audio codec and display audio
- S3 suspend/resume
- SeaBIOS <current version>
- MrChromebox edk2 <current version>
- Super I/O HWM on Linux (using out-of-tree it87 kernel module)
- Booting Arch Linux from NVMe and SATA
- Booting Windows 10 from NVMe
Not working:
- PECI: undocumented protocol and undocumented Super I/O
- Resuming on Windows 10 BSODs with `VIDEO_TDR_FAILURE`
Untested:
- Fan curves: may need to lower the temperature limits a bit
Change-Id: I7e0d395ba3d15dfcf6d47a222b90499ca371e4eb
Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83979
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Trulo ISH uses the MAIN FW loaded by the kernel driver. This commit
enables DRIVER_INTEL_ISH_HAS_MAIN_FW for trulo, which skips printing the
ISH BUP version.
BUG=b:360144613
TEST=Local build successful and tested on trulo by toggling the
config. enabling this config skips printing the ISH version in cbmem.
1. CONFIG enabled
```
trulo-rev1 ~ # cbmem -c | grep ISH
[INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin
```
2. CONFIG disabled
```
trulo-rev1 ~ # cbmem -c | grep ISH
[DEBUG] ISH version: 5.4.2.36864
[INFO ] \_SB.PCI0.ISHB: Set firmware-name: ish_fw.bin
```
Change-Id: Ifebd563ec8ddb0378e1215a90396687857f3f71d
Signed-off-by: Jayvik Desai <jayvik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84494
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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BUG=b:348678529
TEST=Able to build google/fatcat.
Change-Id: I5c90aac4873dcc57e65e641656dca3a96f84d6b8
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84543
Reviewed-by: Pranava Y N <pranavayn@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Change-Id: Ida2499d9894aa99f341c7a6ef2cd93b3f8ea61fe
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84437
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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This also updates the mainboards depending on it.
Change-Id: I1138f27bfd47f6fa70a0c2afcc65a5553a609d57
Signed-off-by: Maximilian Brune <maximilian.brune@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84376
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add default value in nissa and trulo devicetree.cb, ODM have to review
the board design to follow RDC#646929 Power Map requirement.
NOTE: The VccInAuxImonIccImax remains unchanged w/ and w/o this CL.
BUG=b:330117043
BRANCH=firmware-nissa-15217.B
TEST='emerge-nissa coreboot chromeos-bootimage'
Change-Id: Iaedd34757aa6802edcae402e751bc39b9cfe9e0c
Signed-off-by: Simon Yang <simon1.yang@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83725
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Enable the AST 2600 native graphics init driver to have a working
UEFI firmware menu displayed over KVM.
Change-Id: I2961576077ed3286df080cd09ffe68d835d8c3e7
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84427
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
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Update PCIe Segment, Bus, Device & Function for various IIO bridge
devices.
Change-Id: I01d164cf0717b3e817348e64e32478c2bb11a8b8
Signed-off-by: Naresh Solanki <naresh.solanki@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82900
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
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For next DVT build, hw adds this power ctrl.
BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: Id256b3a94d3c8ed6f6832d63ecc74c2438c7d15a
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84254
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When battery not present, increase PL4 limit from 9 to 40.
Get PL setting from internal thermal and power team.
AC+DC/DC:
PL1=15W
PL2=25W
PL4=114W
AC ONLY:
PL1=15W
PL2=25W
PL4=40W
BUG=b:355094551
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Confirm on lotso EVT board, as expected.
Change-Id: I5848c776399a1bdc455db604bb3b22d16f6b2928
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84202
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
BUG=b:342929824
BRANCH=None
TEST=boot to kernel success
Change-Id: Ibc13137488948ec6cea1904b3964ffed4ff7ea7d
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84499
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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We use ALC256 as HDA codec on fatcat hence, added the verb table.
BUG=b:348678529
TEST=Tested audio playback using HDA ALC256 codec on PTL reference
board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d55
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84409
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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BUG=b:348678529
TEST=Memory training is successful on google fatcat board
Change-Id: I914f73ff06bfb801fc319b45b23d7ce4cb7a6d51
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84406
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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This commit updates the fatcat mainboard to use the Panther Lake SoC
instead of Meteor Lake.
The changes include:
- Selecting the `SOC_INTEL_PANTHERLAKE_U_H` config option.
- Updating the `mainboard_update_soc_chip_config()` function to use the
`soc_intel_pantherlake_config` struct.
- Updating the devicetree to use the `soc/intel/pantherlake` chip.
- Updating variant header files to reflect the SoC change.
This update enables support for the Panther Lake SoC and its
features on the fatcat mainboard.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: Ie0c6257dfb9dd1f627472ad220614f9b24c911ef
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84537
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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This commit removes the virtual GPIOs for recovery and write protection
from the fatcat variant.
These GPIOs are not utilized on the fatcat platform, and their removal
simplifies the GPIO configuration and improves code readability.
The `CROS_GPIO_DEVICE_NAME` macro is no longer applicable for Panther
Lake SoCs. Future changes will introduce a suitable GPIO device name
that meets the requirements of Panther Lake.
BUG=b:347669091
TEST=Able to build google/fatcat.
Change-Id: I492fec28637edb2f84e9290b28dabce3f23aa867
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84536
Reviewed-by: Pranava Y N <pranavayn@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable the SOC_INTEL_COMMON_BASECODE_RAMTOP Kconfig option for the
google/vell mainboard. This option ensures improving the boot time
on google/vell by 40ms in an average.
BUG=b:352330495
TEST=Able to reduced google/vell boot time by 40ms.
Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: Iedfd346c62b1ac79796042dd3569d846007b8f10
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84525
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
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|
Deku S0ix is blocked by the SSD. Enable RTD3 for the SSD to unblock
S0ix. RTD3 for SSDs has already been enabled on Rex and Screebo, too.
To prevent this S0ix blocking issue, RTD3 should also be enabled for
Karis.
BUG=361011799
TEST=Run suspend_stress_test and check whether DUT can enter S0iX.
suspend_stress_test w/o this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Suspend failed, s0ix count did not increment from 19182060
Substate Residency
S0i2.0 0
S0i2.1 0
S0i2.2 0
And PC10 residency is only 60% (by SoCWatch)
suspend_stress_test w/ this CL
(with Phison PCIE Gen4 SSD PSENN256GA87FC0)
Substate Residency
S0i2.0 0
S0i2.1 19186
S0i2.2 3389654
And PC10 residency is ~90% (by SoCWatch)
Change-Id: Iaded43a84ad1e245106d36a9d4aa83c40b046649
Signed-off-by: Curtis Chen <curtis.chen@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84452
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Select SOC_INTEL_RAPTORLAKE to force coreboot to use the RPL FSP headers
for FSP as vell is using a converged firmware image.
This effort also helps to save vell boot time by 80-100ms as RPL FSP is
better optimized.
Additionally, Raptor Lake platform only needs 1 SIPI-SIPI which saves
10ms of the boot time.
BUG=b:352330495
TEST=Able to build and boot google/vell.
warm reboot time w/o this CL
```
Total Time: 1,408,669
```
warm reboot time w/ this CL
```
Total Time: 1,235,651
```
Change-Id: I8f7dd76f00cfeff2908aeb805524706ac23403fa
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84491
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch disables unused I2C6 controller for the 'vell' variant of
the 'brya' mainboard.
BUG=b:352330495
TEST=Able to build and boot google/vell.
Change-Id: I5b39e44bb64bf2285c962249c0d94a8d5325f0c7
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84490
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Menu option wasn't showing due to wrong config flag.
Change-Id: I30592a8c3e57017473511366a8cf11928e55b5e9
Signed-off-by: Ana Carolina Cabral <ana.cpmelo95@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84438
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Create the kanix variant of the rex0 reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.5.0).
BUG=b:368501705
TEST=util/abuild/abuild -p none -t google/rex -x -a
make sure the build includes GOOGLE_KANIX
Change-Id: Id74a084ed3cebb65625166e3098f43e41a63f5f9
Signed-off-by: Tyler Wang <tyler.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84432
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Earlier change (https://review.coreboot.org/c/coreboot/+/84019)
pushed to resolve the privacy LED blinking issue regressed the camera
autofocus functionality. This change updates the power resource for
NVM and VCM in line with the tivviks schematics to fix the issue.
BUG=b:365899407
TEST=Build and boot tivviks. Verified the Autofocus and all the
camera basic sanity tests.
Change-Id: Id3e256d59982ac176844e289f18ee450079704b9
Signed-off-by: Sowmya V <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84420
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
|
|
Compared to MT8186, MT8186T requires initializing the PMIC MT6319 in the DTS file, which necessitates using different SKU ID to distinguish between the MT8186 and MT8186T.
For MT8186, factory pre-flashed 0x7fffffff as unprovisioned SKU ID and
kernel can use the corresponding DTS file. To make MT8186T functional
on unprovisioned devices, change the SKU ID to 0x7ffffeff, so that the
correct DTS file will be selected by the payload.
BUG=b:365730137
TEST=1. Pre-flashed 0x7fffffff and boot OS.
2. Check OS boot normally by 0x7ffffeff.
BRANCH=corsola
Change-Id: I91306d3abd508e104851916882fb36a4fd302036
Signed-off-by: Yang Wu <wuyang5@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84342
Reviewed-by: Knox Chiou <knoxchiou@google.com>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yidi Lin <yidilin@google.com>
|
|
This patch updates the fatcat flash map layout to accommodate the growth
in Panther Lake IFWI blobs over Meteor Lake.
Release FMD:
SI_ALL: 8MB -> 9MB
SI_BIOS: 24MB -> 23MB
RW_UNUSED: 4MB -> 3MB
Debug FMD:
SI_ALL: 8MB -> 9MB
SI_BIOS: 24MB -> 23MB
RW_UNUSED: 3MB -> 2MB
TEST=Able to build google/fatcat inside chroot.
Change-Id: I8febb4df5d3b3eb07ebff8e56a1ce2dfd2f52e7d
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84453
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Pranava Y N <pranavayn@google.com>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I6012fd948b4350bda7af5390badac737553fa872
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84430
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I08881e3fb25abca8c34a04b3bea6534c0dbf391a
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84424
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Due to beadrix DB has C1 port before, and add FW_CONFIG without C1 port for LTE sku.
BUG=b:364431483
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Set fw config to DB_PORTS_LTE and check
1.fw_config match found: DB_PORTS=DB_PORTS_LTE <= show LTE present message
2.USB3 port 3: enabled 1 <= LTE port enable
Change-Id: Ica5a2d6e19421b132a0bdbad77806a17e2c1ce69
Signed-off-by: Kevin Yang <kevin.yang@ecs.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84232
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
psys is not an optimal solution for no/low battery boot. Hence remove
function and macros related to psys implementation.
BUG=b:335046538
BRANCH=None
TEST=Build and boot on brox board
Change-Id: I6c0e9561367b5846b00be27012f002dd7c299414
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84397
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ashish Kumar Mishra <ashish.k.mishra@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I01db9dad872cd4c9238b6c6aac73f3e6367710a4
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84416
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I3870bcd2482e55a5abcbd27cd0be18f25a35afbc
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84415
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Add gfx register so GMA ACPI data is generated. Fixes brightness
controls on Windows.
Change-Id: I10948fb2ba670ba5232f1b116acdd1820ad0c07d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84224
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
According to the CL:chrome-internal:7651905,
Riven will use the fw_config to separate SAR setting.
CNVI + ID_0 --> wifi_sar_0.hex for WIFI6
PCIE + ID_1 --> wifi_sar_9.hex for WIFI7
BUG=b:366060274
TEST=build, enabled iwlwifi debug, and check dmesg as below.
iwl_sar_fill_table Chain[0]:
iwl_sar_fill_table Band[0] = 132 * .125dBm
iwl_sar_fill_table Band[1] = 136 * .125dBm
iwl_sar_fill_table Band[2] = 136 * .125dBm
iwl_sar_fill_table Band[3] = 136 * .125dBm
iwl_sar_fill_table Band[4] = 136 * .125dBm
iwl_sar_fill_table Band[5] = 144 * .125dBm
iwl_sar_fill_table Band[6] = 144 * .125dBm
iwl_sar_fill_table Band[7] = 144 * .125dBm
iwl_sar_fill_table Band[8] = 144 * .125dBm
iwl_sar_fill_table Band[9] = 144 * .125dBm
iwl_sar_fill_table Band[10] = 144 * .125dBm
iwl_sar_fill_table Chain[1]:
iwl_sar_fill_table Band[0] = 132 * .125dBm
iwl_sar_fill_table Band[1] = 136 * .125dBm
iwl_sar_fill_table Band[2] = 136 * .125dBm
iwl_sar_fill_table Band[3] = 136 * .125dBm
iwl_sar_fill_table Band[4] = 136 * .125dBm
iwl_sar_fill_table Band[5] = 144 * .125dBm
iwl_sar_fill_table Band[6] = 144 * .125dBm
iwl_sar_fill_table Band[7] = 144 * .125dBm
iwl_sar_fill_table Band[8] = 144 * .125dBm
iwl_sar_fill_table Band[9] = 144 * .125dBm
iwl_sar_fill_table Band[10] = 144 * .125dBm
Cq-Depend: chrome-internal:7651905
Change-Id: I647d64a008991a7a20791b2c87ea6308af6bb82e
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84339
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
|
The real-time feature should also be activated for all mc_ehl
mainboards, as it has already been done for mainboard mc_ehl1. It
improves performance in the real-time environment for these mainboards.
Change-Id: I04859b2f32bc11344b0620925f2414e7a6df625e
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84391
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
The ordering of the USB-C port locations is swapped. When facing the
left panel, the correct ordering is port 1 (left) then port 0 (right).
Swap the positions of the two USB-C ports to their correct values.
BUG=b:349822718
TEST=Booted to OS, confirmed correct physical_location at
/sys/class/typec.
Change-Id: I98e3042c64aba885b602c99916734c2dbb9d66bd
Signed-off-by: Jameson Thies <jthies@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84403
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I60bb9e7df368b786e17bb49a6f35d27372fd21de
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84394
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This was found due to the `_Static_assert()` from CB:84360 failing.
Change-Id: I5cf34d8c4e27835d126eb66f2015d2e9d93b700f
Signed-off-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84396
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
|
|
This commit drops redundant CRASHLOG option for the brox and brya
mainboards as SOC_INTEL_CRASHLOG config is now selected by the
Alder Lake SoC directly.
TEST=Able to build and boot google/brox w/o any functional impact of
the crashlog feature.
Change-Id: I83859d6e61a151d6930785df3466c185c69e8e66
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84366
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch configures the GPIO pins for ISH to notify EC about the
tablet mode change in accordance with schematic_20240607.
BUG=b:347811875
TEST=Build and boot google/trulo. Placed the device in tabletmode & on
EC console,"tabletmode" command shows "tablet mode".
Change-Id: Id22e397e46b522428ffdabe34a445ed7e4fb6fc5
Signed-off-by: Varun Upadhyay <varun.upadhyay@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84351
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BRYA0 and BOARD_GOOGLE_BRASK.
BOARD_GOOGLE_BRYA_COMMON already selects a crashlog config, and
brya0/brask board eventually selects the BOARD_GOOGLE_BRYA_COMMON
config, making SOC_INTEL_CRASHLOG redundant.
TEST=Successfully built and booted google/brya0.
Change-Id: Iaff7954d4dafb4c6ca72a1521dfb434fb36b495a
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84364
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
This patch removes the redundant crashlog config (SOC_INTEL_CRASHLOG)
entry from BOARD_GOOGLE_BASEBOARD_BROX. BOARD_GOOGLE_BROX_COMMON
already selects a crashlog config, and brox baseboard eventually selects
the BOARD_GOOGLE_BROX_COMMON config, making SOC_INTEL_CRASHLOG
redundant.
TEST=Successfully built and booted google/brox.
Change-Id: Idcb03d13ee3943f188246663d47f47cb8afccbd9
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84363
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Commit bc8f5405b542 ("tgl mainboards: Move usb{2,3}_ports settings into
XHCI device scope") not only moved the USB port definitions under the
XHCI device reference, but also combined multiple register definitions.
In doing so, it broke the inheritance from the baseboard, since the
variant overridetree registers now replaced the entire usb2_ports/
usb3_ports structs, rather than replacing individual array elements
therein. This resulted in any USB ports inherited from the baseboard
and not overridden by the variant being non-functional as they were
not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/drobit. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I54921fa4ecf594a1ecbcfa7c45e5d745d4a95652
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84348
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
1)Modify jubilant cpu power limit setting depend on the brox
baseboad settgins,refer to CL:
https://review.coreboot.org/c/coreboot/+/83752
2)Update PL1,PL2, and PL4 value from jubilant thermal design
PL1 = 15W
PL2 = 41W
PL4 = 87W
BUG=b:364441688
BRANCH=None
TEST=Able to successfully boot on jubilant photo SKU1 and SKU2
boards with AC w/o battery.
Test on AC 65W and 45W w/o battery,and check the PL values.
Change-Id: I9a143d9faaa6c57b0d314c0ff6c0e55f556d7216
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
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|
Change-Id: I88baa159475ac57ec6a2a638ab84f76a6af4fe82
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84318
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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When battery is disconnected and only adaptor is connected higher PL2
power draw causes cpu brown out and system does not boot to kernel. To
avoid this set Boot frequency UPD to 1. Reduce PL4 value to overcome
power spikes from SoC during boot. Remove Psys implementation as it
impacts active state platform performance.
BUG=b:335046538,b:329722827
BRANCH=None
TEST=Able to successfully boot on 3 different Brox proto2 SKU1
and SKU2 boards with 65W, 45W and 30W adaptors for 3
iterations of cold boot.
Change-Id: I58e136c607ea9290ecac0cee453d6632760a6433
Signed-off-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83752
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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It return 0 when google_chromeec_command() on success, so
get_input_power_voltage() should return adaptor voltage instead of
psys_config default value.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= cbmem -c | grep -i PsysPmax
Change-Id: I848c92752b7a7b53f47c6296aad0bdda20e9b0bd
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84333
Reviewed-by: Derek Huang <derekhuang@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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To publish the Bluetooth Regulator Domain Settings under the right
ACPI device scope, the wifi generic driver requires the bluetooth
companion to be set accordingly.
BUG=b:362672785
TEST=Build Brox firmware and boot to OS. Ensure that the BRDS table is
populated under the right ACPI device scope.
Scope (\_SB.PCI0.XHCI.RHUB.HS10)
{
Name (BRDS, Package (0x02)
{
0x00000001,
Package (0x0A)
{
0x00000012,
0x00000001,
0x00000001,
0x7C,
0x70,
0x70,
0x70,
0x70,
0x70,
0x70
}
})
}
Change-Id: I9a74a995bca8d412b85c243c7f2f98c9917b5e76
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84296
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Bob Moragues <moragues@google.com>
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Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.
BUG=b:363854853
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I386f8e88a5af661b1f4c04d2e2a34cd181608bd8
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84278
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: <srinivas.kulkarni@intel.com>
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Clean up redundant `struct pad_func` and `PAD_*` definitions. This patch
also refactors the PAD_* macros by,
- Repurposing PAD_FUNC and dropping PAD_FUNC_SEL.
- Adding PAD_FUNC_DOWN and PAD_FUNC_UP to avoid the implicit
initialization.
BUG=none
TEST=emerge-{elm, kukui, asurada, cherry, corsola, geralt, rauru} coreboot
Change-Id: I12b8f6749015bff52988208a7c3aa01e952612c6
Signed-off-by: Yidi Lin <yidilin@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84222
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Remove PL4 value modification based on PsysPL3 value.
BUG=None
BRANCH=None
TEST=Built and boot on brox system
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: Ic7fbc6386769aa9f76a8665a742c97dfd790fd1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83662
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Sowmya Aralguppe <sowmya.aralguppe@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Correct the number of NID entries.
BUG=b:349996984
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I5f5553a5d8014f957d6b89ac4c1039594817bf32
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84184
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Enable ASPM of CPU PCIe4 for SSD to improve power consumption.
BUG=b:364441213
BRANCH=None
TEST="sh -c 'lspci -vvnn || lspci -nn'"
01:00.0 Non-Volatile memory controller
LnkCtl: ASPM L1 Enabled
Change-Id: I4380bb8748f2847b1824e20edb19578c7aedfe4f
Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84279
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
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Change-Id: Ifbe76bd69d847603345a4a1fa4f41e529634fa92
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84158
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Change-Id: I84aad5497d17065f9d42776452f2d2d24cd50a91
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84157
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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lpss_s0ix_enable is already defined as boolean:
`git grep lpss_s0ix_enable $(find -type f -name "*.h")
src/soc/intel/apollolake/chip.h: bool lpss_s0ix_enable;`
Change-Id: I34bd568defe202daaad6136b9c184bc292a226b3
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84160
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
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Check that lnkCap supports ASPM L1, so set it to ASPM_L1
to avoid excessive power consumption.
BUG=b:364484621, b:361828368
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
w/o this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
LnkCtl: ASPM Disabled; RCB 64 bytes, LnkDisable- CommClk+
```
w/ this CL -
```
lspci -vv | grep -A30 "KIOXIA" | grep -E "LnkCap|LnkCtl"
LnkCap: Port #0, Speed 16GT/s, Width x4, ASPM L1, Exit Latency L1 <64us
LnkCtl: ASPM L1 Enabled; RCB 64 bytes, LnkDisable- CommClk+
```
Change-Id: I8a7f69bb82ad24b29566541d7694f87f9c6458d6
Signed-off-by: Wentao Qin <qinwentao@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84241
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: wen zhang <zhangwen6@huaqin.corp-partner.google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Change-Id: I7050a4d12efd65c7026abf3e45961e2061b7170a
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84263
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
These aren't used so remove them
Change-Id: I340b3474fba1bc7fbde520138ae99c3e355882bf
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84262
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
Change-Id: I63612af7320dfdbe57029b898b4cf07e9d6f13b0
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84261
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
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Now that the USB configs are in the devicetree, only the
bootblock_mainboard_early_init function remains in early_init.c. It is
identical between every variant except the E6230, which enabled fewer
decode ranges in the LPC_EN register. Enabling the additional decode
ranges probably shouldn't cause issues, so go with the majority.
TEST=Timeless builds do not change with the exception of the E6230.
Change-Id: Ic43915888f5893652991b7402ebab3bd3a2cf278
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84097
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
|
|
Update eMMC DLL tuning values for improved initialization reliability.
BUG=b:361013271
TEST=Cold reboot stress test over 2500 cycles
Change-Id: Icd1f9c7bdec2bc99152a13ac4ce0724a26718a52
Signed-off-by: Qinghong Zeng <zengqinghong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84248
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Joxer experienced error messages during developer mode entry due to
failed USB-C1 probing.
This patch adds the `DB_USB DB_1C` probe directive to the `conn1`
device in the overridetree, ensuring USB-C1 is only probed when
`FW_CONFIG` supports the applicable hardware SKU.
This should resolve the error flood seen during dev mode entry on
Joxer.
BUG=b:364240631
TEST=Able to build and boot google/joxer to OS without any error.
w/o this patch:
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
update_all_tcss_ports_states: port C1: get_usb_pd_mux_info failed
send_packet: CrosEC result code 9
send_packet: CrosEC result code 3
Failed to get PD_MUX_INFO port1 ret:-3
w/ this patch:
No error reported during dev mode entry
Change-Id: I8cdefa01409d5a8a75032f30dacde40057e064dd
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
|
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Add a Kconfig choice to select the IGD UMA allocation, which selects a
precompiled ACPB binary with the corresponding UMA value set. Default
to the previous value (128MB) for non-ChromeOS builds, and 64MB for
ChromeOS as that is the value used there.
TEST=build/boot google/morphius, verify UMA size changes with selection
via dxdiag tool under Windows.
Change-Id: I6debd10527c33ce37ef3ada20955c8f7b7500039
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84237
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Use the AZALIA_PIN_DESC macro from include/device/azalia_device.h
instead of magic numbers, as well as the enums for each of the register
field values. The macros were generated by running util/hda-decoder
against the original azalia logs used for the original board ports.
TEST=Timeless builds for all variants did not change between main
and this patch
Change-Id: If5ecee39efbddbba101f820dead82efcb848b6bc
Signed-off-by: Nicholas Chin <nic.c3.14@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84099
Reviewed-by: Nicholas Sudsgaard <devel+coreboot@nsudsgaard.com>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Elyes Haouas <ehaouas@noos.fr>
|
|
Add a Kconfig choice to select the IGD UMA allocation. Default to the
previous value (32MB).
TEST=build/boot google/liara, verify UMA size changes with selection.
Change-Id: Ia53d6d39d4f06c896ec13808234144b89da101f8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84235
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Reduce resume time.
BUG=b:361728839
TEST=emerge-dedede coreboot chromeos-bootimage
& test touchscreen function on awasuki DUT
Change-Id: I32b2b1c709ecab964a0e449d416c5d0ee2c1d97d
Signed-off-by: Tongtong Pan <pantongtong@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84196
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Weimin Wu <wuweimin@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Tested using `edk2` from
`github.com/starlabsltd/edk2/tree/uefipayload_vs`:
* Windows 11
* Ubuntu 22.04
* Manjaro 22
No known issues.
https://starlabs.systems/pages/byte-specification
Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: Idff2d883a8c29f0fee9d633708aac92061a45132
Reviewed-on: https://review.coreboot.org/c/coreboot/+/80705
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
|
|
According to the Intel OPS spec, the DC power from display is
12~19V@8A max. It can't set PsysPmax by unknown voltage, so get
voltage by ec command "ectool adcread 4" then calculate PsysPmax value.
The OPS display can supply 90W power, configure psys_pl2 to limit
the system power to 90W.
BUG=b:329037849
BRANCH=firmware-brya-14505.B
TEST= USE="fw_debug" LOCALES="en" emerge-brask chromeos-bmpblk
intel-rplfsp intel-adlfsp coreboot chromeos-bootimage
Check adcread value by ectool adcread 4. If get 19540, PsysPmax
should be 19540 * 8000 ~= 156 W.
Check FSP debug log have the following message.
PsysPmax = 156W
Change-Id: Ic6e9c6ce9f3179c7d63c1169695fbc23188456dd
Signed-off-by: Shon <shon.wang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83593
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Derek Huang <derekhuang@google.com>
|
|
Add control for the 1.2V enable pin in VCM to comply the mipi camera
power sequence.
2.8V enable --> 1.2V enable --> reset
BUG=b:362386165
TEST=Run ITS test
Change-Id: I495b2e266ee3d24ed3334bb9c173b3993d095e8e
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84211
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
|
|
Based on schematics NB7228A_LOTSO_INTEL_MB_PROTO_20240521A_BOM.pdf update devicetree settings.
BUG=b:333494257
TEST=emerge-brox coreboot chromeos-bootimage and boot on
Change-Id: Id8f30597ef9bceb9bdd4a3267266f1d189aa6fd8
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84198
Reviewed-by: Paul Menzel <paulepanter@mailbox.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Power consumption according to RTS5227 datasheet section 6.4, L0s is not supported, so set it to ASPM_L1.
lspci -vvvv -s 01:00 to verify LnkCtl: ASPM L1 Enabled.
BUG=b:359409425
TEST=emerge-brox sys-boot/coreboot sys-boot/chromeos-bootimage
Change-Id: I87bb0d195566d273951dee6eeb54c9b388dd7607
Signed-off-by: Jian Tong <tongjian@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84177
Reviewed-by: Kun Liu <liukun11@huaqin.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
|
|
Update PL1 Min value from 6W to 15W based on the brox thermal cooling
capacity and hardware design.
BUG=None
BRANCH=None
TEST=Build and boot on brox board
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Change-Id: I266a78806e065bf7af0d5fcad9b22ab63aa892e2
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83661
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
When world-facing camera is absent, coreboot need to enable
GPP_R6(DMIC_WCAM_CLK) and GPP_R7(DMIC_WCAM_DATA) for 3rd dmic support
BUG=b:333973512
TEST=Boot google/riven to OS and verify 3rd dmic working properly.
Change-Id: I6c8780ce37b5d3987f5cdf6e6e6d0b4896b33230
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84141
Reviewed-by: Eric Lai <ericllai@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Jayvik Desai <jayvik@google.com>
Reviewed-by: Subrata Banik <subratabanik@google.com>
|
