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2014-01-19jetway/j7f24: Rename to jetway/j7f2.Vladimir Serbinenko
Original actually meant j7f[24] which without square brackets became confusing. There is no such board as j7f24. This is a prerequisite to adding j7f4* as cloned boards Change-Id: Ia7708b13ac4141ef788183c7817fce1366919936 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4728 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-19via/epia-mii and via/epia-ml: Add as clones of epia-m.Vladimir Serbinenko
Change-Id: I4f297e7a7332acc6ceda6a99981599e3a372b696 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4727 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-18iei/rocky-512: Add it as an explicit clone of juki-511p.Vladimir Serbinenko
Change-Id: I87e2768de6728658a87729998648514824d79fd6 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4726 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2014-01-18A8N-SLI: Add it explicitly as a clone of A8N-EVladimir Serbinenko
Change-Id: Ieab7d46177eb92393914f8cb055675df00a9a375 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4723 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-16butterfly: fix compilation with !CHROMEOSVladimir Serbinenko
One of arguments to cbfs_get_file_content was missing. Change-Id: Icb4ef26f18d63c133bc32f1c62a524edee0621ea Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4696 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-15ROMSIZE: Add option for 12M chips.Vladimir Serbinenko
On X230 2 real chips (8 + 4) are merged into one virtual 12M chip. Change-Id: I49c251b1777fc9edccebc4a204b9c4a087bf2a8e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4688 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-15Intel (sandy/ivy): Avoid calling cbmem_initialize() twiceKyösti Mälkki
Delay the copying of MRC cache data from CAR to CBMEM until after sdram_initialize() returns and cbmem_initialize() completes. Calling cbmem_initialize() twice would complicate the decision logic of when CBMEM area needs to be wiped clean. Change-Id: Ic59e94cb2436293efc47b52f7418f5dbf76c714a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4666 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15google/stout: Add EARLY_CBMEM_INITKyösti Mälkki
Required for MRC cache and for HAVE_ACPI_RESUME to work. Change-Id: I7d48b167bd581d7c14ca50bd46e74be0133cecfb Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4665 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com>
2014-01-15Re-declare CACHE_ROM_SIZE as aligned ROM_SIZE for MTRRKyösti Mälkki
This change allows Kconfig options ROM_SIZE and CBFS_SIZE to be set with values that are not power of 2. The region programmed as WB cacheable will include all of ROM_SIZE. Side-effects to consider: Memory region below flash may be tagged WRPROT cacheable. As an example, with ROM_SIZE of 12 MB, CACHE_ROM_SIZE would be 16 MB. Since this can overlap CAR, we add an explicit test and fail on compile should this happen. To work around this problem, one needs to use CACHE_ROM_SIZE_OVERRIDE in the mainboard Kconfig and define a smaller region for WB cache. With this change flash regions outside CBFS are also tagged WRPROT cacheable. This covers IFD and ME and sections ChromeOS may use. Change-Id: I5e577900ff7e91606bef6d80033caaed721ce4bf Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4625 Tested-by: build bot (Jenkins) Reviewed-by: Vladimir Serbinenko <phcoder@gmail.com>
2014-01-14cubieboard: Setup CPU clock in romstage and load ramstageAlexandru Gagniuc
This completes the romstage for the cubieboard. Change-Id: If3272d8a9e414f782892bc41b34b5e2dece5d7e1 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4686 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-13cubieboard: Configure system voltages from devicetreeAlexandru Gagniuc
Change-Id: I93bac9bf94f5bafcd3ff0c3d5763b31d3ee9959b Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4640 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-12X60: Enable WWAN by default.Vladimir Serbinenko
Change-Id: I8e51a8fc03c1d7dbbdc11b121b3ea3ec18f65a5a Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4670 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Make trackpoint enable a CMOS option.Vladimir Serbinenko
To be consistent with touchpad counterpart. Change-Id: I72d09b41b964f80a81fbf409ef69dd368834a3e2 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4654 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Remove trackpoint_enable from device tree.Vladimir Serbinenko
Change-Id: I6652e0ad4e0179950f775bbd0200484907bfc976 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4653 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: make wlan config a CMOS optionVladimir Serbinenko
To stay in line with wwan and bluetooth. Change-Id: Iafe2dc97fc2aec5c2ad1834659b796a6b079c1bc Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4652 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Allow control of low-battery beep.Vladimir Serbinenko
Change-Id: I2f422e83f2afcf0cc3f3ecbace01a8f4f39e87d4 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4663 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Allow user to disable powermanagement beeps.Vladimir Serbinenko
They're pretty annoying. Change-Id: I44d26dc168927a9cedfd6ecc4c9a51a3a7b362c7 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4662 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ibexpeak / bd82x6x: Make SATA mode user-visible option.Vladimir Serbinenko
Ability to choose compatibility mode is interesting for testing payloads and OS for compatibility with older systems. As per comments "ide_legacy_combined # TODO: Does nothing since generations, remove from sb code?" The "combined" mode was removed. It wasn't used by any mobo and the code for it is almost identical to IDE one other than few bits relating to interrupt handling and ISA mode. Change-Id: I407a8fac753b513812a86bef5abcf39c6d81472e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4658 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Implement sticky Fn option.Vladimir Serbinenko
Useful for accessibility. Sticky modifier (sticky Fn) is a behaviour of modifier key when you don't have to hold it pressed to achieve the result. E.g. with normal Fn brightness up is: <Press Fn> <Press Home> <Despress Home> <Depress Fn> With sticky Fn you can do: <Press Fn> <Depress Fn> <Press Home> <Despress Home> Change-Id: I4da5adcea02428d936023891de08684cae77c44e Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4661 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12ec/lenovo/h8: Add an option to swap ctrl and fn.Vladimir Serbinenko
Tested on my X201 and X230. Change-Id: I3c7ec65681157d15c6e87eea64779a08e03ae5a8 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4660 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2014-01-12CBFS: use cbfs_get_file_content whenever possible rather than cbfs_get_fileVladimir Serbinenko
Number one reason to use cbfs_get_file was to get file length. With previous patch no more need for this. Change-Id: I330dda914d800c991757c5967b11963276ba9e00 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4674 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2014-01-12ec/lenovo/h8: Remove wlan_enable and wwan_enable from device tree.Vladimir Serbinenko
wwan_enable was never used. wlan_enable isn't something for device tree but for CMOS config if at all. Change-Id: I765d9d6f0b73b7dc5a57c0c630a53b4b7a0b48cb Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4651 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-10Replace all occurences of sprintf with snprintfVladimir Serbinenko
THis reduces risks of bufer overflows. Change-Id: I77f80e76efec16ac0a0af83d76430a8126a7602d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4279 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2014-01-09X201: set default USB debug controller to 2.Vladimir Serbinenko
The other port is not easily accessible. Change-Id: I6ea31346a375debcd5fc1c27e4078e3a436715e3 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4635 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2014-01-09bd82x6x/ibexpeak: Make DRAM reset gate GPIO configurableVladimir Serbinenko
DRAM reset gate GPIO is different on different mobos move it to hidden config with 60 (current value) as default. Set it to 10 for Lenovo X201. Change-Id: I4f3b6876d7c33d4966315091b63a76a9a0064c16 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4622 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin <adurbin@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-09cubieboard: Initialize memory in bootblockAlexandru Gagniuc
Even though the Allwinner A10 is limited to a 24KiB bootblock, the memory initialization takes only about 3KiB and leaves enough room for an MMC or NAND driver, so init the memory early on. The advantage is that we can eliminate complicated logistics of where to cache CBFS and where to load the ramstage in SRAM. Change-Id: Id549552ed509434e831db60deaef28e04d62417f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4630 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cubieboard: Keep AHB clock within specsAlexandru Gagniuc
The CPU was clocked at 384MHz in the bootblock, but the AHB bus has a maximum rated frequency of 250MHz. Its clock needs to be divided to keep it within spec. Overclocking the AHB bus hung the CPU when memory was accessed. Change-Id: I7cb9cdd1f126b3d5b0446fc68af79b54946bc2d3 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4629 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-09cubieboard: Turn on green LED during bootblockAlexandru Gagniuc
Change-Id: I807060bde374e4a42abe306cecf838ab157c9515 Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4600 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: David Hendricks <dhendrix@chromium.org>
2014-01-08cpu/allwinner/a10: Refactor API for gating clocks to peripheralsAlexandru Gagniuc
Rather than having to track which bit in which register should be cleared or set to gate or ungate the clock to a certain peripheral, provide a simplified enum which encodes the register and bit. This change comes with a function which decodes the enum and gates/ungates the clock. This also removes the register-dependent bitmasks for APB0 and APB1 gating registers. Change-Id: Ib3ca16e54eb37eadc3ceb88f4ccc497829ac34bc Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4571 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08cpu/allwinner/a10: Refactor and document pinmux APIAlexandru Gagniuc
Include a function to multiplex more than one pin at a time. This is useful for peripherals that have the same function number for all their pins. Since we now have two functions for muxing pins, also document them. Change-Id: I53997cc3a2586e3cf749cd672f69fb427659c67f Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4565 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-08mainboard: Add preliminary support for A10-based CubieboardAlexandru Gagniuc
Add a minimal infrastructure which initializes the system clocks and serial console. Change-Id: I768ede6ccf8674ffe9fecd8925cec89768209cab Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-on: http://review.coreboot.org/4553 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
2014-01-04X201: Fix native video initVladimir Serbinenko
Due to recent restructuring X201 native video init has disappeared from config options. Put it back and fix compilation with it. Change-Id: I6d9ba5da196c093abd2df89a6fe5efefece1fb3c Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4606 Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2014-01-03asrock/imb-a180: Configure the 6 COM ports and the keyboardDave Frodin
Change-Id: I66d0715f3be201f8068acd7097e2be49185bee00 Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/4574 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2014-01-03Add the gizmosphere/gizmo mainboardDave Frodin
Gizmo is a AMD-Family14 based board. More information can be found at www.gizmosphere.org Change-Id: I5cfd161b4f408be1f65cf332b083ed7c79a99cfd Signed-off-by: Dave Frodin <dave.frodin@se-eng.com> Reviewed-on: http://review.coreboot.org/4536 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-30AMD K8 (rev F): Move rev F0/F1 workaround to headerKyösti Mälkki
Place this in header so it works also when raminit_f.c and raminit_f_dqs.c are not #included in romstage.c build. The workaround remains to be disabled for all boards. Change-Id: Iff0271ceb21ee1e28a1a31d6bbdb97e29d76461e Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4568 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8 (rev F): Move MEM_TRAIN_SEQ check to northbridgeKyösti Mälkki
Do it just to remove MEM_TRAIN_SEQ test under mainboard/ to see all K8 rev F boards do the same things here. Change-Id: If75035a4ef8882c2618d434d83ba59c408593d86 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4567 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-30AMD K8: Define MEM_TRAIN_SEQ only with K8_REV_F_SUPPORTKyösti Mälkki
Change-Id: I601efbff03d0f0f59557b33be8d6928ede310b62 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4558 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-30AMD K8 (pre-F): Clean platforms without K8_REV_F_SUPPORTKyösti Mälkki
Change-Id: Ie109f58bd8ce54754b8d0b00118e75ace8717df0 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4566 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-29AMD K8 (rev-F): Always have RAMINIT_SYSINFOKyösti Mälkki
K8 Rev F raminit code cannot be built without RAMINIT_SYSINFO, so have the option enabled together with K8_REV_F_SUPPORT. Also move the option under AMD K8. Change-Id: I91fa0b4ae7e3e54fbcb4a4f91eb043956cd0fb60 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4582 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD fam10: Drop RAMINIT_SYSINFOKyösti Mälkki
AMD fam10 raminit cannot be built without RAMINIT_SYSINFO, this is not a true option but copy-paste remainder from AMD K8. Change-Id: Id8edc112f3bacebd1732304ac9ee6e77cc6263b7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4581 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29via/epia-m700: Drop RAMINIT_SYSINFOKyösti Mälkki
Option is for AMD K8 only. Change-Id: Ic55288b3cae2c9bf4f347037e7bf5d9bfcf16689 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4580 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-29AMD K8: Socket implies K8_REV_F_SUPPORTKyösti Mälkki
K8_REV_F_SUPPORT is already set by all affected sockets, (AM2, F, S1G1). Change-Id: If42a4178263d90a4e195fae0c78943ac9eda1ad6 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4557 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-27via: Write »access« without »m« at endPaul Menzel
The comment was copied around so fix all occurrences using the following command. $ git grep -l accessm | xargs sed -i 's/accessm/access/g' Change-Id: I46e117c126c0f851cd5e95cf9e42a77ca5f80996 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4577 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD AGESA: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: Ic1ce60041fef6ddee2dae0e3559fb78f088740af Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4556 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD fam10: Drop MEM_TRAIN_SEQKyösti Mälkki
This config was for AMD K8 only. Change-Id: I76276405b676d1dd4d5dbf8c5b94194a670ccb25 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4555 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-26AMD boards (non-AGESA): Cleanup post_cache_as_ram.c includesKyösti Mälkki
Change-Id: Ib3a69e3364418426438f88ba14e5cf744e2414fa Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4524 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2013-12-26AMD boards (non-AGESA): Cleanup earlymtrr.c includesKyösti Mälkki
Change-Id: I5f4bf9dbaf3470dc83d3e980bb6cab10801e15c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4523 Tested-by: build bot (Jenkins) Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
2013-12-26vortex86ex: Cleanup earlymtrr.c includeKyösti Mälkki
No MTRRs on this platform. Change-Id: Iaef57c8013ae9d40f3b063aae284b3faeeaa43dd Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/4572 Tested-by: build bot (Jenkins) Reviewed-by: Andrew Wu <arw@dmp.com.tw> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
2013-12-24Remove PCI_ROM_RUN optionVladimir Serbinenko
The main purpose of option rom is to supply int* handlers. But supplying those is outside of coreboot scope and if someone needs those they should run SeaBIOS anyway which runs the option roms wonderfully. Running VGA oprom is kept because they're needed to init graphics. This patch still keeps the options to include the option roms to make them available to SeaBIOS. Change-Id: I646334cf88094d3bf8f527779a68a07e0b4b93ec Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4545 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Reviewed-by: Kevin O'Connor <kevin@koconnor.net>
2013-12-23Coding style: punctuation cleanup [1/2].Idwer Vollering
Clean up superfluous line terminators. Change-Id: If837b4f1b3e7702cbb09ba12f53ed788a8f31386 Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: http://review.coreboot.org/4562 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-21exynos5420: Configure the UART pins unconditionallyGabe Black
Configure the pins for the UART unconditionally in the mainboard code (when we know which UART to configure) instead of in the UART driver. This also means the UART will work if later software wants to use it without setting up the pins. Built and booted on pit with the serial turned off and some serial init in the kernel decompression stub fixed. Change-Id: Icab5755e4f935f52d44b9cb3b43d1cb62acce08f Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/65299 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4457 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21exynos5250: Implement support to boot with USB A-A firmware uploadJulius Werner
This patch implements the basic infrastructure required to use the USB A-A firmware upload feature on Exynos5 processors with Coreboot. It will require a corresponding host-side script that activates the feature and uploads the correct image parts in the correct order to harcoded target addresses, as described in the comments of alternate_cbfs.c. Also fixes a bug in the Google Snow mainboard where it would not correctly initialize the pinmux configuration for the SPI flash bus. During a normal SPI boot the IROM would already do that for you, but when booting from USB you have to do it yourself. Change-Id: I40a39f8f5d1d70b58dbf258015c1653a27097d67 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/64875 Reviewed-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4456 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21snow: Set up the i2s0 pins during bootGabe Black
Change-Id: I6729a139091b40d8fd9ba2aa7a8c4e14216d95c5 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64879 Reviewed-by: Stefan Reinauer <reinauer@google.com> Commit-Queue: Stefan Reinauer <reinauer@google.com> Tested-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4440 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21armv7/exynos: Fix and remove memory reset workaroundsHung-Te Lin
The memory corruption problem in Exynos suspend/resume process is caused by two things together: PHY_RESET and MRS command. After stop sending MRS on resume, we can now remove the workaround of skipping PHY_RESET. Change-Id: I64acc27c1d2bb549ae6ad7d32ecda94b0355972c Reviewed-on: https://gerrit.chromium.org/gerrit/64736 Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4433 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: graphicsRonald G. Minnich
This includes the new dp code, which is better, and the fimd code, which is changed and improved. We took the chance to remove un-needed files, and also to remove some foolish u-boot habits, but not all of them. That will take time. With these changes we get graphics. Since the only mainboards we have with 16 bit graphics are 5:6:5, adjust edid.c to just use that format. If at some future time we need 4:4:4, which seems unlikely, we'll need to add a function to adjust the lb_framebuffer. Note that you can't just divine this from the EDID, as the graphics pipe format need not match the actual final format used. The EDID reading works. We've been requested to support hard-coded EDIDs and that will come in the next revision. Currently the hard-coded EDID is ignored for testing. Change-Id: Ib4d06dc3388ab90c834f94808a51133e5b515a4d Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64240 Reviewed-by: Stefan Reinauer <reinauer@google.com> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4432 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby is dead. long live the arm pit.Stefan Reinauer
Remove kirby from our tree. It's dead. BUG=none BRANCH=none TEST=none Change-Id: I0768a9ea40be5d70d845a46f6e28036a133b7aa6 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://chromium-review.googlesource.com/176030 Reviewed-by: Ronald Minnich <rminnich@chromium.org> Commit-Queue: Stefan Reinauer <reinauer@chromium.org> Tested-by: Stefan Reinauer <reinauer@chromium.org> Reviewed-on: http://review.coreboot.org/4548 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: update PMIC write sequence in romstageDavid Hendricks
This update the PMIC write sequence to be correct for newer board revisions. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I2210b0d1945fb19c96a674c8fad1b0ff5a4a381e Reviewed-on: https://gerrit.chromium.org/gerrit/64304 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4427 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21snow: TPS69050 -> TPS65090David Hendricks
This corrects a minor typo used for a part number. Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: I8583cbfc3b4a6c3ad06419f5aab3ba7a8f685575 Reviewed-on: https://gerrit.chromium.org/gerrit/64301 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4424 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby: pit: Fix up wakeup_need_resetGabe Black
In a previous commit the contents of wakeup_need_reset were removed because the GPIO it referred to wasn't connected to anything on pit. I didn't realize at that time that that could have been because we hadn't tried getting suspend/resume working on pit and hadn't updated that file. On snow, the GPIO is the recovery mode pin. This change updates pit to have the right GPIO, kirby to read that GPIO, and makes the comments for both pit and kirby more explicit and spells out the fact that this is the recovery mode GPIO. Having a check here at all may still be a holdover from snow that isn't applicable to pit or kirby, but since there is a parallel as far as the recovery mode GPIO we might as well make them match while waiting for more information. Change-Id: Ic1f3f605a0fddf89e8f5668c7a8df30bdfb91d94 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64164 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4421 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Get rid of the mostly unnecessary exynos5420.hGabe Black
Like on kirby, this header had a single constant in it that was actually used. This change moves that constant inline and gets rid of the header file. Change-Id: Ibe380396f72fddb121fb6ceb3cee24f1b9a85738 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/64163 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4420 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby: Clean some cruft from mainboard.cGabe Black
1. Kirby doesn't have a backlight enable GPIO on the AP since that's handled entirely by the DP-to-LVDS bridge. 2. There is no tps65090 on the other side of the EC who's settings need to be adjusted. If we need to turn on the LCD or backlight power manually, it will have to be done in a different way. 3. The PMIC doesn't provide a 32KHz output for the audio codec. Change-Id: Iadc5f3aec4818805edf3f2517da9e6fee87085dc Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63883 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4413 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21kirby: Neutralize wakeup.c and delete the mostly unused exynos5420.hGabe Black
The function in wakeup.c isn't applicable on kirby. The only constant in exynos5420.h that was used was the speed of the 4th i2c bus. Instead of having a whole header file for that one constant used in one place, the constant is just moved inline along with the comment it had in the header. Change-Id: I5ad50c5eeaecbbf7865d76afb31a12d36c3371ee Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63882 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4412 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add a kirby board which is mostly a copy of pitGabe Black
Change-Id: Ic78c65486816015f7574a13affc6e54acbbea73e Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63875 Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-by: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4411 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Exynos 5420: Enable dynamic CBMEMStefan Reinauer
... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I565c3d6dea747822fbabf6f3845232d4adfbf333 Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63657 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4391 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Exynos 5250: Enable dynamic CBMEMStefan Reinauer
... In order to do this, the graphics memory has to move into the resource allocator and out of CBMEM. Change-Id: I7396da4a7068404b0d2e4d308becab4dd6ea59bb Signed-off-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/59326 Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4390 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21google/pit: disable SYSMMU for graphicsRonald G. Minnich
It's not needed and it's a potential problem source. Change-Id: Ic4cafe74e7fc3a9031d852895ad7fd5e5cd64d11 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62279 Commit-Queue: David Hendricks <dhendrix@chromium.org> Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: David Hendricks <dhendrix@chromium.org> Reviewed-on: http://review.coreboot.org/4410 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Refactor code containing aux callsFurquan Shaikh
Moved a lot of code from i915io.c to intel_dp.c with specific function calls Change-Id: Ib2ed52b4f73ee0076e2dd68a26541e5bbe1366bc Reviewed-on: https://gerrit.chromium.org/gerrit/63950 Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4429 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Slippy/Falco: Fill in right values for PHSYNC and PVSYNC in transcoder flagsFurquan Shaikh
Depending upon the values decoded from edid, the function decides the appropriate bits to be set in flags parameter (Important for fastboot to work correctly in kernel) Change-Id: I3b0f914dc2b0fd887eb6a1f706f87b87c86ff856 Reviewed-on: https://gerrit.chromium.org/gerrit/64265 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4423 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Add cpu transcoder attribute to intel dpFurquan Shaikh
Also, used this attribute in the calculation of htotal and other registers Added intel_dp_* functions for m,n registers and dimension register calculations Change-Id: I99dd7156700d59b0b4c85e34c9aa1c6408c7f31a Reviewed-on: https://gerrit.chromium.org/gerrit/64001 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4422 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Calculate transcoder flags based on pipe configFurquan Shaikh
Works fine with all three panels with the change of 6 bits per color. Change-Id: Ia47d152e62d1879150d8cf9a6657b62007ef5c0e Reviewed-on: https://gerrit.chromium.org/gerrit/63762 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21peppy: Set optimal DTLE register valuesShawn Nematbakhsh
Empirical testing shows that 0x5 is the optimal setting for DTLE DATA / EDGE on Peppy. Change-Id: I273a3a68be97b3eb7c2ee2071e5de1ef7bf7f2d9 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65717 Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4476 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21wtm2: disable SDcard USB portDuncan Laurie
This is causing hangs in depthcharge (again?) so for now turn that port off so the resulting coreboot images are at least useful. Change-Id: I32c7774a95b0020b97105e0fa42c21ccb617c718 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65615 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4467 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: Fix EC wake events in S5Duncan Laurie
The SMI handler code was setting S3 wake events when going into S5 and enabling a key press to wake the system. Change-Id: I6413ef1341e0149187df9f4f7e0c314d4c9e9c6e Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65323 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4459 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Force enable ASPM on PCIe Root Port 1Duncan Laurie
Boot on falco and look in /sys/firmware/log for the string "PCIe Root Port 1 ASPM is enabled" Change-Id: Ie2111e4bb70411aa697dc63c0c11f13fbe66c8d8 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65315 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4454 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Disable unused clocksDuncan Laurie
CLKOUT for PCIE ports 1-5 and CLKOUT_XDP are not used and can be disabled. I couldn't test this directly without a scope so instead I used a modified commit that also disabled PCIe Port 0 and saw that that correctly disabled the WLAN port. Change-Id: I0f996e90f0ae42780de3a0c8dc5db00ec600748b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65251 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4451 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Enable EC controlled throttlingDuncan Laurie
When the EC requests the host to throttle (for charging or thermal related reasons) the package power consumption will be limited. Right now this is set at 12W but that is somewhat arbitrary and may need tuning. 1) define the THRT method in \_TZ scope for EC to call 2) enable SCI events for throttle start and stop 3) define the power limit at 12W and set it in NVS 1) Enable CONFIG_ACPI_DEBUG=y in the kernel 2) Enable the Debug object event in acpi module acpi.debug_layer=0x7f acpi.debug_level=0x2f 3) Using EC console generate host event for throttle start > hostevent set 0x20000 4) Check dmesg for throttle start events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q12] (Node ffff8801002c5988) [ACPI Debug] String [0x12] "EC: THROTTLE START" [ACPI Debug] String [0x10] "Enable PL1 Limit" 5) Using EC console generate host event for throttle stop > hostevent set 0x40000 6) Check dmesg for throttle stop events ACPI: Execute Method [\_SB_.PCI0.LPCB.EC0_._Q13] (Node ffff8801002c59b0) [ACPI Debug] String [0x11] "EC: THROTTLE STOP" [ACPI Debug] String [0x11] "Disable PL1 Limit" Change-Id: I39b53a5e8abc2892846bcd214a333fe204c6da9b Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63989 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4416 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: Drive GPIO59/LTE_DISABLE_L low on S3/S5Duncan Laurie
Try to prevent WWAN from causing spurious wakes. Change-Id: Ifcc44063de0eb1634cab9dd244737071568e3455 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63987 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4414 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Add missing elements to the edid data structureGabe Black
When the edid data structure changed a while ago, it caused hangs on snow which were fixed by adding those missing members. Unfortunately we didn't realize that pit needed the same fix. Change-Id: I81780b8135b99b2e24af723e703b9befff7b5ef0 Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63646 Reviewed-by: David Hendricks <dhendrix@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4389 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21pit: Bump the EC SPI bus speed up to 5 MHzGabe Black
That speed is used with U-Boot instead of the more conservative 500 KHz. Change-Id: Ie9d79db3b52b88c1f3bfec1745634ae6bdc9f4ee Signed-off-by: Gabe Black <gabeblack@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/63193 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Commit-Queue: Gabe Black <gabeblack@chromium.org> Tested-by: Gabe Black <gabeblack@chromium.org> Reviewed-on: http://review.coreboot.org/4386 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21falco: add rtd2132 settings to device treeAaron Durbin
Now that the rtd2132 device has the full settings the panel timings need to be implemented. Sadly, the Tx timings in the rtd2132 aren't 1:1 with the panel's Tx timings. Below is the table equivalent: RTD2132 | Falco Panel --------+------------ T1 | T2 --------+------------ T2 | T8+T10+T12 --------+------------ T3 | T14 --------+------------ T4 | T15 --------+------------ T5 | T9+T11+T13 --------+------------ T6 | T3 --------+------------ T7 | T4 --------+------------ Change-Id: I10a3ad475d6b9485a707eb49e31afd197fc8d24d Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/65858 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4472 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: set PWM to external on ParadeRonald G. Minnich
The PWM is controlled externally from the APU. Change-Id: Ia5130d7616991a78dfde44043a60a32cee4f145c Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61513 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4363 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Pit: move parade writes to mainboard.cRonald G. Minnich
What gets written into the parade is highly mainboard-dependent. So the parade_writes array needs to be there. Change-Id: Ia382d9bf1929e67b7c14d7a09f5461b71866a16b Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61486 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-on: http://review.coreboot.org/4362 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21peppy: Drive WLAN_DISABLE_L / BT_ON low in S3 and S5.Shawn Nematbakhsh
When the board is in S3 and S5 the WLAN_DISABLE_L signal can leak power into the WLAN power well since the GPIO controlling WLAN_DISABLE_L is in the suspend well. Therefore, drive WLAN_DISABLE_L low to avoid the power leak. This is a clone of a Falco change: I1a0df80dd47fdbd535aca7a9d49253794c480606. Change-Id: I625dfbb228d1f293b880a52dfe552842d55a17d1 Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63220 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4383 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21FUI: Fill in link_m and link_n valuesFurquan Shaikh
... based on the EDID detailed timing values for pixel_clock and link_clock. Two undocumented registers 0x6f040 and 0x6f044 correspond to link_m and link_n respectively. Other two undocumented registers 0x6f030 and 0x6f034 correspond to data_m and data_n respectively. Calculations are based on the intel_link_compute_m_n from linux kernel. Currently, the value for 0x6f030 does not come up right with our calculations. Hence, set to hard-coded value. Change-Id: I40ff411729d0a61759164c3c1098504973f9cf5e Reviewed-on: https://gerrit.chromium.org/gerrit/62915 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4381 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Slippy: remove unneeded code in i915io.cRonald G. Minnich
This code is left over from what the VBIOS did; It is redundant. Change-Id: I321c867c81ec8b4d5e10f8b51b872cecb3082d97 Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/62290 Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Commit-Queue: Furquan Shaikh <furquan@chromium.org> Tested-by: Furquan Shaikh <furquan@chromium.org> Reviewed-on: http://review.coreboot.org/4380 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: Route USB to XHCI on resumeDuncan Laurie
Turn on the pei_data flag that will instruct the reference code binary to route all USB ports to the XHCI controller on resume and disable the EHCI controller(s). Change-Id: I2f2ed853a6d17f90ea524bc516f3e78079222739 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63798 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4404 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21haswell boards: fix SATA interrupt in ACPIDuncan Laurie
SATA is routed to PIRQG which should be interrupt 22 and not interrupt 21. The kernel uses MSI with this device so this is only seen when booting with pci=nomsi Change-Id: Ic90ca2c561fc4c53ec1d395c05872222c65ff98a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/63796 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4398 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21slippy/falco/peppy: update ACPI C-state settingsDuncan Laurie
Since these boards do not support C10 we should not bother advertising that state in the ACPI _CST. Instead use this map: ACPI(C1) = MWAIT(C1E) ACPI(C2) = MWAIT(C3) ACPI(C3) = MWAIT(C7S) Change-Id: I37eb02bf9555c74e957316a1ba9778eb2b6ee128 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62898 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Reviewed-on: http://review.coreboot.org/4377 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21lynxpoint me: add support for mbp clear wait in finalize stepDuncan Laurie
The management engine is slow, requiring at least 500ms between when the Dram Init Done message is sent (right after memory training) to when the MBP will report that it is successfully cleared and that the ME can finally be sent the EOP message. Currently this is adding 100-150ms to the boot time. If we defer waiting for the MBP Clear indicator until the finalize step we can gain back that lost time. boot on falco with SMI debugging enabled to ensure that the ME is locked down in the finalize step: Finalizing Coreboot SMI# #0 SMI_STS: PM1 APM ME: MBP cleared ME: mkhi_end_of_post ME: END OF POST message successful (0) Change-Id: Icab4c8c8e00eea67bed5e8154d91a1eb48a492d1 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/62633 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/4375 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21Revert "lynxpoint: Move ME lock down to ramstage"Duncan Laurie
This reverts commit ff81f50f0e4c068b64c4a5c7f5244196ecd24965. Deferring this step until the finalize stage will allow us to defer waiting for the MBP clear indicator and speeding up the boot. Change-Id: Ib8edffd06689e72875830cd68b5aedb7ac3b0559 Reviewed-on: https://gerrit.chromium.org/gerrit/62631 Tested-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Commit-Queue: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4373 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-21SLIPPY: final changes for FUIRonald G. Minnich
The intel_ddi.c change I thought should be in but I don't see it. It just adds two functions back that we need. There are two new files for slippy annotated with comments about how it needs to evolve. That said, this code has been tested on 3 different panels. Both dev and non-dev usages work. physbase initialization to static value removed. Moved spin calls to intel_dp_* Change-Id: I0480af45c21c7dedcaff7e8be729f0eb554ec78a Signed-off-by: Ronald G. Minnich <rminnich@google.com> Reviewed-on: https://gerrit.chromium.org/gerrit/61136 Commit-Queue: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Ronald G. Minnich <rminnich@chromium.org> Tested-by: Ronald G. Minnich <rminnich@chromium.org> Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-on: http://review.coreboot.org/4370 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21peppy: Duplicate SPD data for 2GB configurations.Shawn Nematbakhsh
Peppy SPD table has 4GB configurations followed by 2GB configurations. Current implementation does remapping to point 2GB configuration to the same SPD index as the 4GB. This is different than Falco, which simply duplicates the SPD data for all configurations. To simplify probing in mosys, copy the Falco implementation of duplicating SPD data. Signed-off-by: Shawn Nematbakhsh <shawnn@chromium.org> Change-Id: Idb185a437f3cf4f40d2dae1ae59c30235df8f489 Reviewed-on: https://gerrit.chromium.org/gerrit/61847 Reviewed-by: Dave Parker <dparker@chromium.org> Reviewed-by: Jay Kim <yongjaek@chromium.org> Commit-Queue: Shawn Nematbakhsh <shawnn@chromium.org> Tested-by: Shawn Nematbakhsh <shawnn@chromium.org> Reviewed-on: http://review.coreboot.org/4369 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21haswell boards: Use PECI temp sensor id 0Duncan Laurie
The EC temperature sensors were renumbered and now PECI is at index 0. 1) boot on falco 2) check /sys/class/thermal/thermal_zone0/temp 3) check 'temps' on ec console Change-Id: Idde1457c42c80850b5b8ac22781060ed9b224d13 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61896 Reviewed-on: http://review.coreboot.org/4367 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21falco: Enable RTD2132 spread spectrum at 1.0%Duncan Laurie
This may need further tuning but will start at 1.0%. boot on falco and check /sys/firmware/log localhost ~ # grep RTD2132 /sys/firmware/log RTD2132: Enable 1.0% Spread Spectrum I2C: 01:35 (Realtek RTD2132 LVDS Bridge) Change-Id: I96e1c14dbc6a7bfaf1c8deb1806c48bf2fd3e32a Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61895 Reviewed-on: http://review.coreboot.org/4366 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-21bolt: make the gpio interrupts edge sensitiveAaron Durbin
The drivers in the kernel expect the devices using gpios to generate interrupts to be edge sensitive. Make it so. Change-Id: I920ef621682d33ba081f737e97f0239f903db2f7 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://gerrit.chromium.org/gerrit/61678 Reviewed-by: Stefan Reinauer <reinauer@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/4361 Reviewed-by: Patrick Georgi <patrick@georgi-clan.de> Tested-by: build bot (Jenkins)
2013-12-20armv7: Remove SYS_TEXT_BASE config.Hung-Te Lin
SYS_TEXT_BASE is not used by any one. To prevent confusion when changing memory layout, remove it from current configurations. Change-Id: I15012b864bbb9c12003843b9b24ea64c91f4578b Reviewed-on: https://gerrit.chromium.org/gerrit/61853 Reviewed-by: David Hendricks <dhendrix@chromium.org> Commit-Queue: Hung-Te Lin <hungte@chromium.org> Tested-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: http://review.coreboot.org/4371 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
2013-12-19ec/lenovo/h8: Enable 3G modemVladimir Serbinenko
Just like bluetooth and wlan it need to be enabled in EC. Set the appropriate bit in EC if CMOS config says so. Change-Id: Ia48ca3201f013d3b4c4153f32ff536e06b6a2f6d Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4516 Tested-by: build bot (Jenkins) Reviewed-by: David Hendricks <dhendrix@chromium.org> Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-16X60/T60: Implement "next display output" button.Vladimir Serbinenko
Most of the code needed for this is already in the tree with X201 patch series but code didn't know where to send the next screen notification and so was disabled. Define right video device. Tested by: Sam Noble Change-Id: I4ff0d220afdca342617ce43c6e5d0164ad8eba27 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4494 Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Tested-by: build bot (Jenkins)
2013-12-15lenovo/x201: Add support for Lenovo X201 (Calpella-based laptop)Vladimir Serbinenko
Was extensively tested on my X201. More info on the wiki Change-Id: I503d77749780422e446b48224ca98a1f22a2c180 Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com> Reviewed-on: http://review.coreboot.org/4514 Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
2013-12-15intel/cougar_canyon2/Kconfig: Remove HAVE_ACPI_RESUME as S3 is unsupportedPaul Menzel
According to the commit message for the board Cougar Canyon 2 (48a749a8) resuming from S3 is currently unsupported. The FSP does not support S3 at this time. S3 may be added when it is available in the FSP. Mirror that in the configuration by not selecting the Kconfig option `HAVE_ACPI_RESUME`. Change-Id: I894f103ffa7d8db6342f99fff0867b02bc750752 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: http://review.coreboot.org/4519 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-12 04:36:12 +0000