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Audio DMIC PLL needs to be ON in S0ix to support
Wake on Voice. This requires GPIO_79 and GPIO_80
to be configured as IGNORE IOSSTATE. So DMIC CLKs
will be ON in S0ix.
Change-Id: If91045a8664ce853366b670b9db38d620818fbab
Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-on: https://review.coreboot.org/18155
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This reverts commit 01ba8cf7 (mainboard/google/snappy: Add PowerResource
for ELAN touchscreen)
Change was out of date and broke the build.
Change-Id: Id47631ece1172c3f93bf6f40b8686dfd728842a9
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18158
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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SPI controller need to access flash descriptors/SFDP during s0ix exit,
so all fast SPI IO can't be put into IOSTANDBY state. For reef, that
will be FST_SPI_CLK_FB, GPIO_97, GPIO_99, GPIO_100, GPIO_103 and
GPIO_106.
BUG=chrome-os-partner:61370
BRANCH=reef
TEST=Enter s0ix state in OS, after resume run flashrom to read SPI
content.
Change-Id: I5c59601ec00e93c03dd72a99a739add0950c6a51
Signed-off-by: Lijian Zhao <lijian.zhao@intel.com>
Reviewed-on: https://review.coreboot.org/18137
Tested-by: build bot (Jenkins)
Reviewed-by: Vaibhav Shankar <vaibhav.shankar@intel.com>
Reviewed-by: Venkateswarlu V Vinjamuri <venkateswarlu.v.vinjamuri@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Define reset_gpio and enable_gpio for touchscreen device so that
when kernel puts this device into D3, we put the device into reset.
PowerResource _ON and _OFF routines are used to put the device
into D0 and D3 states.
BUG=chrome-os-partner:59034
BRANCH=master
TEST=emerge-snappy coreboot chromeos-bootimage
Change-Id: I08c05d06b2812a33b3fdff9b42b2a8e0653dd8b4
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17366
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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Combine existing boards google/enguarde and google/ninja using
their common reference board google/rambi as a baseboard.
Variants contain board specific data:
- DPTF ACPI components
- I2C ACPI devices
- RAM config / SPD data
- devicetree config
- GPIOs
- board-specific HW components (e.g., LAN)
Additionally, some minor cleanup/changes were made:
- remove unused ACPI trackpad/touchscreen devices
- correct I2C addresses in SMBIOS entries
- clean up comment formatting
- remove ACPI device for unused light sensor
- switch I2C ACPI devices from edge to level triggered interrupts,
for better compatibility/functionality (and to be consistent
with other recently-upstreamed ChromeOS devices)
The existing enguarde and ninja boards are removed.
Variant setup modeled after google/auron
Change-Id: Iae7855af9a224fd4cb948b854494e39b545ad449
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18129
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Minor cleanup for enguarde and ninja devices:
- enguarde: correct trackpad I2C slave address
- enguarde: remove unused trackpad ACPI devices
- ninja: remove unused PS2 keyboard ACPI device
Change-Id: I1beb34059ba318e2d496a59e4b482f3462faf232
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/18128
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change all instances of "wacbmem_entryanty" to "warranty".
Change-Id: I113333a85d40a820bd8745efe917181ded2b98bf
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18136
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I4077739ac2be09107d8c5a3e4ae7ebd0da3cb876
Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/18147
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
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1. Disable WP
2. Pass SD card detect info in ACPI
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Verified that OS is able to detect SD card and read/write to it.
Change-Id: Ide84d4b86c0fac50a07520dfd76d6d3a921f2ecc
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18138
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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poppy schematics have undergone change after review, update
DQS and DQ Byte mappings based on the new schematics.
BUG=chrome-os-partner:61856
BRANCH=None
TEST= Build and boot all the poppy proto SKUs to OS.
Change-Id: Ie4532035f37c25540abb26122234f6e3346ede69
Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18133
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: Iedc15823dc24b3211fe7954cdf4302934a517afb
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17919
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
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BUG=chrome-os-partner:60513
BRANCH=None
TEST=Verified that EC SW sync is disabled
Change-Id: I399b26aa64084f5d5e91a2e585281dc48fa81c89
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18114
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=chrome-os-partner:60513
BRANCH=None
TEST=Verified that touchscreen works on poppy.
Change-Id: I0fd605048b91b126ca5b5f8c1c4d6d3f46f866a3
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18113
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: Martin Roth <martinroth@google.com>
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BUG=chrome-os-partner:60513
BRANCH=None
TEST=Picks up correct SPD for index.
Change-Id: Iac683ab3b8151747940b0ad7e257da3d9b0ac622
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18112
Tested-by: build bot (Jenkins)
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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BUG=chrome-os-partner:60713
BRANCH=None
TEST=sdcard is detected.
Change-Id: I9ec0cabff0ed7973f5e7dd2c1eae346ae6a1aa99
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/18111
Tested-by: build bot (Jenkins)
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Baytrail SoC has a bug where in some cases the DisplayPort can hang
leading to a non-working display (it just stays black). To avoid this
hang, a patch was introduced in 02/2016
(1c3b1112fa - fsp_baytrail: Fix a possible hanging DisplayPort)
but per default not switched on so that each
mainboard can decide if it wants to use this patch or not.
Recently a new case of this bug was reported by Benoit Sansoni
(benoit.sansoni@kontron.com) and he requested to enable this fix per
default as it costs him a lot of time to find the cause and even the
already available fix in coreboot. To avoid this effort for someone
else in the future we can enable this fix per default as no negative
side effects are known and it is now tested at Siemens and at
Kontron on different mainboards with success.
As the goal is to enable this code permanently the config switch is not
longer needed and is removed.
Change-Id: I15bd682218d0dc887945cc91ee3e5488945a6355
Signed-off-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-on: https://review.coreboot.org/18109
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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The commit 0ba3b2593b0c ("gru: Tuning USB 2.0 PHY to increase
compatibility") bypass ODT to set the max driver strength for
the Type-C otg-port, it works well on otg-port when connected
with USB2.0 devices.
Unfortunately, because the Type-C otg-port and host-port are
consisted in one USB2 PHY, so bypass ODT will have an effect
on both host-port and otg-port. I have tested the host-port
eye-diagram, the result shows that if we bypass ODT, the host-
port eye-diagram height will become to high, more than 500mv,
this may cause USB 2.0 high-speed enumeration failure.
This patch bypass ODT for host-port separately, and then we
can reduce the host-port driver strength without affecting
the otg-port driver strength.
BRANCH=gru
BUG=chrome-os-partner:60727
TEST=Boot system, run 'lsusb' command and check if the usb camera
and usb bluetooth are on usb 2.0 hub or usb 1.1 hub. If they are
on usb 1.1 hub, the issue happens. If not, try to run camera app
and then close camera app, repeat until find that the usb camera
is on the usb 1.1 hub.
Change-Id: Ib693e2a6f2113c06692a7bfee22d85b67ee3b165
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 5ea7660b7b05080b76fc5ca5af3fa18552a03491
Original-Change-Id: Ia1f12182929673c5726df9f77f0903469b5c957a
Original-Signed-off-by: William wu <wulf@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/425739
Original-Commit-Ready: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Douglas Anderson <dianders@chromium.org>
Original-Tested-by: Inno Park <ih.yoo.park@samsung.com>
Original-Reviewed-by: Douglas Anderson <dianders@chromium.org>
Reviewed-on: https://review.coreboot.org/18126
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This driver to configure the clock generator is not used.
Change-Id: I156a42dfc336ff45acdcb6d8618bbd12671b66a7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18104
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Current fw does not create ACPI device for
OS to recognize ELAN touchscreen.
List the touch screen in the devicetree so that
the correct ACPI device are created.
BUG=chrome-os-partner:61803
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: I9015fa63ef3aba74b682da3608a05ee49c4947c5
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/18086
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Die if cbmem_add can't allocate memory for the hob pointer. This
shouldn't ever happen, but it's a reasonable check.
- fsp_broadwell_de already had a check, but it returned to someplace
inside the FSP. Just die instead.
Change-Id: Ieef8d6ab81aab0ec3d52b729e34566bb34ee0623
Found-by: Coverity Scan #1291162
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/18092
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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The Lenovo T400 has a CPU socket that can fit quad cores.
Change-Id: I585775ac9510cc7d2c2d731531f536c1a56b81e8
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18059
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Because Kconfig default values *ONLY* get set when they are first
configured, if you switch mainboards with an existing .config,
the values will not be set as expected for the new board.
This seems to confuse most users, so put a warning in a visible
location to let them know.
Change-Id: Ie6a9c2d139ecd841d654943f14c119ebafd632f2
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17939
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Should have been included in 62902ca45d "sb/ich7: Use common/gpio.h to
set up GPIOs", which was not rebased on addition of this board.
Change-Id: If4547ee43ce6a7a6e4af67e9364613e48f989401
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18047
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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This is more consistent with newer Intel targets.
This a static struct so it is initialized to 0 by default.
To make it more readable:
* only setting to GPIO mode is made explicit;
* only pins in GPIO mode are either set to input or output since this
is ignored in native mode;
* only output pins are set high or low, since this is read-only on
input;
* blink is only operational on output pins, non-blink is not set
explicitly;
* invert is only operational on input pins, non-invert is not set
explicitly.
Change-Id: I05f9c52dee78b7120b225982c040e3dcc8ee3e4e
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17639
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The bare ACPI MMIO address 0xFED80000 was used in multiple
AMD mainboard files as well as the SB800 native code. Reduce
duplication by using a centrally defined value for all AMD
ACPI MMIO access.
Change-Id: I39a30c0d0733096dbd5892c9e18855aa5bb5a4a7
Signed-off-by: Timothy Pearson <tpearson@raptorengineering.com>
Reviewed-on: https://review.coreboot.org/18032
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The console output is garbled until it is fixed in ramstage
by devicetree which sets the uart clock predivider correctly.
Change-Id: I6d6ec0febfec98a8d4a71e1476036c804cf5f08d
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17969
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Restores KB backlight functionality for auron variants
gandof, lulu, and samus.
TEST: boot Lulu and observe KB backlight functional
Change-Id: Iaa852f9327ff1690111db610b4cc5266cd7925b4
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17960
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Previously, all romstages for this northbridge family
would compile via 1 single C file with everything
included into the romstage.c file (!)
This patch separates the build into separate .o modules
and links them accordingly.
Currently compiles and links all fam10 roms without
breaking other roms.
Both DDR2 and DDR3 have been completed
TESTED on REACTS: passes all boot tests for 2 boards
ASUS KGPE-D16
ASUS KFSN4-DRE
Some extra changes were required to make it compile
otherwise there were unused functions in included "c" files.
This is because I needed to exchange CIMX
for the native southbridge routines. See in particular:
advansus/a785e-i
asus/m5a88-v
avalue/eax-785e
A followup patch may be required to fix the above boards.
See FIXME, XXX tags
Change-Id: Id0f9849578fd0f8b1eab83aed910902c27354426
Signed-off-by: Damien Zammit <damien@zamaudio.com>
Reviewed-on: https://review.coreboot.org/17625
Tested-by: build bot (Jenkins)
Tested-by: Raptor Engineering Automated Test Stand <noreply@raptorengineeringinc.com>
Reviewed-by: Timothy Pearson <tpearson@raptorengineering.com>
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Currently, some Intel 945 boards miss some or all of the time stamps
*1:start of rom stage*, *2:before ram initialization*, and *3:after ram
initialization*, so add them.
Use the same formatting as used for the board Lenovo X60, which already
has code for all the time stamps.
Change-Id: Ie25747d02fadd74b7d7b7cab234a7a88b2cc0c42
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17993
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This reverts commit 34a6537512d412363bf56428b7ae284e6dd80fb3, which
appears to cause random stability issues on some elm units.
BRANCH=oak
BUG=chrome-os-partner:60869
BUG=chromium:673349
TEST=None
Change-Id: I5ce9e2673db1bc7a1f487a3c3bcce4651a5e3567
Reviewed-on: https://chromium-review.googlesource.com/419862
Commit-Ready: Nicolas Boichat <drinkcat@chromium.org>
Tested-by: Nicolas Boichat <drinkcat@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/18005
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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This extra check is based on comparing CPU BSEL pins and reports in
MCH configuration. This gives false positives in the case of 1333MHz
CPUs which automatically get downgraded to 1067MHz by the northbridge
(max supported frequency by 945gc).
TESTED with Intel Xeon 5460 (does not boot but completes raminit)
Change-Id: I34cb37912906c803abdad0adbd9c589ca86a67c7
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17997
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Checking for dram self refresh in MCHBAR8(SLFRCS) generates false positives.
Change-Id: I25afd565cae0269616e38ecbcdf385281bae5d1f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17996
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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If the cmos checksum is incorrect it should fall back to sane defaults.
Change-Id: If16cfc73effd4a825d0cefcd30bfd0e48b2d9132
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17968
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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1. Update DPTF TSR1/TSR2 passive/critial trigger points.
TSR1 passive point:53, critial point:80
TSR2 passive point:90, critial point:100
2. Update PL1 Min to 4W and PL1 Max to 12W
3. Update thermal relationship table (TRT) setting.
BUG=none
BRANCH=master
TEST=build, boot on snappy dut and verified by thermal team member.
Change-Id: I8b4fb178daa7c2e4091a14779a125bd5e943d023
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17955
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Update the DPTF parameters based on thermal test result.
(ZHT_DPTF_EVT1_v0.3_20161227.xlsx)
1. Update DPTF CPU/TSR1/TSR2 passive/critial trigger points.
CPU critical point:103
TSR1 passive point:45
TSR2 passive point:55, critical point:90
2. Change thermal relationship table (TRT) setting.
Change CPU Throttle Effect on CPU sample rate to 3secs
Change Charger Effect on Temp Sensor 2 sample rate to 60secs
Change CPU Effect on Temp Sensor 1 sample rate to 8secs
BUG=chrome-os-partner:60038
BRANCH=master
TEST=build and boot on electro dut
Change-Id: I3746750f7ea4a2e01153a36c28a5c33140c9e38c
Signed-off-by: Tim Chen <Tim-Chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/17975
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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The devicetree lacks the 'chip' option for the Super I/O,
which causes the Super I/O related entries to be ignored.
This also adds other LDN that are present on this Super I/O.
Change-Id: Ida1b3c6575aa53bc7060070835c811665bdc1db1
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17965
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Enable an internal pull-up on the power button input as a quick
press is resulting in power button override being asserted.
BUG=chrome-os-partner:61312
TEST=tested on eve P0b to ensure quick power button press does
not result in a shutdown due to power button override.
Change-Id: I3028cf7faef309cf4d60c3585b48adab6e1549d4
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17962
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Correct tabs that were intended as spaces.
Change-Id: Idcf33d829f87a866b5ed880527102918d5b93842
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17905
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
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With the default TCC activation offset value as 0 and Tjmax
temperature value as 100 degree C, Pcode firmware starts taking
prochot action at 100 degree C [Tjmax-Offset].
But before Pcode firmware starts prochot action at 100 degree C,
device is getting shutdown at 99 degree C due to DPTF critical
CPU temperature.
This patch sets TCC activation offset value to 10 degree C for
thermal throttle action to prevent this kind of shutdown.
BUG=chrome-os-partner:59397
BRANCH=None.
TEST=Built, booted on skylake and verified target offset value.
Change-Id: I0811ef481a4b3ce4bd6ef24f2aa8160f44f9c990
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17921
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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SPI_ATOMIC_SEQUENCING was added to accomodate spi flash controllers with
the ability to perform tx and rx of flash command and response at the
same time. Instead of introducing this notion at SPI flash driver layer,
clean up the interface to SPI used by flash.
Flash uses a command-response kind of communication. Thus, even though
SPI is duplex, flash command needs to be sent out on SPI bus and then
flash response should be received on the bus. Some specialized x86
flash controllers are capable of handling command and response in a
single transaction.
In order to support all the varied cases:
1. Add spi_xfer_vector that takes as input a vector of SPI operations
and calls back into SPI controller driver to process these operations.
2. In order to accomodate flash command-response model, use two vectors
while calling into spi_xfer_vector -- one with dout set to
non-NULL(command) and other with din set to non-NULL(response).
3. For specialized SPI flash controllers combine two successive vectors
if the transactions look like a command-response pair.
4. Provide helper functions for common cases like supporting only 2
vectors at a time, supporting n vectors at a time, default vector
operation to cycle through all SPI op vectors one by one.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully
Change-Id: I4c9e78c585ad95c40c0d5af078ff8251da286236
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17681
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Combine existing boards google/auron_paine and google/samus with new
ChromeOS devices auron_yuna, gandof and lulu, using their common
reference board (auron) as a base.
Chromium sources used:
firmware-yuna-6301.59.B 6ed8b9d [CHERRY-PICK: broadwell: Update to...]
firmware-gandof-6301.155.B 666f34f [gandof: modify power limiting for...]
firmware-lulu-6301.136.B 8811714 [lulu: update RAMID table]
Additionally, some minor cleanup/changes were made:
- I2C devices set to use level (vs edge) interrupt triggering
- HDA verb entries use simplified macro entry format
- correct FADT table header version
- remove unused ACPI device entries / .asl file(s)
- clean up ACPI code (e.g., trackpad on Lulu)
- adjust _CID for trackpad on Lulu in order to not load non-functional
Windows driver (does not affect Linux)
- remove unused header includes (multiple/various)
- correct I2C addresses used for SMBIOS device entries
- correct misc typos etc
The existing auron_paine samus boards are removed.
Variant setup modeled after google/slippy
Change-Id: I53436878d141715eb18b8ea5043d71e6e8728fe8
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17917
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Combine existing boards google/guado, rikku, and tidus using
their common reference board google/jecht as a base.
Additional changes besides simple consolidation include:
- simplify power LED functions
- simplify HDA verb definitions using azelia macros
- use common SoC functions to generate FADT table
- correct FADT table header version
- remove unused haswell_pci_irqs.asl
- remove unused header includes (various)
- set sane default fan speed (0x4d) for all variants
Variant setup modeled after google/beltino
Change-Id: I77a2dffe9601734916a33fd04ead98016ad0bc4b
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17913
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Tested to work:
* GPU (Nvidia gt210) in PCIe x16 slot;
* SATA;
* serial;
* 800MHz and 1067MHz FSB Core 2 Duo CPUs;
* ethernet;
* native VGA graphic init.
What does not work:
* resume from s3 suspend;
* superio hardware monitor (not initialised in coreboot).
Quirks:
* does not boot with just one dimm in slot B.
Change-Id: Ide5494be7f2f16d6b5cfd2ccf4ec438f0587add5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17558
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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Make the ending comment associated with "chip ...hudson" match the
appropriate directory name.
Change-Id: I5e0d6d41a2e3f963760aad08ed6108acac5b66b3
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17904
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
|
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Both HDMI and eDP work (simultaneously).
TESTED on Acer C720 (peppy).
Change-Id: Ifc4e3c187bcabd8965d9586237a52b440bfa7f20
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17916
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins)
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Commit bf264e94 (i945:) adds a PCI reset to the romstage, and commit
bc8613ec (Fix i945 based boards) fixes that to use the correct
delay of 200 ms. This code was then copied over, when adding support for
the Lenovo X60.
The reset was related to the shipped crypto card on the Roda RK886EX and
Kontron 986LCD-M, so is not needed on the Lenovo X60. So remove it.
TEST=Build and boot on Lenovo X60t.
Change-Id: Ia37d9f0ecf5655531616edb20b53757d5d47b42f
Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-on: https://review.coreboot.org/17703
Tested-by: build bot (Jenkins)
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
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GPP_D12 needs an internal pull-up to get this rail working on
current boards. GPP_D0-GPP_D3 were changed from SPI interface
and I just missed this change earlier.
BUG=chrome-os-partner:58666
TEST=test camera and touchpad on eve
Change-Id: Idfa186f2930afbe5651f4e0fc11a19cd0dd4295f
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17922
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Add poppy board files using kabylake and FSP 2.0.
BUG=chrome-os-partner:60713
BRANCH=None
TEST=Compiles successfully
Change-Id: Ic9aa5093b319690ae893a21cab98d9b843000e6c
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17866
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
|
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An incorrect board name was propagated over various generations of mainboards.
Correct the comments for these. Addressing the todo items will come in a
later patch.
Change-Id: I4abd028fee5087955a7b6ba8d38f99c8207d24b4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17903
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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Declutter the conditional building of fchec.c. Use the CONFIG
setting directly instead of ifeq ().
Change-Id: I6d3721764e66e5615a639c1979d60ff1291b5d33
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17902
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
|
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Reduce the Bettong devices and match up the comments to the
northbridge.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from e7c38571be6406453640d671210b2074a91f162e)
Change-Id: I53adff741f5cf2bd75c37421949bd30f214f5692
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17849
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Initial work based on db-ft3b-ls and code released by Eltan. Board
boots with some limitation.
Now the AGESA binary is harcoded and board specific until it's fixed
by the SoC vendor.
memtest86+ from external repo skips looking for SPD on SMBus, which when
performed cause memtest86+ to hang. Still didn't tried whole test suit.
SeaBIOS 1.9.3 have some problems with USB which lead to no booting in
some cases. Full log:
https://gist.github.com/pietrushnic/787cbf63f610ff4f6b4ac13e5c20b872
SeaBIOS from PC Engines repository (https://github.com/pcengines/seabios)
works fine. Those changes are planned for upstream.
Information about obtaining and booting Voyage Linux:
https://github.com/pcengines/apu2-documentation#building-firmware-using-apu2-image-builder
Change-Id: Id23e448e27f4bba47b7e9e7fa7679e2690c6e4bc
Signed-off-by: Piotr Król <piotr.krol@3mdeb.com>
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/14138
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
|
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Add the region used by the A-Link to AHB configuration registers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(squashed from 2c8dafdf44cf1a84cbc25e8aa381c04c160ee705
and 3c755f70ffa36c0fc92a1da0e3f5f877c8dc9e8b)
Change-Id: I7398452c6e70b4545e16398f3fec157f2f30293a
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17848
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Add the missing two I2C controllers.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from 0be00a96b9eb40c959a422a5ca4773d2353d244d)
Change-Id: I3ea74a6c0472711102b19a7ca0209aaeeeb2d601
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17847
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Remove the unused Name field. Its previous design generates an FWTS
error and a recommendation for changing it to Serialized.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 1d970f1aa16c647e56a08c83f5719041882a2fc0)
Change-Id: I27748a4f84286e80043f516564ef64350ef3fef9
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/17846
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Having same memory region set as both WRPROT and WRBACK
using MTRRs is undefined behaviour. This could happen if
we allow DCACHE_RAM_BASE to be located within CBFS in SPI
flash memory and XIP romstage is at the same location.
As SPI master by default decodes all of top 16MiB below
4GiB, initial cache-as-ram line fills may have actually
read from SPI flash even in the case DCACHE_RAM_BASE was
below the nominal 4GiB - ROM_SIZE.
There are no reasons to have this as board-specific setting.
Change-Id: I2cce80731ede2e7f78197d9b0c77c7e9957a81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17806
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Larger size fits GRUB payload and fixes case to
build 82801ix with HAVE_INTEL_FIRMWARE.
Change-Id: I90e33fb3a0b0e1a60dcc2a9a022bef034f3270d8
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17830
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Martin Roth <martinroth@google.com>
|
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ELAN touchscreen device expects firmware to export GPIOs and ACPI
regulators for managing power to the device. Thus, provide the
required ACPI elements for OS driver to properly manage this device.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that touchscreen works properly on boot-up and after
suspend/resume.
Change-Id: I298ca5de9c0ae302309d87e3dffb65f9be1e882e
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17799
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Set the thermal throttle (prochot) activation to be 10 degrees
below TJmax so PROCHOT# kicks in at 90C instead of 100C.
BUG=chrome-os-partner:58666
TEST=boot on eve, check msr value before and after resume:
> iotools rdmsr 1 0x1a2
0x000000000a6400e6
> echo mem > /sys/power/state
> iotools rdmsr 1 0x1a2
0x000000000a6400e6
Change-Id: I3ab3a050a1e27c18a940bd7519eabaf015ef93eb
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17901
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
|
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Turn on LPC decoding in romstage.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 5d9dae5a1fdab1bf6c418dc7e6de28069bd342dc)
Change-Id: I937eb5c5b6c6a9f7a13ebd0bec7fcc8d789427ce
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17227
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add ALC286 commands and update the PLATFORM_CONFIGURATION structure
with the list address.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 2dd5cd2f01cd37c9eb7dff85e20e446c7d5ab2ee)
Change-Id: I037b39a8634bf886f82ed93488f1efbf6661c93f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17226
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Change the Carrizo settings used for Bettong to ones specific
to Stoney on Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit e99b2c7e2c913413fdc83ad37c5519837a38c7fb)
Change-Id: I4376421c8c08dab9d7ff1428993eed3978e89657
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17225
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
|
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Duplicate the code from DB-FT3lc and use the correct names.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 935cbe6e8b81f11291322dba3688b0a5a0c3291c)
Change-Id: I3a3c62f09819ea02388bf70945fd0c011ad7555a
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17224
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove a duplicated check and setting for xHCI during the
AMD_INIT_RESET callout. This is handled by the wrapper. Also
remove nearby commented code. EcChannel0 is not a member of
FCH_RESET_DATA_BLOCK.
Leave the check in AMD_INIT_ENV. Although AGESA honors what
was previously requested, additional settings depend on the
state of Usb.Xhci0Enable.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit ca862fbacbe80b1345ad6f23262a9769f05c50fd)
Change-Id: I45a5123e158cd7399d6d286999371d4a0e0fa963
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17223
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change the default configuration for the following settings:
AGPIO14: BT radio disable
AGPIO64: NFC PU
AGPIO65: NFC wake
AGPIO66: Webcam
AGPIO69: PCIe presence detect
AGPIO70: GPS sleep
AGPIO116: MUX for Power Express Eval
EGPIO119: SD power
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit d146af183b9dbbd6bd6c7b6ad1b383bf36203da4)
Change-Id: Ibbde7593f3477e30a45fd4f56f236c6e94e3725f
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17222
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Remove the last bit of Bettong board_id checking from Gardenia.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit b617823d1d2860a3f6d766a40ae95e5486739a5c)
Change-Id: Ibc56dbbfa1b15b21ebadb9f6c9c54936566a2986
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17221
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Gardenia doesn't have the ability to modify settings depending on
the board ID.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 536b4c424e5259ddbd82469f5f426d3189ff3f89)
Change-Id: I2c928431306c669735cf735042855e95721bb107
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17220
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Gardenia makes no special considerations for a board_id regarding
SPD access and addressing. Remove this from the source and use
the standard AGESA call.
Make SPD address changes to devicetree.cb. Note that Gardenia is
designed to be a two channel, single DIMM/channel system (some SKUs
with two DIMMs on the second channel). However, this port is for
the Stoney processor which is a single channel. As a result, the
second DIMM slot is not usable. A future improvement could involve
a port using a different processor, with unique devicetree files
for each.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 77511f98f819dfe08c3ed16ebc11e1b328bdca15)
Change-Id: Id00c2be83340ceeec043ec86e96779e6bf46ae7b
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17219
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Use bettong as the reference for the gardenia mainboard.
Update makefiles etc so it builds.
This patch intentionlly keeps the carrizo_fch.asl file to
remain synchronized with the AMD PI package.
Remove items that do not apply to the Stoney APU, rewrite the
comments associated with the PCIe devices, and fix up the
SPD register association to match the 00670F00 chip.h.
Original-Signed-off-by: Marc Jones <marcj303@gmail.com>
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
(cherry picked from commit 82accfcf9ec76a042156fb6e528f7900987b6e7e)
Change-Id: I014fec5c99c01fc02e129be514b704c8ba27d464
Signed-off-by: Marc Jones <marcj303@gmail.com>
Reviewed-on: https://review.coreboot.org/17218
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Some part of preram cbmem console output is truncated.
Increase preram cbmem console size to 0xd00 to avoid the same.
Change-Id: Idbcbb3d1f433668a0e5375679f56fbe562d39ddd
Signed-off-by: Naresh G Solanki <naresh.solanki@intel.com>
Reviewed-on: https://review.coreboot.org/17840
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add power management type config option that allows mainboards to
either:
1. Define a power resource that uses the reset and enable gpios to
power on and off the device using _ON and _OFF methods, or
2. Export reset and enable GPIOs in _CRS and _DSD so that the OS can
directly toggle the GPIOs as required.
GPIO type needs to be updated in drivers_i2c_generic_config to use
acpi_gpio type so that it can be used for both the above cases.
BUG=chrome-os-partner:60194
BRANCH=None
TEST=Verified that elan touchscreen works fine on reef using exported
GPIOs.
Change-Id: I4d76f193f615cfc4520869dedc55505c109042f6
Signed-off-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-on: https://review.coreboot.org/17797
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Enable the actual touch devices to be probed by the kernel
and remove the placeholder devices that I put in before
and were used for initial bringup.
BUG=chrome-os-partner:58666
TEST=tested on eve
Change-Id: I7fc6f9da83b1abbae6dd069f759b220d59153d1c
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17896
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Put the UART pins into native mode in bootblock so they are not
floating when we try to communicate with H1 over I2C. Without
a serial console enabled BIOS these pins were not configured
until ramstage.
BUG=chrome-os-partner:60935
TEST=Boot Eve board without serial console and H1 TPM enabled
Change-Id: I30f3bf0bacc1bbd776b351a9c09748b0601c39bc
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17893
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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The Roda Lizard RV11 is a comparatively lightweight, full-rugged
notebook. It's based on a 17W TDP dual core Ivy Bridge CPU.
The Lizard RW11 is its bigger brother (45W TDP quad core, more i/o
options).
The RV11 is the first board to use the native graphics initialization
by libgfxinit. Tested so far, are the internal eDP port, DP and VGA.
Change-Id: Iea283059ce3402dc36184baf16928b55285a9eeb
Signed-off-by: Dennis Wassenberg <dennis.wassenberg@secunet.com>
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/17446
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Checking for memory self refresh can generate false positives,
as explained in faa6beb: "northbridge/intel/i945:
CHECK_SLFRCS_ON_RESUME Kconfig option".
This seems to be the case for this motherboard.
TESTED on ga-945gcm-s2l.
Change-Id: Iadf0a73b054470b652e1dc02557fb1715131f823
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/17617
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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For Chrome OS the normal MRC cache should be cleared when a hardware
retrain recovery request is observed. The reason is that since there
are 2 different MRC cache slots there needs to be a mechanism which
allows an end user make a system bootable again if the MRC settings
happen to not allow the system to boot any longer. Therefore, one
just needs to enter recovery with the hardware retrain flag and
the system normal MRC cache slot will be invalidated.
BUG=chrome-os-partner:60592
BRANCH=reef
Change-Id: I6ad32ed0dd217d66404b77467a88689a06044544
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17871
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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VARIANT_DIR is defined in coreboot/Makefile.inc, so doesn't need to be
defined in each mainboard.
Change-Id: Ic93957b710e4a9863774de7fcf3bd006696b6aa1
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/17841
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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On this board i2c3 bus is connected to the display TCON, but it is
acting as the master when it has power so it can read from its own
EEPROM on the bus. In order to prevent any possible issues in S0
make these pins input on the SOC.
BUG=chrome-os-partner:58666
TEST=tested on eve board, but this bus was not used before so
there is no visible change in behavior.
Change-Id: Ide32f45ee33ca986fd3249a5161e01edf99d6e22
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17800
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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On upcoming boards an optional pull up is applied on GPIO_10
to indicate if the board should have security features locked
down for a shipping system. Provide a weak pull down so that
all boards will indicate a logic 0 until the stronger pull up
resistor is stuffed.
BUG=chrome-os-partner:59951
BRANCH=reef
Change-Id: I6f514a69bccd05ca02480f3c30d0ad503a955b1e
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17803
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
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Chrome OS images have three firmware ID regions, to store version
information for the read-only and the two read-write areas. Fill them
with a suitable default and allow configuring a different scheme.
There's already an override in google/foster and google/rotor to match
the naming scheme used so far (in depthcharge).
BUG=chromium:595715
BRANCH=none
TEST=/build/$board/firmware/coreboot.rom has the expected values in the
regions.
Change-Id: I5fade5971135fa0347d6e13ec72909db83818959
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: d2e3be81faa8d21f92325294530714a4b18a1b3e
Original-Change-Id: I2fa2d51eacd832db6864fb67b6481b4d27889f52
Original-Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/417320
Original-Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Original-Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
Reviewed-on: https://review.coreboot.org/17788
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Change-Id: I8313ba1d93922297e5061701dad47d07617d1dcd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17804
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Change-Id: Iacf2e1c0b8003a3588ccbf79e17500ed12f39503
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/17786
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
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This patch sets PL2 override value to 15W in RAPL registers
and sets DPTF PL2 Max to 15W
BUG=none
BRANCH=reef
TEST=emerge-pyro coreboot
Change-Id: Ibadf0fa442f556d018c249b1cf88e29c4d57c97f
Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/17779
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Instead of hardcoding pci_mmio_size in the raminit code,
this makes it a parameter in the devicetree.
A safe minimum of 768M is also defined since using anything
less causes problems (if 4G of ram is used).
Change-Id: If004c861464162d5dbbc61836a3a205d1619dfd5
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/16856
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I2f1f05ef4fc640face3d9dc92d12cfe4ba852566
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17676
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Scratchpad register was read too
late in ramstage so acpi_is_wakeup_s3() did not evaluate
correctly.
This fixes low memory corruption at 0x1000-0x102c and the lack
of coreboot tables (util/cbmem not working) after S3 resume.
This also fixes console log from reporting early in ramstage
"Normal boot" while on "S3 resume" path.
Change-Id: I2922a15a90d2f8272c3482579bdd96f8f33e9705
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17675
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Don't use scratchpad registers when we have romstage_handoff
to pass S3 resume flag. Also fixes console log from reporting
early in ramstage "Normal boot" while on S3 resume path.
Change-Id: I4e2eabc59ff87b7ed40cfc9885bbe0256fe4a695
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17674
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Adapt implementation from skylake to prepare for removal of
HIGH_MEMORY_SAVE and moving on to RELOCATABLE_RAMSTAGE.
With this change, CBMEM region is set early-on as WRBACK
with MTRRs and romstage ram stack is moved to CBMEM.
Change-Id: Idee5072fd499aa3815b0d78f54308c273e756fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15791
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Fill in the NHLT ACPI OEM header fields to differentiate
different audio solutions on a per board basis. This handles
boards that share a firmware that are differentiated by
the SKU id and boards that have their own firmware. For the
latter, the Oem Table ID uses the VARIANT_DIR to differentiate.
"reef" is always used for Oem ID which is treated as more of
family in this case.
iasl -d shows the following on reef:
[00Ah 0010 6] Oem ID : "reef"
[010h 0016 8] Oem Table ID : "reef"
[018h 0024 4] Oem Revision : 00000008
BUG=chrome-os-partner:60494
BRANCH=reef
Change-Id: I5daa6f0306bc05e812a8737ce61ee37177a36b76
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17772
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
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There are 2 gpios on reef-like boards that can be composed
into a SKU. Add support for identifying the SKU value using
the base 3 gpio logic. Also export the SKU information to the
SMBIOS type 1 table.
BUG=chrome-os-partner:59887,chrome-os-partner:60494
BRANCH=reef
Change-Id: I8bb94207b0b7833d758054a817b655e248f1b239
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17771
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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There is ongoing work to link SPI bus and devices in to the devicetree
so this can be generated, but for now put in the raw ASL code to
describe this controller so it can be used by the factory.
BUG=chrome-os-partner:55538
TEST=successfully load fpc1020 kernel module on eve board
Change-Id: I6641664e60fcf2c0bad4b3506c77513b26d7be2e
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: https://review.coreboot.org/17776
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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This patch sets PL2 override value to 15W in RAPL registers.
BUG=chrome-os-partner:60535
TEST=Built, booted on reef and verified PL2 value.
Change-Id: I4ff6a5e7b8686d97134846ee80cdac10916d58ef
Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-on: https://review.coreboot.org/17730
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Simplify set_power_led() by consolidating switch and setting values
as needed inline based on LED state. Remove unnecesary function
param, includes for Tidus.
Change-Id: I28e6fac5f8d7e2ff419002db714ce88697895faf
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17744
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
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Simplify set_power_led() by consolidating switch and setting values
as needed inline based on LED state.
Fix non-off LED polarity for Tricky using correct value from Chromium source
TEST: power on Tricky, observe LED lit / solid
Change-Id: I8bc7c4ae3f83d3f37b76fd5c90a4faed7057ebee
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/17719
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Also remove separate MMCONF_SUPPORT_DEFAULT flag.
Change-Id: Idf1accdb93843a8fe2ee9c09fb984968652476e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17694
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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Doing PCI config operations via MMIO window by default is a
requirement, if supported by the platform. This means chipset
or CPU code must enable MMCONF operations early in bootblock
already, or before platform-specific romstage entry.
Platforms are allowed to have NO_MMCONF_SUPPORT only in the
case it is actually not implemented in the silicon.
Change-Id: Id4d9029dec2fe195f09373320de800fcdf88c15d
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/17693
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
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- Drastically reduced RW_MRC_CACHE size to hold one update. Now
that this area isn't changing after every S5 entry there's no
need make it so large.
- ELOG area reduced by 4KiB for subsequent area alignment. In practice
this doesn't matter because the elog library only uses 4KiB bytes.
16KiB->12KiB is a nop.
- Moved RW_NVRAM for subsequent alignment.
- Most importantly, RW_SECTION_(A|B) are aligned to 64KiB boundaries
and sized to 64KiB multiples. This ensures updates don't need a
read-modify-write that could force a system into recovery if
an inopportune power event occurred.
BUG=chrome-os-partner:60492
BRANCH=reef
Change-Id: I2a2e2797897c934db1a3f9627c6c13a9b2aad540
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/17727
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Update the memory ramid.
Move to one CA training pattern.
BUG=chrome-os-partner:59454
BRANCH=firmware-gru-8785.B
TEST=Build firmware passed
Change-Id: Ic05cbc1700a13e372f63d5202459add0e984f9d8
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 1030a78af3d489d13508f17a79df1e65bd5afa3b
Original-Change-Id: Ibe8acb5b698cec1adcdddbb13d35a5e20a5b8c0d
Original-Reviewed-on: https://chromium-review.googlesource.com/414664
Original-Commit-Ready: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Tested-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Original-Change-Id: I0ae46e496cd18492a2b6c7167081798c2f2479b1
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411645
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17679
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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Add bob in coreboot and update as necessary.
1. Add bob HWID
2. Add supported memory source
BUG=chrome-os-partner:59454
BRANCH=firmware-gru-8785.B
TEST=Build firmware passed
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Change-Id: Iad03a293bdbbb89450f0fea0822e34a4be7064bf
Original-Commit-Id: bff788c71a43403bff2c23b38e69cc27fb869559
Original-Change-Id: I0dcf47eb911337b176f73759a2c70a9dbf4dc68b
Original-Signed-off-by: Shasha Zhao <Sarah_Zhao@asus.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411083
Original-Reviewed-by: Philip Chen <philipchen@chromium.org>
Original-(cherry picked from commit c5925dfcf59ac755a26182744b2bde59e41a37cf)
Original-Reviewed-on: https://chromium-review.googlesource.com/413744
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17678
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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We may support different sdram sizes on one board in future, so
we need to calculate sdram sizes from sdram drvier.
BRANCH=None
BUG=None
TEST=boot kevin
Change-Id: I43e8f164ecdb768c051464b4dbc7d890df8055d0
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 3c4d8b3cb647b2f9cebc416c298817c16d49330e
Original-Change-Id: I95d5ef34de9d79ebca3600dc7a4b9e14449606ff
Original-Signed-off-by: Lin Huang <hl@rock-chips.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/411600
Original-Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://review.coreboot.org/17629
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
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