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2020-12-24mb/google/kukui: Add a new config 'Katsu'Sunway
A new board introduced to Kukui family. BUG=b:176206134 TEST=make # select Katsu BRANCH=kukui Signed-off-by: Sunway <lisunwei@huaqin.corp-partner.google.com> Change-Id: I09fe2b8f6922dfd2af6424830568466fb98f7aee Reviewed-on: https://review.coreboot.org/c/coreboot/+/48874 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-23mb/intel/adlrvp: Make SI_ALL region within 16MiBSubrata Banik
TEST=Able to build and boot ADLRVP. Change-Id: I93da53f8835e0eec4cf4e78daab26332fd55d334 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48753 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-23mb/clevo/cml-u: Reorder selects alphabeticallyFelix Singer
Change-Id: Idd02573e6b47c3bcbdcefa7b04fb9098b600df49 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48804 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-22sb/intel/ibexpeak: Drop ChromeOS setup for GNVSKyösti Mälkki
The CHROMEOS option was never used with ibexpeak, code was copy-pasted and forked from bd82x6x. Since a custom ibexpeak/nvs.h was already made, an accompanying globalnvs.asl is added here too without chromeos_acpi_t. Change-Id: I16406516b51c13d49593bc8a3e1e5b868eea6f24 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48766 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22sb,soc/intel: Drop unnecessary headersKyösti Mälkki
Files under sb/ or soc/ should not have includes that tie those directly to external components like ChromeEC os ChromeOS vendorcode. Change-Id: Ib56eeedaa9d7422e221efa9c8480ed5e12024bca Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48765 Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22mb/google/volteer: Add GPIO to drobit supportFrankChu
Add support for gpio driver for drobit BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I54ba182c6da3db282961b3c72a4d2d11d1001e95 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48497 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-22mb/google/volteer: Update SPD table for drobitFrankChu
drobit memory table as follow: value Vendor Part number 0x00 MICRON MT53E512M32D2NP-046 WT:E 0x00 HYNIX H9HCNNNBKMMLXR-NEE 0x01 MICRON MT53E1G32D2NP-046 WT:A 0x02 HYNIX H9HCNNNCPMMLXR-NEE BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: Icd9439f8449856d4ec6798a4e4310dd139bce05f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48496 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22mb/google/volteer: Update drobit device treeFrankChu
Update drobit device tree override to match schematics. BUG=b:175351914 BRANCH=none TEST=emerge-volteer coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I48a3024df4270b111b90c4fb56847aad6e65bfa1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48495 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-22mb/clevo/cml-u: move gpio early init to bootblock_mainboard_early_initMichael Niewöhner
Move gpio early init to bootblock_mainboard_early_init to make the bootblock console work as early as possible. Change-Id: I619f7d0e15adae284b606dd20c3c1f04f3eafd7b Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48801 Reviewed-by: Felix Singer <felixsinger@posteo.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-22Revert "mb/clevo/cml-u: drop duplicated configuration of UART pads"Felix Singer
This reverts commit 1a0071c7115819302c7df3fa2c07b1ca971e515d. Reason for revert: UART pad configuration should not be done in common code, since it could cause short circuits if the user configures a wrong UART index. Change-Id: I6022935eaab748f82c6330be0729ff72f4880493 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-22mb/google/zork/var/vilboz: Add enable acp_i2s_use_external_48mhz_osc flagJohn Su
Add enable acp_i2s_use_external_48mhz_osc flag and then WWAN sku will use external clock source at next build. BUG=b:174121847 BRANCH=zork TEST=build vilboz and check MISC_CLK_CNTL1. Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ida747938373f648524b1e7f34bc69e372a69c4f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48556 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21Revert "mb/clevo/kbl-u: drop duplicated configuration of UART pads"Felix Singer
This reverts commit ccceb2250eeb820fccfb62d1f3ab407582d2e79f. Reason for revert: UART pad configuration should not be done in common code, since it could cause short circuits if the user configures a wrong UART index. Change-Id: Idc268debc60a027ed2f5a76e0de8ea2d1cde0fc4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48327 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
2020-12-21mb/prodrive/hermes: Update USB 2.0 settingsAngel Pons
Test results show that USB signals look better with these settings. Yes, there's a macro in the devicetree now. All ports use the same settings except for the overcurrent pin, so this avoids redundancy. Change-Id: Ib0dafab88d8dcc05388b724f6a7183c13ac64934 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48694 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21mb/google/octopus/var/phaser: Add support for G2TOUCH Touchscreenrasheed.hsueh
Add devicetree configuration for G2TOUCH Touchscreen controller. BUG=b:175513059 BRANCH=octopus TEST=build bios, check i2c bus and verify touch screen works fine Change-Id: Ib57597c4998f205c664e13befb4c44532b7dbd4f Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48552 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21mb/google/dedede/var/storo: Generate SPD ID for supported memory partsTao Xia
Add supported memory parts in the mem_parts_used.txt and generate the SPD ID for the memory parts. The memory parts being added are: MT53E512M32D2NP-046 WT:E H9HCNNNBKMMLXR-NEE MT53E1G32D2NP-046 WT:A H9HCNNNCPMMLXR-NEE BUG=None TEST=Build the storo board. Signed-off-by: Tao Xia <xiatao5@huaqin.corp-partner.google.com> Change-Id: Ifd935865927bb9fccf95eb4924ca6986d0c19442 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48447 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Xuxin Xiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21mb/google/dedede: Update Boten setting for USI PEN detection.rasheed.hsueh
Update devicetree and gpio driving of boten that enable stylus PEN detect signal is not dual-routed on Boten. Since the gpio_keys kernel driver expects the pad to be owned by GPIO controller (i.e. configured for GPIO IRQ), it cannot be configured for ACPI (i.e. SCI). Thus, this change updates the GPIO configuration for GPP_C12 to PAD_CFG_GPI_GPIO_DRIVER and device tree entry for PENH device to use WAKEUP_ROUTE_GPIO_IRQ. Additionally, the signal is marked as active low in the device tree entry to indicate to the kernel driver that the signal is inverted. Not dual routing the signal results in wake source not being added to eventlog when pen removal results in wake from S0ix. BUG=b:160752604 BRANCH=dedede TEST=Build and check behavior is expected. Signed-off-by: rasheed.hsueh <rasheed.hsueh@lcfc.corp-partner.google.com> Change-Id: I74a17088da64c22ef1c74d201c80274fc65a44c9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48641 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21mb/prodrive/hermes: Enable S3/S4 resumePatrick Rudolph
Change-Id: I75f83bcc6c65a048e87f7295a66526eb384afc5d Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48692 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-21mb/intel/shadowmountain: Add Intel Pre-CEP shadowmountain boardV Sowmya
This patch adds initial support for Alderlake Intel Pre-CEP board called shadowmountain. BUG=b:175808146 TEST=util/abuild/abuild -p none -t intel/shadowmountain -a -c max Change-Id: I9cb650c88986badd6733b001d6f2a0e338421829 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48685 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-21volteer/variants/eldrid: Enable RTD3 for the NVMe deviceNick Chen
Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:161270810 TEST=tested on eldrid Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com> Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-21Revert "mb/google/dedede: Update Imon slope and Offset Value for Drawcia"Maulik V Vaghela
Falling back to default values for Imon slope and offset for Drawcia This is as per recommendation from ODM based on calibration This reverts commit 2ac88f2347352c5dff0af18d5130dbdd6f032930. BUG=b:175629526 BRANCH=dedede TEST=Debug FSP confirms that values are reverted to default Change-Id: I605acdcd0de2c5dfc28af2aea8cefc6b629c0925 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48737 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Vidya Gopalakrishnan <vidya.gopalakrishnan@intel.corp-partner.google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21mb/google/dedede: Add GPIO to galtic supportFrankChu
Add support for gpio driver for galtic BUG=b:170913840 BRANCH=dedede TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I01bb95545705efab1a2adf1582b6293fd89e6420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48684 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-21mb/google/dedede/var/madoo: Configure Acoustic noise mitigation UPDsDtrain Hsu
Enable Acoustic noise mitigation for madoo and set slew rate to 1/8 which is calibrated value for the board. Other values like PreWake, Rampup and RampDown are 0 by default. BUG=b:173765599 BRANCH=dedede TEST=Correct value is passed to UPD and Acoustic noise test passes. Signed-off-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Change-Id: I968d8d43016e3569835b0a777335fa1d5c135f87 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48721 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21mb/google/dedede: Update SPD table for galticFrankChu
galtic memory table as follow: value Vendor Part number 0x00 MICRON MT53E512M32D2NP-046 WT:E 0x00 HYNIX H9HCNNNBKMMLXR-NEE 0x01 MICRON MT53E1G32D2NP-046 WT:A 0x02 HYNIX H9HCNNNCPMMLXR-NEE BUG=b:170913840 BRANCH=none TEST=emerge-dedede coreboot Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I30b8fe3f14e1af7bb5760530477f9311c6a4ee62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48655 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-21zork: update gumboz variantKevin Chiu
gumboz is the dalboz/dirinboz follower. update gumboz variant to align dirinboz settings. BUG=b:174277853,b:173662179 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: I80c03d531761c02b68bd127d889c3ace2dd9e99e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48642 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Kangheui Won <khwon@chromium.org>
2020-12-20mb/clevo/kbl-u: drop duplicated configuration of UART padsMichael Niewöhner
UART pads already get configured in bootblock by the UART driver in soc code. Thus, drop the duplicated code from the mainboard. Change-Id: I95565a74e19d693a7d5ead81e72592cc4ca2038c Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48594 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-20mb/clevo/cml-u: drop duplicated configuration of UART padsMichael Niewöhner
UART pads already get configured in bootblock by the UART driver in soc code. Thus, drop the duplicated code from the mainboard. Tested successfully on Clevo L141CU. Change-Id: I05a459b0af79c75c31b1bb26ea1a1a40857ef9bf Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48593 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-17soc/intel/skylake: Drop duplicate PmConfigPciClockRun configurationBenjamin Doron
coreboot already unconditionally enables CLKRUN_EN in SoC common code. Tested on an out-of-tree Acer Aspire VN7-572G, PCCTL[CLKRUN_EN] of LPC is still enabled. Change-Id: I65e85015bdd0f766ca8021a3d4c0b0d799f0ccc5 Signed-off-by: Benjamin Doron <benjamin.doron00@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48325 Reviewed-by: Felix Singer <felixsinger@posteo.net> Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17mb/intel/coffeelake_rvp: Stop using headers for HDA verbsAngel Pons
One of the variants lacks an hda_verb.h, and hda_verb.c can't be built. Follow-up changes will make mainboard hda_verb.c files always get built through AZALIA_PLUGIN_SUPPORT, and breaks building this contraption. Turn the headers into standalone compilation units to prevent this issue. Since they contain definitions, including them from multiple compilation units wasn't a good idea anyway. Change-Id: I00d968563539a4e1b8d1e12145293439d8358555 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48360 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17mb/google/zork: update USB 2.0 controller Lane Parameter for morphiusKevin Chiu
from AMD USB phy specialist recommended that TXVREFTUNE0 shouldn't over 0xD (the maximum) in order to have enough room to accomdate a safe disconnect threshhold in COMPDISTUNE0. TXVREFTUNE0: 0xf -> 0xd BUG=b:172687208 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com> Change-Id: Ia104454d95e5e8d6a212c97fb09d61125945eeea Reviewed-on: https://review.coreboot.org/c/coreboot/+/48653 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-17mb/intel/adlrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4 portsV Sowmya
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4 ports. Referred from TGLRVP -> https://review.coreboot.org/c/coreboot/+/41543 Change-Id: I5f883dac0d7e5fa84ad2e1683f84c933a90cea51 Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48619 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2020-12-17mb/google/guybrush: Add new mainboardMathew King
Guybrush is a new Google mainboard with an AMD SOC. BUG=b:175143925 TEST=builds Change-Id: I1792f21ff7616f364ddc8b0c04481049b2a5fb04 Signed-off-by: Mathew King <mathewk@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48479 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-17soc/intel/cannonlake: Change mainboard_silicon_init_params argumentPatrick Rudolph
Use FSPS_UPD instead of FSP_S_CONFIG as argument as already done on xeon_sp and denverton_ns. This allows to set test config UPDs from mainboard code as well. Change-Id: I6d67264e22df32b9210ce88b99d6a7a4f6b97ffb Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48644 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Felix Singer <felixsinger@posteo.net>
2020-12-17drivers: Replace set_vbe_mode_info_validPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel+Aspeed on server platforms or Intel+Nvidia on consumer notebooks. The goal is to remove duplicated fill_fb_framebuffer(), the advertisment of multiple indepent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Replace set_vbe_mode_info_valid with fb_add_framebuffer_info or fb_new_framebuffer_info_from_edid. Change-Id: I95d1d62385a201c68c6c2527c023ad2292a235c5 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39004 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-17mb/google/zork: Add GPIO to Shuboz supportKane Chen
1. AGPIO5 to NC 2. EGPIO141 to NC 3. EGPIO144 to NC BUG=b:174528384 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I51f291476e01982e1a3f92cd1b338a528434112d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48002 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16soc/amd/picasso: Fix the typo in GPIO defineZheng Bao
Change-Id: I8c9eed5d0e320b02382c24304a44e51e89eb6ac5 Signed-off-by: Zheng Bao <fishbaozi@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48633 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-12-16mb/ocp/tiogapass/devicetree.cb: Add P2SB deviceArthur Heymans
This fixes ocp/tiagopass not booting as after FSP-S the P2SB is accessed to read out or reconfigure the HPET and PCH IOAPIC BDF. Change-Id: Ia37bd0f14627980345cd07f20e935a10d4760b69 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48654 Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/dedede/var/magolor: Add Wifi SAR for magolor and magliaRen Kuo
Add wifi sar for magolor and maglia: Using tablet mode of fw config to decide to load custom wifi sar or not. same wifi sar value for magolor and maglia (shared firmware) BUG=b:173001370, b:173001251 TEST=enable CHROMEOS_WIFI_SAR in config of coreboot, emerge-dedede coreboot-private-files-baseboard-dedede coreboot chromeos-bootimage. Cq-Depend: chrome-internal:3453724 Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Change-Id: I44ab68c9ee5deced90d3858161571ab4b39b4c8a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48448 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/dedede/var/sasuke: Add memory part and generate DRAM IDSeunghwan Kim
This change adds memory part used by variant sasuke to mem_part_used.txt and generates DRAM ID allocated to the part. BUG=b:172104731 Change-Id: Ie8d66261cb5b4493afb1c677839f807bca994af5 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48451 Reviewed-by: Raymond Chung <raymondchung@ami.corp-partner.google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/poppy: Fix race condition in acpi camera_pmicRicardo Ribalda
Newer kernels can re-schedule new acpi command calls during a Sleep(). This causes that the following trace fails to detect the cameras: [ 15.764725] drivers/acpi/power.c:358 Power resource [OVFI] turned on start [ 15.772180] drivers/acpi/power.c:358 Power resource [OVTH] turned on start [ 15.834970] drivers/acpi/power.c:362 Power resource [OVFI] turned on start [ 15.852456] drivers/acpi/power.c:415 Power resource [OVFI] turned off start [ 15.955987] drivers/acpi/power.c:420 Power resource [OVFI] turned off end ERROR!! [ 16.030896] drivers/acpi/power.c:362 Power resource [OVTH] turned on end Which can be triggered more frequently if the Sleep() commands in OVTH _ON Method are increased. To avoid the race condition, we create a new Power Resource that handles the common resources of both cameras and make both cameras depend on that resource. This also simplifies the acpi table by removing a Mutex. BRANCH=poppy BUG=b:171955583 TEST=while true; do if ssh $DUT "dmesg | grep \"failed to find sensor\" "; then break; fi; ssh $DUT reboot; sleep 30 ; done Signed-off-by: Ricardo Ribalda <ribalda@chromium.org> Change-Id: I25df0225699759c1828b8791c5bdee66529858a7 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48631 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/zork/: Remove WRDD from VilbozEric Lai
After checked, this project doesn't need this feature. BUG=b:173066178 BRANCH=zork TEST=check no WRDD method in acpi. Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9a662953f3047d771f2df919ac80d0440842738e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48621 Reviewed-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/purism/librem_cnl: Use FMAP-based SPD cacheMatt DeVillier
Use a FMAP region to cache SPD data, providing improvements in boot time and detection of change in DIMM population (which FSP will sometimes fail to detect / fail to invalidate the MRC cache). Adapted from implementation used in google/hatch. Test: build/boot Librem Mini v2, verify SPD cache used, changes in DIMM population properly detected. Change-Id: I15cb9aa8b00d39d098a0f901aee026bac1161a80 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48549 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-16mb/google/octopus/variants/casta: Add support zinitix touchpadSeunghwan Kim
This change adds support zinitix touchpad for casta/bluebird. BRANCH=firmware-octopus-11297.B BUG=b:175618033 TEST=built and verified touchpad worked on casta Change-Id: I1a8f562de19d1a8160d52c65400553f0c68393e0 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48634 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-15mb/purism/librem_mini: Adjust PL1/2 levelsMatt DeVillier
While the Librem Mini (v1/v2) are more than capable of higher PL1/2, they currently ship with a 40W power supply, so set PL1/2 accordingly to avoid power spikes above the PSU rating (which can result in unexpected showdowns/reboots) Change-Id: Ia7f89e885f1af29cbbb67d6fb844257ba2b87417 Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48586 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-12-15mb/google/asurada: Initialize displayHuijuan Xie
Enable ANX7625 panel and configure display in mainboard_init() to support display in firmware screen. BUG=b:155713214 BRANCH=none TEST=Recovery screen is shown in recovery mode. Signed-off-by: Huijuan Xie <huijuan.xie@mediatek.corp-partner.google.com> Change-Id: If730c42451f7b392285df686abc4ca252d8d42cf Reviewed-on: https://review.coreboot.org/c/coreboot/+/46578 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-15mb/google/kukui: help payload to identify correct speaker amp typeHung-Te Lin
Kukui based devices may use different speaker amplifiers, for example MAX98357A, RT1015, or RT1015Q/automode. To help payloads identifying which component was installed on board, we want to pass the speaker GPIO in different name. This can be set in Kconfig as CONFIG_SPEAKER_GPIO_NAME. BUG=b:174534548 TEST=emerge-kukui coreboot depthcharge chromeos-bootimage BRANCH=kukui Signed-off-by: Hung-Te Lin <hungte@chromium.org> Change-Id: I4b44b026bee4d3b58646eee207aea0120071dd46 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48558 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>
2020-12-14mb/intel/tglrvp: Enable CNVi Bluetooth for UP4Bora Guvendik
Turn on CNVi Bluetooth for UP4 in devicetree. BUG=none TEST=Boot to OS, check BT enumeration. Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Change-Id: I6a3ec7014c41713697e0fcc90e28bc7bbe6aa1e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Selma Bensaid <selma.bensaid@intel.com> Reviewed-by: Ravishankar Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-12-14mb/prodrive/hermes: Update PCIe slots in devicetreePatrick Rudolph
* Drop PcieRpSlotImplemented on internal slots * Add PCIe port 15 that connected to CNVi/M.2 E Change-Id: Iaa05affa760b447fc1725e674b12366684a63720 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47239 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-12-14soc/intel/braswell: Clean up devicetree settingsAngel Pons
Remove unreferenced settings and factor out common settings. Many of these are not mainboard-specific, and all boards use the same value. Change-Id: Iecae61994a068e8022638a2ad9ca10174427f0a4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48577 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero ProbelessTrace dt settingAngel Pons
This seems to be a debugging option. Since unset devicetree options default to zero, drop the setting. If it is needed in the future, a user-visible Kconfig option would probably make more sense. Change-Id: I0a71bc407fa92da3dcc0e3dbd666438d4280ffcb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop always-zero PowerLimit4 dt settingAngel Pons
Unset devicetree settings default to zero, so the devicetree setting can be removed. Looks like no one needs it anyway. Change-Id: Iad94538c5465347b37a99c6c9f20988168661593 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48575 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14soc/intel/skylake: Drop unreferenced PttSwitch dt settingAngel Pons
The value for this setting is not used anywhere. Drop it. Change-Id: I75f6cdec6c69b374a07519bf9058b8f6e4916307 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48573 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-14mb/purism/librem_cnl: move setting of FSP-M UPDs into variant.cMatt DeVillier
The upcoming Librem 14 variant won't use the same SATA HSIO adjustments as the Librem Mini, so move these settings into a variant-specific file. Rename existing gpio.h to variant.h, move to board root directory, and use for all variant-specific declarations; adjust references as needed. Add newly-created variant.c to Makefile. Test: build/boot Librem Mini, verify SATA functionality unchanged. Change-Id: Ie8f714cc759675c692ad6e3f20e50adad8d09d4b Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48519 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14src/lib: Add Kconfig option for SPD cache in FMAPMatt DeVillier
Currently, the option to cache DIMM SPD data in an FMAP region is closely coupled to a single board (google/hatch) and requires a custom FMAP to utilize. Loosen this coupling by introducing a Kconfig option which adds a correctly sized and aligned RW_SPD_CACHE region to the default FMAP. Add a Kconfig option for the region name, replacing the existing hard- coded instance in spd_cache.h. Change the inclusion of spd_cache.c to use this new Kconfig, rather than the board-specific one currently used. Lastly, have google/hatch select the new Kconfig when appropriate to ensure no change in current functionality. Test: build/boot WYVERN google/hatch variant with default FMAP, verify FMAP contains RW_SPD_CACHE, verify SPD cache used via cbmem log. Also tested on an out-of-tree Purism board. Change-Id: Iee0e7acb01e238d7ed354e3dbab1207903e3a4fc Signed-off-by: Matt DeVillier <matt.devillier@puri.sm> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48520 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/google/glados/var/caroline: Drop zero setting from dtAngel Pons
Unset devicetree options already default to zero. Note that this setting is not referenced anywhere else, and will be removed in a follow-up. Change-Id: I7bcc1c66caa9167c2327e1dc782f69c5de0fac2e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48579 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-14mb/intel/ehlcrb: Remove unrelated Kconfig settingsTan, Lean Sheng
Update Kconfig to remove unrelated configs inheritted from JSL_RVP. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ia744b57302f7c8310c42e12cf019b7f6e7b8f9e9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48544 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-13mb/google/kahlee: move SMI/SCI GPIO setup to ramstageFelix Held
SMIs and SCIs aren't used before ramstage or the OS, so there should be no need to already set them up in romstage. Not using this GPIO configuration functionality allows untangling the GPIO and smi_util code and only linking smi_util in ramstage in follow-up patches. In romstage the pins get initialized as inputs with pull-up, so that at least that part still matches the configuration before this patch. BUG=b:175386410 Change-Id: I733bb91ef60dc66093781a376a2e9837f5209671 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48608 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2020-12-12mb/intel/adlrvp: Make CLKSRC and CLKREQ proper for PCIE RP8Subrata Banik
1. Make CLKSRC -> 7 and CLKREQ -> 6 2. CLK 6 is using free running CLK 3. Make LAN CLK 7 as unused as GbE is disable TEST=Able to detect PCIE SD card on 0x1 slot. Change-Id: I7fbde9492a0c59fc76931bfb7c9522d4f208ebb0 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48449 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: V Sowmya <v.sowmya@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11mb/supermicro/x11ssm-f: disable unconnected and unused/strap-only padsMichael Niewöhner
There is a whole bunch of pads being configured by the vendor firmware that are either unconnected due to unpopulated resistor pads, only connected to test points for vendor debugging purposes or just used as strap. Configure them as NC with an appropriate pull to disable the RX/TX functions. The pads have been determined by dissecting a dead board. This patch has been tested thoughroughly on a machine, normally used productive, to see if any issues arise. No problems occurred at all. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I06b942e3182469f87e41914c893e5b485ccca420 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11hatch: enable genesis PCIe/USB devicesJoe Tessler
Updates PCIe registers and GPIO CLKREQ lines to match the schematic. BUG=b:173566597,b:173567124,b:173566890 TEST=build AP firmware; flash device BRANCH=none Change-Id: Ibf519b812022839f749e503436f097d3b48c4383 Signed-off-by: Joe Tessler <jrt@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48523 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11soc/amd/cezanne: add 0xcf9 resetFelix Held
Change-Id: Ibb78661c102e0d0327f3e74173bf98bc40e13960 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48488 Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Mathew King <mathewk@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11mb/google/volteer: Clean up romstage and ramstage UPDsTim Wawrzynczak
Move the manual calls to fw_config_probe() into the devicetree; the AUDIO probe is trivial, and the TCSS devices (DMA0, iTBT RP0 & RP1) are already guarded with probe statements in the baseboard devicetree, so the code in romstage.c was redundant. The variants seem to have their USB4 probe statements correct as well, so the manual UPD setting in mainboard.c was also unnecessary. BUG=none TEST=abuild google/volteer Change-Id: I1d067ff3d181b152c784634ff99202bb2b9202f7 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-12-11mb/google/volteer: Make use of fw_config_is_provisioned()Tim Wawrzynczak
In cases when a volteer device is unprovisioned, the safest thing to do for GPIOs that will normally be used for audio codec buses is to leave them disabled (configured as PAD_CFG_NC). This patch adds support for that. BUG=none TEST=add debug print to new if branch; remove fw_config from CBI and see print on console Change-Id: I8efd101174f6e3d7233d2bf803b680673cada81a Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47972 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11mb/ocp/deltalake: Update GPIO configurations according to schematicsJingle Hsu
On Delta Lake DVT, dump GPIO settings from UEFI firmware for new PCH (C621A) by util/inteltool and generate the header file by util/intelp2m. The DVT and EVT GPIO configurations are the same. The initial value of GPP_B20 (POST complete) should be high, otherwise BIC would get incorrect sensor readings and see events like PCH prochot. Tested=On OCP Delta Lake DVT, dump GPIO configurations by Intel ITP and verify the results match with the header file. Change-Id: Ic9837a22bc231a4cb919de316ff6f6ee88411ab8 Signed-off-by: Jingle Hsu <jingle_hsu@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47229 Reviewed-by: Tim Chu <Tim.Chu@quantatw.com> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Johnny Lin <Johnny_Lin@wiwynn.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-11mb/google/volteer/variant/lindar: Correct IOM port configurationKevin Chang
Correct IOM setting and TCSS AUX setting to fix type C C0 port display can't output after flip. BUG=b:173093980 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS, test USB function normally. Change-Id: I827a2d8a5b01dce412b4170fde0f638670ab8baf Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47785 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Improve type-C Port 1 USB2 Eye Diagram for delbinFrankChu
In order to pass DB type-C Port 1 USB2 eye diagram, DB USB2 PHY register needs to be overridden. port#1 PortUsb20Enable=1 Usb2PhyPetxiset=3 Usb2PhyTxiset=2 Usb2PhyPredeemp=7 Usb2PhyPehalfbit=1 BUG=b:173676539 BRANCH=None TEST=emerge-volteer coreboot chromeos-bootimage Signed-off-by: FrankChu <frank_chu@pegatron.corp-partner.google.com> Change-Id: I41cda27f97287fae5c23dc9843fdf0a8a33057f8 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-11mb/google/volteer: Assert BT_DISABLE_L (GPP_A13) in early_gpio_tableAlex Levin
BT_DISABLE_L (GPP_A13) has to asserted in early_gpio_table to reset bluetooth on reset. BUG=b:171085081 TEST=volteer2 boots; scope shows assertion of the signal Change-Id: Iaa5799e9cab69c074b7920604c8a6c85ad07358a Signed-off-by: Alex Levin <levinale@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48518 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-12-11soc/amd/picasso: rename PICASSO_CONSOLE_UART to AMD_SOC_CONSOLE_UARTFelix Held
This allows factoring out the common initialization for the integrated UARTs. Change-Id: I7399a13b9280b732086c6f8e6dfd9f1207d8c8ff Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48508 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10lib/edid_fill_fb: Support multiple framebuffersPatrick Rudolph
Currently it's not possible to add multiple graphics driver into one coreboot image. This patch series will fix this issue by providing a single API that multiple graphics driver can use. This is required for platforms that have two graphic cards, but different graphic drivers, like Intel and Aspeed on server platforms or Intel and Nvidia on consumer notebooks. The goals are to remove duplicated fill_fb_framebuffer(), to advertise multiple independent framebuffers in coreboot tables, and better runtime/build time graphic configuration options. Add an implementation in edid_fill_fb that supports registering multiple framebuffers, each with its own configuration. As the current code is only compiled for a single graphics driver there's no change in functionality. Change-Id: I7264c2ea2f72f36adfd26f26b00e3ce172133621 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/39002 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-12-10mb/google/zork: Remove unsused codeMathew King
Remove unused code that appears to be left over from grunt. Signed-off-by: Mathew King <mathewk@chromium.org> Change-Id: Id5bdb1c957342d55c5e6378c503b8d90da050601 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48505 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/google/volteer: Fix a few devicetree device refsTim Wawrzynczak
Commit b0e169ac85 included a few small omissions and typos when converting 'device pci xx.y' to 'device ref blah' after adding the new chipset.cb file for TGL. This patch fixes these errors: 1) MIPI camera support requires I2C2 & I2C3 enabled 2) Malefor SAR sensor is on I2C2, not I2C3 BUG=b:175165653 TEST=abuild -p none -t google/volteer -x -a -c max Change-Id: I577957d67f47bbe88bbc2535fb1cb5c8f7390438 Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48511 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2020-12-10soc/intel/xeon_sp/nvs: Use common global NVSMarc Jones
The xeon_sp ACPI NVS and ramstage NVS were out of sync. Since there isn't anything uncommon with the soc NVS, use the Intel common NVS. This covers the NVS cases of common code used by xeon_sp. Update the mainboards for this change. Change-Id: Icf422f5b75a1ca7a3d8f3d63638b8d86a56fdd7b Signed-off-by: Marc Jones <marcjones@sysproconsulting.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48491 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Jay Talbott <JayTalbott@sysproconsulting.com>
2020-12-10soc/mediatek/mt8192: Init DPMHuayang Duan
DPM is a hardware module for DRAM power management and for better power saving in low power mode. BUG=none TEST=Boots correctly on Asurada Signed-off-by: Huayang Duan <huayang.duan@mediatek.com> Change-Id: I16b341ad63940b45b886c4a7fd733c1970624e40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46393 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Add EHL CRB memory initialization supportTan, Lean Sheng
Update memory parameters based on memory type supported by Elkhart Lake CRB: 1. Update spd data for EHL LPDDR4X memory - DQ byte map - DQS CPU-DRAM map - Rcomp resistor - Rcomp target 2. Add configurations for vref_ca & interleaved memory 3. Add EHL CRB on board LPDDR4X SPD data bin file 4. Update mainboard related FSPM UPDs as part of memory initialization Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ifd85caa9ac1c9baf443734eb17ad5683ee92ca3b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Update ehl_crb device treeTan, Lean Sheng
Update Elkhartlake CRB devicetree devices based on EHL EDS. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I88097ced03f4376f309487b9d5207473f77742ef Reviewed-on: https://review.coreboot.org/c/coreboot/+/48124 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Remove JSL sku id info in SMBIOSTan, Lean Sheng
Remove JSL specific SMBIOS sku id info as it is not required by EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Ib672eb456ba62f2eb7f941630c4fbb34823664f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48123 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Remove IPU & MIPI related support from EHL CRBTan, Lean Sheng
THis patch removes IPU & MIPI related support from EHL CRB as they are not supported in EHL. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I3eb038009daaabd048f40c7953cb2c111cd4fe63 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10mb/intel/ehlcrb: Remove board ID detection via ECTan, Lean Sheng
Since there is no EC support on EHL CRB, this patch removes board ID detection via EC (board_id.c & board_id.h) and its related files. Temporarily removes variant_memcfg_config function in romstage_fsp_param.c, will be added back when updating memory configs later. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I40d96285dc05ec5faabc123950b6b3728299e99a Reviewed-on: https://review.coreboot.org/c/coreboot/+/48121 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Remove ChromeOS EC related headersTan, Lean Sheng
Since EHL CRB does not support ChromeOS, this patch removes ChromeOS EC related headers (ec.h & gpio.h) and #includes. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I9c0c3722065c041769081f3d564646ce6a565a9b Reviewed-on: https://review.coreboot.org/c/coreboot/+/48119 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10mb/intel/ehlcrb: Remove ChromeOS EC support from smihandlerTan, Lean Sheng
Since there is no ChromeOS support for EHL CRB, drop smihandler.c which just deals with ChromeOS support. Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: Id474c3b04a82c03dda6514cc4565b58fb790b9c1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48118 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-12-10mb/intel/ehlcrb: Remove ChromeOS support from mainboardTan, Lean Sheng
Since ChromeOS is not officially supported for EHL CRB, removing ChromeOS related codes. Here are the change details: - Remove ChromeOS related kconfig switches, including SOC_INTEL_CSE_LITE_SKU which has dependency on ChromeOS flag - Remove chromeos.c file - Remove ChromeOS dsdt related codes from dsdt.asl & mainboard.c - Remove ChromeOS GPIO related codes from variants.h & gpio.c Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I4aabd40a4b46d4e64534b99e84e0523eaeaff816 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48117 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10mb/intel/ehlcrb: Add missing 'include <console/console.h>'Tan, Lean Sheng
"Die()" needs <console/console.h>, as per this patch: https://review.coreboot.org/c/coreboot/+/45540 Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I0f9fae4a1e43477ca8e78ebbebd8c0729f8b7668 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48116 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/intel/ehlcrb: Add initial mainboard codeTan, Lean Sheng
This is a initial mainboard code cloned entirely from jasperlake_rvp aimed to serve as base for further mainboard check-ins. This patch is based on TGL_upstream series patches: https://review.coreboot.org/c/coreboot/+/37868 List of changes on top off initial jasperlake_rvp clone: 1. Replace "Jasperlake" with "Elkhartlake" 2. Replace "jsl" with "ehl" 3. Replace "jslrvp" with "ehlcrb" 4. Remove unwanted SPD file, add empty SPD as placeholder 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config 7. Empty GPIO configurations, to be filled as per board 8. Empty memory.c configurations, to be filled as per board 9. Add board support namely BOARD_INTEL_ELKHARTLAKE_CRB 10. Replace jslrvp variant with ehlcrb variant Changes to follow on top of this: 1. Add correct memory parameters, add SPDs 2. Clean up devicetree as per tigerlake SOC 3. Add GPIO support 4. Update ehl fmd file to replace 32MB chromeos.fmd Signed-off-by: Tan, Lean Sheng <lean.sheng.tan@intel.com> Change-Id: I2cbe9f12468318680b148739edec5222582e42a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47707 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2020-12-10soc/mediatek/mt8192: add spmfw loaderRoger Lu
This patch adds support for loading spm firmware from cbfs to spm sram. Spm needs its own firmware to enable spm suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. BUG=b:159079649 TEST=suspend with command `powerd_dbus_suspend` and wake up the DUT by powerkey Signed-off-by: Roger Lu <roger.lu@mediatek.com> Change-Id: I6478b98f426d2f3e0ee919d37d21d909ae8a6371 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: enable AER for PCIe root portsMichael Niewöhner
Follow vendor and enable Advanced Error Reporting for PCIe root ports. This enabled the Linux AER driver, which handles PCIe error conditions. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I9d9b5afca0ca891e2812445db1d42a46ba16199e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48369 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: add subsystem ids to PCI ports and devicesMichael Niewöhner
Add the subsystem ids to PCI ports and devices, which were dumped on vendor firmware using `lspci`. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Idb36c5c72e1b0b8303439ae5dce772822f551d2d Reviewed-on: https://review.coreboot.org/c/coreboot/+/48368 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11ssm-f: enable LTR for all root portsMichael Niewöhner
Follow vendor and enable LTR on all root ports to optimize for devices' latency requirements and also optimize power management while preventing failure due to wrongly guessing idle states, which happens without LTR. Tested successfully. No errors show up in dmesg. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: I8f72087c71e291d2412dc7b3e16ee7f419e2ca0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/48367 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-10mb/supermicro/x11-lga1151-series: drop HAVE_ACPI_RESUMEMichael Niewöhner
All X11 boards currently supported have Intel SPS without support for S3/S5. Thus, drop it from Kconfig. Note: not all X11 boards are server boards. When a X11 desktop or workstation board should be added, this can be selected by the boards, where S3/S5 work. Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Change-Id: Ie75c9217078d38c42eba2b30c078b8bb1c2ca694 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure unconnected padsMichael Niewöhner
Correct unconnected pads that are configured different currently by copying vendor configuration while porting the board. Add internal pull resistors to all unconnected pads, that do not have an external pull resistor, to prevent floating. The pads have been determined by dissecting a dead board. This commit only changes pads, that are not connected at all and don't have any via, so we can be absolutely sure there is no other connection. Change-Id: I991fe270b42f430f7447712236e0f80b3d5bba2a Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48099 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-10mb/supermicro/x11ssm-f: (re)configure and document various padsMichael Niewöhner
(Re)configure various pads found by dissecting a dead board and vendor firmware, as well as the BMC firmware: - GPP_B14: input connected to jumper JBR1 - could be used to implement "BIOS Recovery" ("Top-Block Swap") functionality; external pull-up - GPP_C20: output to BMC alert CPU_THROTTLED# - can be used to notify the BMC about a thermal throttling event. Not implemented in vendor firmware. - GPP_C23: input connected to the CPU's CATERR# output; external pull-up Not actively used by vendor firmware. - GPP_D1: output connected to on-board and front panel power LEDs - GPP_D18: output connected to PERST# of both CPU PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D19: output connected to PERST# of both PCH PCIe Slots. Can be used for testing/debugging only, since it resets both slots at once. Not actively used by vendor firmware. - GPP_D22: input connected to the BMC enable/disable jumper JPB1; Will be used later in CB:48096 and CB:48097; external pull-up - GPP_G0 - GPP_G3: dedicated/integrated CPU switching; probably not useful, since the IGD is not connected to any ports on this board. External pulls ensure correct function of a dGPU even without driving the gpios. Not used by vendor firmware. - GPP_G12 - GPP_G16: inputs for binary SKU_ID; external pulls - GPP_G20: PWRFAIL# input from JPI2C1 (pin 3); external pull-up; Not used by vendor firmware. Also add comments for documentation. While at it, mark ME-owned pads as reserved. Change-Id: I9f9328e9ce6f7e291b171f776bb98bc617b64b93 Signed-off-by: Michael Niewöhner <foss@mniewoehner.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48098 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Christian Walter <christian.walter@9elements.com>
2020-12-09mb/google/volteer/variant/volta: add Synaptics touchpad.Sheng-Liang Pan
add new Synaptics touchpad for volta. BUG=b:174802144 TEST=emerge-volteer coreboot and check touchpad function work. Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: I7fc8d08b8b2229ca9252618f159fc9c6f91f9d7f Reviewed-on: https://review.coreboot.org/c/coreboot/+/48395 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/volteer: Reorganize FMAPFurquan Shaikh
This change reorganizes FMAP for volteer to make use of the lower 16MiB of the SPI flash for RW_SECTION_A and RW_MISC in addition to RW_LEGACY. This is now possible because TGL supports memory mapping of BIOS region greater than 16MiB. Following changes are made in chromeos.fmd as part of this: 1. Move RW_SECTION_A and RW_MISC to lower 16MiB. 2. Reduce size of RW_LEGACY to 2MiB since we longer need to use it as a placeholder in the lower half of the SPI flash. 3. Reduce size of RW_ELOG to 4KiB as coreboot does not support a larger region for ELOG. 4. Increase WP_RO to 8MiB to allow larger space for firmware screens. GBB size is thus increased to 448KiB. BUG=b:171534504 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I0c3c0af94183a80c23d196422d3c8cf960b9d9f5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48187 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-09mb/google/dedede: Update Boten GPIO setting for PEN detection.Stanley Wu
AP_PEN_DET_ODL isolated by a diode and need to pull up internally. BUG=b:160752604 BRANCH=dedede TEST=Build and confirm waveform by google EE parter. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: I85f3d0209094af07891a5c0cc218443da586e6e2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48294 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/zork/var/vilboz: Update telemetry settingsJohn Su
Update telemetry settings. VDD Slope : 32643 -> 26939 VDD Offset: 208 -> 125 SOC Slope : 22742 -> 20001 SOC Offset: -83 -> 168 BUG=b:171668654 BRANCH=zork TEST=1. emerge-zork coreboot 2. pass AMD SDLE test report Signed-off-by: John Su <john_su@compal.corp-partner.google.com> Change-Id: Ic63e069310aa4a66cd4c9058790dbed37e6967f4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48288 Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/intel/adlrvp: Add PMC.MUX.CONx device config for Conn2V Sowmya
This patch adds the PMC MUX and CONx devices for adlrvp for conn2. BUG=b:170607415 TEST=Built and booted adlrvp. Verified the PMC.MUX CONx objects in SSDT tables. Change-Id: I52afbd429750cfa416f4ed93aeb1be590f8c3a5c Signed-off-by: V Sowmya <v.sowmya@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48230 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-12-09mb/google/dedede/var/metaknight: Support Elan/Synaptics touchpadTim Chen
Add Elan and Synaptics touchpad settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: Ice0a86cd5610db269d44acb1d51cb652110d9b0c Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47441 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-09mb/google/dedede/var/metaknight: Add audio related settingsTim Chen
Add HDA,speaker codec and speaker amp settings. BUG=b:169813211 BRANCH=None TEST=build metaknight firmware Change-Id: I9b1057eac94b568914f17fcccee58a0e403ccec0 Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47438 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raymond Wong <wongraymond@google.com> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-12-08mb/google/deltaur: Restrict RW_DIAG to lower 16MiBFurquan Shaikh
This change restricts RW_DIAG region to lower 16MiB to ensure that the extended BIOS checker for FMAP does not complain about 16MiB boundary crossing. I haven't updated any other regions to occupy the newly freed space but it is fine since this board is dead and should be dropped from coreboot soon. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I19ab204fbe3e020e42baf68bfa350dcff32066a3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48190 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-12-08mb/intel/tglrvp: Restrict SI_ME region to lower 16MiBFurquan Shaikh
This change restricts SI_ME region to live below the 16MiB boundary to ensure that no regions cross the 16MiB boundary as the extended BIOS window checker for FMAP complains about it. Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib0838ff4c63b06b8dc169b40d3022965b2f2f8f9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48189 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2020-12-08mb/google/volteer/variant/lindar: Add PMC.MUX.CONx device configuration and ↵Kevin Chang
disabling DDI port 1 and 2 HPD. This patch adds the PMC MUX and CONx devices for lindar. Device specific method contains the port and orientation details used to configure the mux. BUG=b:172533907 BRANCH=firmware-volteer-13521.B TEST=Built and booted into OS. Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com> Change-Id: Id5ee78b7ece8421144086af9b95f5f0d849be56c Signed-off-by: Kevin Chang <kevin.chang@lcfc.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/47434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-12-08mb/*: Remove SATA mode config for CNL based mainboardsFelix Singer
SATA_AHCI is already the default mode for CNL based mainboards. Therefore, remove its configuration from all related devicetrees. Built clevo/l140cu with BUILD_TIMELESS=1, coreboot.rom remains identical. Change-Id: I814e191243224a4b021cd7d4c1b611316f1fd1a4 Signed-off-by: Felix Singer <felixsinger@posteo.net> Reviewed-on: https://review.coreboot.org/c/coreboot/+/48391 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 10:08:42 +0000