summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2018-10-06mb/google/octopus/variants/fleex: Disable I2C0 in devicetreeFurquan Shaikh
Fleex does not have any device on I2C0 and hence this change disables I2C0 device (16.0) in devicetree and gets rid of the I2C tuning parameters for I2C0. BUG=b:115600671 Change-Id: Ib799eae05b667cee2272bbd37f0ca44b7cec66cd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-06mb/google/octopus: Disable I2C3 in devicetreeFurquan Shaikh
I2C3 is connected to the debug header and won't be required unless connecting the debugger. This change disables I2C3 device (16.3) in devicetree. Change-Id: I650fa040075119a21864c83d8470dd2155c9edb9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28930 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
2018-10-06mb/google/poppy/variants/nocturne: Add DMIC properties to ACPI DSDFurquan Shaikh
This change uses the generic device driver to provide DMIC properties in ACPI table to the OS driver. BUG=b:112888584 Change-Id: I239f571bc29f02793f017a4713b5af03b23cfa3e Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28797 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: HARSHAPRIYA N <harshapriya.n@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-06soc/intel/.../hda: Add and use config for initialization of HDA codecsFurquan Shaikh
Config option SOC_INTEL_COMMON_BLOCK_HDA is currently used for initialization of HDA codecs only. This prevents adding of any static devices under the HDA device node. However, there can be boards which want to add devices under HDA node (e.g. nocturne that wants to provide DMIC properties to OS) without performing any codec initialization using the HDA. This change: 1. Adds a new config option SOC_INTEL_COMMON_BLOCK_HDA_VERB that can be set explicitly by the boards that want to perform codec initialization. 2. Uses newly added config option is used to guard the initialization functions for the codec. Rest of the device operations can still be used by all the other boards without having to use HDA codec initialization. 3. Selects the newly added option SOC_INTEL_COMMON_BLOCK_HDA_VERB in kblrvp which is the only board enabling HDA codec initialization using common block code. 4. Selects original config SOC_INTEL_COMMON_BLOCK_HDA for skylake SoC. Above changes need to be bundled and pushed in as a single change in order to avoid breaking existing users. BUG=b:112888584 Change-Id: Ie6f39c13a801833b283120a2d4b6f6175688999c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28806 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-10-05mb/google/octopus: adjust Bobba I2C CLK under 400KHzPan Sheng-Liang
Need to tune I2C bus 0/6/7 clock frequency under the 400KHz for digitizer, touchpad, and touchscreen. Bug=b:117126484 TEST=flash coreboot to the DUT and measure I2C bus 0/6/7 clock frequency whether can <400KHz Change-Id: Icb9592c688b864a21efd4963a4463845dfaa06fb Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28907 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05mb/google/poppy/variants/nautilus: Change SlowSlewRate settings for LTE skuSeunghwan Kim
Nautilus-LTE sku shows abnormal reset symptom at high temperature chamber test, but the root cause is unclear. Experimentally, setting SlowSlewRate IA/GT/SA to 1/2 improves this abnormal reset issue, so we would apply it until find root cause of this issue. BUG=b:117130599 BRANCH=poppy TEST=Built and passed on reliability test with modified coreboot Change-Id: I7fa0041989113097e3b283dbcf4ca2a73629fe54 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28785 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-05atlas: control touchscreen power using ACPICaveh Jalali
This adds the ACPI controls for power sequencing the touchscreen. The initial setting is to keep the touchscreen powered off and in reset. When linux is ready to talk to the touchscreen, it powers it on and releases reset via ACPI. BUG=b:110286344 TEST=verified touchscreen is functional in chromeos Change-Id: I58c42a8f09342cfe54f82ef0e6cd8ea72a5140dc Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28869 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/kahlee: Don't set stapm parametersMartin Roth
Setting the stapm parameters is causing S3 resume failures and performance issues. Removing these settings until more testing is done and the issues are solved. BUG=b:117252463, b:116870267 TEST=boot grunt Change-Id: I2299ab81fcc2af0529bfac3be562b05116c64a49 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28925 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
2018-10-04google/grunt: Correctly extract OEM string from CBFSKevin Chiu
In CBFS layout: oem.bin size is 10 bytes. In cbfs_boot_load_file, buffer size will need to be larger than decompressed_size, otherwise CBFS data can not be extracted into buffer. Then we need to check buffer whether it's empty string separately. BUG=b:79874904 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I4f1bbb690ecca515ac920f5058ee19b5bfd8fa5e Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28889 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-04mb/intel/cannonlake_rvp: Move FSP param override function to separate fileRizwan Qureshi
Move the FSP param initialization function to a separate file, as being done on the SoC side and remove the empty romstage.c file. Change-Id: Ibe64bc4ebfdbbb124bcd460dc419da1f469aa7fa Signed-off-by: Rizwan Qureshi <rizwan.qureshi@intel.com> Reviewed-on: https://review.coreboot.org/28662 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mb/google/poppy/variant/nocturne: update GPIO configurationNick Vaccaro
GPP_C19 is not being set as the code is incorrectly setting GPP_C16 instead, causing SAR sensor not to work, so this change sets GPP_C19 to NF1. GPP_E3 is not being initialized in the code. Initialize GPP_E3 to a no connect as documented in the board schematic. BUG=b:117124878 TEST: 'emerge-coreboot chromeos-bootimage', flash nocturne and verify that i2c transactions work for the left SAR sensor. Change-Id: I9e972dbe4214cdd15d80d63dfa058e7755f7ecbb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28867 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variant/nocturne: increase touchscreen reset delayNick Vaccaro
Increase the reset delay for the touchscreen to 10 ms. BUG=b:116857433 TEST='emerge-nocturne coreboot chromeos-bootimage', flash and boot nocturne to kernel, log in and execute the following two commands: echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/unbind echo "i2c-WCOM50C1:00" > /sys/bus/i2c/drivers/i2c_hid/bind and verify the bind command does not echo back a "-bash: echo: write error: No such device" error. Change-Id: I102b57ea5a10d22bee6d4f7c6f114b380a5d586b Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28803 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Caveh Jalali <caveh@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-04mb/google/poppy/variants/rammus: Shorten oem_table_id to RAMMUSmarxwang
This patch modifies "oem_table_id" from "RAMMUSMAX" to "RAMMUS" so that the audio topology file can be loaded properly by the operating system. BUG=b:112945714 BRANCH=master TEST=There is no error message like "failed to load topology firmware" in kernel v4.4 log. Change-Id: I66a38ea38791dd3d9606a05b7b696236c350237f Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28870 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for FleexIvy Jian
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 2 for DVT. BUG=b:116721822 TEST=Verified it in Fleex EVT board which rework ram id. Change-Id: I0f191c950aa6a70069bffa1f1802386ab263a310 Signed-off-by: Ivy Jian <ivy_jian@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28782 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marco Chen <marcochen@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-10-04mb/google/nocturne: Define GPP_D17 as EC_SYNC_IRQDuncan Laurie
Use GPIO GPP_D17 pin as the EC sync interrupt and provide this value to the embedded controller to be exported to the OS. This interface was tested on a reworked Nocturne board with modified EC and a modified kernel driver to ensure that the interrupt asserts as expected and can be used by the kernel driver. Change-Id: Ie2b33692367b5d9ecc2b128180d8cfe4f6b347b1 Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/28759 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-04mc_apl1: Set up SPI OPCODE menu before lockingWerner Zeh
In order to enable the OS SPI driver to use the software interface of this controller the OPCODE menu has to be set up properly before locking the controller. This is done on baseboard level so that all variants will get this done as well. Change-Id: I0bf0619ff0610c00325f03d13b6794aee8a62504 Signed-off-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-on: https://review.coreboot.org/28834 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
2018-10-03mb/google/kahlee: Update careena Audio/TP i2c timingKevin Chiu
After adjustment on Careena Audio: 402.805 kHz -> 396.8 kHz TP: 406.1 kHz -> 399.5 kHz BUG=b:110984023 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ia3eb91ca3772d5f122498e3989ec03838fce06a5 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-10-03google/kahlee: Enable IOMMU deviceMarc Jones
Enable the IOMMU device on all kahlee based mainboards. BUG=b:116196614 TEST=Check dmesg for AMD-Vi messages. Change-Id: I18b9ba1a970c6973226e736d72f82fd53010f31c Signed-off-by: Marc Jones <marc.jones@scarletltd.com> Reviewed-on: https://review.coreboot.org/28754 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01mb/google/octopus: Operate touchpad I2C CLK in specChris Zhou
Need to tune I2C bus 6 clock frequency under the 400K Hz Bug=b:115600671 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 398.07K Hz Change-Id: I5cc1f67f0db0553cb8424f81408ed4686cddb2fb Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28760 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-10-01google/kahlee: Run FCH PTS and WAK methodsMarshall Dawson
The FCH ASL is now capable of controlling the D-states of most AOAC devices, as well as properly reinitializing the xHCI firmware on a resume. Call the FPTS and FWAK methods. BUG=b:77602074 TEST=On Grunt, go to S3 and wake with a USB keyboard Change-Id: I4df8523569dc3dfbd87f79e780c18d39f0d9a37f Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/28773 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-10-01siemens/mc_apl1: Activate clock spreading for PTN3460Mario Scheithauer
In order to minimize Electromagnetic Interference (EMI) on the LVDS interface driven by PTN3460, clock spreading must be activated for mc_apl1 mainboard. The modulation ratio is set to 1 % of the nominal frequency. Change-Id: Ie457fcdbb6239dc0b25e2c35ad7a310ee80383f9 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28761 Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-30mainboard/opencellular/elgon: Add mainboard supportPhilipp Deppenwiese
Tested on Elgon EVT board and boots into GNU/Linux. TODO: * Add hard reset function for VBOOT. * Add EC code * Add SPI flash write protection Change-Id: I9b809306cc48facbade5dc63846c4532b397e0b5 Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org> Reviewed-on: https://review.coreboot.org/28024 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-28mb/lenovo/t400: Add 154WX5-TLB2 to display backlight PWM freq listArthur Heymans
Vendor VBT on ThinkPad R500 intends to set a 220MHz backlight PWM frequency which seems to work well. Change-Id: Ic1a12c7e3173468561ed5615319962d0abc6d61b Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28643 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-28mb/lenovo/t400: Link the gpio.c settingsArthur Heymans
Linking this file instead of including a header makes it possible to easily change gpio settings for a variant. Change-Id: Ifd496510d4868f5901a9dbbf7f1523ccffaf15ab Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28628 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28mb/lenovo/t400: Trim down the gpio.h fileArthur Heymans
Some settings like direction are only used if the mode is GPIO. Change-Id: I4efc54dfef3721b528b90d49f490014d9132cdf8 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28627 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28src/mb/asrock/g41c-gs: Add variant g41m-s3Angel Pons
This board is pretty much like the G41M-GS, but with DDR3 memory instead. The PCB layout is almost identical. What works: - S3/S4 resume - RAM init - Booting to Debian - Display lights up w/ libgfxinit - Both PS/2 work - Ethernet - Graphics card on PEG - USB - SATA ports - NVRAM debug_level - Internal flashing - PCI slots (tested with CT4810 audio card) - fancontrol (Only CPU fan can be regulated) - Audio (Rear ports only) What does not work: - Hell knows what might be wrong What is not tested: - PCIe x1 - IDE - Floppy - Parallel port Change-Id: I66b216af740680c390ea82e4fe07737c20227cc6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28434 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-28mb/intel/coffeelake_rvp: Enable GbE supportLijian Zhao
Enable Gigabit Ethernet network controller on whiskey lake rvp platform, add NVM bin file as well. BUG=N/A TEST=Build and boot up into chromeos on whiskey lake rvp platform, and check eth0 can get IP address assigned, Change-Id: Ia299a2aa78108175074e084cc34a7d2b38cf1c72 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27848 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28mainboard/google/poppy/variants/rammus: Modify VR settingstatham_chu
We refer to Intel Doc#594883. The recommended Ac/Dc loadline values are as below: # VR Settings Configuration for 4 Domains #+----------------+-------+-------+-------+-------+ #| Domain/Setting | SA | IA | GTUS | GTS | #+----------------+-------+-------+-------+-------+ #| Psi1Threshold | 20A | 20A | 20A | 20A | #| Psi2Threshold | 2A | 2A | 2A | 2A | #| Psi3Threshold | 1A | 1A | 1A | 1A | #| Psi3Enable | 1 | 1 | 1 | 1 | #| Psi4Enable | 1 | 1 | 1 | 1 | #| ImonSlope | 0 | 0 | 0 | 0 | #| ImonOffset | 0 | 0 | 0 | 0 | #| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | #| AcLoadline | 14.4 | 4.2 | 5.7 | 4.47 | #| DcLoadline | 14.0 | 4.17 | 4.2 | 4.3 | #+----------------+-------+-------+-------+-------+ BUG=b:112167318 BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I2d83d835ec841ac4cc811a0a69f74d203d5ea173 Signed-off-by: statham_chu <statham_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28695 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-28soc/intel/cannonlake: Update UPD from device switchLijian Zhao
Some of the FSP silicon UPD entry can be updated base on device switch in pci device tree, have both static config setting and device tree "on" and "off" will be redundant. BUG=N/A TEST=Build and boot up fine with Whiskey Lake RVP platform. Change-Id: Ia36cfab03c4613786e5580a039d89007b630adf9 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27766 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-28src/*: normalize Google copyright headersPatrick Georgi
As per internal discussion, there's no "ChromiumOS Authors" that's meaningful outside the Chromium OS project, so change everything to the contemporary "Google LLC." While at it, also ensure consistency in the LLC variants (exactly one trailing period). "Google Inc" does not need to be touched, so leave them alone. Change-Id: Ia0780e31cdab879d2aaef62a2f0403e3db0a4ac8 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28756 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Joel Kitching <kitching@google.com>
2018-09-27siemens/mc_apl1: Add new mainboard variant mc_apl2Mario Scheithauer
This mainboard is based on mc_apl1. In a first step, it contains a copy of mc_apl1 directory with minimum changes. Special adaptations for mc_apl2 mainboard will follow in separate commits. Change-Id: I0af60ab0dfe556dd95da2cf1a49c685a8f0ae4eb Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28735 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-27siemens/mc_apl1: Make the DDR memory swizzle data configurableMario Scheithauer
In preparation for a future MC Apollo Lake board which will be equipped with LPDDR4 modules, it is necessary to make the swizzle data configurable. Starting from the mc_apl1 baseboard, which is equipped with DDR3L memory and therefore does not need swizzle data, the structures are initialized with zero. Change-Id: I4954d0a00d1d5fc28a8dda45a9fb27f98d5c3f1e Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28730 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-09-26mb/google/poppy/variants/nocturne: Update PowerLimit1 maximum valueSumeet Pawnikar
Increase power limit1 maximum value from 5W to 7W. This value as per recent measurement on closed system which shows better performance results. BUG=None TEST=Build and tested on Nocturne system. Performance tests show better results. Change-Id: I7485b1d2afde46ec28d548c13be35a43e7572918 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28686 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-26mb/google/poppy/variants/nocturne: Add tdp_pl1_override valueSumeet Pawnikar
Add tdp_pl1_override value as 7W. BUG=None BRANCH=None TEST=Build coreboot for Nocturne board Change-Id: I16d3894da68bc3be6eff526062f9a88ef2df60c7 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28708 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Puthikorn Voravootivat <puthik@chromium.org>
2018-09-26mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
The previous does not work well enough when testing with high ambient temperature. Update DPTF settings to make it work better. List of tweaks: 1. Raise DRAM Critical temperature from 48C to 55C Note that there are mechanisms in EC that complement this because of DPTF limitation that we can't have multiple passive temperatures. 2. Lower response time for DRAM temp sensor from 60s to 5s. 3. Increase throttle priority to the charger when DRAM hit passive temperature from 100 to 200. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: Idf7efa76b2c6085cf97aa9f65c6ce066e8cff99a Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28738 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26cheza: Wrap FMAP sections with calibration data in RO_PRESERVE sectionJulius Werner
The Cheza board contains a couple of non-standard FMAP sections that contain per-board calibration data. When flashing new firmware to the board, care should be taken to copy these sections over so that all features can still function correctly afterwards. This patch wraps a new RO_PRESERVE FMAP section around these sections to make them easier to preserve as a group. Change-Id: I77919336f609a1be399598736f46921c3da99e68 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28728 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: T Michael Turney <mturney@codeaurora.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
2018-09-26src/mainboard/pcengines/apu2/Kconfig: Clean up PINMUX settingsMichał Żygowski
Configuration of pins exposed by superIO are inconsistent between board variants. Each platform should have UARTs enabled, this is expected behaviour of these pins. Given that APU2_PINMUX_UART_x can be set for all boards as default. Change-Id: Ifb7dfe23a95ba0e572adc38212333d9fdd234d53 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/28720 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-26mb/lowrisc: Remove the Nexys4DDR portJonathan Neuschäfer
This board doesn't support the newest RISC-V Privileged Architecture spec (1.10), and it's based on an FPGA so it's a moving target. Now that there's actual RISC-V silicon out there (from SiFive), mb/lowrisc/nexys4ddr will only continue to bitrot. Change-Id: I4e3e715106a1a94381a563dc4a56781c35883c2d Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-on: https://review.coreboot.org/28706 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Hug <philipp@hug.cx> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-26src/mainboard/pcengines/apu2/Kconfig: Remove TPM1 optionMichał Żygowski
Apu2 boards use Infineon SLB9665 TT 2.0 module which is TPM2.0. Remove TPM1 option to allow choice between TPM1 and TPM2. SLB9665 TT 2.0 detection fixed in change 21983. Change-Id: Ie9788c43d8b32b2f6329a072b88c962c34eca119 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/28000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-26mb/google/octopus: Touchpad I2C CLK (405.25KHz)over spec(＜400KHz)peichao.wang
Need to tune I2C bus 6 clock frequency under the 400KHz Bug=b:116543001 TEST=flash coreboot to the DUT and measure I2C bus 6 clock frequency whether arrive to 399.1KHz Change-Id: I95b535a6b429fc34961a4953004a1c51e53a9be6 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28747 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26Revert "mb/google/poppy/variants/nautilus: Set grip sensor threshold"Seunghwan Kim
This reverts commit aef592d9b66aa18d83b0a211ead26013ff1f7d98. Reason for revert: Use values from driver instead of hardcoding in firmware (b:113303916) Change-Id: I02d21803f38da227f1d85b00cb6b5274d81dbbb4 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28690 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-26mb/google/octopus: Close unused I2C bus 7 include SCL and SDA for PhaserPeichao Wang
Since I2C bus 7 attached the touchscreen device however Phaser units that haven't it. So for avoiding side effects, we need close I2C bus 7 SCL and SDA respectively. BUG=none TEST=according to sku_id (Phaser: 0x1, Phaser360: 0x2, Phaser360s: 0x3) distinguish whether close these gpios. Change-Id: I8ad17761f2a053dc329bbec0a0a3284d47289666 Signed-off-by: Peichao.Wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28669 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Jett Rink <jettrink@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-25mainboard/google/kahlee: Only read a single vendor from oem.binMartin Roth
Since each variant has a separate build, we don't need to support multiple manufacturers in a single file. BUG=b:79874904 TEST=Build, boot, see updated mainboard manufacturer Change-Id: I0ccf207ba8d5e5200aa4b19c46784bbda82f7b6e Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28729 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-09-25mb/google/kahlee/variants/liara: Disable NbP-state on LiaraAmanda Huang
To disable NB-Pstate, the system wouldn't auto restart on EVT board when idling. BUG=b:116082728 Change-Id: Iec4f0355cb6eb1c2b0372e3d131cc5e6ba36635e Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28726 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25mb: Use 'unsigned int' to bare use of 'unsigned'Elyes HAOUAS
Change-Id: I3a8e077656df02912b4e67c3947bd5af054a18bf Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28701 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-25mb/asrock/g41m_vs3_r2: Add mainboardArthur Heymans
The following was tested: - CPUs with 800, 1067, 1333MHz FSB (1333MHz FSB needs a jumper set) - The VGA output with libgfxinit - USB - COM1 - Ethernet - SATA - PCIe - PCI Has the following problems: - The Ethernet NIC is not usable after S3 resume and requires Linux to reload the driver. Vendor firmware also has this problem so it is quite likely it is just a atl1c driver problem. TODO: Add documentation Change-Id: Ibce9ecdc0e44db3703401f116c9a8bff5b66437f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28596 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-24soc/amd/stoneyridge/romstage.c: Move STAPM code to SOC specificRichard Spiegel
STAPM programming was created inside function OemCustomizeInitEarly(). It should be SOC specific, and called by agesawrapper just before the call to OemCustomizeInitEarly(). BUG=b:116196626 TEST=build and boot grunt Change-Id: I8a2e51abda11a9d60a9057b38f2a484e1c8c9047 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28705 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/octopus: Create ampton variantJustin TerAvest
This commit creates an ampton variant for Octopus. The initial settings are copied from Bip, but the following changes are made to support hardware differences: * GPIO_66 is not connected (LTE). * GPIO_67 is not connected (LTE). * Updated comment for GPIO_134 (EC_AP_INT_ODL), but not configured yet. * GPIO_143 is not connected. * GPIO_144, GPIO_145 mapped to PEN_EJECT are not connected. * EN_PP3300_TOUCHSCREEN moved from GPIO_213 to GPIO_146. * GPIO_213 is not connected. * GPIO_214 is not connected. BUG=b:111498206 TEST=None Change-Id: I7d6cf19c906df19115b1101e3d91c62f5f3f61e3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/28663 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-21mb/intel/coffeelake_rvp: Add whiskey lake rvpLijian Zhao
Add new mainboard variant of whiskey lake rvp, which is primary validation platform for whiskey lake silicon, support socket DDR4 memory module. BUG=N/A TEST=Build and flash, confirm boot up into kernel on whiskey lake rvp platform. Change-Id: I4a5e8a9ec76d5e55e55ef9bf968825c17fbe9816 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/27628 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21mb/google/poppy/variants/rammus: Disable command TriState for rammusmarxwang
This patch sets the MRC UPD "CmdTriStateDis" to disable TriState for the rammus boards. Rammus is LPDDR3 design without RTT for CMD/CTRL. BUG=none TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: Iee115f49ba5b36dc5b0425e9da02b58cd19b2236 Signed-off-by: Marx Wang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28568 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/intel/coffeelake_rvp: Correct LPDDR4 to DDR4 in mainboard infoLijian Zhao
There's only DDR4 or LPDDR3 support for coffelake processor line, details can be found out on EDS #570805. BUG=N/A TEST=N/A Change-Id: I8ba6b6861b15b40b01237f87c8d55394f7fd6706 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28236 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-21mb/intel/coffeelake_rvp: GPIO support for whiskey boardLijian Zhao
Add gpio programming difference for whiskeylake rvp platform. BUG=N/A TEST=N/A Change-Id: I35a0384f828fd3219e0c3adb4830f5bdab800e32 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28367 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21google/kukui: Set up EC_IN_RW GPIO for ChromeOSTristan Shieh
Set up EC_IN_RW GPIO to boot depthcharge. Without this patch, depthcharge will fail to tell if the EC firmware is RW. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC_IN_RW GPIO. Change-Id: Icb39d663f65b72e0ad54059c9590d9693106ee25 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28670 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mb/google/poppy/variant/nocturne: set DMIC1 to NCNick Vaccaro
Change GPP_D17 and GPP_D18 to no connects as DMIC was moved to DMIC0. BUG=b:113744731,b:111106010 TEST=none Change-Id: I8ef42627e542182707c81389af9da33a114bc184 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/28689 Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-21mainboard/google/kahlee: allow oem.bin file to update smbiosMartin Roth
Grunt variants need a way to customize the mainboard vendor based on the platform. For future boards, this can probably be done via CBI, but grunt doesn't support that method. BUG=b:79874904 TEST=Build, boot, see updated mainboard vendor Change-Id: I997dc39c7f36f70cf4320ef335831245889eb475 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28651 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@google.com>
2018-09-21mb/google/octopus/variants/fleex: Update DPTF parametersSumeet Pawnikar
Update Power Limit1 and Power Limit2 values along with stepsize. Correct the charger effect for Temperature sensor2. BUG=b:112448519 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I01e0a94fe694537d9eebe3b92c11d0c83137d716 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28530 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/lenovo/{T500, R400, W500}: Unify variants under T400Arthur Heymans
A negative side-effect is that those boards disappear from the board-status output, but this is an issue on all variants. Change-Id: Ic80804dc1f7d9c6f83ceee3db667019532c31d4c Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28626 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/zoombini: Use Chrome EC BOARDID definitionKarthikeyan Ramasubramanian
The board_id() definition is the duplicate of chrome EC board_id definition. Remove the duplicate definition and select EC_GOOGLE_CHROMEEC_BOARDID Kconfig item. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Id8b7027d653649e8e5791e455652c4e893a746c2 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Tested-by: Karthikeyan Ramasubramanian <kramasub@codeaurora.org> Reviewed-on: https://review.coreboot.org/28609 Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20ec/google/chromeec: Update google_chromeec_get_board_version prototypeKarthikeyan Ramasubramanian
The helper function to get the board version from EC returns 0 on failure. But 0 is also a valid board version. Update the helper function to return -1 on failure and update the use-cases. BUG=b:114001972,b:114677884,b:114677887 Change-Id: I93e8dbce2ff26e76504b132055985f53cbf07d31 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28576 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com>
2018-09-20mb/google/poppy/variants/nocturne: Update DPTF settingsPuthikorn Voravootivat
Update DPTF settings based on recommendation from thermal team. BUG=b:112550414 BRANCH=None TEST=Manually tested by thermal team. Change-Id: I26f09392a3293ce4b3481f2be341a667d606bc10 Signed-off-by: Puthikorn Voravootivat <puthik@chromium.org> Reviewed-on: https://review.coreboot.org/28666 Reviewed-by: Todd Broch <tbroch@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-20mb/google/octopus: Enable DRAM_PART_NUM_IN_CBI feature for meepWisley Chen
Enable DRAM_PART_NUM_IN_CBI feature to get DRAM part number from CBI and set DRAM_PART_IN_CBI_BOARD_ID_MIN to 1 for EVT. BUG=b:115965629 TEST=verified it in meep proto board which rework ram id. Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Change-Id: I962b099d5b9fbe0ca29708be1e9c6ed60b10d363 Reviewed-on: https://review.coreboot.org/28658 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-09-20mb/lenovo: Add libgfxinit support on Lenovo T520Evgeny Zinoviev
Change-Id: I4fcdb7467f1911af722f4c24ce64807079a91340 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28620 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-18mb/asrock/g41c-gs: Link separate gpio.c filesArthur Heymans
With the addition of new boards using macros to set per board settings in the same gpio.c file is getting too complicated so link separate files. Change-Id: I3ab05f1af6ba0a04dd827816b3bcaa506a3f6aff Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28630 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2018-09-18mb/google/kahlee/variants/careena/devicetree.cb: Set STAPM valuesRichard Spiegel
AMD has tested careena, and for the time being is recommending a scalar of 68%, power limit of 7.8 W and time constant of 2500. Using new STAPM configuration code, set the desired values. BUG=b:111561217 TEST=none, code was tested with grunt. Change-Id: I42671ab0e66b21dc4f8c8c326c1fa33328b1390e Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28597 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com>
2018-09-18mainboard/google/kahlee: Set EMMC reset pin to output lowMartin Roth
While the pin was set to a pull-down, with the external pull-up, this wasn't enough to keep the pin low. Set to output low to drive to 0V. TEST=Boot grunt, verify EMMC_BRIDGE_RST is 0V. BUG=b:115661061 Change-Id: Ife014b8a879274df5d892c1de386976808de1df0 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28649 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18mainboard/google/kahlee: Don't set global subsystem IDsMartin Roth
These values override the default subsystem IDs, and aren't needed. BUG=b:113253260 TEST=Boot grunt Change-Id: I3c56534b094ede8d8200b72f4433a891d0094064 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/28652 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Marc Jones <marc@marcjonesconsulting.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-18mainboard/pcengines: select ADD_SEABIOS_SERCON_PORT_FILEMichał Żygowski
PC Engines boards are interfaced mainly via serial console. Enable SeaBIOS serial console for these boards by default when SeaBIOS selected as payload. Change-Id: I9e65dd1e28859028c8c46f28a5442de8c59d4893 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Reviewed-on: https://review.coreboot.org/27824 Tested-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2018-09-17mb/google/kahlee/variants/baseboard: Set STAPM percentageRichard Spiegel
Default STAPM percentage causes a lot of thermal throttling on grunt. AMD experimented with 80%, it works for grunt. This is initial code to provide easy change path for other grunt based platforms. BUG=b:111608748 TEST=build and boot grunt. Change-Id: I22863f6ed76152bf872fce3e275f8a7fd8077504 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/28564 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-17google/buddy: Add board as variant of google/auronMatt DeVillier
Add google/buddy (Acer Chromeboase 24) as a variant of google/auron, with the following changes: - add buddy-specific variant code - add handling to auron for buddy's lan init, which no other variants have - add handling to auron's mainboard ACPI due buddy having different PCIe port assigments than all other variants Ported from Chromium branch firmware-buddy-6301.202.B, commit ebb82ce [Buddy: Lock management engine + SPI descriptor] Test: build/boot Linux on google/buddy using SeaBIOS and Tianocore payloads Change-Id: Ib76eef47677b72ddaef81a2decef189a5f20c20a Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28613 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-17google/auron: Clean up variant-specific romstage codeMatt DeVillier
Use an empty weak function for variant_romstage_entry(), rather than having separate empty functions for boards which don't utilize it. Change-Id: I7a278ed716484bea377a5dd98d4a534502c8bab6 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28612 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-09-16google/kukui: Configure EMMCTristan Shieh
Set up EMMC gpios for payloads. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui Change-Id: I1e7ee9bfe3a26ed04374e8c74243f48552a1d254 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28546 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-09-16mb/google/poppy/variants/rammus: fix S0ix entering issueZhuohao Lee
As we don't use the MIPI camera on Rammus, disable SA Imaging Unit and CIO2 devices to avoid the system failed to enter S0ix. BUG=b:114502527 BRANCH=master TEST=On DUT, echo freeze > /sys/power/state 1. check the S0ix status on EC console 2. check the value of /sys/kernel/debug/pmc_core/slp_s0_residency_usec Change-Id: I91629732db01ee534f0ddb67a2b358d725ef810e Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-16google/kukui: Notify EC that AP is in S0Hung-Te Lin
We have a pin from AP to EC, called AP_IN_SLEEP_L (SRCLKENA0 on AP side, pad R23) that is supposed to be high in S0, and low in S3 (and X/don't care in S5). This should be set as early as possible in bootblock. BUG=b:113367227 TEST=make; boots and verified AP_IN_SLEEP_L GPIO is high. BRANCH=None Change-Id: Icd59fa366c162e7443b8932a851e65f110f551ab Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/28585 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@google.com>
2018-09-16mb/intel/coffelake_rvp: Implement mainboard memory informationLijian Zhao
Turn on SOC_INTEL_CANNONLAKE_MEMCFG_INT for coffeelake rvp platform for easier collabration on newer platform. The setting in memory.c get from board design itself. BUG=N/A TEST=Build and boot up with whiskey lake rvp platform. Change-Id: I10f3af4bed511153cef4d6f3a93caea57cc4ae90 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28257 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-16mb/google/poppy: Set UPD CmdTriStateDis for AtlasCaveh Jalali
This patch sets the MRC UPD CmdTriStateDis for the atlas boards. Atlas is a LPDDR3 design without RTT for CMD/CTRL. The original change for nocturne is I0f593761dcbd121e7e758421af178931b9d78295 mb/google/poppy: Set UPD CmdTriStateDis for Nocturne BUG=b:111812662 Change-Id: I45b6dd22412c689c8db64f4650e9fa9e87dec2ec Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28540 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-09-15mb/lenovo: Add Lenovo W500 as clone of Lenovo T400Paul Menzel
At ECC 2017 user Bob reports, that an image built for the Lenovo T500 runs on the Lenovo W500 without any issues. Change-Id: I17fd9725ab85ba2f0c99a70f40e35432265a81c1 Signed-off-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-on: https://review.coreboot.org/22226 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Felix Singer <migy@darmstadt.ccc.de> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15sifive/hifive-unleashed: enable CBMEM supportPhilipp Hug
Change-Id: I3eacba9c1c20bbfa270dd7a9afabe48ed9092bcc Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28622 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15soc/sifive: move ram_resource to mainboardPhilipp Hug
ram_resource is board specific and should be moved there. Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-15pcengines/apu2: enable IOMMU for all apu2 variantsPiotr Król
IOMMU was tested on Xen 4.8 and Linux kernel 4.14.33. Following feature set is enabled: (XEN) AMD-Vi: Disabled HAP memory map sharing with IOMMU (XEN) AMD-Vi: IOMMU Extended Features: (XEN) - Peripheral Page Service Request (XEN) - Guest Translation (XEN) - Invalidate All Command (XEN) - Guest APIC supported (XEN) - Performance Counters (XEN) AMD-Vi: IOMMU 0 Enabled. Change-Id: I6dbfae78849248f3532caa78974c8f2ce61a530d Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/26116 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetreeArthur Heymans
Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-14soc/sifive/fu540: Initialize SDRAMPhilipp Hug
Based on SiFive bootloader code Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28604 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14soc/sifive/fu540: Switch clock to 1GHz in romstagePhilipp Hug
Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14mb/google/octopus: Query the EC for board versionKarthikeyan Ramasubramanian
The board version is part of EC's EEPROM, but is not being populated from EEPROM. Instead a default Kconfig parameter is returned as board version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable requesting the EC for board version. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-14mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phasepeichao.wang
This modification for DVT build and use CBI method enable all memory particles. BUG=b:112870780 TEST=verify it under the EVT unit and pre-test EVT unit(rework RAM ID follow the proposal) respectively. Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-13src/mainboard/*/*: Set Mini-ITX boards' category to "mini"Angel Pons
Change-Id: I637792d3bf22d2e452144d44ba03cfe45b47501d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12mainboards: Add SMMSTORE region in chromeos configsPatrick Georgi
Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12rammus: add SPD mapping for rammus and shyvana supportkane_chen
Add MICRO 4G and 8G SPD file. BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28484 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy/variants/nami: Add SPD for two memory partsRen Kuo
add two memory parts and ram id: hynix_dimm_H5ANAG6NCMR-VKC micron_dimm_MT40A1G16KNR-075E BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/28536 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mainboard/google/poppy/variants/rammus: Enable DA7219marxwang
On rammus, headset uses DA7219 so that we need to enable it. BUG=b:112945714 BRANCH=master TEST=emerge-rammus coreboot chromeos-bootimage Flash FW and check in kernel to see if DA7219 is up. Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 Signed-off-by: marxwang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28537 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy: Set UPD CmdTriStateDis for NocturneShaunak Saha
This patch sets the MRC UPD CmdTriStateDis for the nocturne boards.Nocturne is LPDDR3 design without RTT for CMD/CTRL. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: I0f593761dcbd121e7e758421af178931b9d78295 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/28379 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09drivers/vpd: Add VPD supportPatrick Rudolph
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md Copy ChromeOS VPD driver to add support for VPD without CROMEOS. Possible use case: * Storing calibration data * Storing MAC address * Storing serial * Storing boot options + Now it's possible to define the VPD space by choosing one of the following enums: VPD_ANY, VPD_RW, VPD_RO. + CHROMEOS selects now VPD as part of it. + VPD is implemented as driver. Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09mainboard/google/kahlee: Reset trackpad & touchscreenMartin Roth
AMD chips don't hold off a reset to the end of I2C transitions, so devices on the i2c bus can be left in a bad state. To avoid this, make sure the trackpad and touchscreen chips get disabled during boot. BUG=b:114411165 TEST=build, reboot watch trackpad enable go low Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28538 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07mb/google/poppy/variants/atlas: enable NVMeCaveh Jalali
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and clock#4. BUG=b:113369699 TEST=booted on atlas Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-07wedge100s: Add TPM supportMikolaj Walczak
Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81 Signed-off-by: Mikolaj Walczak <mwalczak@fb.com> Reviewed-on: https://review.coreboot.org/28529 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07fsp_broadwell_de: enable spi consoleOkash Khawaja
this enables spi console for wedge100s with broadwell_de. the console size is 64kb. enabling spi console in `board.fmd` enables code which calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and `udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE` in fsp_broadwell_de's Kconfig to satisfy that. Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06mb/google/octopus: Configure H1 interrupt pad using Rx level configFurquan Shaikh
This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06wedge100s: enable mrc cache in fmapOkash Khawaja
this enables mrc cache in fmap for wedge100s and always enable it in Kconfig. Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28527 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.kane_chen
On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0Sathyanarayana Nujella
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/28433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-06 09:53:02 +0000