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Use include folder for header files allowing proper includes.
Change-Id: I80066fb925b918d040062397e633c5d499a50dbe
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47973
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Hook up the mainboard_ops driver and configure the GPIOs using .init,
since mainboard_silicon_init_params() is meant for the configuration of
the FSP, not the GPIOs.
Change-Id: I6ab8d258c6f81c90d835cb8d07c6387d3de76d85
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47850
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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PICASSO_LPC_IOMUX was only used in the amd/mandolin board, but not in
the corresponding SoC code, so remove it from the SoC's Kconfig and
reanme it in the mainboard's Kconfig to MANDOLIN_LPC.
Change-Id: I261e093d6c56be6073a816b79c60d3a0457616f8
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47891
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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Create the drobit variant of the volteer reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:171947885
BRANCH=none
TEST=emerge-volteer coreboot
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I63b7312bba236bd5af028359804d042f6850d8ba
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47787
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Updating Imon slope and offset values as per recommendation of
ODM based on calibaration.
Updating Imon slope to 1.0 and offset to 1.4
BUG=b:167294777
BRANCH=dedede
TEST=Boot dedede platform and confirm values in FSP.
Change-Id: I3eb32218040163f0abef9b8dd4c52efb16289fe7
Signed-off-by: Meera Ravindranath <meera.ravindranath@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48072
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Vinay Kumar <vinay.kumar@intel.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
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Create the sasuke variant of the waddledoo reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:172104731
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_SASUKE
Signed-off-by: Raymond Chung <raymondchung@ami.corp-partner.google.com>
Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Henry Sun <henrysun@google.com>
Reviewed-by: SH Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Remove the devices unused or not present on this laptop.
Signed-off-by: Mike Banon <mikebdp2@gmail.com>
Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47913
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The current I2C5 bus frequency is 367 kHZ, which does not meet the spec.
This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring
the bus frequency closer to 400kHz.
BUG=b:173670150
TEST=Verified that I2C5 frequency is between 386-387kHz.
Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com>
Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Add support for the following 5 LPDDR4x memory parts:
- MT53E512M64D4NW-046 WT:E
- H9HCNNNCRMBLPR-NEE
- MT53D1G64D4NW-046 WT:A
- H9HCNNNFBMBLPR-NEE
- MT53D512M64D4NW-046 WT:F
DRAM Part Name ID to assign
-------------------------------------------
MT53E512M64D4NW-046 WT:E 0 (0000)
H9HCNNNCRMBLPR-NEE 0 (0000)
MT53D1G64D4NW-046 WT:A 1 (0001)
H9HCNNNFBMBLPR-NEE 2 (0010)
MT53D512M64D4NW-046 WT:F 0 (0000)
BUG=b:172993397
TEST=none
Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777
Signed-off-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47981
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This allows dropping ugly preprocessor usage from this file.
Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47959
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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Having variants' gpio.c call the `gpio_configure_pads` function results
in an API that does not need to pass data around, which is much simpler.
Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Most of the existing comments are C-style already.
Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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There's one copy of this function for all variants except mc_apl4. Move
one copy into common mainboard.c and exit early if running on mc_apl4.
Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47402
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
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A MAC address that is neither 00:00:00:00:00:00 nor ff:ff:ff:ff:ff:ff is
considered valid. Instead of using a temporary buffer and memcmp(), use
a single loop that exits as soon as the MAC cannot possibly be invalid.
Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47405
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
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Define and use the MAC_ADDR_LEN macro in place of the `6` magic value.
Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47404
Tested-by: siemens-bot
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
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Break down multi-line compound conditions into multiple if-statements,
and leverage `continue` statements to avoid nesting multiple checks.
Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47403
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
Reviewed-by: Uwe Poeche <uwe.poeche@siemens.com>
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Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices
can be hooked up together via devicetree aliases.
BUG=b:172528109
BRANCH=firmware-volteer-13521.B
TEST=built and USB3.0, type-c display work.
Signed-off-by: Scott Chao <scott_chao@wistron.corp-partner.google.com>
Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48066
Reviewed-by: Zhuohao Lee <zhuohao@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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TEST=Able to pass MRC training on DDR4/5 SKUs
Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Set the FADT PM profile to ENTERPRISE_SERVER, since the currently
supported X11 boards are server boards.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I8fb5c7c262fbd3f3c085d7c2e2ef3d6ff6ce73eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48088
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rework gpio setup for the board series to not use headers but
stage-specific compilation units.
Tested successfully on X11SSM-F.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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GPIO needs to be initialized before the IPMI device gets initialized,
so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus,
use mainboard_ops.init for GPIO configuration instead of using the
indirection via a mainboard_enable function.
To make it more visible, that we use chip.init, rename `mainboard_init`
to `mainboard_chip_init`.
Tested successfully on X11SSM-F including the IPMI changes.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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The ITSS override is not needed for LPC_CLKOUT* pads. Drop it.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Move gpio configuration from the Fsp callback to mainboard init.
Tested successfully on X11SSM-F.
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48086
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Drop zero-value devicetree options and move PcieRpEnable options down to
the corresponding devices.
Test: built with TIMELESS=1; binaries remain identical
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Change-Id: I9285d786e973621a732e2627c734adc930e54207
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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Drop the TODO comment, since there is no TODO left. Also drop the now
obsolete TODO section from the board documentation.
Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Felix Singer <felixsinger@posteo.net>
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Create the galtic variant of the waddledee reference board by
copying the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.3.1).
BUG=b:170913840
BRANCH=None
TEST=util/abuild/abuild -p none -t google/dedede -x -a
make sure the build includes GOOGLE_GALTIC
Signed-off-by: FrankChu <Frank_Chu@pegatron.corp-partner.google.com>
Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47900
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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1. Disable M.2 WWAN and Type-A Port A1
2. Change register 4 to 3 and tuning USB2 Port1 eye diagram
3. Lower camera driving
BUG=b:169105751
Signed-off-by: Nick Chen <nick_xr_chen@wistron.corp-partner.google.com>
Change-Id: I6b8a5c0d5e814de232d79a43354f5ec0220fc5ea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47863
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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RasModesEnabled
Use RasModesEnabled from SystemMemoryMapHob to define SMBIOS type
16 error correction type
Tested=Execute "dmidecode -t 16" to check if error correction type
is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I3636fcc4a874261cf484c10e2db15015ac5d7e68
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47509
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Selecting SOC_INTEL_CSE_LITE_SKU without conditioning on CHROMEOS
force-selects CHROMEOS, per src/soc/intel/common/block/cse/Kconfig.
Conditioning on CHROMEOS allows for non-ChromeOS targets to be built.
Test: build wyvern variant with CONFIG_CHROMEOS=n
Change-Id: I61c9c78a3b02d64bab2813b7a80915b7ecf7f934
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47725
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Lindar change amp to ALC1011
Add ALC1011 amp acpi info to devicetree
BUG=b:171771736
BRANCH=firmware-volteer-13521.B
TEST=build and verify ALC1011 can be recognized.
Change-Id: I4d83a19b3baa87cc926bb7c3a2cb96bf3165d2f4
Signed-off-by: Stanley Wu <stanley1.wu@lcfc.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47009
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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Some LPC debug boards hard strap SIO address to be at
0x164e/0x164d vs 0x4e/0x4d. Add support for configurable
SIO address to support these cards.
BUG=b:159933344
TEST=boot with LPC debug card, verify serial output
Change-Id: I103c61f21f13970dfa3b9a788b29964e478fb84c
Signed-off-by: Nikolai Vyssotski <nikolai.vyssotski@amd.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47545
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Add H5ANAG6NCJR-XNC.
BUG=b:165461530
BRANCH=volteer
TEST=emerge-volteer coreboot
Change-Id: I827158ce0abe764f1e3b5de46abf50dc148a6ff0
Signed-off-by: Wisley Chen <wisley.chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Save for the IO_APIC2_ADDR definition, they are equivalent.
Change-Id: I14da3d9aeefcc725428957ce0c9ac164eabacec6
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47408
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Hook up the mainboard_ops driver and configure the GPIOs using .init,
since mainboard_silicon_init_params() is meant for the configuration of
the FSP, not the GPIOs.
Change-Id: I82f1eaf6693d9b117fb211776047058cdc787288
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I008de1bf91ba97ee5eefbde11947c73059fff5f7
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47851
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Id73a7385f7701920efebaa3e293ac50a6ba93272
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47849
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This option only applies to boards using the Lenovo H8 EC code.
Change-Id: I3b16a61a0aa9f51a4061b1b5e58fc276e7383415
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47150
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Only Sandy Bridge MRC stores scrambler seeds in CMOS. Non-Sandybridge
boards ended up with these entries because of copy-paste programming.
Change-Id: I5a5bda6ea4e63ba03a4219bb2a6aa546bb6ecd7a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47149
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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update the DPTF parameters received from the thermal team.
BUG=b:167523658
TEST=emerge-volteer coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: Iafc3fb389ade5cfec79a816a28880262bdce7c74
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47858
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch adds three settings for the new sd readers.
The new assigned values are:
1. RTS5227S: 3
2. L9750: 4
3. SD_OZ711LV2LN: 5
BUG=b:173676531
BRANCH=volteer
TEST=abuild -t google/volteer
Change-Id: I595695f99d3298f146fcdb7c2b942ce007ae9327
Signed-off-by: Zhuohao Lee <zhuohao@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47856
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
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From spec, [31:28] "HS DC Voltage Level Adjustment" is "TXVREFTUNE0".
correct rx_vref_tune -> tx_vref_tune
BUG=None
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Change-Id: I27003a952d8f8bdd8fe52af8a37010e23ee9cdfd
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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Change-Id: I93e09fc9801f6d32cade351bac0cba82f671acfe
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Tested-by: siemens-bot
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
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Split up gpio.h into two seperate compilation units, gpio.c and
gpio_early.c, containing the complete configuration and a minimal
configuration used in early stages.
Tested on clevo/l140cu and it still boots.
Change-Id: I5b056e8faac0c426a37501dbc175373c22dde339
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47836
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Get rid of cnl_configure_pads() since it is a hack for the FSP. Instead,
hook up to the mainboard_ops driver and configure the GPIOs using .init.
Tested on clevo/l140cu and it still boots.
Change-Id: I75dd15ab6d2b3b72b3ad0398df87b349fd00bc3c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47835
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: Ifca49c656f259b08fb8ab47fe36e93c146f25266
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47834
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Change-Id: I50be3d9b829f624cbe460060c40482047f39774c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47833
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Move hda_verb.c from the variant's Makefile to the mainboard's Makefile,
because every variant needs one.
Change-Id: Ia94813f68620abcff48de4fdb117466c91f6863c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47820
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Time has shown that using spaces never converges into proper alignment.
Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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Most of these comments have been copy-pasted or serve no purpose other
than to eventually turn into misleading info. While the description of
the first 120 bits of CMOS could be useful, it should instead be added
to the documentation for the CMOS option infrastructure, or /dev/null.
Moreover, trim down newlines to no more than two consecutive newlines.
Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
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List of changes:
1. Configure CTRLCLK and CTRLDATA for HDMI
2. Enable Ddc and HPD for Port-B
3. Disable dual eDP configuration for Port-A and B
TEST=Able to see depthcharge pre-boot screens over HDMI-B port.
Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected.
Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct.
Signed-off-by: Tim Chu <Tim.Chu@quantatw.com>
Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47562
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jonathan Zhang <jonzhang@fb.com>
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Based on USB DB report.
BRANCH=puff
BUG=b:163561808
TEST=build and measure by EE team.
Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3
Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Sam McNally <sammc@google.com>
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Remove the following devices
- Goodix Touchscreen
- SAR0 Proximity Sensor
BUG=b:173480406
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled.
Add dependency of USE_VENDORCODE_ELTAN.
Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex.
BUG=none
BRANCH=octopus
TEST=emerge-octopus coreboot
Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com>
Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Based on latest schematic and gpio table of voema, update gpio and
devicetree settings for voema Proto.
BUG=b:169356808
TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47667
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Add VBOOT support.
Disable USE_VENDOR_ELTAN when VBOOT is enabled.
Add FMD file and split binary into RW and RO region settings.
Tested on Facebook FBG1701
Signed-off-by: Frans Hendriks <fhendriks@eltan.com>
Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46219
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
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This patch adds support for the Kontron mAL10 COMe module with the
Apollo Lake SoC together with Kontron T10-TNI carrierboard.
Working:
- UART console and I2C on Kontron kempld;
- USB2/3
- Ethernet controller
- eMMC
- SATA
- PCIe ports
- IGD/DP
- SMBus
- HWM
Not tested:
- IGD/LVDS
- SDIO
TODO:
- HDA (codec IDT 92HD73C1X5, currently disabled)
Tested payloads:
- SeaBIOS
- Tianocore, UEFIPayload - without video, EFI-shell in console only
Tested on COMe module with Intel Atom x5-E3940 processor (4 Core,
1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS
(5.0.0-32-generic linux kernel)
Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea
Signed-off-by: Maxim Polyakov <max.senia.poliak@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4,
the interrupt line used by the device is required to be level triggered.
Hence, this change updates the configuration of the HID over I2C devices
to be level triggered.
References:
[1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx
BUG=b:172846122
TEST=./util/abuild/abuild
Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e
Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47424
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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This commit is a stub for brya, which is a an Intel Alder Lake-P
reference platform.
BUG=b:173562731
TEST=util/abuild/abuild -p none -t google/brya -a -c max
Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
|
|
Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47839
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
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Update APU CHTC thermal temperature protection point:
Temperature limit(C'): 90
Update system config=2 to meet TDP 15W design.
BUG=b:162377903
BRANCH=zork
TEST=1. emerge-zork coreboot
2. check CHTC temperature by AMD utility
Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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On Chromebooks the RAM code is implemented by the resistor straps
that we can read and decode from ADC. For Asurada the RAM code can be
read from ADC channel 3.
Signed-off-by: CK Hu <ck.hu@mediatek.com>
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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|
Create the gumboz variant of the dalboz reference board by copying
the template files to a new directory named for the variant.
(Auto-Generated by create_coreboot_variant.sh version 4.2.0).
BUG=b:173536689
BRANCH=zork
TEST=util/abuild/abuild -p none -t google/zork -x -a
make sure the build includes GOOGLE_GUMBOZ
Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47717
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
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Add Hynix DDR4 DRAM, index was generated by gen_part_id
H5ANAG6NCJR-XNC
BUG=b:173480390
BRANCH=zork
TEST=emerge-zork coreboot
Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47700
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
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Add DDR4 part H5ANAG6NDMR-XNC. Attributes are derived from data
sheets.
BUG=None
TEST=Compared generated SPD with data sheets and checked in SPD
Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510
Signed-off-by: Kevin Chiu <kevin.chiu@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47698
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
|
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Update Woomax to improve the performance.
BUG=b:168073070
BRANCH=zork
TEST=emerge-zork coreboot
Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com>
Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47743
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
|
|
Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC)
activation.
BUG=b:171531244
TEST=build and verify by thermal team
Signed-off-by: John Su <john_su@compal.corp-partner.google.com>
Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691
Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Ben Kao <ben.kao@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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As a part of trying to get our boot time as low as possible, any delays
in the code should try to be refactored out. This removes the 50ms
delay in the WIFI sequence by enabling power and putting the wifi module
into reset in bootblock, then bringing it out of reset in ramstage.
This is significantly longer than the 50ms requirement. The reset GPIO
was already being set high in ramstage, so that code didn't need to be
added.
BUG=b:171513520
TEST=Boot on boards with different module types, WIFI works on both.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47719
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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1. Config EN_PP3300_SSD (GPP_B2) to gpo
2. EMMC_CLKREQ_ODL(GPP_C1) change to GPP_H11
3. WLAN_PERST_L (GPP_H10) change to GPP_H10
BUG=b:172630765, b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot chromeos-bootimage and boot into emmc
Change-Id: I9d112373c4ecd2cea5ce3d2d47b190c061d50da6
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47705
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
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Enable Genesys GL9763E as PCI-to-eMMC bridge.
BUG=b:171467336
BRANCH=volteer
TEST=emerge-volteer coreboot
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Change-Id: I858c12151df5b6fc19132869317edfa1b090335d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47040
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Currently, the PCIe bridge 00:15.2 is not detected by coreboot, causing
the connected network device also to be missing.
This is caused by not configuring the third of the four PCIe General
Purpose Ports (GPP) of the AMD Fusion Controller Hub (FCH), which can be
exposed as one to four PCIe devices.
So, enable it in AGESA but disable enumeration in coreboot. Otherwise,
the serial console stops working in romstage after
[…]
PCI: 00:15.1 bridge ctrl <- 0013
PCI: 00:15.1 cmd <- 06
PCI: 00:15.2 bridge ctrl <- 0013
PCI: 00:15.2 cmd <- 07
and the system hangs in the payload (SeaBIOS banner is shown on VGA
attached monitor).
TEST=Serial console and payload works, and Linux 5.10-rc2 configures
PCIe bridge. Output of `lspci -t`:
-[0000:00]-+-00.0
+-00.2
+-01.0
+-01.1
+-10.0
+-10.1
+-11.0
+-12.0
+-12.2
+-13.0
+-13.2
+-14.0
+-14.2
+-14.3
+-14.4-[01]--
+-14.5
+-15.0-[02]--
+-15.1-[03]----00.0
+-15.2-[04]----00.0
+-18.0
+-18.1
+-18.2
+-18.3
+-18.4
\-18.5
Change-Id: Ia1d60a212b0d249c7d8b3f8ec16baf5e93c985da
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46527
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
Working:
- TianoCore
- NVMe, SATA3
- USB2, USB3
- Thunderbolt
- Graphics (GOP and libgfxinit)
- Sound
- Webcam
- WLAN, LAN, Bluetooth, LTE
- Keyboard, touchpad
- TPM
- flashrom support; reading / flashing from Linux
- ACPI S3
WIP:
- Documentation
Not working:
- EC ACPI (e.g. Fn keys, battery and power information)
Boots Arch Linux (Linux 5.8.12) successfully.
Change-Id: I364f5849ef88f43b85efbd7a635a27e54d08c513
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/28640
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
|
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The auxadc (auxiliary analogue-to-digital conversion) is a unit
to identify the plugged peripherals or measure the temperature
or voltages.
The MT8183 auxadc driver can be shared by multiple MediaTek SoCs
so we should move it to the common folder.
Signed-off-by: Po Xu <jg_poxu@mediatek.com>
Change-Id: Id4553e99c3578fa40e28b19a6e010b52650ba41e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46390
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
|
|
Change-Id: Ic3ed97fc2b54d4974ec0b41b9f207fe3d49d2cce
Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/25436
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
|
|
A new field was defined for different keyboard layouts, so add this field
to the list and provide the two options that were defined.
Change-Id: Ic357446725e34221040705929d54cbce94c5ab8b
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47478
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
|
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Set the default state of the TCSS PCIe RP0 to hidden so that coreboot
does not allocate resources to this hotplug root port. The default
behavior on the reference design is that there is only one USB4 port
attached to port C1 while port C0 is only a USB3 port.
Meanwhile the Voxel and Terrador variants do have USB4 on both C0 and
C1 ports, so these boards change the default to 'on' so that coreboot
does allocate resources for the hotplug port.
BUG=b:159143739
BRANCH=volteer
TEST=build volteer and voxel and check the resulting static.c to
ensure the device is hidden or not. Also boot with the two different
configurations and ensure resources are assigned or not. Finally
check that S0ix still functions with the C0 port set to 'hidden'
after authorizing a PCIe tunnel on port C1.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I8bb05ae8cd14412854212b7ed189cfa43d602c1d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47198
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
|
|
There is an issue with the storage device being mis-detected on exit
from S0ix which is causing the root device to disappear if the power
is actually turned off via RTD3.
To work around this read the RX state of the pin and apply the IOSSTATE
setting to drive a 0 or 1 back to the internal controller. This will
ensure the device is detected the same on resume as on initial boot.
BUG=b:171993054
TEST=boot on volteer with PCIe NVMe and SATA SSD installed in the M.2
slot and ensure this pin is configured appropriately. Additionally
test with PCIe RTD3 enabled to ensure suspend/resume works reliably.
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Change-Id: I85542151eebd0ca411e2c70d8267a8498becee78
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47255
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shreesh Chhabbi <shreesh.chhabbi@intel.corp-partner.google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
|
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Enable the PCIe RTD3 driver for the PCIe attached SD card interface
and provide the enable/reset GPIOs. These GPIOs are common across
all variants so this is implemented in the baseboard devicetree with
an fw_config probe if the device is present. The RTS5261 device
does not have an enable GPIO so it is disabled in a workaround in
mainboard.c, along with marking the SD-Express device as external.
BUG=b:162289926, b:162289982
TEST=Tested on Delbin platform to ensure the system can enter the
S0i3.2 substate and suspend/resume is stable.
enabling this for the regular Genesys
Change-Id: I40fe05829783c7bce2a2c4c1520a4a7430642e26
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47377
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Enable Runtime D3 for the volteer variants that have GPIO power control
of the NVMe device attached to PCIe Root Port 9.
Enable the GPIO for power control for variants that do not already have
it configured to allow the power to be disabled in D3 state.
BUG=b:160996445
TEST=tested on delbin
Change-Id: I6ebf813c6c3364fec2e489a9742f04452be92c45
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46262
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Replace the two obsolete LPID implementations with the new PEPD device.
The PEPD device gets included in the plaforms' `southbridge.asl`, since
it is required to load the `intel_pmc_core` module in Linux, which
checks for the _HID. (See CB:46469 for more info on that.)
There is no harm for mainboards not supporting S0ix, because the _DSM
function won't be called with the LPS0 UUID on such boards. Such boards
can use the debugging functionality of `intel_pmc_core`, too.
Change-Id: Ic8427db33286451618b50ca429d41b604dbb08a5
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46471
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Rename LPID to PEPD for consistency. PEPD means "Power Engine Plug-In
Device" and is the name Intel and vendors usually use, so let's comply.
Change-Id: I1caa009a3946b1c55da8afbae058cafe98940c6d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46470
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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GPIO 86 should be set high on boot to save power.
BUG=b:173340497
TEST=Build only
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I31ef1d2a1967d82ba5370462783a909417088d2f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47673
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Rob Barnes <robbarnes@google.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
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The GPP_F16 is for enable_gpio after check the schematic.
BUG=b:151978872
TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Change-Id: I63f43c231e624ed034ef18e8f06942ff3622d821
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47742
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>
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Extend the Kconfig option text of L140CU with L141CU since the hardware
of both is equal.
Change-Id: If0e5061fc345208688a678a4cdf7c5ecaf47c17d
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47716
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
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Change-Id: I531865416b1bf9c5a73c809590059e7d7c8f373a
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47715
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Volteer has a new Audio option in FW_CONFIG. This patch adds
support for it and when enabled, programs GPIO pins for I2S
functionality.
BUG=b:171174991
TEST=emerge-volteer coreboot
Change-Id: I85bc37980957a3fb6c795858a4e4f44f3e3cc332
Signed-off-by: Wisley Chen <wisley.chen@quantatw.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
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Ambassador is similar to puff. This change matches the
PcieRpSlotImplemented configuration with Puff's, originally made for
Puff in https://review.coreboot.org/c/coreboot/+/39986.
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Change-Id: I5b6246f58c10e03a0d02278ad3621ded39bb6d6e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47685
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Fan table: provided by the ODM (see attachment in bug) based on
measurements with EVT unit.
BUG=b:173134210
TEST=flash to DUT
Change-Id: I9f727f0f7e2eb7fe70385ebc843558d51e1860c5
Signed-off-by: Matt Ziegelbaum <ziegs@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47556
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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HPD_1: A19 -> E14
HPD_2: A20 -> A18
Change-Id: Idf3c8f4931bf8364bb9216a9369df7e05dcde047
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47683
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
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Configure the pins for SD to msdc1 mode and change the driving
value to 8mA. Enable VCC and VCCQ power supply for SD.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Change-Id: I11151c659b251db987f797a6ae4a08a07971144b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47008
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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SD Card driver needs to access two regulators - MT6360_LDO5 and
MT6360_LDO3. These two regulators are disabled by default.
Two APIs are implemented:
- mainboard_enable_regulator: Configure the regulator as enabled/disabled.
- mainboard_regulator_is_enabled: Query if the regulator is enabled.
BUG=b:168863056,b:147789962
BRANCH=none
TEST=emerge-asurada coreboot
Change-Id: I391f908fcb33ffdcccc53063644482eabc863ac4
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46687
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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Currently, five regulator controls are implemented for DRAM
calibration and DVFS feature.
The regulators for VCORE and VM18 are controlled by MT6359.
The reguatlors for VDD1, VDD2 and VMDDR are controlled by MT6360
via EC.
BUG=b:147789962
BRANCH=none
TEST=verified with DRAM driver
Signed-off-by: Yidi Lin <yidi.lin@mediatek.com>
Change-Id: Id06a8196ca4badc51b06759afb07b5664278d13b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46406
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
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MT6359P is a PMIC chipset for Mediatek MT8192 platform.
Reference datasheet: MT6359_PMIC_Data_Sheet_V1.5.docx, RH-D-2018-0205.
BUG=b:155253454
BRANCH=none
TEST=boot asurada correctly
Signed-off-by: Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>
Change-Id: I62f69490165539847b8b7260942644533b15285b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45399
Reviewed-by: Hung-Te Lin <hungte@chromium.org>
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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The current CSE firmware update implementation adds CSE RW binary to
FW_MAIN_A/B and this increases the boot time due to the size increase
of these regions leading to higher loading and hashing time.
To mitigate this issue, CSE RW binary is moved from FW_MAIN_A/B to new
region, ME_RW_A/B under RW_SECTON_A/B, and this updates the flashmap to
add ME_RW_A/B region for CSE RW binary.
BUG=b:169077783
TEST=build with cse rw binary, flash and verify volteer2 boots to OS.
Verify me_rw binary is added to ME_RW_A/B region.
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Change-Id: I87da3824933ed2dd8e8ed0fed8686d2a3527faea
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46431
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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This patch modifies flash layout to add ME_RW_A/B to add
the CSE RW blob and also enable the CSE RW update feature for
JSLRVP
BUG=b:169077783
TEST= Built for jslrvp. Verified that CSE RW and metadata files
are included in cbfs.
Change-Id: I13baa317a06d00cec0337f08754892c7c8737f5d
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47557
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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Existing implementation adds the CSE RW update binary to FW_MAIN_A/B
regions and this has significant impact on boot time due to the
increase in the size of these regions leading to higher loading
and hashing time.
This patch modifies flash layout to add new ME_RW_A/B fmap regions
in the RW_SECTION_A/B.
BUG=b:169077783
TEST= Built for dedede. Verified that CSE RW binary is added to the
CSE_RW_A/B fmap region.
Change-Id: I23a3e22a569488b39beb4d12f5b6309c7c742992
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47439
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
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Add Elan and Goodix touchscreen settings.
BUG=b:169813211
BRANCH=None
TEST=build metaknight firmware
Change-Id: Ib2acd31a8076533c3b927d37127e7d27bac0bb57
Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47433
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
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When the system shuts down, turn the fingerprint sensor off. This sets
the GPIOs correctly for the next boot. The fingerprint sensor was
previously left on, and was just powering down when the rails went low.
On suspend, the fingerprint sensor stays awake and puts itself in a low
powerstate mode based on the SLP_Sx_L pin states.
BUG=b:171837716
TEST=Fingerprint sensor still works after S3, GPIO state on the boot
following a shutdown is low.
BRANCH=Zork
Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: I3837b58372d8f4a504535e76bd21c667d68f8995
Reviewed-on: https://review.coreboot.org/c/coreboot/+/47311
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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"Die()" needs <console/console.h>.
Change-Id: I250988d77b0b0a093a1d116bea44a0cbb84189dd
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45540
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
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