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2018-04-06purism/librem_skl: Set TCC Activation at 95CYouness Alaoui
Set the Thermal Control Circuit (TCC) activaction value to 95C even though FSP integration guide says to set it to 100C for SKL-U (offset at 0), because when the TCC activates at 100C, the CPU will have already shut itself down from overheating protection. This was tested on Purism Librem 13 v2. A bisect showed that the immediate shutdowns happened after commit [1] was merged which led to this solution. [1] ec5a947b (soc/intel/skylake: make tcc_offset take effect) Change-Id: Idfc001c8e46ed3b07b24150c961c4b9bc9b71a62 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/25323 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-06purism/librem_skl: Enable VMX and Intel SpeedStep in devicetreeYouness Alaoui
Although VmxEnable is currently ignored by FSP, a forthcoming patch explicitly enables it in coreboot, so set it in anticipation of that. Enable Intel SpeedStep to ensure the ACPI tables are generated for the C-states/P-states which are required for the xen-acpi-processor module to be loaded. Without it, the Qubes 4.0-rc4 installer will complain at boot about modules that could not be loaded. Change-Id: I968ef36ec9382a10db13d96fd3a5c0fc904db387 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/23684 Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-06purism/librem_skl: Enable TPM supportYouness Alaoui
Change the GPIO to match the TPM-enabled motherboards, and add TPM support in devicetree and enable the config. After changing the GPIO table, the librem 13v2 and librem 15v3 now have the same GPIOs, so use a single gpio.h file instead of one file per variant. Change-Id: I425654c1c972118aa81c27961246238c2eef782d Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/23683 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-04-05mb/google/poppy/variants/nami: Add SPD file for Vaynechriszhou
Add SPD file for sdp hynix_dimm_H5AN8G6NAFR-UHC (ram id: 6). BUG=b:77290144 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I33503de21c9fc14537c00c092986fd4d2998dace Signed-off-by: chriszhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25461 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Shelley Chen <shchen@google.com>
2018-04-05mb/amd/gardenia/gpio.c: Convert GPIO to new formatRichard Spiegel
New macros were developed that replace previous way of defining GPIO, with pin and intention very clear while keeping the table mostly identical to previous method (there's no pull up or pull down when a GPIO is set as an output). Change current gardenia table to use the new macros. BUG=b:72875858 TEST=Build Gardenia. Change-Id: I402b95374cc5ba01bb961ebcb34d8e465b443c08 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25512 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-04-05mainboard/google/kahlee: Update WP to active lowMartin Roth
The WP signal to the AP isn't inverted as it is on other platforms, so it was reporting incorrectly. Change the ACPI table to be active low, and invert the signal when reporting it to everything else. BUG=b:74946358 TEST=Boot grunt with battery inserted, WP signals both report 1. Remove battery, WP_CUR reports 0, WP_BOOT still reports 1. Change-Id: Ic1369dbda609e34b308af308880449643be6af39 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/25469 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-04mb/google/octopus/variants/baseboard: Set PL1 and PL2 valueSumeet Pawnikar
This patch sets PL1 value to ~6W. Here, 8W setting gives a run-time 6W actual measured power. Also, this patch sets PL2 value to 15W. BUG=None BRANCH=None TEST=Build and read the MSR 0x610. Change-Id: I2439a49b9917db0d9b05f333ce1c35003da493f6 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/25341 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-04-03mainboard/google/zoombini: Enable HAVE_ACPI_RESUMEVaibhav Shankar
This patch selects `HAVE_APCI_RESUME` to enable S3 resume. This has a dependency on EC to store the hash. BUG=b:72472969 TEST=suspend and resume from S3 should work. Change-Id: I9de84dfd450936b3bc08e016bec6cf5ae88eab3d Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25390 Reviewed-by: Aseda Aboagye <aaboagye@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-04-02mb/google/octopus: Fix Trackpad interrupt GPIO configHannah Williams
BUG=b:73137125 TEST= tested trackpad on Octopus Change-Id: Icc416e7be4e42bda188f74c69db150ba42562128 Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25415 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-02mb/google/octopus: Make PMC I2C pads IOSTANDBY_IGNOREHannah Williams
This fixes wake from S0ix Change-Id: I3b340deafccbf909ec1f4b11ba9a77c6b13a89fd Signed-off-by: Hannah Williams <hannah.williams@intel.com> Reviewed-on: https://review.coreboot.org/25467 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-04-01mb/google/octopus: update SSP port and DMIC 4CH nhlt supportM Naveen
Patch corrects SSP configuration to enable audio on GLK boards. Octopus variant board uses max98357a speaker codec and 4CH DMIC, Select the appropriate NHLT blob to be packaged in CBFS. Change-Id: I101ed80f4421925120116b018424ef19d95a2a3a Signed-off-by: Naveen Manohar <naveen.m@intel.com> Reviewed-on: https://review.coreboot.org/25387 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.corp-partner.google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-30mb/google/octopus: Enable i2c4 which is the root port for audio codecShamile Khan
BUG=None BRANCH=None TEST=On octopus, "aplay -l" shows the Audio codec. Change-Id: I5d837d62f00d34edf28fd472ae0dbe7c0d94447a Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25376 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-30mb/google/poppy: Add variant for AtlasDuncan Laurie
Add a new variant of Poppy for the Atlas board. BUG=b:75454415 TEST=tested on a P0 board. System boots and is mostly functional, though some peripherals are not ready so there are no touchpad/touchscreen devices configured yet. Change-Id: I5a0bccd1bda0134aa51885ac2c6e7bb5b45de924 Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25389 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-29mb/google/octopus: Fix wifi configurationFurquan Shaikh
This change updates devicetree and GPIO configurations to match the schematics: 1. pcie_rp...[2] is the one being used for wifi, thus, clk_req and deemphasis_enable for [2] need to be set instead of [0]. 2. WLAN power enable, wifi disable and PERST# GPIOs need to be configured correctly. BUG=b:76180142 TEST=Verified that wlan0 scan works. Change-Id: Ic51a94902e2cac3491081ade32079e5b88719f45 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25417 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hannah Williams <hannah.williams@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-28soc/intel/skylake: Limit xDCI feature when VBOOT is enabledDuncan Laurie
Use the common xDCI function to check if the controller is allowed in the current mode before enabling it. Otherwise, disable the PCI device if it has been enabled in devicetree. To make the SOC behavior consistent the XdciEnable config option is removed in favor of direct control by devicetree.cb and the mainboards that had defined it were adjusted accordingly. This was tested on an Eve board with xDCI enabled in devicetree.cb to ensure the xDCI device is enabled in developer mode and disabled in normal mode. Change-Id: Ic3c84beac87452f17490de32082030880834501d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25365 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28sb/intel/common: Add common code for SMM setup and smihandlerArthur Heymans
This moves the sandybridge both smm setup and smihandler code to a common place. Tested on Thinkpad X220, still boots, resume to and from S3 is fine so smihandler is still working fine. Change-Id: I28e2e6ad1e95a9e14462a456726a144ccdc63ec9 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/23427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-28mb/intel/glkrvp: Enable ThunderPeak wifi cardRoy Mingi Park
This enables ThunderPeak WiFi card on M.2. TEST=Verify wlan card shows up in lspci Change-Id: I5b3f871bdc67bfc4ed283b997b2a5698451b2bd2 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/24931 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-28mainboard/google/meowth: Disable debug consent and enable S0ixVaibhav Shankar
This patch disables debug consent in the devicetree. When debug consent is set to DBC by default, it prevents some clocks from turning off during S0ix. This blocks S0ix entry. This patch also enables S0ix from the devicetree. BUG=b:76163091 TEST=enter S0ix and check if slp_s0 is asserted Change-Id: I05001a41b13e7784c34fa8f1f773fb94bbdcd01f Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25312 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-28mb/google/poppy/variants/nami: Add SPD file for sona.Van Chen
Add SPD file for sdp samsung_dimm_K4A8G165WC-BCTD (ram id: 8). BUG=b:76086834 TEST=Verified that the device with this memory part boots to OS fine. Change-Id: I49fa114f07ad2eef10f18de9f6c3380173681bdd Signed-off-by: Van Chen <van_chen@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25379 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-27mainboard/google/poppy: Add SPD for Hynix H9CCNNNCLGALAR-NUDDuncan Laurie
Add an SPD for this particular Hynix memory type to the poppy board so it can be used by poppy variants. BUG=b:75454415 Change-Id: I2249c7a4f2c83ec2b3266047a74b9bc22dad43be Signed-off-by: Duncan Laurie <dlaurie@google.com> Reviewed-on: https://review.coreboot.org/25368 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-27mb/google/octopus: Remove emmc tuning parameters from devicetreeFurquan Shaikh
Current emmc tuning parameters for octopus were copied over from other boards and result in failure to boot from emmc. This change gets rid of the emmc tuning parameters in devicetree. Once emmc tuning tests are run for octopus, these parameters can be added back. BUG=b:75986903 BRANCH=None TEST=Verified that octopus boots from eMMC without any errors in depthcharge. Change-Id: I7ac44a54afd1ecfe355a9654ac8e92133b67637f Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-26ec/purism: Fix CPU Turbo value (PPCM) set by the ECYouness Alaoui
The EC needs to set the PPCM value depending on whether Turbo is enabled or not, and the values differ between Broadwell (0, 1) and Skylake (1, 2) platforms. Change-Id: I662dce54415e685c054ffc00b6afde0f1f7765e2 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25329 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-26purism/librem13v1, librem13v2, liberm15v3: Fix EC LPC I/O portYouness Alaoui
The LPC I/O ports for EC communication were not set properly, causing ectool to fail to read the Index I/O from the EC. The EC Index I/O is on port 0x380 and the LPC I/O port needs to be decoded by the PCI device for it to be accessible. Correct the value for the Librem 13v1, 13v2 and 15v3. Change-Id: Ide1d158340eadfabbce5f70ceccddfabb4db188a Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/25328 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-26mb/google/poppy/variant/nautilus: Turn off MIPI camera in PMOF methodSeunghwan Kim
This change remove work-around code for the power issue of MIPI and USB cameras on previous board revision. With the work-around code, PMOF ACPI method cannot turn off MIPI camera. So we need to remove it. BUG=b:74214248 BRANCH=poppy TEST=emerge-nautilus coreboot Change-Id: I7becaf61de364f82976ec0be7f8c9e4ef1a7aedd Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/25337 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-26mainboard/hp: Add Elitebook Folio 9470mBill XIE
The code is based on autoport and that for revolve_810g1 Tested: - CPU i5-3437U - Slotted DIMM 8GiB - Onboard USB2 interfaces (wlan slot, wwan slot, camera, smart card) - Mini pci-e on wlan slot - On board SDHCI connected to pci-e - USB3 ports - USB3 hub on dock (connected to USB3 port 1) - NVRAM options for North and South bridges - S3 - TPM1 on LPC - Linux 4.13.17-1 within Debian GNU/Linux testing, loaded from SeaBIOS, or Linux payload (Heads) Not tested: - Fingerprint reader on USB2 Not working well: - EHCI debug on port SSP2,(The USB port on the left, wired to ehci before OS) it has always-on enabled by default (maybe via EC), which disturbs FT232H's own power up, requiring a very critical timing to plug it in for it to work. Change-Id: I52e549ec18e8aa661a506a16dbc7f83417c0da78 Signed-off-by: Bill XIE <persmule@gmail.com> Reviewed-on: https://review.coreboot.org/25218 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-26mainboard/google/cheza: Add support for ChezaT Michael Turney
TEST=build Change-Id: I32d185741ce20a3a82e6895de3026ade52d0bcc8 Signed-off-by: T Michael Turney <mturney@codeaurora.org> Reviewed-on: https://review.coreboot.org/25200 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-03-26mb/octopus: Set PNP config to PNP_PERF_POWERShaunak Saha
This patch sets the PNP config value to PNP_PERF_POWER. The config values for soc can be found in chip.h TEST = Build for octopus. Change-Id: I2239aa70cb708e6e1c06339ca9d517e7eaa198ed Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25310 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-25mb/glkrvp: Set PNP config to PNP_PERF_POWERShaunak Saha
This patch sets the PNP config value to PNP_PERF_POWER. The config values for soc can be found in chip.h TEST = Built and booted glkrvp, verified warm and cold reboot and suspend resume. Change-Id: Ia390c0fafe2de64bd9e4ca44e5ed5d904663ae3c Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/25309 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-24mb/google/octopus: Select TPM options only if mocktpm is not selectedFurquan Shaikh
This change adds a new Kconfig option for mainboard octopus "HAS_TPM" that auto-selects all TPM related options only if VBOOT_MOCK_SECDATA is not selected. BUG=b:76203913 TEST=Compiles fine with mocktpm. Change-Id: Ib28fc47a70be58cd9a9ec65ce3b1cda68d558437 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25340 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23mainboard/intel/cannonlake_rvp: Enable S0ixVaibhav Shankar
This patch enables S0ix from the devicetree. Change-Id: I38662dc7203366bdee5f1c7aaa18979867a79ba1 Signed-off-by: Vaibhav Shankar <vaibhav.shankar@intel.com> Reviewed-on: https://review.coreboot.org/25293 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-23mb/google/zoombini: always report EC is in RO modeNick Vaccaro
Always report that EC is in RO mode. This is a temporary workaround for a hardware issue that is causing EC to appear to be in RW mode when it is not. This change will be reverted once transition is made to newer hardware. BUG=b:74215817 BRANCH=master TEST=Verify meowth can boot to recovery's insert screen. Change-Id: Ib3705bba0bb1f351da79e599566fbffab94428f3 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25298 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-23mb/intel/kblrvp8: Add KBLRVP8 supportV Sowmya
Add the config for setting SPD DIMM size to 512 bytes for KBLRVP8 with DDR4 memory. Configure the DIMM1 memory SPD data for channel0 and channel1. Set the UserBd UPD to BOARD_TYPE_DESKTOP for kblrvp8. Signed-off-by: V Sowmya <v.sowmya@intel.com> Change-Id: I985968d331991884050c3920ec9798cd4cb371c7 Reviewed-on: https://review.coreboot.org/25194 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-03-22mb/google/zoombini: Enable NVMeNick Vaccaro
BUG=b:72120814 BRANCH=master TEST=none Change-Id: I64ab38dda78345c1f3d7d3f2bf3cb04c19290ceb Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25256 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-22mb/google/octopus: Add CLKREQ and de-emphasis settings for PCIe Wi-FIShamile Khan
BUG=b:73292699 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: Ic73ad38ad9a12bec614e530f7f35619246b9f57f Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25288 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/fizz: Enable I2C bus 2Zhongze Hu
I2C bus 2 goes to the custom add-in card slot and it was disalbed cuase it was idle. Google CFM add-in card is going to use this I2C bus so it needs to be re-enabled. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware and verified I2C bus 2 is working properly. Change-Id: I2c9b5a9323fd51872e340c35005c4a3432716808 Signed-off-by: Zhongze Hu <frankhu@chromium.org> Reviewed-on: https://review.coreboot.org/25258 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com>
2018-03-21mb/intel/glkrvp: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate builds using debug FSP. Change-Id: I8b24422e1eef2d0a81006286d4fc58f238fdce11 Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25255 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/octopus: Re-size flash WP_RO segmentSrinidhi N Kaushik
Update the size in WP_RO segment of the flash to accommodate builds using debug FSP. Change-Id: I0a0d1d0121b503ff390adf3ce25973d72e59fdeb Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> Reviewed-on: https://review.coreboot.org/25253 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21mb/google/octopus: Create bip variantJustin TerAvest
This creates a bip variant for octopus. Nothing is set in the variant files here-- everything is picked up from baseboard. BUG=b:75976864 TEST=None Change-Id: I7a8ac3d8bb71416f05ef1a605684d92d5902abda Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25285 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mainboard/google/kahlee: Update GPIOs based on board IDMartin Roth
BUG=b:73078053 TEST=build & boot Grunt Change-Id: I2d4ba197b19c4948b867a61575e858b2a826a286 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25287 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-21mb/google/poppy/variants/nami: change type of board_sku_id() to uint32_tZhuohao Lee
Tools/scripts, like mosys/arc-setup, use int (4 bytes) to read the sku id. In order to support "-1", we need to use uint32_t (4 bytes) instead of using uint16_t (2 bytes) data type. Otherwise, tools/scripts will read 65535 instead of -1. Another reason to change this is that sku_id can be supported by ec up to 4 bytes. BUG=b:73792190 TEST=mosys output "Platform not supported" for -1 sku id arc-setup read -1 sku id Change-Id: Ib3baa8419f138abeb412ac09c2e7dc608e3b758b Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/25252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21mb/google/octopus: Enable TPM on GSPIRavi Sarawadi
BUG=b:73133848 BRANCH=None TEST=Build coreboot for Octopus board. Tested the GSPI interface with a SPI EEPROM and got correct response to a RDID command Change-Id: Ia10ab9da0055b54a96134a6e4c51b2a229a6fecf Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Reviewed-on: https://review.coreboot.org/24907 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-21mb/google/poppy/variant/nautilus: Enable CABC feature as defaultSeunghwan Kim
This change configures GPP_E22 to GPO_HIGH to enable CABC feature on nautilus board. BUG=b:68789889 BRANCH=poppy TEST=emerge-nautilus coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: Ifed0d37bf8147aa1b580f594f36f186051c2eb52 Reviewed-on: https://review.coreboot.org/25120 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-21mb/google/kahlee: Add register address mapping for FCH MISCAkshu Agrawal
Audio machine driver will enable/disable clock by making it as a CCF clock in kernel. BUG=b:74570989 TEST=cherry-picked https://patchwork.kernel.org/patch/10291875/ on 4.14 kernel aplay -vv <file> check register to see clock enabled kill aplay check register to see clock disabled Change-Id: Ia553e55ffb358415067000d2d2d2744322d1c4db Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/25263 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-20mainboard/google/kahlee: Initialize EC earlier in the bootblockMartin Roth
Set up the EC communication a little earlier so we can read the board ID before programming GPIOS. BUG=b:73078053 TEST=Build & Boot grunt, board_id() now gets ID correctly Change-Id: Icf3f598824cfed69fa03ba2bb86503bb3c3699a5 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25286 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/octopus: Configure PERST_0 pinJustin TerAvest
According to the schematic, Octopus boards have WLAN_PE_RST connected to GPIO_164. This change configures that properly in devicetree. BUG=None TEST=None Change-Id: I2ba4839e036f02c5e0316d08599894879133894a Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25248 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/octopus: Fix GPIO config for DRAM_IDsJustin TerAvest
The GPIO pad configurations for GPIO68-71 are incorrectly configured as outputs. This change corrects them to be inputs. BUG=b:74932341 TEST=None Change-Id: I319f8a64d83c29ed150316c15a8d429cc7c024f3 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25217 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-19mb/google/poppy: Config GPIO for DMIC by different sku idamanda_hwang
BUG=b:74177699 BRANCH=poppy TEST=Verify audio recorder function by different SKU ID Change-Id: Ic6570703f6ab4a1b03cbba8370fc0f597ab6bcf2 Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25148 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19mb/google/octopus: Configure PCH_WP_OD early.Justin TerAvest
The GPIO for EEPROM write-protect should be configured early, before romstage. This change configures that pad earlier. This pad is the same on the existing Octopus schematics. BUG=None TEST=None Change-Id: Idf296ba6aad75b890afabd6f7c7c51fbaf911214 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19mb/google/fizz: Enable VMXShelley Chen
We are enabling at the kernel level, but that is triggering an issue where FSP expects it to be disabled so it forces a cold reboot on every warm reboot, clearing the ramoops logs. Enabling in BIOS so it matches what the kernel expects. This is the same change that were done for eve: https://review.coreboot.org/#/c/22449/ BUG=None BRANCH=None TEST=echo PANIC > /sys/kernel/debug/provoke-crash/DIRECT check for /dev/pstore/console-ramoops Change-Id: Icd0bd01f5aee4c89f503eebba0808a1f3059e739 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25251 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-19soc/amd/stoneyridge/southbridge.c: Remove configure_stoneyridge_uartRichard Spiegel
The GPIO programming of configure_stoneyridge_UART() can be done by the early GPIO table, AOAC enabling was already removed. So configure_stoneyridge_uart() became redundant. Remove procedure configure_stoneyridge_uart(). BUG=b:74258015 TEST=Build and boot kahlee, observing serial output does not changes from previous serial output. Change-Id: Ie67051d7b90fa294090f6bfc518c6c074d98cc98 Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com> Reviewed-on: https://review.coreboot.org/25192 Reviewed-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-17mb/google/octopus: Do not configure GPIO_149 as GPOFurquan Shaikh
GPIO_149 is used as ESPI clock feedback and configuring it as a GPO results in EC communication failure. This change removes the configuration of GPIO_149 as GPO in ramstage so that it remains configured for ESPI (as it was when AP came out of reset). BUG=b:75348718 Change-Id: Ie4f21b12fae027cdba54ce147e6d1a88ee854792 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16soc/intel/apollolake and mainboards: Use pcie_rp_clkreq_pin arrayFurquan Shaikh
This change uses an array pcie_rp_clkreq_pin for accepting CLKREQ# from mainboards instead of defining a separate property for each root port. This allows us to use memcpy to copy the entire array into FSP params as well as new properties for PCIe root ports can be added as arrays in future CLs. BUG=b:74633273 BRANCH=reef,coral Change-Id: Ifa05f1e38fcfd95063ec327712e472cdbd12dbb7 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25186 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-16mb/google/eve: Update DPTF parametersDuncan Laurie
1) Set the critical temperature threshold to 100C to match changes on other boards. This is intended to reduce DPTF-initiated thermal shutdowns before it has had a chance to react. 2) Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. BUG=b:67459049 BRANCH=eve TEST=manual performance/power testing on Eve hardware Change-Id: Ib660dcb25422fea0aa692fac5ba65b49808965ba Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/25153 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-15mb/google/poppy/variants/nami: Add gpio-keys ACPI node for PENHShelley Chen
Use gpio_keys driver to add ACPI node for pen eject event. Also setting gpio wake pin for wake events. BUG=b:73121017 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I5d87d938ac3a4e52e676850b9d8b80e83726275d Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-15mb/google/poppy/variants/nami: Use GPP_B4 as Touchscreen Power EnableShelley Chen
Touchscreen power enable for Nami has moved from GBB_C22 to GPP_B4 in the latest schematics. BUG=b:74347464 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I3b1794d44f25c0d42d082d63b9e3ec3dfcef7528 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25154 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-15mb/google/octopus: Enable audio components.Shamile Khan
Octopus uses MAX98357A speaker amplifier and DA7219 codec. Add device tree entries and Kconfig settings for these components. BUG=b:73292699,b:73230879 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I27b5113677a8bd44dbbae587e27616d9e0b90d7f Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/25117 Reviewed-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-14mb/google/poppy/variants/baseboard: Add gpio-keys ACPI node for PENHNicolas Boichat
This change uses gpio_keys driver to add ACPI node for pen eject event. BUG=b:74413116 TEST=Verified using evtest that pen eject event results in events as expected. Change-Id: I6019d633f4337137bb9fbba770040cb5b30da773 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/25147 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-14mb/google/zoombini/variants/meowth: Make FPMCU interrupt level-triggeredVincent Palatin
Fix the IRQ configuration: it must be level-sensitive not edge-sensitive (and match the GPIO configuration). BUG=b:71986991 BRANCH=none TEST=on Meowth, /proc/interrupts shows 'IO-APIC 46-fasteoi chromeos-ec' then run 'ectool --name=cros_fp fpmode fingerup' and see the number of interrupts incrementing and the MKBP event happening. Change-Id: Iba8cff21d637fe6bf4ef5152fc01aaf98906477d Signed-off-by: Vincent Palatin <vpalatin@chromium.org> Reviewed-on: https://review.coreboot.org/25110 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-14mainboard/google/meowth: Enable System Agent dynamic frequencyLijian Zhao
Enable System Agent dynamic frequency support by default. BUG=None TEST=Build and flash with debug version FSP, check SaGv in serial print to be set to "4". Change-Id: I7dd29db206b06e600407bb0b1d0bc7530f4ac93e Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25093 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13mb/google/octopus: Add yorp variantJustin TerAvest
This creates a yorp variant for octopus; nothing too interesting now, just picks up values from the baseboard. BUG=b:74443669,b:74067452 TEST=Build Change-Id: I55af8f02d33138a3b6bab7860a665e3deb5595c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25086 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-13mb/google/poppy/variants/nautilus: Enable SAR configsFurquan Shaikh
This change enables SAR configs when building with CHROMEOS option. BUG=b:74439919 Change-Id: I11a8fa04a77f688ed288780f2c605b8ac701f5a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25104 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-13mb/google/poppy/variants/nami: Use internal pulldown for MEM_CONFIG_4Furquan Shaikh
Since nami proto did not have any external pull on MEM_CONFIG_4, use a weak internal pull down before reading it. BUG=b:74420123 TEST=Verified that the value read for MEM_CONFIG_4 is correct on nami. Change-Id: I45989d2ca35b863f391baba9e2f2e602033217d4 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-12mb/google/octopus: Fix lpddr4 skusJustin TerAvest
The current lpddr4 skus entries do not match the RAMID table in the schematic. This commit updates that so they are consistent. Thankfully, the values are the same as for glkrvp, so I just copied from there. BUG=b:74392818 TEST=None Change-Id: I2e63ea0b27ef58038e5a37949c31a808989c98c2 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/25063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-12mb/google/zoombini/variants/meowth: change gpios to no-connectsNick Vaccaro
The following gpios are no longer needed and are now configured as no-connects : GPP_C6, GPP_H4, GPP_H5 BUG=b:74406599 BRANCH=master TEST=none Change-Id: I55769336195db0e57dfbaf5b5770e15050138341 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/25070 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-12mb/google/poppy: Clear memory_params before initializing themNicolas Boichat
Make sure that fields that are not updated in variant_memory_params keep a default value of 0. In particular, use_sec_spd is intended to have a default value of 0 on all platforms. Without this patch, a random value is used and all boards (except nami) get stuck on boot. BRANCH=poppy BUG=b:74439917 TEST=Nautilus and poppy can boot, and do not get stuck at "CBFS: 'sec-spd.bin' not found." Change-Id: I06c6511625de930903ae13788bdcd27667a17886 Signed-off-by: Nicolas Boichat <drinkcat@chromium.org> Reviewed-on: https://review.coreboot.org/25101 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-10meowth: Add SAR Sensor in devicetreeGwendal Grignou
Add left and right semtech SAR sensor. BUG=b:74363445 TEST=Test on meowth, alongside 24962. Check in sysfs that SX9310 is presented: /sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:09/SX9310:00 /sys/devices/LNXSYSTM:00/LNXSYBUS:00/PNP0A08:00/device:0d/SX9310:01 Change-Id: I017db1105800003b312e75dc7e1e27be535a457a Signed-off-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-on: https://review.coreboot.org/25062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
2018-03-09mb/google/zoombini: re-enable software syncCaveh Jalali
we had disabled software sync for bringup - we now have enough functionality in place to turn on software sync. Change-Id: Ib7f5a24ed8a47cb44b3f505e3cd49e0cb6931dc0 Signed-off-by: Caveh Jalali <caveh@google.com> Reviewed-on: https://review.coreboot.org/23630 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-09mb/google/poppy/variants/nami: Fix typo in nami MakefileFurquan Shaikh
Change SECONDARY_SPD_SOURCES to SEC_SPD_SOURCES as that is what the spd target expects. TEST=Verified that sec-spd.bin is present in coreboot.rom Change-Id: I4299df1eb9009095ef899c5b83823750dfc715d8 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/25083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-09mainboard/google/kahlee: Set GPIO 40 to inputMartin Roth
GPIO 40 isn't currently being used, so set it to be an input. BUG=b:73387647 TEST=Build & boot grunt Change-Id: I5a04cbab1276cd20e7f9c7576e8111089dd2b155 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25016 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-09mainboard/google/kahlee: Disable Bayhub part on board_id 0Martin Roth
The Bayhub part is not used on proto with board_id 0, so disable it. BUG=b:74248569 TEST=Build & boot Grunt. Bayhub part is disabled. Change-Id: I635356d41bab637726594d403d66dde730f12256 Signed-off-by: Martin Roth <martinroth@chromium.org> Reviewed-on: https://review.coreboot.org/25015 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-08mb/google/poppy/variants/nami: Define smbios_mainboard_sku to return SKU IDsShelley Chen
Return proper SKU IDs so that mosys can return the proper variant. BUG=b:74059798 BRANCH=None TEST=./util/abuild/abuild -p none -t google/poppy -x -a Change-Id: I665fa491de6e277fea5cc071b1f04a21317bccba Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25028 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-08mb/google/kahlee: Do not define SIO_EC_ENABLE_COM1Daniel Kurtz
This #define tells superio.asl to add a "PNP0501" "Plug and Play 16550A-compatible COM port" entry to kahlee's ACPI tables. The EC on kahlee boards do not provide a "Serial Port 1" that should be exposed via ACPI to the OS. In fact, this entry confuses the kernel and in some cases can cause it to try to redirect output to a non existing port. BUG=b:74200887 TEST=Deploy to grunt. Boot kernel with SERIAL_PORT_DFNS undefined and "earlycon=uart,mmio32,0xfedc6000,115200,48000000" on the kernel command line, and with an image with serial console enabled. => System boots with (kernel) serial console enabled, starting from 0.00 (earlycon), with no gaps in its output, and serial console also allows logging in. Change-Id: I0eaed9b4461bb6a6c1aa4ce97752f588d4322b35 Signed-off-by: Daniel Kurtz <djkurtz@chromium.org> Reviewed-on: https://review.coreboot.org/25021 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-08mb/google/poppy : Get SKU_ID from EC for Nami/Vayneamanda_hwang
CBI abbreviates Cros Board Info. BUG=b:74177699 BRANCH=master TEST=Verify CPU log shows expected SKU ID on Nami. Change-Id: I42dd177de8c49cf3c122c2ebb1fcf42e5ba4cd75 Signed-off-by: amanda_hwang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24996 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-03-08google/scarlet: Adjust K&D power sequence from softwareBrian Norris
Hardware updates have suggested we need to configure the K&D panel's power sequence in software, not in hardware. Without this change, K&D panels will no longer power on correctly and will instead display a black screen. Per K&D's suggestion, we tweak these two commands. From the little HW docs I have, this looks like it's: (Address 0xB7, Value 0x02) -> set BC_CTRL=bit(1) (Back light control) to 1 (Address 0xF1, Value 0x22) -> change GPO2_SEL=bits(0:3) from MIPI_TE(0001b) to BC_CTRL (0010b) BRANCH=scarlet BUG=b:73133861 TEST=KD display with and without HW fix on Scarlet Change-Id: Ia076a378b10417dd9891746f9bc1086360a0f6e6 Signed-off-by: Brian Norris <briannorris@chromium.org> Reviewed-on: https://review.coreboot.org/25023 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Reviewed-by: Matthias Kaehlcke <mka@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-08mb/google/octopus: Add gpio configs for communitiesShaunak Saha
This patch configures the gpios for all the gpio communites. Change-Id: Ibc16edd96f4ef6d55f3a99b195bf4920929b1578 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org>
2018-03-08mb/google/octopus: Add device tree settingsShamile Khan
Change-Id: Id45409a9561671237410dd2f8f0bbfe61ff33562 Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/23846 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-08mb/google/nautilus: Correct LINK FREQ of imx258 sensorAlan Chiang
Per vendor datasheet, corrected linkfreq of imx258 as {633600000, 320000000} BUG=None BRANCH=None TEST=Verified the MIPI and USB camera function on DUT board Change-Id: Ie5beed44c15e26b9f82cb305a91b8ff90a9ea867 Signed-off-by: Andy Yeh <andy.yeh@intel.com> Reviewed-on: https://review.coreboot.org/24990 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-08mb/google/kahlee: Add SKU supportSimon Glass
We want to report the board SKU via the SMBIOS tables. Add support for this, obtaining the ID itself from the EC. BUG=b:74175244 BRANCH=none TEST=manually on grunt with another CL: mosys platform sku 0 Change-Id: I9e08d64df3f89d3703de047dd9ec8e1717e6b212 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-on: https://review.coreboot.org/25011 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-08mb/google/poppy/variants/nami: Add WACOM EMR supportjasper lee
Add WACOM EMR in devicetree I2C #2. BUG=b:72062737 BRANCH=master TEST=Verify EMR on nami Change-Id: Icbe809a48959e5749262aeb1b89b09c4bdafbbc2 Signed-off-by: jasper lee <jasper_lee@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24997 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add SPD files for namijasper lee
This change adds SPD files for memory IDs 7 on nami. BUG=b:73807138 Change-Id: I25fe3b347057eea75c58bfb88df41bdb28cc1460 Signed-off-by: jasper lee <jasper_lee@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/25007 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/zoombini/variants/meowth: enable SAR powerNick Vaccaro
BUG=b:69011806 BRANCH=master TEST=none Change-Id: I2ea44b03336b901af68f9092f3386b42d8516b72 Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/24962 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07mb/google/poppy/variant/nautilus: Configure GPP_B0 for WLAN wakeSeunghwan Kim
As per the latest schematics, this change configures GPP_B0 as wake source for WLAN. BUG=NONE BRANCH=master TEST=emerge-nautilus coreboot Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Change-Id: I72b940452cfbbe471279ef117a868a8ae0b65b8b Reviewed-on: https://review.coreboot.org/23526 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07mb/scaleway/tagada: populate smbios informationJulien Viard de Galbert
This is done by overriding the weak functions from smbios.c Some values are hardcoded as they are characteristics of the Tagada system. Other are retrieved from the BMC through the bmcinfo interface. Change-Id: I9b08660c6677864f5c96c66002b35bd05a366053 Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23843 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-07mb/scaleway/tagada: Override baudrate with bmcInfoJulien Viard de Galbert
Change-Id: Idd93b64ef91a569127a0713fdb499dff2a1f11db Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23815 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/scaleway/tagada: Implement console loglevel override using bmcInfoJulien Viard de Galbert
Change-Id: I0093cfafe7eaa4a4381e67c9b871fdf28abc470d Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23814 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/scaleway/tagada: Add bmcInfo interfaceJulien Viard de Galbert
This interface gives access to configuration information stored in flash by the Tagada BMC before booting the SoC. Change-Id: I4351aa11b08bdf65e14706b261c532bbf8837aed Signed-off-by: Julien Viard de Galbert <jviarddegalbert@online.net> Reviewed-on: https://review.coreboot.org/23813 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-07mb/google/poppy/variants/nami: Add memory detection logicShelley Chen
Alkali will use LPDDR3, so need to have Nami support both DDR4 and LPDDR3. We do this with the PCH_MEM_CONFIG4 GPIO. BUG=b:73514687 BRANCH=None TEST=None Change-Id: Ife6740ce0e8fe109ded7b954134171ba91895628 Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25000 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-07mb/google/poppy/variants/nami: Add spd filesShelley Chen
Add spd files for LPDDR3 based on info received from factory team. BUG=b:73287172 BRANCH=None TEST=None Change-Id: I8924ce97ea422ef1e9a5becb5ea2fda3bf77d8cf Signed-off-by: Shelley Chen <shchen@chromium.org> Reviewed-on: https://review.coreboot.org/25001 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06google/snappy: enhance CCD type-A USB 2.0 phy strengthKevin Chiu
Alan(11")/BigDaddy(14") right type-A(port#2), CCD(port#4) are occasionally undetectable. USB 2.0 phy needs an override to enhance drive strength. right type-A port#2 PERPORTPETXISET: 4 PERPORTTXISET: 4 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 CCD port#4 PERPORTPETXISET: 7 PERPORTTXISET: 7 IUSBTXEMPHASISEN: 1 PERPORTTXPEHALF: 0 BUG=b:72922816 BRANCH=reef TEST=emerge-snappy coreboot Change-Id: I2b18c11709280d00ec3a6ef10f93a416acb4fb45 Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/24969 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06mainboard/google/fizz: Check HDMI HPD and DisplayPort HPDDaisuke Nojiri
Some type-c monitors do not immediately assert HPD. If we continue to boot without HPD asserted, Depthcharge fails to show pictures on a monitor even if HPD is asserted later. Also, if an HDMI monitor is connected, no wait is needed. If only an HDMI monitor is connected, currently the API always loops until the stopwatch expires. This patch will make the AP skip DisplayPort wait loop if it detects an HDMI monitor. And if an HDMI monitor is not detected, the AP will wait for DisplayPort mode (like before) but also its HPD signal. This patch also extends the wait loop time-out to 3 seconds. BUG=b:72387533 BRANCH=none TEST=Verify firmware screen is displayed even when a type-c monitor does not immediately assert HPD. Verify if HDMI monitor is connected, AP does not wait (and firmware screen is displayed on HDMI monitor). Change-Id: I0e1afdffbebf4caf35bbb792e7f4637fae89fa49 Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> Reviewed-on: https://review.coreboot.org/23816 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-03-06mb/google/fizz: Skip FSP init for UART 0Duncan Laurie
The GPIO pins for UART 0 on Fizz are routed to the add-in card slot and should not be used as a UART device. coreboot is setting the pins to GPIO Mode but FSP is re-configuring them for Native Mode and the behavior is unexpected when the kernel tries to initialize the UART device. The UART 0 device is PCI function 0 so it needs to be enabled for other functions to be visible to the OS so it can't just be disabled. Instead, set the device to PchSerialIoSkipInit so that FSP will not change the pin state. BUG=b:73006317 TEST=Tested with add-in card on fizz hardware to ensure the pin state does not change when FSP runs or the kernel boots. Change-Id: Id97c1e482ef0d5642fcf9018d802e1d0e073263d Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: https://review.coreboot.org/24973 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-06Revert "mainboard/google/meowth: enable PCH iSCLK"Lijian Zhao
This reverts commit 2e81f394cffc6f1993a5f004356ed35f6064fe48, as it will have side effect that will make system shutdown failure. System will not enter S5 sleep state, instead a global reset will be generated. Once camera driver ACPI framework ready, isclk programing will be moved into APCI method, in _PS3, isclk will be turned off to save power. BUG=b.72532565 BRANH=master TEST=Apply the changes and flash coreboot, on meowth devices, issue "halt" in OS stage, system can shutdown successfully. Change-Id: If35697911f97c524d9b52bdf4dae5c9ef1cc8618 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/25006 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-05mb/google/poppy: Allow use of optional secondary SPDFurquan Shaikh
This change adds support for variants to use secondary SPD if required. This enables a variant to have different types of memory supported using the same image. BUG=b:73514687 Change-Id: I3add65ead99c510f2d6ec899fbf2cb9a06c79b0c Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24972 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-03-05mb/google/poppy/variants: Set pch_trip_temp to 75CFurquan Shaikh
Similar to Soraka, this change sets the pch_trip_temp value to 75C. This is important so that PMC can shutdown the thermal sensor when CPU is in C-state and DTS temp <= pch_trip_temp. BUG=b:74089135 Change-Id: Ic46fa0681796b821dfb014ab91734c960df7846a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/24968 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-03-02sb/intel/common: Fix conflicting OIC register definitionNico Huber
Commit d2d2aef6a3 (sb/intel/{bd82x6,ibexpeak}: Move RCBA macros to a common location) makes some platforms use the wrong OIC register defi- nition. It was extended to 16-bit in the corporate version of ICH10. So let's give the new size and location a new name: EOIC (extended OIC). This only touches the systems affected by the mentioned change. Other platforms still need to be adapted before they can use the common RCBA definitions. Change-Id: If9e554c072f01412164dc35e0b09272142e3796f Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/24924 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-03-02mb/google/zoombini/variants/meowth: Enable NVMeBora Guvendik
Turn on pcie ports 9,10. Enable Root Port 9 and set up clkreq 3. BUG=b:72120814 TEST: Boot to OS via NVMe Change-Id: I272b63b11e6b00ae5bdbef5a37ee517cc0636f6d Signed-off-by: Bora Guvendik <bora.guvendik@intel.com> Reviewed-on: https://review.coreboot.org/23208 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-02mb/hp: Enable additional ports at WWAN slot for ElitebooksIru Cai
2760p: enable PCIe 8470p: enable mSATA 8460p: enable PCIe, also add comments according to circuit diagram 2570p: comment for some USB ports Change-Id: Ib5209f2dfb249fca5bae89bc6da3b704c8e903dd Signed-off-by: Iru Cai <mytbk920423@gmail.com> Reviewed-on: https://review.coreboot.org/23357 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bill XIE <persmule@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-03-02mainboard/google/zoombini/variant/meowth: enable speed shiftNick Vaccaro
BUG=b:73817825,b:69011806 BRANCH=master TEST=Build and flash to meowth, verify cpufreq shows up in kernel for all cores : localhost ~ # find / -name "cpufreq" /sys/devices/system/cpu/cpu3/cpufreq /sys/devices/system/cpu/cpu1/cpufreq /sys/devices/system/cpu/cpufreq /sys/devices/system/cpu/cpu2/cpufreq /sys/devices/system/cpu/cpu0/cpufreq /sys/module/cpufreq /usr/share/laptop-mode-tools/modules/cpufreq Change-Id: I63242b2b049e37167c0d3b8eab630cb6e15a75fd Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/24902 Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mb/google/reef/sand: Override USB2 phy settingsKatherine Hsieh
Sometimes the USB device is not detected. USB2 port#1 and #4 PHY register need to be overridden. port#1: PERPORTPETXISET = 4 PERPORTTXISET = 4 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 port#4: PERPORTPETXISET = 7 PERPORTTXISET = 7 IUSBTXEMPHASISEN= 1 PERPORTTXPEHALF= 0 BUG=b:72623892 BRANCH=master TEST=emerge-sand coreboot chromeos-bootimage Change-Id: I4051aefbec4583bb1f8babec08fdbeb27f749769 Signed-off-by: Katherine Hsieh <Katherine.Hsieh@quantatw.com> Reviewed-on: https://review.coreboot.org/23879 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-03-01mainboard/google/meowth: Turn on DBC over USB3.0Lijian Zhao
Intel DCI (direct connect interface) allows debug Intel target using USB3.0 ports. It will support debug via USB stack (DCI Dbc) using USB3.0 only. BUG=None TEST=Turn on DCI trace hub in descriptor.bin and flash the coreboot image. Using DAL to halt/run CPU. Change-Id: I39e68dabfcb9e659733019334299e562eee3681d Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/23446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-27 12:58:33 +0000