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2020-01-18google/eve: tweak VBT settingsMatt DeVillier
- Disable Windows driver DPST function - Set POST resolution to 1800x1200 - Set POST brightness to 225 (0-255 scale) Test: Boot Windows on EVE, verify display backlight control functional and no lock ups from switching in/out of tablet mode. Change-Id: Ida64a44df2449f1ff0dc5c8d0ec7b40a183566a7 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38396 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mainboard/google/puff: update SATA strengthTim Chen
Base on SATA SI report to fine tune the strength for port 1. BRANCH=none BUG=b:147351936 TEST=build and test SATA port works fine. Change-Id: Ib82b7e5df32b4ce794682781f33c44dfeb6e68bf Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38458 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18mb/facebook/monolith: Enable the xDCI controllerWim Vervoorn
Enable the VBOOT_ALWAYS_ALLOW_UDC option to actually enable the xDCI controller. BUG=N/A TEST=build Change-Id: Ib51f2c82e69db83cebceb71ba5f1305764e0feca Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38451 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/intel/tglrvp: Update tglrvp_up3 devicetreeRavi Sarawadi
Update Tigerlake RVP UP3 devicetree to reflect devices used by tglrvp_up3. BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Idd0d9efe0ab4e050d2160f7662e4dc40a002672f Reviewed-on: https://review.coreboot.org/c/coreboot/+/37929 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18soc/intel/tigerlake: Update chip filesRavi Sarawadi
Update chip files to include : - Update chip.c based on TGL FSP - Update chip.h based on TGL FSP - Update Kconfig : Define CONFIG_MAX_PCIE_CLOCKS for chip.h update - Update pmc_utils.c and JSL devicetree for build failure Reference PCH EDS#576591 vol1 rev1.2 BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: Ie1518a7ffa69079fe82232afe229d9e1ffe29067 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37783 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/intel/jasperlake_rvp: Remove sd card detect gpioMaulik V Vaghela
Tigerlake SoC doesn't have GPIO defined for GPP_G. so compilation is failing due to this. We will update correct gpio for sd card detect once we have Jasper Lake soc gpio patch. partner bug for tracking: https://ticket.coreboot.org/issues/251 BUG=None BRANCH=NONE TEST='jslrvp' mainboard builds successfully Change-Id: I097b2f3a4fef1a487495a4aa9d2bcf88aa64f017 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38259 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
2020-01-18mb/opencellular/elgon: Fix typoElyes HAOUAS
Change-Id: I6724637c7333ae6be7ada3e8ebe878b2a1061dd1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-18mb/amd/bettong: Fix typoElyes HAOUAS
Use 'irremovable' over 'unremovable' Change-Id: Id305dbe56a93740abc49d85d11402d1b63989dad Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37527 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mainboard/google/puff: update USB configurationJamie Chen
Base on USB SI report to fine tune the strength and correct some OC pin settings. BRANCH=none BUG=b:147206010 TEST=build and test all usb ports function work fine. Change-Id: Idbee5cdddf3a83f97109214a95e0f9875b3b3f8f Signed-off-by: Jamie Chen <jamie.chen@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38425 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kangheui Won <khwon@chromium.org> Reviewed-by: Kane Chen <kane.chen@intel.corp-partner.google.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-18mb/google/link: drop dummy mainboard_post functionPatrick Georgi
It was never filled it, it probably never will be filled in, so stop the pretense. Change-Id: I7632b763b8518304d36a818ce262cc127f95b9f0 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38407 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-18mb/facebook/monolith: Describe device 4.0 in devicetreeWim Vervoorn
BUG=N/A TEST=build Change-Id: Id7267aa6d4266bb7807fb3c25b5e2704c8d81df7 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38430 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-18mb/facebook/monolith: Add support to read cpu temperatureWim Vervoorn
Read the CPU temperature from the EC. For this board the EC support is limited to reading the CPU temperature sensor at this moment. Events are not supported. BUG=N/A TEST=tested on facebook monolith using acpidbg The TSR0._TMP method is returning the correct values. Change-Id: I6793070602e253f1e15cfc641bb47d25d269b136 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mb/facebook/monolith: Update power supply settingsWim Vervoorn
Update the IccMax for the SYSTEM_AGENT and IA_CORE power supplies according to the information in the schematic. The IccMax for these supplies is lower than the standard supported by the SoC. BUG=N/A TEST=build Change-Id: I20b92e7dfc85427bcf9cb9f0efda02459c862809 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38429 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-18mainboard/puff: Fix ACPI tables to advertise correct featuresEdward O'Callaghan
Provide Puff with it's own copy of ec.h copied from the baseboard/includes however with the battery, lid and ps2 defines stripped. This is to ensure the correct ASL is generated so that we don't advertise PS2 keyboard support and battery/lid interrupts which don't exist. V.2: drop EC_ENABLE_ALS_DEVICE as well. V.3: set MAINBOARD_EC_SMI_EVENTS to 0 and drop EC_HOST_EVENT_LID_CLOSED smi event. V.4: drop EC_HOST_EVENT_MODE_CHANGE && provide wake pin for EC for _PRW WoL method V.5: drop EC_HOST_EVENT_KEY_PRESSED BUG=b:147850335 BRANCH=none TEST=builds Change-Id: If13bd124c7229ced996efb841980604d13be09af Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38454 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-01-17mb/tglrvp: update gpio pin mux for NVMeWonkyu Kim
BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board from NVMe Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ib4b85db667c27d266d2ed5a4aa4f4dffa3dd527e Reviewed-on: https://review.coreboot.org/c/coreboot/+/38286 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-16/mb/google/hatch/variants/helios: Remove MAX98357A devicetree entryKrishna Prasad Bhat
Helios does not have MAX98357A speaker amplifier, so remove the devicetree entry. BRANCH=firmware-hatch-12672.B Change-Id: Id02410553f018385d407086b2f9bc3ee1e7a5f40 Signed-off-by: Krishna Prasad Bhat <krishna.p.bhat.d@intel.com> Signed-off-by: Sathya Prakash M R <sathya.prakash.m.r@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Shelley Chen <shchen@google.com>
2020-01-15mb/pcengines: Enable SuperIO LDN 0xf for GPIO soft resetPiotr Kleinschmidt
LDN 0xf keeps registers with open-drain configuration of the GPIO. Enabling the LDN is required for proper GPIO soft reset operation by the SuperIO driver. Signed-off-by: Piotr Kleinschmidt <piotr.kleinschmidt@3mdeb.com> Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: Ia769e3d8e66015297942bddf328a6fde0bb27ce6 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2020-01-15mb/google/slippy: update VBTMatt DeVillier
The current BIOS-extracted VBT breaks backlight control with Tianocore, so replace it with one that does. Settings were exported using Intel BMP tool and the overlayed onto a GOP-format (vs BIOS format) VBT file. Test: boot google/wolf with both SeaBIOS and Tianocore payloads, verify backlight control functional under both Linux and Windows. Change-Id: Id6281c8dfb6e0001be8c4d9be1013f2d4bbb5880 Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org>
2020-01-14mb/google/dedede: Add dedede mainboardKarthikeyan Ramasubramanian
Add mainboard stubs for Dedede. More functionalities will be added later. BUG=b:144768001 TEST=Build test. Change-Id: I7e6cb8adaee7b6bb95e9a96f96466646a78bd0fc Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38277 Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14mb/intel/tglrvp: Update KconfigWonkyu Kim
Updating Kconfig to add Chrome OS support with both internal and external EC BUG=none BRANCH=none TEST=Build and boot tigerlake rvp board Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com> Change-Id: Ia63c06e3b4b4effcace7a8458b1066a615de2008 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38148 Reviewed-by: Subrata Banik <subrata.banik@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-14mb/intel/tglrvp: Add initial mainboard codeRavi Sarawadi
This is a initial mainboard code aimed to serve as base for further mainboard check-ins. This is a copy patch from icelake_rvp as on commit ID: I64db2460115f5fb35ca197b83440f8ee47470761 Below are the changes done over the copy patch: 1. Rename "Icelake" with "Tigerlake". 2. Replace "icelake_rvp" with "tglrvp". 3. Rename "icl" with "tgl". 4. Remove unwanted SPD file, add empty SPD as placeholder. 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake". 6. Empty romstage_fsp_params.c, to fill it later with SOC specific config. 7. Empty GPIO configuration, to be filled as per board. 8. Change copyright year to 2019. 9. Add board support namely BOARD_INTEL_TGLRVP_UP3 10. Replace icl_u and icl_y variant with tglrvp variant. 11. Remove basebord gpio.c and rely on variant override. 12. Remove HDA verb table and config support. Changes to follow on top of this: 1. Add correct memory parameters, add SPDs. 2. Clean up devicetree as per tigerlake SOC. 3. Add GPIO support. 4. Update chromeos.fmd to make 32MB BIOS region. 5. clean up and make empty devicetree setting TEST=Build tigerlake rvp board Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com> Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-01-14mb/google/kukui: Support panels using ANX7625Hung-Te Lin
For Kukui followers using ANX7625 eDP bridge to access panel. BUG=b:140132295 TEST=make # board = kukui Change-Id: I7dc9c68d076fd0ba4e963cde9414d25c17b332cb Signed-off-by: Hung-Te Lin <hungte@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36767 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-01-14mb/google/drallion: Enable dynamic sarEric Lai
Drallion will use two sar table for tablet and clam shell mode. BUG=b:140469407 TEST=Build and check the config has enable BRANCH=none Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I0367741e795a3b00c490ecb1972d22b9f454134f Reviewed-on: https://review.coreboot.org/c/coreboot/+/38386 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Mathew King <mathewk@chromium.org>
2020-01-13mb/packardbell/ms2290/acpi_tables: Remove unneeded includesElyes HAOUAS
Change-Id: Iba380cf96991c9e1fec96aa3d793818524388897 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38375 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/lenovo/thinkcentre_a58/acpi_tables: Remove unneeded includesElyes HAOUAS
Change-Id: I8f8e43d0f146b1050eb68da197504441b60a4120 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/intel/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: I3b110ab749992d1c1793b1d4de43c1d2e8ca15ac Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38373 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/asus/*/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: Iba39673a81f235204d6ae9fe9e18239e5b81b17f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38372 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/gigabyte/ga-g41m-es2l/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: I4b3b2d801698305dc6c214c58d367772ea2096a3 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26894 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/gigabyte/ga-b75m-d3h/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: Ic94e60188dbb9cdee959ecfa5ef14c92f125e3f2 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26892 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/foxconn/g41s-k/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: I41e3cbb4fbdd6680c1d9d347efc35d1618233a64 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26901 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/asrock/g41c-gs/acpi_tables.c: Remove unneeded includesElyes HAOUAS
Change-Id: Icd9efdf5fb4d57756704c62b5f575a3835a8ce11 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/26900 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/asus/p8z77-m_pro: Fix typosElyes HAOUAS
Change-Id: I3c63ca745bf10ec0b0c4cef898db3f7ebfee5bde Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38364 Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-13mb/asrock/imb-a180: Fix typoElyes HAOUAS
Change-Id: Iff032a321301772789a42f29cfc187c446b4cfa1 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38360 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jacob Garber <jgarber1@ualberta.ca> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-13mb/facebook/monolith: Enable SpeedStep and DPTFWim Vervoorn
BUG=N/A TEST=tested using fwts on facebook monolith. Change-Id: Ia3dd195f887055448d42a7584e2c88322f0ec44b Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38131 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12mb/*/*: use ACPIMMIO common block wherever possibleMichał Żygowski
TEST=boot PC Engines apu2 and launch Debian Linux Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I648167ec94367c9494c4253bec21dab20ad7b615 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37401 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-12aopen/dxplplusu,intel/e7505: Move mainboard_romstage_entry()Kyösti Mälkki
Change-Id: I15aaefdf0c81f58adfeb6f4dde2f05b3c06fd145 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38266 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12intel/e7505,i82801dx: Remove wrapper spd_read_byte()Kyösti Mälkki
Change-Id: I4a2d3043f77c9aa9c93b4718c5742fbd8d69b79f Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38235 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12asus/{p2b-x,p3b-f},intel/i440bx: Move mainboard_romstage_entry()Kyösti Mälkki
Change-Id: I3598f548c2d122906fda09c85b5a1c82b0da993b Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38255 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-12intel/i440bx,i82371: Remove wrapper spd_read_byte()Kyösti Mälkki
Change-Id: Ib94ce73eb22c5b4b489dbd871279e8cd9a7010a7 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38234 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12asus/p3b-f,intel/i440bx: Move enable/disable_spd() callKyösti Mälkki
Change-Id: I4a324dcebcd53439206205e64c5bbb7c6eac4fb2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38254 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-12mb/lenovo/g505s: Fix typosElyes HAOUAS
Change-Id: I38fdc8ff92cffe467b2ca176e841bf601be9d24b Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38369 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Alexander Couzens <lynxis@fe80.eu>
2020-01-11src/mainboard/*.asl: Remove _HID / _ADR objects overlappingJonas Moehle
ACPI spec: "A device object must contain either an _HID object or an _ADR object, but should not contain both." Signed-off-by: Jonas Moehle <ad-min@mailbox.org> Change-Id: I949393558f5af66689c167b2e593a1461f641962 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37935 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10HP sandy/ivy laptops: Sort Kconfig `select` linesAngel Pons
Sort them alphabetically. Change-Id: Ica7462d28d2aad184b6545db46547a01bc2a8ccb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38089 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/revolve_810_g1: Drop default DRAM_RESET_GATE_GPIOAngel Pons
When this board was added, S3 resume was tested and working, so it must be good enough. Change-Id: Ie095868ea2de7846b995271baf8155e57b495e40 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38088 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/8770w/Kconfig: Drop INTEL_INT15Angel Pons
This laptop does not have integrated graphics. Change-Id: Id2209973f66536c8a3ead4bc3e9d5a05b7970c64 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38087 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/{folio_9470m,revolve_810_g1}: Trim gfx.did to sizeAngel Pons
These values are the same that were hardcoded in autoport before. As done in commit 08caa79 (util/autoport: Trim gfx.did to size), ensure that the hardcoded values make at least some sense. Change-Id: I9950fd10e45f5016611a5d5b6a9e41c2b0f25a5f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38086 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10HP sandy/ivy laptops: Enable SMBus on devicetreeAngel Pons
It has no reason to be disabled. Change-Id: Iba82b6f71bc3d3a86576b719f2709595b530b702 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38085 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10HP sandy/ivy laptops: Align devicetreesAngel Pons
This makes it easier to spot differences. Change-Id: I16596a661ee4e56c2cb1d0aef663067ae6159705 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10HP sandy/ivy desktops: Fix Kconfig symbol namesAngel Pons
hp/z220_sff_workstation was using BOARD_HP_COMPAQ_8200_ELITE_SFF_PC, and hp/compaq_8200_elite was using a very long name. Fix that. Change-Id: I434cde42c7b9f30f8de77b96bc924aa298bad921 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38083 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/hp/*/devicetree.cb: Move northbridge devices upAngel Pons
It makes more sense for them to be above the southbridge block. Change-Id: I7dc06a46123f4bfc23d91f9c8cc4c9bdc4fb64f5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38082 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/hatch/variants/helios: Modify DPTF parametersKane Chen
Modify DTRT CPU Throttle Effect on TSR0 change to TSR3. BUG=b:131272830 BRANCH=firmware-hatch-12672.B TEST=emerge-hatch coreboot chromeos-bootimage Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I5b4645d7552e795a33c1b86d95c4061da71c65bd Reviewed-on: https://review.coreboot.org/c/coreboot/+/38299 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Shelley Chen <shchen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10asus/am1i-a: fix the blue "USB 3.0" ports for OHCI/EHCI "USB 2.0" modeMike Banon
Set up the proper IRQ routing for OHCI/EHCI devices which appear if XHCI controller is disabled (CONFIG_HUDSON_XHCI_ENABLE is not set). Now both "USB 3.0" ports are working fine at OHCI/EHCI "USB 2.0" mode. They also work fine if XHCI controller is enabled. Signed-off-by: Mike Banon <mikebdp2@gmail.com> Change-Id: I50a773eeab890627abc963e0a61f781d1cea3259 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38241 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-10mb/lenovo/t431s/devicetree: Rebalance against t430s onePeter Lemenkov
Change-Id: Iec40dd20c87b97dbd81ba3c63486cb5e66d99dc6 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37600 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/t431s/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I247129317799d342b28f2c0ed68949ecbe7d9c75 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37301 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10src: Remove blank acpi_tables source filesKarthikeyan Ramasubramanian
Due to build rules, dummy acpi_tables source files were added in many mainboards. With commit 1e83e5c61a3aa98f58f7d8cbf8d1eb9532896cc3 ("src/arch/x86: Build mainboard acpi_tables source if present"), the build system will build mainboard acpi_tables only if present. Remove the dummy/empty/blank acpi_tables source files. BUG=None TEST=Build test with some google mainboards. Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Change-Id: I0cef34368e2e5f5e3b946b22658ca10c7caad90a Reviewed-on: https://review.coreboot.org/c/coreboot/+/37854 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-01-10mb/hp/*/devicetree.cb: Inherit the subsystemidAngel Pons
Since all the `subsystemid` lines in these devicetrees use the same values, factor them out via inheritance. There are some exceptions though. There are some enabled devices which lack a `subsystemid` entry. Looks like HP uses the same subsystem ID on every device, so assume that these devices should also use that subsystem ID as well. While we are at it, tidy up all the now-empty device blocks. Change-Id: Iccd74fff9456e1204735a80ecc4f7685624cb78e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38081 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/pcengines/apu1/bootblock.c: Add possibility to redirect output to COM2Michał Żygowski
Enable COM2 port on SuperIO if UART index is 1. This change allows to use full RS232 COM1 port for different purposes when COM2 is selected as main port. TEST=flash coreboot with console on COM2 and observer output with UBS-TTL converter connected to COM2 header on PC Engines apu1 Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com> Change-Id: I1e72c5a43a302658f86dafd863e5a67580eae3e4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/29791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-10mb/facebook/monolith: Remove SDIO controller from devicetreeWim Vervoorn
The SDIO device is disabled so remove it from the devicetree. BUG=N/A TEST=build Change-Id: I6497f6134d8fc001bf4cb7e348ae00077aa34814 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38129 Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/facebook/monolith: Enable HDA for HDMI outputWim Vervoorn
The HDA controller was disabled because no codec exists on the board. However, this also disabled audio over HDMI. To correct this, enable Azalia and the HDA controller in the devicetree. BUG=N/A TEST=tested on facebook monolith Change-Id: I7be2c29151dc9d6c247c3332fb9adfb34449c703 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38128 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/facebook/monolith: Add UNIFIED_MRC_CACHE region in fmd fileWim Vervoorn
The RW_MRC_CACHE was not included in a UNIFIED_MRC_CACHE region which is expected by some parts of the code. Add the UNIFIED_MRC_CACHE and include the RW_MRC_CACHE in this region. BUG=N/A TEST=tested on facebook monolith Change-Id: I1654ca210dc2a8e976d698fd8330641da23e8380 Signed-off-by: Wim Vervoorn <wvervoorn@eltan.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38130 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/**/devicetree.cb: Remove untrue commentsAngel Pons
Even if they were corrected, they just rephrase the code. Change-Id: Iebc4e8c9eb0f44f84acf532ad12a5d064075a102 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38047 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/lenovo/t530/devicetree: Use subsystemid inheritancePeter Lemenkov
Missing PCI IDs are checked against those collected at https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad. Change-Id: I61457b7a791dc3341d582f67e651acc6230c525c Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37399 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1/devicetree: Rebalance against x220 onePeter Lemenkov
Change-Id: Ib009c33d8393d4a76036941ac77965dc12e4ec3e Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37603 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1/devicetree: Use subsystemid inheritancePeter Lemenkov
Change-Id: I0081b5f219447b110dddfa82cbae51d9ca282f5b Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37384 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/lenovo/x1_1st_gen/devicetree: Use subsystemid inheritancePeter Lemenkov
PCI ID was changed according to the reports from Linux Hardware Project: https://github.com/linuxhw/LsPCI/tree/master/Notebook/Lenovo/ThinkPad Change-Id: I67b81a4c9378c13d557e5d9c5d3797cebeeff5a1 Signed-off-by: Peter Lemenkov <lemenkov@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37942 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/google/fizz: Add Endeavour variantJeff Chase
Use the existing Karma variant as a base. BUG=b:144307303 TEST=build Change-Id: I09a10e99877d18361b31b36bed703b02508ccd05 Signed-off-by: Jeff Chase <jnchase@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36791 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Shelley Chen <shchen@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-01-10mb/msi/ms7707/devicetree.cb: Align contentsAngel Pons
Change-Id: I2e8100d01d1feb29df83c400f712e58ae9a5e402 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38080 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/wtm2/devicetree.cb: Align commentsAngel Pons
Change-Id: I701aea4656e59a369c2e663438a4b2f9644f0ed6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38079 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/emeraldlake2/devicetree.cb: Align contentsAngel Pons
Change-Id: I4ad24a011bd0711dc9a1133dc6188a213cc3926b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38078 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/intel/dg43gt: Make devicetree prettierAngel Pons
Use lowercase for hex constants and align comments and register values. Change-Id: Ib14906113e366a2a6f268fe8b8be32b1794fb344 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38077 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/intel/dcp847ske: Make devicetree prettierAngel Pons
Align contents and fix some redundant comments. Change-Id: I45fb02ac90fe3d280379b08c9931f1064c71633f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
2020-01-10mb/foxconn/d41s/devicetree.cb: Indent with tabsAngel Pons
As on most other boards, use tabs to indent the devicetree. Change-Id: I1d2fd6e758a3b2dccb8fc43d425f4520fd2e544f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38075 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-10mb/compulab/intense_pc: Reformat devicetreeAngel Pons
Use subsystemid inheritance, which results in a much more compact devicetree. In addition, align and correct various comments. Change-Id: Iafce736691b62ae8f359c2d74f8bd3549493029a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38074 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/compulab/intense_pc: Drop zero valuesAngel Pons
They default to zero already. Change-Id: Iaa557b18c34584dccb5c889ab8bd2173ed4ea04b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38073 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/roda/rk886ex/devicetree.cb: Align commentsAngel Pons
Change-Id: I67e3149657c04f72aac0b20bc31af338129a13b2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38072 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5ql-em/devicetree.cb: Do minor fixesAngel Pons
Use lowercase for hex constants, remove registers that default to zero already and drop outdated comment about AHCI mode. Change-Id: I6833462ea11e988eaab7913cf98853cebe4c7a9f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38071 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8z77-m_pro: Make devicetree prettierAngel Pons
Align comments, and make PCIe port comments consistent. Change-Id: Id39337236deff7721183e749a6b63aadaa036b2f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38070 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Drop zero valuesAngel Pons
They default to zero already. Moreover, the comment about AHCI mode no longer applies, as it was made the default mode. Change-Id: Ife99a79df0289c6db87510ed917438bf47b7f6ca Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qc/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants and align some comments. Change-Id: I418ed29dfbc90feb591a2b30e994d9b3e6176f86 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38068 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p5qpl-am/devicetree.cb: Do minor cosmetic fixesAngel Pons
Use lowercase for hex constants, inline a lone `end` and align a comment. Change-Id: Ibf3882dd134d33611138c2a9f89a3b2b37c136b4 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38067 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro: Make devicetree prettierAngel Pons
Replace a bunch of spaces with tabs, put host bridge and friends above southbridge, fix "TPM Module" (Trusted Platform Module Module) and add some empty lines to help the reader. Change-Id: I3a89893f943057ef7a4f973eaa65dba259e8a49d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38066 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/asus/p8h61-m_pro/devicetree.cb: Drop zero fieldsAngel Pons
They default to zero already. Change-Id: I5c99043f16bc65de952afa0ce8d40bf947bfee15 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38065 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/veyron/devicetree.cb: Drop illogical commentAngel Pons
This comment seems to have been copied off some QEMU board. As it would not apply to any veyron variant, drop it. Change-Id: I70a2923520f5c59ae31d149920cf4b096e5a11d1 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-10mb/google/nyan/devicetree.cb: Correct some commentsAngel Pons
Use a consistent spelling for SoC (System-on-a-Chip), and fix a few minor typos. Change-Id: I29eacc9e93b2eb686ce945de0173844ef5eae1b9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38063 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-09src/mainboard: remove MMIO macrosIdwer Vollering
This touches several mainboards. Replace the macro with C functions. The presence of bootblock.c is assumed. Change-Id: I583034ef0b0ed3e5a5e3dd680c57728ec5efbc8f Signed-off-by: Idwer Vollering <vidwer@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37738 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
2020-01-09AGESA,binaryPI boards: Declare some IRQ tables staticKyösti Mälkki
Change-Id: Ib45c6372df6068ab041a055dad8bacf597717ba2 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38261 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
2020-01-09drivers/pc80/rtc: Separate {get|set}_option() prototypesKyösti Mälkki
Long-term plan is to support loading runtime configuration from SPI flash as an alternative, so move these prototypes outside pc80/. Change-Id: Iad7b03dc985550da903d56b3deb5bd736013f8f1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38192 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-09soc/intel/{cnl,icl,tgl}: Move northbridge.asl into common/block/acpiSubrata Banik
This patch creates a common instance of northbridge.asl inside intel common code (soc/intel/common/block/acpi/acpi) and changes cnl,icl & tgl soc code to refer northbridge.asl from common code block. TEST=Able to build and boot Hatch and ICL DE system. Dump DSDT.asl to verify Device(MCHC) presence after booting to OS. Change-Id: Ib9af844bcbbcce3f4b0ac7aada43d43e4171e08b Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38155 Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Lance Zhao <lance.zhao@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08drivers/spi: remove SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B optionAaron Durbin
The SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B option is no longer being used in the code. There's a runtime check for supporting fast read dual output mode of the spi flash. Remove the references to SPI_FLASH_FAST_READ_DUAL_OUTPUT_3B. Change-Id: Ie7d9d3f91f29a700f07ab33feaf427a872bbf7df Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38166 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-08mb/google/hatch: Remove fixed IccMax valuesJamie Chen
Remove fixed IccMax values for all domains. IccMax will be selected by CPU SKU in fill_vr_domain_config function. BUG=b:145094963 BRANCH=None TEST=build coreboot and fsp with enabled fw_debug. Flashed to device and checked the log. Signed-off-by: Jamie Chen <jamie.chen@intel.com> Change-Id: I3f623d143f66c4f6ec63705844c9be7173feeb52 Reviewed-on: https://review.coreboot.org/c/coreboot/+/38237 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Edward Hill <ecgh@chromium.org> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-01-07mb/google/{beltino,jecht}: Drop SIO configuration linesNico Huber
These are meaningless for boards without SIO devices. Change-Id: I252bba6ff1a2547fd0661ad3076470376e95bdd6 Signed-off-by: Nico Huber <nico.h@gmx.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38032 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-01-07src/mainboard: Fix typoElyes HAOUAS
Change-Id: I8a486ce12d6a5f6de31afd279612dc37d3fffd83 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-07mb/google/kahlee/treeya: Tune VIH and meet specPeichao Wang
According to vendor Bayhub requirement need tune VIH make it meets spec --0x304(6:4) CLK = 3 --0x304(3:0) DAT = 5 BUG=None TEST=build firmware and measure VIH whether meets spec Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I4de9e6cfb37e3b76f7afc206cbe3396b8da2d6dd Reviewed-on: https://review.coreboot.org/c/coreboot/+/37458 Reviewed-by: Raul Rangel <rrangel@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-07mb/google/kahlee/treeya: tune eDP delay time to 20 msPeichao Wang
tune eDP delay time to 20 ms ensure satisfy panel spec BUG=b:147270512 TEST=verify panel sequences by ODM. Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: Ia38fbcb976de55baae480d33c6000c91dc9de6bb Reviewed-on: https://review.coreboot.org/c/coreboot/+/38024 Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: chris wang <Chris.Wang@amd.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-06util/supermicro: Add and use new tool smcbiosinfoPatrick Rudolph
The BMC and tools interacting with it depend on metadata placed inside the ROM in order the flash the BIOS. Add a new tool smcbiosinfo, integrate it into the build system, and generate a 128byte metadata file called smcbiosinfo.bin on build. You need to provide the BoardID for every SMC mainboard through a new Kconfig symbol: SUPERMICRO_BOARDID Some fields are unknown, but it's sufficient to flash it using SMC vendor tools. Tested on Supermicro X11SSH: * Flashing using the WebUI works * Flashing using SMCIPMITool works No further validation is done on the firmware. Change-Id: Id608c2ce78614b45a2fd0b26d97d666f02223998 Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/35484 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-06mb/*/*: Remove unused option_table.h includesKyösti Mälkki
These should have been removed together with read_option(). Change-Id: Ia6f268ac4551de14f9821c789844adfdf428b843 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38177 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-01-05mb/sapphire/pureplatinumh61: Make devicetree prettierAngel Pons
Align contents, and fix some redundant comments. Change-Id: I0c9e98281aeb887308c3cbb421105b1faf922063 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38062 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/sapphire/pureplatinumh61/devicetree.cb: Drop zero valuesAngel Pons
They default to zero already. Change-Id: Ib888377f06d6fcb79cff5e30155971c17aa2597c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38061 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/gigabyte/ga-b75m-d3h/devicetree.cb: Drop zero fieldsAngel Pons
They default to zero already. Change-Id: I76bbf4593c43ce24c28568f1b8faefb1be81b4cb Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38060 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-01-05mb/gigabyte/ga-b75m-d3h: Align devicetree linesAngel Pons
Aligned text is easier to read. Change-Id: I66a8efec3587649746bd56cd17eac2a06c9cc500 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38059 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 16:43:31 +0000