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2020-07-21mb/biostar: Add TH61-ITX portMate Kukri
- CPU: only tested with a Xeon E3-1220 (Sandy Bridge) - RAM: native raminit tested (4G+4G, 8G+8G) - USB: both chipset and ASMedia USB3 work, tested in SeaBIOS and Linux (5.4) - LAN: tested in Linux - SATA: all 4 ports work, tested in SeaBIOS and Linux - iGPU: I can't test it as I only have a Xeon for this socket - PEG: tested with an nVidia GT210, initialized by SeaBIOS - PS2 keyboard and mouse combo port: no devices to test with - Front panel header: tested, works - Audio: tested, works - Diagnostic LEDs: TBD Change-Id: I9fd3c0b148b694fcb8e728cc17f0bd45eb5af9f2 Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43165 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20google/trogdor: Remove write_protect_stateEric Lai
This is no longer used for chromeos.c. BUG=b:160752610 Signed-off-by: Eric Lai <ericr_lai@compal.corp-partner.google.com> Change-Id: I9a716a88ff9811fff46abca229be15522733bfef Reviewed-on: https://review.coreboot.org/c/coreboot/+/43472 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: Julius Werner <jwerner@chromium.org>
2020-07-20sb/intel: Define CONFIG_FIXED_SMBUS_IO_BASEAngel Pons
Make it default to 0x400, which is what the touched southbridges use. Change-Id: I95cb1730d5bf6f596ed1ca8e7dba40b6a9e882fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43037 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2020-07-20mb/google/dedede: Update link frequency and end point structure for OV9734Pandya, Varshit B
1. Update Link frequency to 180 Mhz 2. Set data-lanes to 1 and 3. Update the clock-lane used by sensor BUG=b:155285666 BRANCH=None TEST=Build and able to capture image using user facing camera. Signed-off-by: Pandya, Varshit B <varshit.b.pandya@intel.com> Change-Id: I164cb6af1003de561be8ce640e7653b7bcb3a22f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42679 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
2020-07-20mb/amd/mandolin: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=none Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic8ee8fb6b6bcd04c653ab77cdc5e746a8cbd0c4a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43466 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Delete sleep.aslRaul E Rangel
These methods are empty and the kernel treats these as optional. BUG=b:153001807, b:154756391 TEST=Suspend and resume trembyle Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I5f2b375c1186951f95b7ac44dc7158a0299013a1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43465 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for dalboz referenceFurquan Shaikh
This change drops internal pulls for dalboz reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_11(EC_IN_RW_OD): Pulled up to PP3300_A GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP1800_S0 GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_32: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_116(CLK_REQ2_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: I62e9dbac7a55efa1e055983a7c126168ee516151 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43555 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-20mb/google/zork: Drop unnecessary PULL_UPs for trembyle referenceFurquan Shaikh
This change drops internal pulls for trembyle reference configured on pads which already have external pull-ups in hardware. GPIO_0(PWR_BTN_L): Pulled up to PP3300_A GPIO_2(WAKE_L): Pulled up to PP3300_A GPIO_10: Unused. Changed to PAD_NC. GPIO_12(USI_INT_ODL): Pulled up to PP3300_A GPIO_16(USB_OC0_L): Pulled up to PP3300_A GPIO_17(USB_OC1_L): Pulled up to PP3300_A GPIO_21(EMMC_CMD): Pulled up to PP3300_A GPIO_22(EC_FCH_SCI_ODL): Pulled up to PP3300_A GPIO_31(EC_AP_INT_ODL): Pulled up to PP1800_A GPIO_90: Unused. Changed to PAD_NC. GPIO_113(I2C2_SCL): Pulled up to PP3300_S0 GPIO_114(I2C2_SDA): Pulled up to PP3300_S0 GPIO_129(KBRST_L): Pulled up to PP1800_S0 GPIO_130(EC_IN_RW_OD): Pulled up to PP3300_S0 GPIO_92(CLK_REQ0_L): Pulled up to PP3300_S0 GPIO_115(CLK_REQ1_L): Pulled up to PP3300_S0 GPIO_132(CLK_REQ4_L): Pulled up to PP3300_S0 BUG=b:154351731 Change-Id: Id84b801e019eede7ef543c24aac968f3ef99b3fd Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43526 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-20mb/google/puff: update USB3 gen2 parametersTim Chen
Based on USB3 gen2 SI report to fine tune the parameters for USB3 gen2. BRANCH=none BUG=b:150515720 TEST=build and check the USB3 gen2 register on DUT is correct. Change-Id: I6ec109871d682a1ae2fa4c22fdd6b87ad8a39e9e Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43482 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Jamie Chen <jamie.chen@intel.com> Reviewed-by: Edward O'Callaghan <quasisec@chromium.org>
2020-07-20mb/asrock/b85m_pro4: Enable VGA portAngel Pons
Now that libgfxinit has been fixed, trying to enable the Analog port no longer hangs the system, nor fills the monitor with unreadable garbage. Tested with linear framebuffer, displays correctly on a 1920x1080 VGA monitor. Scaling also works when a smaller HDMI monitor is connected as well. Legacy VGA text mode is also functional on either monitor, too. Change-Id: Ie2f88edcb7ed1984adebf2af23195767af13654c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43560 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-19mb/qemu-i440fx/memmap: Add warning when falling back to CMOS infosNico Huber
Change-Id: Iefac6fd45791cf6a051450b41046f7e7ebc1dc41 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43446 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19mb/qemu/fw_cfg: Fix return code check for fw_cfg_e820_select()Nico Huber
Change-Id: I22b9eb6ead37dbba6807d145468843bd01c94c84 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43445 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-19mb/qemu/fw_cfg: Add info messages about (not) found filesNico Huber
Print some more information at BIOS_INFO, like our CBFS code does. Change-Id: I1431d569c57634277ea5cf7feb352419db432b44 Signed-off-by: Nico Huber <nico.huber@secunet.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43444 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/dedede: Convert static DPTF ASL into devicetree entriesTim Wawrzynczak
Since there is now a mechanism to generate DPTF ACPI tables and methods at runtime, dedede should switch to using that instead of raw ASL files. This patch converts the existing .asl files into devicetree entries. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I6bb6e6e15f50a1e510080e16bbca09dfc5f16b1a Reviewed-on: https://review.coreboot.org/c/coreboot/+/43422 Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-18mb/google/volteer: Update DPTF with temp sensor 3Tim Wawrzynczak
While the DPTF refactor was in progress, TSR3 was added to volteer's dptf.asl file, and I forgot to update the devicetree with TSR3 as well. Also missed a swap in the passive policies of TSR0 and TSR1. This patch fixes those. BUG=b:149722146 TEST=boot volteer, dump SSDT & DSDT, verify TSR3._STA returns 0xF Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: I71bc798492ec45bb1e2f8d779e6829db52ef4499 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Deepika Punyamurtula <deepika.punyamurtula@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-17mb/google/zork/var/vilboz: Use AMDI1015 HID for I2S machine deviceFurquan Shaikh
Vilboz requires a different HID than rest of the zork variants. Hence, this change sets the HID to AMDI1015 for I2S machine device in vilboz overridetree.cb. BUG=b:157708581 Change-Id: Ibae343f21cf8f0c782dc8a461f69172bf0da7eba Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43545 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Switch to using newly added i2s_machine_dev driverFurquan Shaikh
This change switches zork devices to use the newly added i2s_machine_dev driver in devicetree rather than passing dmic_select_gpio in SoC config. BUG=b:157708581 Change-Id: I76c633694cbfb454c081ab2a4af4765bfbbae16b Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-17mb/asrock/b85m_pro4: Select MAINBOARD_USES_IFD_GBE_REGIONAngel Pons
This board uses the in-PCH GbE controller, and its IFD has a GbE region. Change-Id: Ifc09640b2ebd613d3d5566a13b50d36c11e3c346 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43522 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/amd/mandolin: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. Change-Id: I879b5614fb5d12c4814ee52f840a000744a7aab9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43520 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Drop mainboard.aslFurquan Shaikh
This change drops mainboard.asl from zork because none of the objects defined in it are used. BUG=b:153879530 Change-Id: If5440bcbce39b4461b44acaec69561663b1ea329 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43519 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17soc/amd/picasso: Move PMOD global variable to globalnvs.aslFurquan Shaikh
Global variable `PMOD` that stores the interrupt mode used by OS is required by all mainboards. This change moves the variable definition to globalnvs.asl under picasso. Additionally, ACPI spec says that BIOS should assume interrupt mode as PIC until _PIC() method is called by OS. Thus, this change also updates the default value of PMOD as 0 i.e. PIC mode. BUG=b:153879530 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I731c03d965882281a7a23f55894451210ba72274 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43514 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: correct wake gpe value for gpio 9Aaron Durbin
GPIO_9 is associated with gevent 22. Correct all the misconfigurations and use macros for clarity as to what bit offset is being used instead of open coding things. BUG=b:161205804 Change-Id: Ic4cfd62763d72d12a55f89585f24e07df6af0f4f Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43516 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-17mb/google/zork: Enable ACP_PME_EN and ACP_I2S_WAKE_ENFurquan Shaikh
This change enables ACP_PME_EN and ACP_I2S_WAKE_EN for dalboz and trembyle boards using devicetree settings. BUG=b:161328042,b:146317284 Change-Id: Ie367a9ba878a1892177df874bbcb8005efeb0880 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43496 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16soc/amd/picasso: remove unused fadt_pm_profile devicetree settingFelix Held
commit 56da63c3dc3f50cfac541c779b608e1bae9e635c removed overriding that field in the FADT. Change-Id: I0c8ff9ab125129dc856949c47a3a0c14e4109c73 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43417 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/amd/mandolin: add SATA DXIO descriptor for Dali SKUsFelix Held
Dali supports two SATA ports, but no PCIe alternate function on those pins. Change-Id: I27a13100e80565eb1dade2d703ba3d1f8b5f630f Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43493 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/amd/mandolin: fix DXIO lane numbersFelix Held
The DXIO descriptors use the logical and not the physical lane numbers, which are different. Change-Id: I7a90056d782d8d32fe34a0f5bdb61c3b61df1af8 Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43492 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16soc/amd/picasso/acpi,mb/{zork,mandolin}: Stop clearing PciExpWakeStatusRaul E Rangel
The kernel already clears this: https://source.chromium.org/chromiumos/chromiumos/codesearch/+/master:src/third_party/kernel/v5.4/drivers/acpi/acpica/hwregs.c;l=390 No reason to have the firmware do it as well. BUG=b:153001807, b:154756391 TEST=Build Trembyle, boot, suspend, and resume and didn't see any ACPI errors. Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ia5c79fb95dc885eaef8abc4257b6ba18c1ef1b66 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43428 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16soc/amd/picasso,mb/{zork,mandolin}: Remove invalid UPWS variableRaul E Rangel
PMx0EE is not defined in the Picasso PPR. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I98caf0cd2d0bdcf19de2b945dcf74f5cf7354769 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43424 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/amd/mandolin/.../sleep.asl: Remove unnecessary variableRaul E Rangel
There is no reason to create a named variable. We can just return the package. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ic0ca2e6d4fb833c68d29e9948a670ace7c89b6a5 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43464 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-16mb/google/zork: Move variant_pcie_gpio_configure() to bootblockFurquan Shaikh
On zork, bootblock is part of RW firmware in non-recovery mode, so PCIe GPIOs can be configured early on in bootblock rather than waiting until romstage. This change moves the call to variant_pcie_gpio_configure() to happen in bootblock and drops romstage.c file. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ic515304f35fe5623d58d6000efcb11fb9039e137 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43476 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop variant_romstage_gpio_table()Furquan Shaikh
gpio_set_stage_rom table is now configuring only PCIe related GPIOs in romstage. This change moves the configuration of PCIe related GPIOs to variant_pcie_gpio_configure() to keep all the configuration for WiFi and non-WiFi PCIe pads in one place. It also drops the function variant_romstage_gpio_table() as it is unused. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ib1c41ba141dce6b52b6e0a250a3aa07c296068aa Reviewed-on: https://review.coreboot.org/c/coreboot/+/43475 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Drop redundant romstage GPIO tableFurquan Shaikh
Now that the power and reset GPIO configuration for non-PCIe devices is dropped from romstage GPIO table, the tables for pre-v3 and v3 version of schematics are exactly same. So, this change drops the duplicate table and also removes the check for v3 schematics when configuring the pads in romstage. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I67ca9f587c3f47912393ebaf38badcc9d76cc393 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43474 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Drop power and reset control in romstage for dalbozFurquan Shaikh
This change drops power and reset control for non PCIe devices in romstage for dalboz reference as this is not required. +---------------------------------------------------------------------------------------+ | GPIO| Net name | External| Internal| Domain| State at reset | State on S3 resume | | # | | Pull | Pull | | | | +---------------------------------------------------------------------------------------+ | 5 | PEN_POWER_EN | 100K PD | PD | S5 | Powered off | Powered on | | | | | | | (because of | (since power is not| | | | | | | internal PD) | disabled when | | | | | | | | entering S3) | +---------------------------------------------------------------------------------------+ | 6 |EN_PWR_TOUCHPAD| 499K PD | PU | S5 | Powered on | Powered on | | | | | | | (because of | (since trackpad | | | | | | | internal PU) | is wake source) | +---------------------------------------------------------------------------------------+ | 68 | EMMC_RESET_L | 100K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 76 | EN_PWR_CAMERA | 499K PD | PD | S0 | Powered off | Powered off | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 140 | USI_RESET | 10K PD | PD | S0 | Deasserted | Deasserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 141 | USB_HUB_RST_L | 10K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------+ | 67 |EN_PWR_TOUCHPAD| 10K PU | PD | S0 | Powered off | Powered off | | |_PS2 (pre-V3) | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ GPIO_140 starts deasserted out of reset and S3 resume, but gets asserted in ramstage since it is eventually deasserted by OS using ACPI methods. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ie792a5a9d6420763ff10d1e475c094b6ee514888 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43463 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Drop power and reset control in romstage for trembyleFurquan Shaikh
This change drops power and reset control for non PCIe devices in romstage as this is not required. +---------------------+--------------------------------------------+--------------------+ | GPIO| Net name | External| Internal| Domain| State at reset | State on S3 resume | | # | | Pull | Pull | | | | +---------------------------------------------------------------------------------------+ | 5 | PEN_POWER_EN | 100K PD | PD | S5 | Powered off | Powered on | | | | | | | (because of | (since power is not| | | | | | | internal PD) | disabled when | | | | | | | | entering S3) | +---------------------------------------------------------------------------------------+ | 13 |EN_PWR_TOUCHPAD| 499K PD | PU | S5 | Powered on | Powered on | | |_PS2 | | | | (because of | (since trackpad | | | | | | | internal PU) | is wake source) | +---------------------------------------------------------------------------------------+ | 68 | EMMC_RESET_L | 100K PU | PD | S0 | Asserted | Asserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 76 | EN_PWR_CAMERA | 499K PD | PD | S0 | Powered off | Powered off | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ | 140 | USI_RESET | 10K PD | PD | S0 | Deasserted | Deasserted | | | | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | +---------------------------------------------------------------------------------------+ +---------------------------------------------------------------------------------------+ | 67 |EN_PWR_TOUCHPAD| 10K PU | PD | S0 | Powered off | Powered off | | |_PS2 (pre-V3) | | | | (because of | (because of | | | | | | | internal PD) | internal PD) | | | | | | | | | +-----+---------------+---------+---------+-------+----------------+--------------------+ GPIO_140 starts deasserted out of reset and S3 resume, but gets asserted in ramstage since it is eventually deasserted by OS using ACPI methods. BUG=b:154351731 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: Ieadc62f1a13857209cf0a62f204efb9278e0e97d Reviewed-on: https://review.coreboot.org/c/coreboot/+/43462 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-16mb/google/zork: Keep USI_RST asserted in ramstageFurquan Shaikh
This change keeps USI_RST(GPIO_140) asserted in ramstage since it gets deasserted by OS using ACPI methods. BUG=b:160854397 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I8feced788e471a0efb2358d42b2146df04fb7a0c Reviewed-on: https://review.coreboot.org/c/coreboot/+/43461 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Keep pen power enabled in sleep stateFurquan Shaikh
This change keeps pen power enabled in sleep state to allow it to charge in S3. BUG=b:155422911 Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I6190496653878327f34a01f6a743db474d32e929 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43452 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16Revert "mb/ocp/deltalake: Select IPMI OCP to send POST start/end command"Philipp Deppenwiese
This reverts commit a5ca4a0c75237093f1a4d90f30c0c932e5fcd05d. Reason for revert: Breaks coreboot tree because of non existent kconfig symbol Change-Id: Ib8f55dc2f6444690945bc2dc64baad5d0c39cdf4 Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43069 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com>
2020-07-16mb/ocp/deltalake: Select IPMI OCP to send POST start/end commandTimChu
Implement sending POST start/end command to BMC. TEST=Read POST command log in OpenBMC, if command received successfully, message may show as below, root@bmc-oob:~# cat /var/log/messages |grep -i "POST" 2020 May 28 13:21:22 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST Start Event for Payload#1 2020 May 28 13:21:25 bmc-oob. user.info fby3-v2020.20.2: ipmid: POST End Event for Payload#1 root@bmc-oob:~# Signed-off-by: TimChu <Tim.Chu@quantatw.com> Change-Id: I38b512ee97c0eda6ba54482a448ef9ffc27b4ddb Reviewed-on: https://review.coreboot.org/c/coreboot/+/41993 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Jonathan Zhang <jonzhang@fb.com> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/ocp/deltalake: Config PCH PCIe ports in devicetreeMorgan Jang
Tested on OCP Delta Lake with lspci checking if PCIe speed is changed are expected. Change-Id: I189027c403814d68db2b7c5f41fc254a293fe3a1 Signed-off-by: Morgan Jang <Morgan_Jang@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41690 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maxim Polyakov <max.senia.poliak@gmail.com>
2020-07-16mb/google/kukui: Add new config 'willow'Sheng-Liang Pan
New board introduced to Kukui family. BUG=b:159194582 TEST=None BRANCH=kukui Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Change-Id: Icc6bcbd006008a05303693e481a54636f0645887 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43318 Reviewed-by: Hung-Te Lin <hungte@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16google/trogdor: Remove GPIO_AP_SUSPEND_LJulius Werner
This pin has been removed from recent revisions (or at least moved to a pin that's not controlled like a normal GPIO). It has also never been used on older ones (I think?). The same GPIO is now used as a SKU ID pin, so make sure we're not incorrectly configuring it as an output (although sku_id() overrides that later anyway, but it's still incorrect). BUG=b:160754995 Signed-off-by: Julius Werner <jwerner@chromium.org> Change-Id: I6e0d56e230d0bef172d7b78cc48263e9b6f059de Reviewed-on: https://review.coreboot.org/c/coreboot/+/43471 Reviewed-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Philip Chen <philipchen@google.com> Reviewed-by: Bob Moragues <moragues@google.com> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-16mb/google/zork: Remove redundant PCI info from overridetreesRob Barnes
This information is redundant since it's already specified in baseboard/devicetree_trembyle.cb or baseboard/devicetree_dalboz.cb domain 0 is still required because sconfig uses it as an identity anchor to match devicetree and overridetree. BUG=b:157580724 TEST=Boot zork, usb functional Change-Id: I3c3c1c2410166b99599d7343fae3ee756f4da321 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43437 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/dedede: Enable SIS touchscreen for WaddledeeKarthikeyan Ramasubramanian
Add SiS9813 USI touchscreen support. BUG=b:160129126 TEST="emerge-dedede coreboot chromeos-bootimage", build successful. Change-Id: I42fdc5e8243d2c70c953b2f516c10f84a041c035 Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43304 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/volteer: Enable SATA Port Dito ConfigShaunak Saha
Enable SataPortsEnableDitoConfig for port 1. BUG=b:151163106 BRANCH=None TEST=Build and boot volteer. Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Change-Id: I552faaa0e7172e77208025cf4251bb848cc90709 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42415 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/zork/.../sleep.asl: Remove unnecessary variableRaul E Rangel
There is no reason to create a named variable. We can just return the package. BUG=b:153001807, b:154756391 TEST=None Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: I4f8f0362adf5ea5f026d0ba5ac6ac917fa160142 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43423 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-15mainboard: Drop optional and empty ACPI \_BFS methodsAngel Pons
The ACPI specification, version 2.0 says: _BFS is an optional control method. So, remove them. They have been copy-pasted around quite a bit, and do not do anything useful. Plus, it's deprecated in later ACPI versions. Change-Id: I9ef21f231dd6051d410ac3a0fe554908409c2fa7 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43443 Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/lippert/frontrunner-af: Drop commented-out Kconfig symbolAngel Pons
Drop it before it grows moss. Change-Id: I0b4f5487cca3c864ba531cc6c78a20c2682fc43d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43287 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/zork: Change SPI fast speed to 66mhzRob Barnes
Morphius cannot support 100Mhz fast SPI causing it to not boot. Downgrade all zork boards to fast=66mhz and normal=33mhz to be safe. BUG=b:161233767 TEST=Boot morphius Change-Id: I7744dd0cb8dede985fbdc28a64385e0bc4048402 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43459 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Eric Peers <epeers@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-15mb/google/oak: Add new DRAM modules for oakwuxy
Add DRAM support for oak: Samsung K4E6E304ED-4GB # 1001 Nanya NT6CL512T32AM-H0-4GB # 1010 BUG=b:157702981 BRANCH=oak TEST=emerge-hana chromeos-ec coreboot chromeos-bootimage depthcharge, update FW to DUTs,these DUTs can pass 'memtester' test over 48 hours. Signed-off-by: Xingyu Wu <wuxy@bitland.corp-partner.google.com> Change-Id: I95eb51debac905145f16b83c9b74a2bd31dbef45 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42184 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2020-07-14mb/hatch: Fix Puff baseboard missing mainboard symbolsEdward O'Callaghan
Fix a missing CONFIG_ prefix in Makefile. BUG=b:161154280 BRANCH=puff TEST=builds Change-Id: I177fcd830a8a03a8db1910bfbfd784a60dc08e11 Spotted-by: Ryan Lin. Signed-off-by: Edward O'Callaghan <quasisec@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43438 Reviewed-by: Sam McNally <sammc@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <cpu/x86/msr.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <cpu/x86/msr.h>' -- src/) <(git grep -l 'IA32_EFER\|EFER_\|TSC_MSR\|IA32_\|FEATURE_CONTROL_LOCK_BIT\|FEATURE_ENABLE_VMX\|SMRR_ENABLE\|CPUID_\|SGX_GLOBAL_ENABLE\|PLATFORM_INFO_SET_TDP\|SMBASE_RO_MSR\|MCG_CTL_P\|MCA_BANKS_MASK\|FAST_STRINGS_ENABLE_BIT\|SPEED_STEP_ENABLE_BIT\|ENERGY_POLICY_\|SMRR_PHYSMASK_\|MCA_STATUS_\|VMX_BASIC_HI_DUAL_MONITOR\|MC0_ADDR\|MC0_MISC\|MC0_CTL_MASK\|msr_struct\|msrinit_struct\|soc_msr_read\|soc_msr_write\|rdmsr\|wrmsr\|mca_valid\|mca_over\|mca_uc\|mca_en\|mca_miscv\|mca_addrv\|mca_pcc\|mca_idv\|mca_cecc\|mca_uecc\|mca_defd\|mca_poison\|mca_sublink\|mca_err_code\|mca_err_extcode\|MCA_ERRCODE_\|MCA_BANK_\|MCA_ERRTYPE_\|mca_err_type\|msr_set_bit\|msr_t\|msrinit_t' -- src/) |grep '<' Change-Id: I45a41e77e5269969280e9f95cfc0effe7f117a40 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41969 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <stdint.h>Elyes HAOUAS
Found using: diff <(git grep -l '#include <stdint.h>' -- src/) <(git grep -l 'int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX' -- src/) |grep -v vendorcode |grep '<' Change-Id: I5e14bf4887c7d2644a64f4d58c6d8763eb74d2ed Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41827 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <types.h>'Elyes HAOUAS
Files found using: diff <(git grep -l '#include <types.h>' -- src/) <(git grep -l 'BIT(\|size_t\|wchar_t\|wint_t\|NULL\|DEVTREE_EARLY\|DEVTREE_CONST\|MAYBE_STATIC_NONZERO\|zeroptr\|int8_t\|int16_t\|int32_t\|int64_t\|intptr_t\|intmax_t\|s8\|u8\|s16\|u16\|s32\|u32\|s64\|u64\|INT8_MIN\|INT8_MAX\|INT16_MIN\|INT16_MAX\|INT32_MIN\|INT32_MAX\|INT64_MIN\|INT64_MAX\|INTMAX_MIN\|INTMAX_MAX\|bool\|true\|false\|cb_err\|CB_SUCCESS\|CB_ERR\|CB_ERR_ARG\|CB_CMOS_\|CB_KBD_\|CB_I2C_\|cb_err_t\|DIV_ROUND_CLOSEST\|container_of\|__unused\|alloca(\|ARRAY_SIZE\|ALIGN\|ALIGN_UP\|ALIGN_DOWN\|IS_ALIGNED\|__CMP_UNSAFE\|MIN_UNSAFE\|MAX_UNSAFE\|__CMP_SAFE\|__CMP\|MIN(\|MAX(\|ABS(\|IS_POWER_OF_2\|POWER_OF_2\|DIV_ROUND_UP\|SWAP(\|KiB\|MiB\|GiB\|KHz\|MHz\|GHz\|offsetof(\|check_member\|member_size' -- src/)|grep -v vendor |grep '<' Change-Id: I5d99d844cc58d80acb505d98da9d3ec76319b2eb Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41677 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14src: Remove unused 'include <string.h>'Elyes HAOUAS
Found using: diff <(git grep -l '#include <string.h>' -- src/) <(git grep -l 'STRINGIFY\|memcpy\|memmove\|memset\|memcmp\|memchr\|strdup\|strconcat\|strnlen\|strlen\|strchr\|strncpy\|strcpy\|strcmp\|strncmp\|strspn\|strcspn\|strtok_r\|strtok\|atol\|strrchr\|skip_atoi\|snprintf' -- src/) |grep -v vendorcode |grep '<' Change-Id: I12802d0a6254b2fa39d59f485008bb2012f7b32d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41913 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/zork: Add USB to baseboard devicetreeRob Barnes
Add USB ports, USB user-facing camera and USB bluetooth to devicetree. USB ports 4 and 5 are duplicated for picasso and dali. BUG=b:158096224 TEST=Boot Trembyle and Dalboz, Dump acpi tables Change-Id: Icf8628d91e27a3afdc5fd67a53b44089c809da87 Signed-off-by: Rob Barnes <robbarnes@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42799 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14mb/google/zork: Split devicetree between baseboardsRob Barnes
Split zork baseboard devicetree between dalboz and trembyle. The devicetree is simply duplicated, no other changes in this commit. BUG=b:158096224 TEST=Build coreboot for zork Signed-off-by: Rob Barnes <robbarnes@google.com> Change-Id: I5b26770790092c69db9567fa4337edd21a6ed809 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42741 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2020-07-14mb/google/hatch: Set SA slow slew rate to 1/2 for jinlon/dratiniWisley Chen
Screen flickered on VT2 on some devices after idle a period of time. Remove SSR (1/8) setting for SA to default SSR (1/2), screen flicking issue disappeared, and didn't affect acoustic noise much. Because CB:38212 (commit eae254e) caused this issue. BUG=b:160754994 TEST=build dratini, observe that screen flick issue disapppered Change-Id: I9e81c2f15dd6babfa360eee213fc4ab6310c7455 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43284 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mainboard/volteer: Enable SaGv for volteer2, delbin & voxelShreesh Chhabbi
SaGv needs to be enabled for only QS. On ES2, we are seeing system instability. BUG=b:159198381 TEST=Tested for boot. Power and performance tests were run with volteer2 with qs setup. System showed stability. Tested for boot stability on on delbin. Change-Id: I1bce3b9f837fb19ba5a20ae31750a73474a86788 Signed-off-by: Shreesh Chhabbi <shreesh.chhabbi@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42483 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-14mb/google/kukui: Add new configs 'Cerise' and 'Stern'xuxinxiong
New boards introduced to Kukui family. BUG=b:160854400 TEST=make # select Cerise and Stern BRANCH=kukui Change-Id: I5841d57c0891d5191dd96097b90da889855b56c8 Signed-off-by: xuxinxiong <xuxinxiong@huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43320 Reviewed-by: Zhaoyou Hong <hongzhaoyou@huaqin.corp-partner.google.com> Reviewed-by: Hung-Te Lin <hungte@chromium.org> Reviewed-by: Chen-Tsung Hsieh <chentsung@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-14mb/google/volteer: config QS silicon devices for CSE LITENick Vaccaro
Configure volteer2 and delbin, the two variants currently using preQS or QS silicon, to use CSE Lite. BUG=b:158140797 TEST=cd to volteer's asset_generation folder, execute "./gen_all_variant_images.sh" and verify that all variant images are produced. Change-Id: I5e444529b090d82094b9da0df2648ea4cdb2888e Signed-off-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43413 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org>
2020-07-13mb/google/zork: Fix check for variant_uses_v3_schematics()Furquan Shaikh
CB:43224 ("mb/google/zork: Add helpers for v3 schematics and wifi power enable") added helper functions for determining if a board uses v3 schematics. However, it introduced a regression by adding a wrong check for variant_uses_v3_schematics() in variant_audio_update(). This change fixes the check to ensure that dmic_gpio is updated when variant is not using v3 schematics. BUG=b:161141258,b:161128964 TEST=Verified on trembyle that trackpad works again (it was broken because of the regression). Signed-off-by: Furquan Shaikh <furquan@google.com> Change-Id: I0e6ad844f68cface7b545f1547bd94470c30dde4 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43415 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Rob Barnes <robbarnes@google.com> Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-13mb/google/zork: Create Woomax variantKane Chen
Create the woomax variant of the zork reference board by copying the template(coreboot-zork/util/mainboard/google/trembyle) files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.1.1). BUG=b:158343602 BRANCH=None TEST=emerge-zork coreboot Signed-off-by: Kane Chen <kane_chen@pegatron.corp-partner.google.com> Change-Id: I0bb8ce1851f4064d24e48fd8957e2f9fe1e80b53 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42680 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-07-12mb/google/beltino/bootblock.c: Drop unused includeAngel Pons
Change-Id: I2994b8bf5521b539a9f3585a3221452b1807837a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43366 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
2020-07-12mb/google/zork: Update SPI mode to 100MHz, 1-2-2Martin Roth
Change SPI speed from 66MHz, mode 1-1-2 to 100MHz mode 1-2-2. “1-2-2" means command, address and data are transmitted through 1 wire, 2 wire and 2 wire, respectively. BUG=b:160603142 TEST=Boot on trembyle, verify register settings. Signed-off-by: Martin Roth <martinroth@chromium.org> Change-Id: I14f96e3c085126c70e64ef3a3f5b7b54ce6cbffe Reviewed-on: https://review.coreboot.org/c/coreboot/+/43306 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Rob Barnes <robbarnes@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12soc/intel/baytrail: Add dedicated devices for MMC and MMC 4.5 controllerMate Kukri
- Correctly detect device 17h as the MMC 4.5 controller - Support detection of the "old" MMC controller at device 10h Signed-off-by: Mate Kukri <kukri.mate@gmail.com> Change-Id: I9f0007b1cf01df09f775c088397c3b9c846908c3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/43086 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2020-07-12mb/intel/tglrvp: Add SMI handler for tglrvpJohn Zhao
This change adds SMI handler for SCI, S3/S5 wake up and LID closed events on tglrvp platform. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I0bc72f164e86f1921e0cad39f9749e8e3be0778f Reviewed-on: https://review.coreboot.org/c/coreboot/+/42957 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-12mb/intel/tglrvp: Add EC_HOST_EVENT_USB_MUX for tglrvpJohn Zhao
This change allows EC to change state of host-controlled USB MUX. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: Ia7c331157b1b4039e42c373f5b130a66f7594458 Reviewed-on: https://review.coreboot.org/c/coreboot/+/42955 Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/prodrive/hermes: Deselect PCIEXP_CLK_PM and L1_SUB_STATEChristian Walter
Set default of PCIEXP_CLK_PM and PCIEXP_L1_SUB_STATE to n as this breaks booting Windows with a PCIE NVIDIA. Change-Id: Ie8768b91c27c4159f9b3c7f94699134a82decea0 Signed-off-by: Christian Walter <christian.walter@9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43179 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wim Vervoorn <wvervoorn@eltan.com>
2020-07-12mb/google/volteer: Convert static ASL files to new DPTF implementationTim Wawrzynczak
This patch converts the current DPTF policies from static ASL files into the new SSDT-based DPTF implementation. All settings are intended to be copied exactly. Change-Id: I964c53afbd503d47a07b982672425f0e7a986a3f Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41895 Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/dedede: Add ability to provide override GPIO tableKarthikeyan Ramasubramanian
For variants with slightly different GPIO configuration, add support to pass an override GPIO configuration table. BUG=None TEST=Build and boot the waddledee mainboard. Change-Id: I2f1c6dc2ea5499bff96a471c4461339ef01ee19a Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43279 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-07-12mb/ocp/deltalake: Pull POST complete pin low before booting payloadJohnny Lin
Delta Lake uses GPIO pin GPP_B20 for POST complete event, BIOS needs to pull this pin low for BIC (Bridge IC) to start reading sensors. Tested=On Delta Lake oBMC, bic-util slotx --get_gpio to confirm the pin is low. Change-Id: I7e05f8a7caead8ee0632af4ff60ccd8b2412b3dd Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43162 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2020-07-12mb/intel/tglrvp: Enable PCIEXP_HOTPLUG for TCSS TBT/USB4Brandon Breitenstein
This change enables PCIEXP_HOTPLUG to support resource allocation for TCSS TBT/USB4. BUG=b:149186922 Change-Id: Id3066204c8a780ade251c7be4052a60a861e43db Signed-off-by: Brandon Breitenstein <brandon.breitenstein@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/41543 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-12mb/intel/tglrvp: Enable recovery in TGL RVPShaunak Saha
Share "EC in RW" GPIO with depthcharge. Also we define the CONFIGS needed CHROME, CHROME_EC and use the chrome lid and recovery. BUG=None BRANCH=None TEST=Build and boot TGL RVP. Check recovery works with crossystem recovery_request. Change-Id: I1e88200e3f8418e5b0ab39ac65ed1b3545ce111e Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/40861 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
2020-07-12mb/google/dedede/var/drawcia: support internal usb cameraWisley Chen
BUG=b:160741778 TEST=build drawcia, and check camera can be regconized Change-Id: I67bee9773b53451653abd76088d1d4062fe3da8f Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42929 Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com> Reviewed-by: Justin TerAvest <teravest@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/google/dedede/var/drawcia:Add audio support (ALC5682 codec, MX98360A spk amp)Wisley Chen
Select the drivers for ALC5682 codec and MX98360A spk amp BUG=b:158202026 TEST=FW_NAME=drawcia emerge-dedede coreboot chromeos-bootimage Change-Id: If271f11f10a85ade6f61ff8c25bfafeb67a69af6 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42928 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
2020-07-12mb/ocp/deltalake: Use VPD data to configure FSP UPD at romstageJohnny Lin
Read VPD variable 'fsp_log_enable' to decide enabling FSP log or not. With VPD_RW_THEN_RO, VPD_RW takes precedence over VPD_RO, and would be set to enabled if both places cannot find it. Tested=On OCP Delta Lake, use vpd to create and set fsp_log_enable and verified the results are expected. Change-Id: I0b3463acedd90e8e17f7e4eedc2fab63644f87e1 Signed-off-by: Johnny Lin <johnny_lin@wiwynn.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42903 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Christian Walter <christian.walter@9elements.com> Reviewed-by: insomniac <insomniac@slackware.it>
2020-07-12mb/getac/p470: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: Ida12426c51313a7642b5c363e58a79d77b1b096b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43240 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-12mb/supermicro/x9scl: Drop dead codeAngel Pons
This code is not even being build-tested. Drop it before it grows moss. Change-Id: I65fedfa7e8b2fbb72b3109a8790445e38909976a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43235 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Michael Niewöhner
2020-07-12mb/intel/tglrvp: Enable s0ix for tglrvp up3 and up4John Zhao
This change enables s0ix for tglrvp up3 and up4 platform. TEST=Built image and booted to kernel. Signed-off-by: John Zhao <john.zhao@intel.com> Change-Id: I657bee1d7ee120ae15ccb4a33f9eb2fcf5cca65a Reviewed-on: https://review.coreboot.org/c/coreboot/+/42954 Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/intel/tglrvp: Enable CpuReplacementCheckJamie Ryu
Enable CpuReplacementCheck for TGLRVP with a CPU socket. Test=build and verified with tglrvp Change-Id: I75b4a4609c172c341087077228e23c6d31a9e7e1 Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42789 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
2020-07-12haswell: Move some MRC settings to devicetreeAngel Pons
There's no generic way to tell whether a mainboard has an EC or not. Making Kconfig symbols for these options seems overkill, too. So, just put them on the devicetree. Also, drop unnecessary assignments when the board's current value is zero, as the struct defaults to zero already. Change-Id: If2ebac5fcab278c97dfaf8adc9d1e125888acafe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43129 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Automatically check if Intel GbE is to be enabledAngel Pons
If the Intel in-PCH GbE MAC is enabled in the devicetree, then tell MRC to enable it as well. No one can ever forget to set this option anymore! Change-Id: I946af36d16c94bb1a0f146604d0329fe6d6ce7e2 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43128 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Add function to retrieve SPD addressesAngel Pons
And use it instead of directly writing to the MRC struct. Change-Id: I7f04db29a08512c1a8b2b2300dba71cb3b84a5c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43127 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Automatically determine system typeAngel Pons
Check the PCH's LPC device ID to know the system type instead of relying on hardcoded numbers. The `get_pch_platform_type` function is MRC-safe. Change-Id: Icfe7c2dccb7c7a178892ad3a2e34ca93b33b2bb9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43124 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Introduce ENABLE_DDR_2X_REFRESH Kconfig optionAngel Pons
This Kconfig symbol allows doubling the memory's refresh rate, assuming that the MRC actually cares about it. It is disabled by default except on the mainboards which explicitly enabled this setting in `pei_data`. Change-Id: I6318dad0350d1c506c67f9d117d0ae8dad871281 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43122 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell boards: Drop unused romstage.c includesAngel Pons
Several of these includes are no longer necessary. Get rid of them. Since "raminit.h" already includes "pei_data.h", we can omit including the latter for brevity's sake. Change-Id: Ia7e9dadf87114ca9ea4761b89909ea035cdfc38a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43121 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Factor out `max_ddr3_freq`Angel Pons
All mainboards choose the maximum speed of DDR3-1600. Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12haswell: Compute disabled channel masks at runtimeAngel Pons
All mainboards have a non-zero SPD address to implemented DIMM slots. Knowing this, it is possible to compute the MRC slot population masks automatically instead of hardcoding the values on each mainboard. Change-Id: Ia8f369dd1228d53d64471e48700e870e01e77837 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43119 Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2020-07-12mb/lenovo/t440p: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: I43922b2a1fdf90aa5004a43a17e9bc53337d88c5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12mb/google/slippy: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: I4c6b65bce42b875bb55e8d04da44afe9c18fb6e5 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12mb/google/beltino: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: I62f5014cf1fea093aee17023b48fd4d404279410 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43113 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12mb/intel/baskingridge: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: If0cbc147791496bafc85831c1f88d3eb71b63350 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43112 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12mb/supermicro/x10slm-f: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: Iee5ca6188de4cea9393efb66baa089969353b4e6 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43111 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12mb/asrock/h81m-hds: Factor out common MRC settingsAngel Pons
There's no need to redefine common settings. Change-Id: Ie4ced6efc8119afca070ce86634a3c31c6580d0f Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43110 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12mb/asrock/b85m_pro4: Factor out common MRC settingsAngel Pons
These settings are the same on all boards. Since the other boards currently overwrite the struct contents, it doesn't make a difference. To ease review, the same settings will be dropped from other boards in separate commits, one board at a time. Change-Id: I500b7a1d7d97c6976e0c7c10ca491d3875cae22b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43109 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Relocate `mainboard_romstage_entry` to northbridgeAngel Pons
This is what sandybridge does, and if done properly allows factoring out common settings. Said refactoring will be handled in subsequent commits. Change-Id: I075eba1324a9e7cbd47e776b097eb940102ef4fe Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43108 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell boards: Fix writes to 16-bit DxxIR registersAngel Pons
The DxxIR (Device xx Interrupt Route) registers in RCBA are 16-bit wide, so do not use 32-bit operations to program them. Note that the DxxIP (Device xx Interrupt Pin) registers are 32-bit, so using 32-bit operations on them is correct. Change-Id: I9699b98d5fcd26b2c710bf018f16acc65dcb634e Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43107 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Drop `struct romstage_params` typeAngel Pons
It only contains a pointer to another struct. Flatten it. Change-Id: Iab427592c332646e032a768719fc380c5794086b Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43106 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
2020-07-12haswell: Make `copy_spd` a weak functionAngel Pons
Instead of using function pointers, we can use weak functions. So, drop the pointer from `romstage_params`, leaving `pei_data` as the only remaining member. This will be cleaned up in a follow-up commit. Change-Id: I3b17d21ea7a650734119a5cab4892fcb158b589d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/43105 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2020-07-11mb/asrock/b85m_pro4: Reduce Super I/O ACPI codeAngel Pons
We only need ACPI for the PS/2 devices. Plus, the NCT6776 ACPI code makes Windows BSOD with STOP 0xA5 (ACPI_BIOS_ERROR), which is bad. Change-Id: I4cfad012684264b21284674e8e3713a5d8bb37be Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/42430 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-01 21:11:43 +0000