summaryrefslogtreecommitdiff
path: root/src/mainboard
AgeCommit message (Collapse)Author
2018-09-15soc/sifive: move ram_resource to mainboardPhilipp Hug
ram_resource is board specific and should be moved there. Change-Id: I50bd9aaaae39422e565d8bf205a6365c59299df0 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28621 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-15pcengines/apu2: enable IOMMU for all apu2 variantsPiotr Król
IOMMU was tested on Xen 4.8 and Linux kernel 4.14.33. Following feature set is enabled: (XEN) AMD-Vi: Disabled HAP memory map sharing with IOMMU (XEN) AMD-Vi: IOMMU Extended Features: (XEN) - Peripheral Page Service Request (XEN) - Guest Translation (XEN) - Invalidate All Command (XEN) - Guest APIC supported (XEN) - Performance Counters (XEN) AMD-Vi: IOMMU 0 Enabled. Change-Id: I6dbfae78849248f3532caa78974c8f2ce61a530d Signed-off-by: Piotr Król <piotr.krol@3mdeb.com> Reviewed-on: https://review.coreboot.org/26116 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-15mb/asrock/g41c-gs: Add more buildin PCI devices to the devicetreeArthur Heymans
Change-Id: I9f7e7d70b850619e34a60fd8e7b16b44c728e9ca Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-09-14soc/sifive/fu540: Initialize SDRAMPhilipp Hug
Based on SiFive bootloader code Change-Id: I71043ce9e458e25e64da28d53cd36b02d2e22acc Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28604 Reviewed-by: Ronald G. Minnich <rminnich@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-14soc/sifive/fu540: Switch clock to 1GHz in romstagePhilipp Hug
Invoke clock_init in romstage for SiFive Unleashed. Change-Id: Ib869762d557e8fdf4c83a53698102df116d80389 Signed-off-by: Philipp Hug <philipp@hug.cx> Reviewed-on: https://review.coreboot.org/28602 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
2018-09-14mb/google/octopus: Query the EC for board versionKarthikeyan Ramasubramanian
The board version is part of EC's EEPROM, but is not being populated from EEPROM. Instead a default Kconfig parameter is returned as board version. Select GOOGLE_SMBIOS_MAINBOARD_VERSION Kconfig item to enable requesting the EC for board version. BUG=b:114001972,b:114677884,b:114677887 Change-Id: Ib404a9da35156e197d232088fd7ca69432effbca Signed-off-by: Karthikeyan Ramasubramanian <kramasub@google.com> Tested-by: Karthikeyan Ramasubramanian <kramasub@google.com> Reviewed-on: https://review.coreboot.org/28539 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Jett Rink <jettrink@google.com> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-14mb/google/octopus: fetch DRAM part number from CBI for phaser after DVT phasepeichao.wang
This modification for DVT build and use CBI method enable all memory particles. BUG=b:112870780 TEST=verify it under the EVT unit and pre-test EVT unit(rework RAM ID follow the proposal) respectively. Change-Id: I488a0652ba348eff9a6d8591b0cfa6ed4fe808aa Signed-off-by: peichao.wang <peichao.wang@bitland.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28579 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-13src/mainboard/*/*: Set Mini-ITX boards' category to "mini"Angel Pons
Change-Id: I637792d3bf22d2e452144d44ba03cfe45b47501d Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28580 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Nico Huber <nico.h@gmx.de>
2018-09-13src/*/intel/: clarify Kconfig options regarding IFDStefan Tauner
HAVE_INTEL_FIRMWARE is used to enable certain options that rely on a valid Inter Flash Descriptor to exist. It does *not* identify platforms or boards that are capable of running in descriptor mode if it's valid. Refine the help text to make this clear. Introduce a new option INTEL_DESCRIPTOR_MODE_CAPABLE that does simply declare that IFD is supported by the platform. Select this value everywhere instead of the HAVE_INTEL_FIRMWARE and default HAVE_INTEL_FIRMWARE to y if INTEL_DESCRIPTOR_MODE_CAPABLE is selected. Move the QEMU Q35 special case (deselection of HAVE_INTEL_FIRMWARE) to the mainboard directory. Change-Id: I4791fce03982bf0443bf0b8e26d9f4f06c6f2060 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28371 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12mainboards: Add SMMSTORE region in chromeos configsPatrick Georgi
Only for those that are x86 and also have a RW_LEGACY region. The assumption is that all devices touched have 64k block sizes when choosing size and alignment of the region. Change-Id: I12addb137604f003d1296f34f555dae219330b18 Signed-off-by: Patrick Georgi <pgeorgi@google.com> Reviewed-on: https://review.coreboot.org/28532 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-12rammus: add SPD mapping for rammus and shyvana supportkane_chen
Add MICRO 4G and 8G SPD file. BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: I7cb5b7f2bcdc6fbe0cbc640cad4af014f1a0edd6 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28484 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy/variants/nami: Add SPD for two memory partsRen Kuo
add two memory parts and ram id: hynix_dimm_H5ANAG6NCMR-VKC micron_dimm_MT40A1G16KNR-075E BUG=b:113983573 BRANCH=Nami TEST=emerge-nami coreboot chromeos-bootimage Change-Id: Ia052f16b6c1e64ee6458fbdeea56a482a728c35a Signed-off-by: Ren Kuo <Ren.Kuo@quantatw.com> Reviewed-on: https://review.coreboot.org/28536 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com> Reviewed-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mainboard/google/poppy/variants/rammus: Enable DA7219marxwang
On rammus, headset uses DA7219 so that we need to enable it. BUG=b:112945714 BRANCH=master TEST=emerge-rammus coreboot chromeos-bootimage Flash FW and check in kernel to see if DA7219 is up. Change-Id: I92dd412374d007aab264661e698fbbbbcf1eae45 Signed-off-by: marxwang <marx.wang@intel.com> Reviewed-on: https://review.coreboot.org/28537 Reviewed-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-10mb/google/poppy: Set UPD CmdTriStateDis for NocturneShaunak Saha
This patch sets the MRC UPD CmdTriStateDis for the nocturne boards.Nocturne is LPDDR3 design without RTT for CMD/CTRL. BUG=b:111812662 TEST=Run memtester app and also webgl fishtank on the LPDDR3 kabylake boards and also check the margin data is proper in FSP. Change-Id: I0f593761dcbd121e7e758421af178931b9d78295 Signed-off-by: Shaunak Saha <shaunak.saha@intel.com> Reviewed-on: https://review.coreboot.org/28379 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09drivers/vpd: Add VPD supportPatrick Rudolph
VPD reference: https://chromium.googlesource.com/chromiumos/platform/vpd/+/master/README.md Copy ChromeOS VPD driver to add support for VPD without CROMEOS. Possible use case: * Storing calibration data * Storing MAC address * Storing serial * Storing boot options + Now it's possible to define the VPD space by choosing one of the following enums: VPD_ANY, VPD_RW, VPD_RO. + CHROMEOS selects now VPD as part of it. + VPD is implemented as driver. Change-Id: Id9263bd39bf25d024e93daa57053fefcb1adc53a Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Reviewed-on: https://review.coreboot.org/25046 Reviewed-by: David Hendricks <david.hendricks@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-09mainboard/google/kahlee: Reset trackpad & touchscreenMartin Roth
AMD chips don't hold off a reset to the end of I2C transitions, so devices on the i2c bus can be left in a bad state. To avoid this, make sure the trackpad and touchscreen chips get disabled during boot. BUG=b:114411165 TEST=build, reboot watch trackpad enable go low Change-Id: Ie50f4a102249df79517da571a6e768dba804cd57 Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28538 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07mb/google/poppy/variants/atlas: enable NVMeCaveh Jalali
This adds support for a x2 NVMe device on PCIe bus PCIe lines 5+6 and clock#4. BUG=b:113369699 TEST=booted on atlas Change-Id: I08e7c4d65662ddbb7d936915c896eb1fcb240ba8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28535 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-09-07wedge100s: Add TPM supportMikolaj Walczak
Change-Id: Id7e8ad63de2a6094c66cbd47ae9b7707a9af4e81 Signed-off-by: Mikolaj Walczak <mwalczak@fb.com> Reviewed-on: https://review.coreboot.org/28529 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-07fsp_broadwell_de: enable spi consoleOkash Khawaja
this enables spi console for wedge100s with broadwell_de. the console size is 64kb. enabling spi console in `board.fmd` enables code which calls into `timer_monotonic_get` (from `spi_flash_cmd_poll_bit`) and `udelay` (from `ich_status_poll`). this patch selects `TSC_CONSTANT_RATE` in fsp_broadwell_de's Kconfig to satisfy that. Change-Id: Ib925c5aee88b65c46a81534405c364dd5649f8e8 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28528 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
2018-09-06mb/google/octopus: Configure H1 interrupt pad using Rx level configFurquan Shaikh
This change configures GPIO_63 (which is used for H1 interrupts) as Rx Level. This ensures that the signal gets passed on to the next logic state as is and the APIC entry can be configured to trigger interrupt on level or edge as per the kernel driver expectation. TEST=Verified that no H1 interrupt timeouts are seen with 100 iterations of warm and 100 iterations of cold reboot. Change-Id: I7aac30300a4251d9b40276dcca7ebc6a6d814c40 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28507 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-09-06wedge100s: enable mrc cache in fmapOkash Khawaja
this enables mrc cache in fmap for wedge100s and always enable it in Kconfig. Change-Id: I27cd236f67a6500b40fc3eb731397d408402f041 Signed-off-by: Okash Khawaja <okash.khawaja@gmail.com> Reviewed-on: https://review.coreboot.org/28527 Reviewed-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mainboard/google/poppy/variants/rammus: Enable GSPI clock for bus 0.kane_chen
On rammus, system halt was observed because of gspi clk value being set to 0. Log info from serial coreboot: FMAP: area RW_NVRAM found @ 9fa000 (24576 bytes) SF: Detected FAST_SPI Hardware Sequencer with sector size 0x1000, total 0x1000000 VBNV: Restore from flash failed ASSERTION ERROR: file 'src/soc/intel/common/block/gspi/gspi.c', line 443 gspi.c 442 443 assert(gspi_clk_mhz != 0); 444 assert(ref_clk_mhz != 0); 445 return (DIV_ROUND_UP(ref_clk_mhz, gspi_clk_mhz) - 1) & SSCR0_SCR_MASK; BUG=none BRANCH=master TEST=emerge-rammus coreboot chromeos-ec chromeos-bootimage Flash FW to DUT, and make sure system boots up. Change-Id: Ibe3937902901b2cdc1a196415c08fabb0f3155f2 Signed-off-by: YanRu Chen <kane_chen@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28405 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-06mb/google/poppy/variants/nocturne: Enable DMIC CLK0/DATA0Sathyanarayana Nujella
DMIC's are now connected to DMIC_CLK0/DMIC_DATA0. So, enable the pins accordingly. BUG=b:113744731,b:111106010 BRANCH=none TEST='emerge-nocturne coreboot chromeos-bootimage' builds the image Change-Id: I48cace3c6099a2853fcb377c695a5e325094baf6 Signed-off-by: Sathyanarayana Nujella <sathyanarayana.nujella@intel.com> Signed-off-by: Harsha Priya <harshapriya.n@intel.com> Reviewed-on: https://review.coreboot.org/28433 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06mb/google/poppy/variants/nautilus: Bump VCC_SA voltage offset 75mVSeunghwan Kim
Nautilus-Wifi with m3 AP got a halt issue during CTS test. Nautilus-Wifi was FCS with Celeron AP first and also its PCB/BOM was validated only with Celeron. Since Celeron deos not support turbo boost mode, its steady power demend and lower CPU frequency may not reflect the potential noise hidden inside the board. Bumping VCC_SA voltage offset 75mV confirmed works to mitigate the potential noise coupling to VCC_GT/SA, and we verified this change makes this issue go away on Nautilus-Wifi board. Nautilus-LTE doesn't show this issue, since it has 10L PCB, will have better grounding and less noise/ripple than 8L PCB. BUG=b:111417632 BRANCH=poppy TEST=Verified CTS test pass without an issue. Change-Id: Id13fcc36a5b6ed42620c66f57a7303f30bff1a50 Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28439 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-06mb/google/octopus: Enable TBMC deviceAmanda Huang
This change enables tablet mode ACPI device for all octopus boards. BUG=b:113348027 Change-Id: I69a5dd41cd0958b93f8eed338fed4b6ee77a178f Signed-off-by: Amanda Huang <amanda_hwang@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28466 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-05mainboard/google/kahlee: Enable the BCLK bufferMartin Roth
Set GPIO135 high to enable audio through the BCLK buffer. BUG=b:113559558 TEST=None BRANCH=grunt Change-Id: I1dcecf5960d3c91e0c2165e7f8856ff423c06e8c Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28482 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-05mb/intel/dg43gt/dsdt.asl: fix globalnvs.asl include pathStefan Tauner
Use ICH10's file instead of ICH7's. Change-Id: I02678179e8f1dbd9b9f7d6407383a7a6cad15011 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: https://review.coreboot.org/28450 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
2018-09-05mb/lenovo: Support dual graphics for xx20/xx30 ThinkPadsEvgeny Zinoviev
Add CMOS option that allows to use both integrated and discrete GPU. Tested on ThinkPad W530. Change-Id: I8842fef0fa1235eb91abf6b7e655ed4d8598adc7 Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28393 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-04mb/google/poppy/variants/rammus: add sku info into smbios tableZhuohao Lee
This patch adds the mainboard.c in order to support the sku id in smbios table where the sku id is queried from the eeprom via EC. BUG=b:113714761 BRANCH=master TEST=check the result of 'dmidecode' Change-Id: I3413784cca1ac10a2468d84f2d06c0e1d701fdcb Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28426 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02mb/lenovo: dGPU power handling on T430, T530Evgeny Zinoviev
Enable dGPU power handling on Lenovo ThinkPad T430, T530 via PMH7 register 0x50. Although there's no Thinker-1 chip on these models according to schematics, dGPU power control via PMH7 works the same as on T420/T520, so they can be considered Thinker-1-compatible. It can be tested from linux userspace using util/pmh7tool. To turn dGPU power off: pmh7tool -c 0x50 7 pmh7tool -c 0x50 3 To turn it on: pmh7tool -s 0x50 3 pmh7tool -s 0x50 7 To check whether it is on (bash): reg=0x$(pmh7tool -r 0x50) echo "$(( (( reg & 0x08 )) >> 3 ))" or just `pmh7tool -b 0x50 3` with https://review.coreboot.org/#/c/coreboot/+/28388/ Tested on ThinkPad W530. Change-Id: Ieab1a33b3c680c757cc0999660b5cb7e122474cc Signed-off-by: Evgeny Zinoviev <me@ch1p.com> Reviewed-on: https://review.coreboot.org/28392 Reviewed-by: Patrick Rudolph <siro@das-labor.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-09-02mb/google/poppy/Kconfig: Fix missing device node /dev/tpm0 for H1Zhuohao Lee
This patch adds the DRIVERS_SPI_ACPI to enable the tpm device node. Without DRIVERS_SPI_ACPI, the kernel will popped out the below error: cr50-update[592]: Starting cr50 update cr50_get_name[595]: updater is /usr/sbin/gsctool -s cr50-update[609]: exit status: 3 cr50-update[613]: output: Could not open TPM: No such file or directory cr50_get_name[615]: board_id: '' board_flags: '0x', extension: 'prod' cr50-update[617]: hashing /opt/google/cr50/firmware/cr50.bin.prod cr50-update[678]: current state 3 in /var/cache/cr50.a3055efbc9.state cr50-update[682]: not running cr50-result[782]: Not running normal image. Skip setting Board ID trunksd[795]: TPM: Error opening tpm0 file descriptor at /dev/tpm0: No such file or directory BUG=none BRANCH=master TEST=/dev/tpm0 is created Change-Id: I35287c6c54299c2677c41fc830675570b9d45a94 Signed-off-by: Zhuohao Lee <zhuohao@chromium.org> Reviewed-on: https://review.coreboot.org/28400 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-09-02mainboard/google/kahlee/var/liara: Enable Synaptics touchpad deviceCrystal Lin
Enable Synaptics touchpad device for liara BUG=b:113309346 BRANCH=master TEST=Verify touchpad on liara works with this change Change-Id: Icdafe34a00fd55d5338fa07ffa304e48e7b85e7b Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28398 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-31google/cheza: Adjust FMAP to fit new requirementsJulius Werner
This patch overhauls the Cheza FMAP, removing some sections we don't seem to need (RW_CDT, the two RW_XBL_BUFFERs, and the second copy of RW_DDR_TRAINING), and adding new sections we're going to need soon or should have had anyway (RO_DDR_TRAINING, RO_FSG, RW_LEGACY). Make more use of implicit offsets and sizes, because we can and because it should make future adjustments easier. Change-Id: I0bd9e59e9cfa162c478c4bd1f048fcac61ad5062 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28403 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: T Michael Turney <mturney@codeaurora.org>
2018-08-31mb/google/kahlee/variants/liara: Update Audio/H1/TP i2c timingsChris Zhou
After adjustment on Liara Proto Audio: 399.2 KHz H1: 398.3 KHz TP: 399.0 KHz BUG=b:113319200 BRANCH=master TEST=emerge-grunt coreboot chromeos-bootimage measure by scope Change-Id: Ibba8c823ed8451a804cf731d49e7568a94ac7c6b Signed-off-by: Chris Zhou <chris_zhou@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28397 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Daniel Kurtz <djkurtz@google.com> Reviewed-by: Raul Rangel <rrangel@chromium.org>
2018-08-31siemens/mc_apl1: Correct the Tx signal from SATA interfaceMario Scheithauer
Because of an incorrect transmit voltage swing, the signal must be adjusted. The factor of slices for full swing level can be corrected via the High Speed I/O Transmit Control Register 3. Change-Id: I116802cd2a944658fc3022e948eba43cebe52bb4 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28285 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Alex Thiessen <alex.thiessen.de+coreboot@gmail.com>
2018-08-30mb/google/poppy/variants/nautilus: Set grip sensor thresholdSeunghwan Kim
Set threshold parameter for grip sensor STH9321 .ProxCtrl6: 75 .ProxCtrl7: 99 BUG=b:113303916 BRANCH=poppy TEST=Built and verified parameter passed to driver Change-Id: I8a410a23b5e3831fc8e90118b810fc2409a026eb Signed-off-by: Seunghwan Kim <sh_.kim@samsung.com> Reviewed-on: https://review.coreboot.org/28381 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Enrico Granata <egranata@chromium.org>
2018-08-30mb/google/octopus: Add missing IOstandy settings.Shamile Khan
Also removed internal pull ups for CX_PREQ_L and CX_PREQ_L signals as they have external pull ups. BUG=b:110654510 TEST=On Yorp Proto 2, flashed image and verified that it boots to OS. Checked Wake-on-Wifi works with both cnvi and pcie modules. Also executed a few suspend resume cycles. Change-Id: I0a76cd2a1481c828fc092aaf7e870a411624879c Signed-off-by: Shamile Khan <shamile.khan@intel.com> Reviewed-on: https://review.coreboot.org/28328 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-29mainboard/google/kahlee: Enable EC firmware update screenMartin Roth
Grunt takes a few seconds to update the EC, so display a notification screen while that's happening. BUG=b:113286040 TEST=Boot Grunt with old EC firmware, see update screen Change-Id: I95fc4d3430bac66c09f57a4d34abde08752e5f0e Signed-off-by: Martin Roth <martinroth@google.com> Reviewed-on: https://review.coreboot.org/28374 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Raul Rangel <rrangel@chromium.org> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28mb/google/octopus/variants/meep: Add weida touchscreen supportTony Huang
Add weida touchscreen support BUG=none BRANCH=master TEST=emerge-octopus coreboot, and verified that touchscreen works on meep. Change-Id: I4352322820237e4c2289410af6643e15109060a1 Signed-off-by: Tony Huang <tony-huang@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28361 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-28soc/intel/cannonlake: Change LPDDR4 to MEMCFGLijian Zhao
Modify the previously SOC_CNL_LPDDR4_INIT to SOC_CNL_MEMCFG_INIT, to make the infrasturture to handle both LPDDR4 and DDR4 cases in the future. Consider the case of reading SPD from SMBus other than providing SPD pointer directly. BUG=N/A TEST=Verify "./util/abuild/abuild -p none -t google/zoombini -x -a" compiles successfully. Change-Id: I2f898147f67dd52b89cc3d9fc4e6b3854fa81f57 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28248 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Init SPI bus for ECTristan Shieh
Set EC SPI bus config and init SPI bus according to the config. BUG=b:80501386 BRANCH=none TEST=EC is not working yet. This makes depthcharge go forward a little. Change-Id: Id9209b6429417430cfcf7f5a5a1659e7e4bc7866 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28251 Reviewed-by: Joel Kitching <kitching@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-28google/kukui: Set up GPIOs for ChromeOSTristan Shieh
Set up EC interrupt GPIO to boot depthcharge. Without this patch, depthcharge will fail to detect EC interrupt GPIO. BUG=b:80501386 BRANCH=none TEST=Boots correctly on Kukui and see in logs, that depthcharge detects EC interrupt GPIO. Change-Id: I0ec2c70c189a059219954e0384aaf98995285728 Signed-off-by: Tristan Shieh <tristan.shieh@mediatek.com> Reviewed-on: https://review.coreboot.org/28250 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Julius Werner <jwerner@chromium.org>
2018-08-28siemens/mc_apl1: Extend circuit life by clock gating and power gatingMario Scheithauer
The firmware of devices connected to LPC should deassert the LPC CLKRUN# signal when there is no bus activity on LPC. Necessary changes: - Enable LPC CLKRUN# - Enable LPC PCE (Power Control Enable) - Enable LPC CCE (Clock Control Enable) - Remove I/O decoding range on LPC for COM 3 - Disable I/O UART driver Change-Id: I2fd80e3fdcf23658f97b8182a77df7e09ddf25d6 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28268 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-28google/grunt: Reset BayHub EMMC freq to SD base CLK 50MHzKevin Chiu
Bayhub eMMC controller default runs SD base 50MHz at the first power on. After boot into OS, mmc kernel driver will config controller to HS200/208MHz and send MMC CMD21 (tuning block). But Bayhub PCR register 0x3E4[22] (eMMC MODE select) is not clear after system warm reset. So eMMC will still run 208Mhz but there is no block tuning cmd in depthcharge. It will cause two Sandisk eMMC (SDINBDA4-64G-V/SDINBDA4-32G-V) to fail to load kernel and trap in 0x5B error (No bootable kernel found on disk). BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: Ic080682e67323577c7f0ba4ed08f8adafca620cc Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28353 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27mb/google/poppy/variants/atlas: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:113101335 BRANCH=atlas TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU0: Package temperature above threshold' Change-Id: I2dc9d157b54500bae29e123978bb8ad6e05ef619 Reviewed-on: https://review.coreboot.org/28325 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/poppy/variants/nocturne: Update DPTF parametersTodd Broch
Reduce the CPU passive threshold sample rate from 5 seconds to 1 second so DPTF will react faster to rapid temperature increases. Signed-off-by: Todd Broch <tbroch@chromium.org> BUG=b:67459049 BRANCH=nocturne TEST=manual performance/power testing on nocturne. No longer see messages like below in syslog, 'CPU3: Package temperature above threshold' Change-Id: Ic20c718fd3a496db7c7192feec4f230d924cc458 Reviewed-on: https://review.coreboot.org/28324 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/octopus/variants/baseboard: Update DPTF parametersSumeet Pawnikar
Update TSR1 trip point from 48C to 50C. Also, change power limit2 minimum value from 8W to 10W. These are the values as per recent thermal tuning. BUG=b:79779737 BRANCH=None TEST=Build coreboot for Octopus board. Change-Id: I33a9d2dc3e0e5566d95b1f1e46d3922dc8965b2b Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar@intel.com> Reviewed-on: https://review.coreboot.org/28187 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-27mb/google/kahlee: Fix I2C bus 0 timing for GruntAkshu Agrawal
This commit fixes the values and thus fixes the issue of audio device not getting detected on random reboots. Change-Id: I34a4f62815d192005c3324d4f71b0aba377fe738 Signed-off-by: Akshu Agrawal <akshu.agrawal@amd.com> Reviewed-on: https://review.coreboot.org/28280 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Daniel Kurtz <djkurtz@google.com>
2018-08-27mb/supermicro/h8qme_fam10: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: Ie3ee4acfd272991133f02a56df6e23aa6071d3e9 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27866 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27mb/kontron/986lcd-m: Use common pnp_{enter,exit} functionsElyes HAOUAS
Some unneeded includes are also removed. Change-Id: Icd518c46d8503d11d24466c30840d7e514e9a05d Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27865 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-27update all FADT version 3.0 to use the get tables functionMarc Jones
Most FADT report using ACPIv3 FADT table. Using the get revision function keeps the table versions in sync. Change-Id: Ie554faf1be65c7034dd0836f0029cdc79eae1aed Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28277 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-27siemens/mc_apl1: Disable PCI clock outputs on XIO bridgeMario Scheithauer
This patch disables the unused PCI clock outputs on the XIO2001 PCI Express to PCI Bridge. Change-Id: I0b9cf51a713f4ab46e71d250397486d136c26177 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28284 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-27mb/google/octopus: add Digitizer and Synaptics Touchpad for bobbaPan Sheng-Liang
add device "WCOM Digitizer" and "Synaptics Touchpad" for bobba BUG=none BRANCH=master TEST=emerge-octopus coreboot Change-Id: Ie0bf8ebab6d9cb9c8fe42a500efaa3d11ae359db Signed-off-by: Pan Sheng-Liang <sheng-liang.pan@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28332 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-25mb/intel/coffeelake_rvp: Remove superfluous header fileArthur Heymans
TEST: same sha256sum with BUILD_TIMELESS=1. Change-Id: Icf3368bcf1351f0e7cd4041c3792d76362aec9e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28331 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com>
2018-08-24siemens/mc_apl1: Select DDR50 mode for eMMCMario Scheithauer
To increase the lifetime of the circuit, it is necessary to reduce the eMMC speed to DDR50 mode. Change-Id: I40658b44a99e6600ed00950a1a177961f0055e7a Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28283 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-23mb/google/poppy/variants/nocturne: enable "Base Attached Switch" deviceDmitry Torokhov
This enables CBAS device on Nocturne to allow hid-google-whisker driver in kernel properly detect device configuration. Change-Id: I5905a2de208e94062f2768a9b7d22147f85c7f38 Signed-off-by: Dmitry Torokhov <dtor@chromium.org> Reviewed-on: https://review.coreboot.org/28262 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23siemens/mc_apl1: Make adjustments for the 1st redesign of this mainboardMario Scheithauer
For the 1st redesign of mc_apl1 mainboard some adjustments are necessary: - The FPGA is now connected directly via a PCIe Root Port - Internal Apollo Lake UARTs are now used - Adjusting GPIO settings Change-Id: I8917a52325306f24d1c39a88dac47b0cee760d57 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28270 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-23siemens/mc_apl1: Move board specific things to mc_apl1 variantMario Scheithauer
A FPGA is not necessarily available in further mc_apl1 variants. So we move the loading of the driver and the notify function to the mc_apl1 variant. Setting the CPU to Max Non-Turbo Ratio is also not absolutely necessary for further variants. Change-Id: I9f8438407f231df08e1ad04655bb6f747257e268 Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com> Reviewed-on: https://review.coreboot.org/28269 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
2018-08-23mb/foxconn/d41s: Add mainboardArthur Heymans
This supports the Foxconn d41s, d42s, d51s, d52s. The following is tested (SeaBIOS 1.12 + Linux 4.9) and works: - COM1 - S3 resume (with SeaBIOS needs sercon disabled) - Native graphic init on VGA output - SATA - USB - Ethernet - PS2 keyboard The base for this mainboard port was the Intel D510MO port. Change-Id: Ie4ec9cbf70adcdddbc2e5d805e4806825c320072 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28227 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23mb/google/octopus: Add null pointer checkJohn Zhao
src/mainboard/google/octopus/mainboard.c Function dev_find_slot may return NULL, check before its usage. Found-by: klockwork BRANCH=None TEST=Built & booted Yorp board. Change-Id: I160adbe3b0a5a2b0f11fd1567513860664d4bee3 Signed-off-by: John Zhao <john.zhao@intel.com> Reviewed-on: https://review.coreboot.org/28235 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-23mb/google/octopus/var/meep: Update GPIO config for meepWisley Chen
The change updates GPIO configuration for meep. 1. Update touchscreen power enable GPIO in devicetree. 2. Provide default override tables for GPIO configuration. BUG=b:112955087 TEST=Boot on meep proto board with Intel (Jefferson Peak) wifi card. Change-Id: Idb4e7a510eef15c2e118058d5848080782f4f665 Signed-off-by: Wisley Chen <wisley.chen@quantatw.com> Reviewed-on: https://review.coreboot.org/28252 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-22src/mainboard/*: Remove IFD_*_REGION values for ifdfakeAngel Pons
Since ifdfake has been deprecated in favor of better alternatives, such as flashrom IFD parsing. Therefore, there is no need to support ifdfake any further. Remove the IFD_*_REGION values on the few motherboards with them. Change-Id: Ie07116a7fb960c6ca832d802016f22c6677baac9 Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/28232 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-22mb/google/octopus/variants/bobba: Apply new GPIO configs for bid >= 2Furquan Shaikh
This change updates the board id check for version >=2 to apply new GPIO configs. BUG=b:112618194 Change-Id: I3544c9596c465615818d2040682e554a64fc6b1a Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/28263 Reviewed-by: Justin TerAvest <teravest@chromium.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-21nb/intel/pineview: Use a common MMCONF_BASE_ADDRESSArthur Heymans
This should not be board specific. Change-Id: Ifa617e84af767f33a94f1ddfa7d4883c1a45198f Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28224 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20eve: Add PL1 override to 7WLucas Chen
Change PL1 from 4.5W to 7W, based on thermal test results. BRANCH=eve BUG=b:73133864 TEST=Verify the MSR PL1 limitation is set to 7W. Change-Id: Ic3629f9c3b7eb6eef1a1b5a3051c9a11448bc9ad Signed-off-by: Lucas Chen <lucas.chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28078 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20atlas: enable keyboard backlight supportCaveh Jalali
This adds support for controlling the keyboard backlight over ACPI. BUG=b:112619894 BRANCH=none TEST=verified keyboard backlight can be adjusted using keyboard shortcuts Change-Id: I25713f341e8b5a4e50903ac109bfa717f20969d8 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28205 Reviewed-by: Caveh Jalali <caveh@google.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20mb/google/poppy/variants/nocturne: enable eistMatt Delco
Enable Enhanced Intel SpeedStep (EIST) on nocturne. Change-Id: Ie9b832f5bc3a5ef300783bd9bcd7cf5d186b98fa Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28103 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20mb/google/eve: enable eistMatt Delco
Enable Enhanced Intel SpeedStep (EIST) on eve. Change-Id: I49b18b817cda570f5c3c4d048c4e03329ac10b87 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28102 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20soc/intel/common/block: Move common uart function to block/uartSubrata Banik
This patch moves uart functions which are common across multiple soc to block/uart. This will remove redundant code copy from soc {skylake/apollolake/cannonlake}. BUG=b:78109109 BRANCH=none TEST=Build and boot on KBL/APL/CNL platform. Change-Id: I109d0e5c942e499cb763bde47cb7d53dfbf5cef6 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/26164 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-20nocturne: Enable debouncing of SX9310 CLOSE / FAR IRQsEnrico Granata
This is meant to solve an issue where the proximity sensor may fluctuate between CLOSE / FAR in rapid succession upon the user removing their hand from the unit, before settling on the correct output. Using the hardware debouncing filter solves this issue and removes the spurious fluctuations. BRANCH=None BUG=None TEST=manual on Nocturne, observing events come in Change-Id: I78cc4852d42fcda6209fedce1ce91236b5814571 Signed-off-by: Enrico Granata <egranata@chromium.org> Reviewed-on: https://review.coreboot.org/28112 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Gwendal Grignou <gwendal@chromium.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-20mb/google/octopus/variants/fleex: Increase weida touchscreen reset delayCrystal Lin
Weida touchscreen controller needs 130 ms delay after reset BUG=b:111102092 BRANCH=master TEST=Verify touchscreen on fleex works with this change Change-Id: Ia86c3acf3c0e09ca05cc1681113672b546f830a0 Signed-off-by: Crystal Lin <crystal_lin@compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28115 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2018-08-20mb/asus/kfsn4-dre: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: I4b0577bf3c00307733a1096749c1835d86764f29 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27867 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-20mb/kontron/ktqm77: Use common pnp_{enter,exit} functionsElyes HAOUAS
Change-Id: Ib5799cceacefa89385a7615ef1c4b4d06157044f Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/27868 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-19google/cyan: Fix ACPI resource scope for Melfas touchscreenMatt DeVillier
Fix scope of ResourceSource, which should match the scope of the device itself. Change-Id: I9d0ff0ecc2721ec55b1ed12dddb495cd55966daf Signed-off-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-on: https://review.coreboot.org/28114 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
2018-08-19mb/lenovo/x1_carbon_gen1: add support for hynix memoryAlexander Couzens
All different memory configuration should be supported by now. Thanks to Igor Lee. Change-Id: Ib93c0e3cbdc29cbf6cff26292df4fbbb8208082f Signed-off-by: Alexander Couzens <lynxis@fe80.eu> Tested-by: Igor Lee <getrun@gmail.com> Reviewed-on: https://review.coreboot.org/27781 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-17arm64: Factor out common parts of romstage execution flowJulius Werner
The romstage main() entry point on arm64 boards is usually in mainboard code, but there are a handful of lines that are always needed in there and not really mainboard specific (or chipset specific). We keep arguing every once in a while that this isn't ideal, so rather than arguing any longer let's just fix it. This patch moves the main() function into arch code with callbacks that the platform can hook into. (This approach can probably be expanded onto other architectures, so when that happens this file should move into src/lib.) Tested on Cheza and Kevin. I think the approach is straight-forward enough that we can take this without testing every board. (Note that in a few cases, this delays some platform-specific calls until after console_init() and exception_init()... since these functions don't really take that long, especially if there is no serial console configured, I don't expect this to cause any issues.) Change-Id: I7503acafebabed00dfeedb00b1354a26c536f0fe Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/28199 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17google/grunt: Update TP/TS/H1 i2c timingsKevin Chiu
After adjustment on Careena EVT TP: 400.0 KHz TS: 396.8 KHz H1: 396.8 KHz BUG=b:112663934,b:112664258 BRANCH=master TEST=emerge-grunt coreboot measure by scope Change-Id: I9eeaf9290d95969a283f14618878e28faf0ea46f Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28119 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17mainboard/google/kahlee: Fix ACPI method Not Serialized errorMarc Jones
Fix the following failure from FWTS: FAILED [LOW] AMLAsmASL_MSG_SERIALIZED_REQUIRED: Test 1, Assembler remark in line 131 Line | AML source -------------------------------------------------------------------------------- 00128| } 00129| } 00130| }) 00131| Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings | ^ | Remark 2120: Control Method should be made Serialized (due to creation of named objects within) 00132| { 00133| Name (RBUF, ResourceTemplate () 00134| { ================================================================================ ADVICE: (for Remark #2120, ASL_MSG_SERIALIZED_REQUIRED): A named object is created inside a non-serialized method - this method should be serialized. It is possible that one thread enters the method and blocks and then a second thread also executes the method, ending up in two attempts to create the object and causing a failure. BUG=b:112476331 TEST= Run FWTS. Change-Id: I6f4f6e7e94b01f673afc97d9415481ee63e406e3 Signed-off-by: Marc Jones <marcj303@gmail.com> Reviewed-on: https://review.coreboot.org/28122 Reviewed-by: Martin Roth <martinroth@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-17mb/intel/coffeelake_rvp: Update spd details as per Coffeelake boardMaulik V Vaghela
Update SPD details to match with Coffeelake U RVP board BUG=none BRANCH=none TEST=Boot on coffelake U rvp board and check if memory training is passing and board boots till payload. Change-Id: I953354cf5c6045731262f4f4e9da230187c2d246 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27906 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com>
2018-08-17mb/intel/coffeelake_rvp: Update GPIO table for Coffeelake U RVPMaulik V Vaghela
Update GPIO table as per board schematics. GPIO table for other variants will be added later. Change-Id: Ieb55d160ae2d6bff940840b1fba9411979332d4d Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27907 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-08-17Nami: Disable powering off EC on cr50 updateDaisuke Nojiri
Nami doesn't support wakeup from hibernation by CR50. This causes the device to remain turned off after CR50 update. This patch disables turning off EC on cr50 update. CR50 resets the whole system. So, EC reset is not required. Signed-off-by: Daisuke Nojiri <dnojiri@chromium.org> BUG=b:112604277 BRANCH=none TEST=gsctool -a -u /media/removable/cr50.bin && reboot Verify EC reboots. AP prints 'Waiting for CR50 reset to pick up update' then reboots. Change-Id: I06f5eb6100e8af6ffec45d4de2b40eff44f89709 Reviewed-on: https://review.coreboot.org/28113 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-16mb/*/*/cmos.default: Harmonise CMOS files syntaxElyes HAOUAS
These files are being updated to match the prevailing style of cmos.default files. Change-Id: I47d31d6fec8c9eb856aed0c63824d9556b7705e4 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28051 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-16google/grunt/aleena: Update Raydium TS device ACPI nodesTim Chen
change I2C irq to EDGE trigger BUG=b:112616824 BRANCH=master TEST=emerge-grunt coreboot Raydium TS is working. Change-Id: I86ec32bb3f2626e65d76c3259e3c4244a970e5de Signed-off-by: Tim Chen <tim-chen@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/28095 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15mb/*/*/cmos.default: Decrease debug_level to 'Debug'Elyes HAOUAS
Used default console log level is 7 in src/console/Kconfig. So let cmos.default use the same level as default. Change-Id: Ia39ee457a8985142f6e7a674532995b11cb52198 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28006 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15google/grunt: Remove BayHub EMMC driving strength overrideKevin Chiu
Side effect was observed that after override BayHub EMMC driving strength to the max, EMMC CLK will be reduced to 51.x Mhz from 200 Mhz. This will cause OS installation fail on Samsung EMMC sku. BUG=b:111964336 BRANCH=master TEST=emerge-grunt coreboot Change-Id: I848ab0cae474b15fbc4264c8ade63d5c6b4e489d Signed-off-by: Kevin Chiu <Kevin.Chiu@quantatw.com> Reviewed-on: https://review.coreboot.org/28084 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
2018-08-15mb/google/poppy/variants/nocturne: remove dup'ed dptf_enableMatt Delco
This file contains two instances of "dptf_enable" = "1". This change removes the 2nd instance (it doesn't have an explicit comment like the 1st instance). The dptf devices still seem to be present even with this change, as expected. Change-Id: I890006644be9176ebaf555cc121c816e12f2b596 Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28076 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-15mb/google/poppy/variants/nocturne: sx9310 to 400kbMatt Delco
The spec of the sx9310 says the I2C interface can handle standard (100kb/s) and fast mode (400kb/s). The current setting is using fast plus (1000kb/s) so this change is reducing the speed to fast mode. I've been using the sensors with this change for a few weeks now, though I also don't recall seeing an issue prior to this change. Change-Id: I337fc02c52565d6ec4d7bac1b3564f65238962dc Signed-off-by: Matt Delco <delco@chromium.org> Reviewed-on: https://review.coreboot.org/28075 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-15Revert "mb/google/poppy/variants/atlas: enable camera power and release reset"Caveh Jalali
This reverts commit 1fdb76945a9d06bbff37dee9da69e13a86c933f4. Camera power is now handled by ACPI rules - no need to force the GPIOs on by default. BUG=b:80106316,b:111141128 Change-Id: Ifefec320884989f106a4b09c956d3a3279a1491a Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28072 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Ping-chung Chen <ping-chung.chen@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15mb/google/atlas: Add DISPLAY_DCR_EN GPIO pinCaveh Jalali
This defines new GPIO pin for controlling the display panel CABC function. The default value is high (enabled). BUG=b:112154569 Change-Id: I29083ab18e37f929a55b450b143463c67fe0abea Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28070 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-15mb/google/atlas: Update DPTF sensor namesCaveh Jalali
This updates the DPTF sensor names to reflect the sensor locations on the board. BUG=b:75454415 TEST=verified new strings show up in /sys/devices/LNXSYSTM:00/LNXSYBUS:00/INT3400:00/*/description Change-Id: Ibffe6cb361de212ca03e75deaa8c454546d267a5 Signed-off-by: Caveh Jalali <caveh@chromium.org> Reviewed-on: https://review.coreboot.org/28069 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14src: Remove duplicated 'include <device/device.h>'Elyes HAOUAS
Change-Id: Ia38c6f8d978065090564d449cae11d54ddb96421 Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/28064 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
2018-08-14mb/google/poppy/variants/nocturne: Update PL1/PL2 for AMLRoy Mingi Park
This patch updates Power Limit (PL) for AML. - PL1 as 5W TDP as POR - PL2 as 18W TDP as POR BUG=None BRANCH=None TEST=Build coreboot for Nocturne board and check default PL1/PL2 TDP. cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_0_power 5000000 (5W TDP) cat /sys/class/powercap/intel-rapl/intel-rapl\:0/constraint_1_power 18000000 (18W TDP) Change-Id: Icb02a8a7c5fcd5e6aee45f14eba540a6b3ed3d67 Signed-off-by: Roy Mingi Park <roy.mingi.park@intel.com> Reviewed-on: https://review.coreboot.org/27427 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com>
2018-08-14mb/google/poppy/variant/nami: Add TSR2 on DPTFT.H. Lin
Add TSR2 DART/DTRT package BUG=b:110451144 BRANCH=nami TEST=emerge-nami coreboot chromeos-bootimage Test image with dptf.dv Change-Id: I3328e17328415f5ebdcf84263e5456e11e55f769 Signed-off-by: T.H. Lin <t.h_lin@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/27999 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar@intel.com>
2018-08-14mb/google/octopus/var/bobba: Update GPIO config for bobba bid >= 1Justin TerAvest
This change updates GPIO configuration for bobba boards with id >= 1 This follows the same model as fleex: a. Dynamically update touchscreen power enable GPIO in devicetree. b. Provide default and bid0 tables for GPIO configuration in ramstage. c. Configure WLAN enable GPIO differently in bootblock based on boardid. BUG=b:112354568 TEST=Built firmware for bobba Change-Id: Id4ee4a1815e16ddfe60ed268688a8aaf4fb75579 Signed-off-by: Justin TerAvest <teravest@chromium.org> Reviewed-on: https://review.coreboot.org/28071 Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-14mb/intel/coffeelake: Enable 32MB rom compilation for Coffeelake UMaulik V Vaghela
Coffeelake U has 32MB flash chip support. Adding fmd file and enabling CFL U board's Kconfig to output 32MB rom file. Change-Id: I21431b7ac813781b12b95f80c6f8960a78caf4bc Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27905 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com>
2018-08-14mb/intel/coffeelake_rvp: Add support for new board coffeelake RVPMaulik V Vaghela
Add support for new board coffeelake RVP. This patch is a copy patch and copies entire coffeelake_rvp folder from cannonlake_rvp. Changes done on top of copy: 1. Change copyright year from 2017 to 2018 2. Rename Cannonlake to Coffelake whenever applicable 3. Update entries in Kconfig and Kconfig.name 4. Rename variant directories to match coffeelake boards Change-Id: Id37bfeb0ae51fd630fec96273216dbb2900782c7 Signed-off-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-on: https://review.coreboot.org/27904 Reviewed-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-by: Naresh Solanki <naresh.solanki@intel.com> Reviewed-by: Lijian Zhao <lijian.zhao@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/kahlee: Remove unneeded blank linePaul Menzel
Change-Id: I189c981f3334836ab24bbc74491e9b58a2d403a4 Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de> Reviewed-on: https://review.coreboot.org/27921 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
2018-08-13mb/intel/cannonlake_rvp/Kconfig: Don't redefine firmware pathsArthur Heymans
The paths defined in southbridge/intel/common/firmware/Kconfig should work just fine. Change-Id: Iaa780d9b3080416c6b1a7f24d97ecb8214962405 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28012 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13soc/intel/broadwell/Kconfig: Clean up redefined config optionsArthur Heymans
All broadwell board set HAVE_IFD_BIN to default n, overloading the option in soc, therefore just use the defaults in sb/intel/common/firmware. Change-Id: I250dbbc9d61ecedc1a1eb48751ad966732604349 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28011 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2018-08-13mb/google/rambi: Don't set defaults for HAVE_IFD_BINArthur Heymans
There is no need set the default HAVE_IFD_BIN explicitly to n. Change-Id: I4a5fe45e7f8f6dd018937861b0fb92a8da49904e Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/28008 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Reviewed-by: Tristan Corrick <tristan@corrick.kiwi> Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-09 15:16:36 +0000